Gate drive circuit, display substrate and display device

Abstract

The invention provides a gate drive circuit, a display substrate and a display device. The display substrate comprises a gate drive circuit arranged in a semiconductor substrate and a plurality of pixel circuits arranged in the semiconductor substrate, the gate drive circuit comprises cascaded single-stage gate drive circuits, and each single-stage gate drive circuit comprises a first circuit and a second circuit, the semiconductor substrate comprises a first well region and a plurality of second well regions, the depth of the first well region is greater than that of the second well regions, the second circuit and the pixel circuit are arranged in the first well region, and the first circuit is arranged in the plurality of second well regions.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a gate driving circuit, a display substrate, and a display device. Background Art

[0002] This section is intended to provide a background or context to the embodiments recited in the claims. No admission is made that anything herein is prior art by virtue of its inclusion in this section.

[0003] Micro-OLED is a new type of OLED display device based on a silicon substrate. Silicon-based OLED display substrates are compact and high-resolution. They are manufactured using a mature integrated circuit CMOS process, enabling active pixel addressing. They can integrate gate drive circuits, source drive circuits, crystal oscillators, gamma registers, pixel circuits, and more. Silicon-based OLED display substrates are widely used in near-eye displays, virtual reality, and augmented reality, particularly in AR / VR head-mounted displays. Summary of the Invention

[0004] The present disclosure provides a gate driving circuit, a display substrate, and a display device.

[0005] The present disclosure adopts the following technical solution: a gate drive circuit, including a cascaded single-stage gate drive circuit, the single-stage gate drive circuit including: a single-stage shift register circuit, a logic operation circuit and a drive output circuit; the single-stage shift register circuit is used to transfer a coding sequence to the single-stage shift register circuit in the next-stage single-stage gate drive circuit; the logic operation circuit is used to map the coding sequence into multiple drive signal waveforms; the drive output circuit is used to drive multiple gate lines in a one-to-one correspondence according to the multiple drive signal waveforms.

[0006] In some embodiments, the single-stage shift register circuit includes: a plurality of D flip-flops numbered in sequence, and two transmission gates correspondingly connected to each D flip-flop; the input end of the D flip-flop is connected to the output end of the correspondingly numbered D flip-flop in the next single-stage shift register circuit through a transmission gate, and the output end of the D flip-flop is connected to the input end of the correspondingly numbered D flip-flop in the next single-stage shift register circuit through another transmission gate.

[0007] In some embodiments, the D flip-flop includes: a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a first NAND gate, a second NAND gate, a first transmission gate, a second transmission gate, and a third transmission gate; the clock signal terminal of the D flip-flop is connected to the input terminal of the first NOT gate, and the output terminal of the first NOT gate is connected to the first node; the input terminal of the second NOT gate is connected to the first node, and the output terminal of the second NOT gate is connected to the second node; the first terminal of the first transmission gate is connected to the input terminal of the D flip-flop, the second terminal of the first transmission gate is connected to the first input terminal of the first NAND gate and the output terminal of the third NAND gate, the high-level effective enable terminal of the first transmission gate is connected to the first node, and the low-level effective enable terminal of the first transmission gate is connected to the second node; the second input terminal of the first NAND gate is connected to the enable terminal of the D flip-flop, and the output terminal of the first NAND gate is connected to the third NAND gate. the input terminal of the D flip-flop and the first terminal of the second transmission gate; the high-level effective enable terminal of the third NOT gate is connected to the second node, and the low-level effective enable terminal of the third NOT gate is connected to the first node; the second terminal of the second transmission gate is connected to the first terminal of the third transmission gate and the input terminal of the fourth NOT gate, the high-level effective enable terminal of the second transmission gate is connected to the second node, and the low-level effective enable terminal of the second transmission gate is connected to the first node; the second terminal of the third transmission gate is connected to the inverting output terminal of the D flip-flop and the output terminal of the second NAND gate, the high-level effective enable terminal of the third transmission gate is connected to the first node, and the low-level effective enable terminal of the third transmission gate is connected to the second node; the output terminal of the fourth NOT gate is connected to the output terminal of the D flip-flop and the first input terminal of the second NAND gate; the second input terminal of the second NAND gate is connected to the enable terminal of the D flip-flop.

[0008] In some embodiments, the logic operation circuit includes: a NOT gate, a NAND gate, a NOR gate, a multiplexer, and a D latch.

[0009] In some embodiments, the logic operation circuit includes three output terminals to output three different driving waveforms.

[0010] In some embodiments, the single-stage gate drive circuit also includes a level conversion circuit, which includes: a fifteenth NOT gate, an N-type first transistor, an N-type second transistor, a P-type third transistor and a P-type fourth transistor; the input end of the level conversion circuit is connected to the input end of the fifteenth NOT gate and the gate of the third transistor; the output end of the fifteenth NOT gate is connected to the gate of the fourth transistor; the source of the third transistor and the source of the third transistor are both connected to the first power supply end; the drain of the third transistor is connected to the reverse output end of the level conversion circuit, the drain of the first transistor, and the gate of the second transistor; the drain of the fourth transistor is connected to the output end of the level conversion circuit, the gate of the first transistor, and the drain of the second transistor; the source of the first transistor and the second transistor are connected to the second power supply end.

[0011] In some embodiments, the level conversion circuit further includes: a fifth transistor and a sixth transistor, the gate, source and drain of the fifth transistor are all connected to the second power supply terminal, the gate, source and drain of the sixth transistor are all connected to the second power supply terminal, the fifth transistor and the first transistor are adjacent to each other in the layout, and the sixth transistor and the second transistor are adjacent to each other in the layout.

[0012] In some embodiments, the drive output circuit includes: at least one Class A drive output circuit; the Class A drive output circuit includes: a sixth NAND gate, a seventh NAND gate, a sixteenth NAND gate, a P-type seventh transistor and an N-type eighth transistor; the input terminal and the enable terminal of the Class A drive output circuit are connected to the input terminal of the sixth NAND gate, the output terminal of the sixth NAND gate is connected to the gate of the seventh transistor, and the source of the seventh transistor is connected to the first power supply terminal; the reverse input terminal and the enable terminal of the Class A drive output circuit are connected to the input terminal of the seventh NAND gate, the output terminal of the seventh NAND gate is connected to the input terminal of the sixteenth NAND gate, the output terminal of the sixteenth NAND gate is connected to the gate of the eighth transistor, and the source of the eighth transistor is connected to the second power supply terminal; the drain of the seventh transistor and the drain of the eighth transistor are connected to the output terminal of the Class A drive output circuit.

[0013] In some embodiments, the class A driver output circuit further includes: a third transmission gate that is normally on, and the output end of the sixth NAND gate is connected to the gate of the seventh transistor via the third transmission gate.

[0014] In some embodiments, the drive output circuit includes: at least one Class B drive output circuit; the Class B drive output circuit includes: at least one N-type transistor, the source of the at least one N-type transistor receives a second power supply voltage, the drain of the at least one N-type transistor is connected to the output end of the Class B drive output circuit, and the gate of the at least one N-type transistor receives a signal after an AND operation is performed between the reverse input end and the enable end of the Class B drive output circuit; at least two P-type transistors, the sources of the at least two P-type transistors are connected to the first power supply end, the drains of the at least two P-type transistors are connected to the output end of the Class B drive output circuit, and the gates of the at least two P-type transistors receive multiple control signals in a one-to-one correspondence, and the multiple control signals are obtained by performing an AND-NOT operation between the input end of the Class B drive output circuit and multiple rising edge adjustment ends.

[0015] In some embodiments, the plurality of control signals are respectively transmitted to the gate of the corresponding P-type transistor via a normally-on transmission gate.

[0016] The present disclosure adopts the following technical solution: a display substrate, comprising: the aforementioned gate drive circuit.

[0017] The present disclosure adopts the following technical solution: a display device includes the aforementioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a layout diagram of a display substrate according to an embodiment of the present disclosure.

[0019] Figure 2 1 is a planar layout diagram of a single-stage gate driving circuit in a display substrate according to an embodiment of the present disclosure.

[0020] Figure 3 4 is a circuit diagram of a single-stage shift register circuit in two adjacent single-stage shift register circuits according to an embodiment of the present disclosure.

[0021] Figure 4 FIG. 4 is a circuit diagram of a portion of a logic operation circuit according to an embodiment of the present disclosure.

[0022] Figure 5 is an exemplary circuit diagram of a pixel circuit according to an embodiment of the present disclosure.

[0023] Figure 6 yes Figure 5 Timing diagram of the pixel circuit shown.

[0024] Figure 7 yes Figure 1 An exemplary schematic diagram showing a cross-sectional view of a substrate is shown.

[0025] Figure 8 yes Figure 2The layout of the single-stage gate drive circuit is shown.

[0026] Figure 9 yes Figure 2 The metal layer layout of the single-stage gate drive circuit is shown.

[0027] Figure 10 It is a partial layout diagram of the display substrate according to an embodiment of the present disclosure.

[0028] Figure 11 This is a partial metal layer layout of a single-stage gate drive circuit in an embodiment of the present disclosure.

[0029] Figure 12 FIG. 4 is a circuit diagram of a single-stage shift register circuit according to an embodiment of the present disclosure.

[0030] Figure 13 4 is a circuit diagram of a D flip-flop according to an embodiment of the present disclosure.

[0031] Figure 14 is a circuit diagram of a logic operation circuit according to an embodiment of the present disclosure.

[0032] Figure 15 4 is a block diagram of a level conversion circuit and a drive output circuit in a single-stage gate drive circuit according to an embodiment of the present disclosure.

[0033] Figure 16 FIG. 4 is a circuit diagram of a level conversion circuit according to an embodiment of the present disclosure.

[0034] Figure 17 2 is a circuit diagram of a first drive output circuit and a second drive output circuit according to an embodiment of the present disclosure.

[0035] Figure 18 FIG. 4 is a circuit diagram of a third drive output circuit according to an embodiment of the present disclosure.

[0036] The attached symbols are: 1, display substrate; AA, display area; GIP, single-stage gate drive circuit; Cell1, single-stage shift register circuit; Cell2, logic operation circuit; Level Shift1, first level conversion circuit; Level Shift2, second level conversion circuit; Level Shift3, third level conversion circuit; Driver1, first drive output circuit; Driver2, second drive output circuit; Driver3, third drive output circuit; D1, D2, D3, D4, D flip-flop; CLK, clock signal; D, input terminal of D flip-flop; Q, output terminal of D flip-flop; QN, inverting output terminal of D flip-flop; CP, clock input terminal of D flip-flop; Driver1_Out, voltage output terminal of the first drive output circuit; Driver2_Out, voltage output terminal of the second drive output circuit; Driver3_Out, voltage output terminal of the third drive output circuit Output terminal; DATA, data line; ELVDD, power supply terminal; GND, ground terminal; VCOM, common electrode; LED, light-emitting diode; T1, T2, T3, T4, transistors; C1, C2, capacitors; PSUB, P-type substrate; NWELL, N well; DNELL, deep N well; PWELL, P well; N+, N-type heavily doped region; P+, P-type heavily doped region; GI, gate insulation layer; G, gate; M1, first metal layer; M2, second metal layer; M3, third metal layer; GIP1 to GIPn, single-stage gate driver circuit; A1 to An, single-row pixel circuit; CKV1, CKV2, CKV3, CK V4, clock signal terminal; GSD_BW, control signal; GSD_FW, control signal; TG1 to TG8, transmission gates; A_Dn, B_Dn, C_Dn, D_Dn, input terminals of the n-th single-stage shift register circuit; A_Dn+1, B_Dn+1, C_Dn+1, D_Dn+1, input terminals of the n+1-th single-stage shift register circuit; A_Qn, B_Qn, C_Qn, D_Qn, output terminals of the n-th single-stage shift register circuit; A_Qn+1, B_Qn+1, C_Qn+1, D_Qn+1, output terminals of the n+1-th single-stage shift register circuit; A_Qn-, B_ Qn-, C_Qn-, D_Qn-, the inverting output terminal of the n-th stage single-stage shift register circuit; Rn, the reset signal terminal; NOT1, the first NOT gate; NOT2, the second NOT gate; NOT3, the third NOT gate; NOT4, the fourth NOT gate; TG9, the first transmission gate; TG10, the second transmission gate; TG11, the third transmission gate; NAND1, the first NAND gate; NAND2, the second NAND gate; CP-, the first node; CP', the second node; NAND3, the third NAND gate; NOT5, the fifth NOT gate; NOR1, the first NOR gate; NOT6, the sixth NOT gate; NOR2, the second NOR gate; NOT7, the seventh NOT gate;MUX2, multiplexer; NOR3, third NOR gate; NOT8, eighth NOT gate; NOR4, fourth NOR gate; NAND4, fourth NAND gate; NOT9 to NOT14, ninth to fourteenth NOT gates; D_latch, D latch; NOR5, fifth NOR gate; NAND5, fifth NAND gate; WSn', WSn', WSn, third gate drive signal; AZn', AZn'', AZn, first gate drive signal; DSn', DSn'', DSn, second gate drive signal; WSn_b'', third reverse gate drive signal; AZn_b'', first reverse gate drive signal; DSn_b' ', second reverse gate drive signal; M1, first transistor; M2, second transistor; M3, third transistor; M4, fourth transistor; M5, fifth transistor; M6, sixth transistor; NOT15, fifteenth NOT gate; VDD, positive power supply terminal; VSS2, negative power supply terminal; NAND6, sixth NAND gate; NAND7, seventh NAND gate; NOT16, sixteenth NOT gate; TG11, third transmission gate; M7, seventh transistor; M8, eighth transistor; NAND8 to NAND12, NAND gates; NOT17, NOT gate; TG12 to TG15, transmission gates; M9 to M12, P-type transistors; M13 to M16, N-type transistors.; DETAILED DESCRIPTION

[0037] The present disclosure will be further described below with reference to the embodiments shown in the accompanying drawings.

[0038] Figure 1 is a layout diagram of a display substrate according to an embodiment of the present disclosure.

[0039] The display substrate is, for example, a silicon-based OLED display substrate. The substrate of the display substrate is not limited to silicon. In other embodiments, the substrate of the display substrate is a semiconductor substrate such as a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, a silicon-germanium substrate, or a gallium arsenide substrate.

[0040] The display area of the display substrate is provided with an array of pixel circuits ( Figure 1 The pixel circuits are fabricated on a semiconductor substrate. Due to the relatively high cost of semiconductor substrates, the size of the light-emitting elements should be as small as possible to increase pixel density (PPI).

[0041] A gate drive circuit is provided outside the display area AA of the display substrate. The gate drive circuit includes a plurality of cascaded single-stage gate drive circuits GIP. Each single-stage gate drive circuit GIP can be used to provide a gate control signal for a row of pixel circuits, for example.

[0042] Figure 2 FIG. 1 is a planar layout diagram of a single-stage gate driving circuit GIP in a display substrate according to an embodiment of the present disclosure. Figure 3 1 is a circuit diagram of a single-stage shift register circuit Cell1 of two adjacent single-stage shift register circuits GIP according to an embodiment of the present disclosure.

[0043] Figure 3 In the illustrated embodiment, a single-stage shift register circuit Cell1 includes four D flip-flops D1, D2, D3, and D4. The cascaded single-stage shift register circuits Cell1 receive the same clock signal. In two adjacent single-stage shift register circuits Cell1, the output Q of the D flip-flop D1 of the previous single-stage shift register circuit Cell1 is connected to the input D of the D flip-flop D1 of the next single-stage shift register circuit Cell1; the output Q of the D flip-flop D2 of the previous single-stage shift register circuit Cell1 is connected to the input D of the D flip-flop D2 of the next single-stage shift register circuit Cell1; the output Q of the D flip-flop D3 of the previous single-stage shift register circuit Cell1 is connected to the input D of the D flip-flop D3 of the next single-stage shift register circuit Cell1; and the output Q of the D flip-flop D4 of the previous single-stage shift register circuit Cell1 is connected to the input D of the D flip-flop D4 of the next single-stage shift register circuit Cell1.

[0044] The waveforms of signals output by the D flip-flops D1, D2, D3, and D4 in the first stage of the cascaded single-stage shift register circuit Cell1 are different, so that the cascaded single-stage shift register circuit Cell can transmit four signal waveforms simultaneously.

[0045] For example, D flip-flops D1, D2, D3, and D4 each transmit a high-level pulse, with their phases delayed by one clock cycle. Then, the single-stage shift register circuit Cell1 is equivalent to transmitting the codes (1, 0, 0, 0), (0, 1, 0, 0), (0, 0, 1, 0), and (0, 0, 0, 1) to the next single-stage shift register circuit. The above example simply indicates that within the same clock cycle, the state output of at least one D flip-flop is different from the state outputs of the other D flip-flops.

[0046] The logic operation circuit Cell2 performs logic operations on the output terminals and / or inverted output terminals of each D-type flip-flop in the single-stage shift register circuit Cell1, thereby obtaining outputs of multiple different waveforms. That is, the logic operation circuit Cell2 maps the aforementioned coding sequence into drive signals of different waveforms.

[0047] In some embodiments, the logic operation circuit Cell2 includes an inverter, a NAND gate, a transmission gate, a NOR gate, a latch, a transmission gate, etc. In some embodiments, the logic operation circuit Cell2 also receives a global control signal as an input signal of some gates or devices.

[0048] Figure 4 FIG. 4 is a circuit diagram of a portion of the circuits in the logic operation circuit Cell2 according to an embodiment of the present disclosure.

[0049] The state output of the D flip-flop D3 is recorded as D3_Q, the state output of the D flip-flop D2 is recorded as D2_Q, the state output of the D flip-flop D4 is recorded as D4_Q, and the global reset signal is recorded as RESET.

[0050] Figure 4 The circuit shown provides a pulse signal to the first level shift circuit Level Shift 1. The logic operation circuit Cell 2 also provides pulse signals to the second level shift circuit Level Shift 2 and the third level shift circuit Level Shift 3. The waveforms of the three pulse signals are different.

[0051] The first, second, and third level shift circuits Level Shift1, Level Shift2, and Level Shift3 can convert the high-level voltage or low-level voltage of the pulse signal. For example, they can convert the low-level voltage from 0V to -3V or -5V. This provides a sufficiently low turn-off voltage for the NMOS transistors in the display area, or a sufficiently low turn-on voltage for the PMOS transistors in the display area.

[0052] The first driver output circuit Driver1, the second driver output circuit Driver2, and the third driver output circuit Driver3 buffer the pulse signals output by the first, second, and third level shift circuits Level Shift1, Level Shift2, and Level Shift3, respectively, and provide three different pulse signals to three gate lines. The three gate lines are connected to the three signal terminals in the pixel circuit.

[0053] Figure 5 is an exemplary circuit diagram of a pixel circuit according to an embodiment of the present disclosure. Figure 6 yes Figure 5 Timing diagram of the pixel circuit shown.

[0054] Figure 5The pixel circuit shown includes four transistors T1, T2, T3, and T4, and two capacitors C1 and C2. A power supply terminal ELVDD provides a high-level power supply voltage for the pixel circuit, a ground terminal GND provides a ground signal, and a common electrode VCOM provides a common voltage. The voltage output terminal Driver1_Out of the first driver output circuit Driver1 is connected to the control electrode of transistor T3; the voltage output terminal Driver2_Out of the second driver output circuit Driver2 is connected to the control electrode of transistor T4; and the voltage output terminal Driver3_Out of the third driver output circuit Driver3 is connected to the control electrode of transistor T1.

[0055] from Figure 6 It can be seen that the logic operation circuit Cell2 maps the state sequence of the single-stage shift register circuit Cell1 into three different waveforms.

[0056] The present disclosure does not limit the specific logic definition of the logic operation circuit, the definition of the state sequence of the single-stage shift register circuit Cell1, and the circuit structure of the pixel circuit. The above is only an explanation of the division of the functional modules of the single-stage shift register circuit.

[0057] In some other embodiments, the logic operation circuit Cell2 receives a negative power supply voltage, so that the level conversion circuit can be omitted.

[0058] In these embodiments, the output terminal of the logic operation circuit is connected to the input terminal of the driving output circuit via an inverter.

[0059] In this embodiment, the single-stage shift register circuit, the logic circuit and the driving output circuit are arranged in a row along a first direction, which is the connection direction between the gate driving circuit and the display area, and the plurality of pixel circuits are located in the display area.

[0060] Figure 7 yes Figure 1 An exemplary schematic diagram showing a cross-sectional view of a substrate is shown.

[0061] A deep N-well DNWELL is formed in the P-type substrate PSUB. A P-well PWELL (for forming an NMOS transistor) is then formed within the deep N-well DNWELL. An N-well (for forming a PMOS transistor) is then formed within the deep N-well DNWELL. The first, second, and third level shift circuits (Level Shift1, Level Shift2, Level Shift3), the first, second, and third driver output circuits (Driver1, Driver2, Driver3), and the pixel circuits within display area AA all operate at negative voltages. To improve process consistency, these circuits are fabricated within the same deep N-well DNWELL. Furthermore, the deep N-well DNWELL region housing these circuits can be considered a redundant (dummy) region within display area AA, significantly improving process consistency for the pixel circuits within display area AA.

[0062] Since the single-stage shift register circuit Cell1 and the logic operation circuit Cell2 do not require a negative operating voltage, these circuits do not need to be arranged in a deep N-well.

[0063] Figure 9 Schematically shows a planar NMOS transistor and a planar PMOS transistor located outside the deep N well DNWELL, and also shows a planar NMOS transistor and a planar PMOS transistor located inside the deep N well DNWELL.

[0064] The NMOS transistor is located in the P-well PWELL. Its source and drain regions are heavily N-type doped regions (N+). A gate insulating layer (GI) covers the source and drain regions, as well as the channel region between them. The gate G is located on the gate insulating layer (GI). A heavily P-type doped region (P+) is located on the top surface of the P-well PWELL for connection to the substrate electrode (not shown).

[0065] The PMOS transistor is located in the N-well NWELL. Its source and drain regions are heavily P-type doped regions (P+). A gate insulator (GI) covers the source and drain regions, as well as the channel region between them. The gate (G) is located on the gate insulator (GI). A heavily N-type doped region (N+) is located on the top surface of the N-well NWELL for connection to a substrate electrode (not shown).

[0066] Reference again Figure 2The first level shifter circuit Level Shift1 and the first driver output circuit Driver1 have the same low-level operating voltage, for example, -3V. These two circuits are placed together in the layout design. The second and third level shifters Level Shift2 and Level Shift3, as well as the second and third driver output circuits Driver2 and Driver3, have the same low-level operating voltage, for example, -5V. These two circuits are placed together in the layout design.

[0067] The first driving output circuit Driver1 is closer to the display area AA than the first level shift circuit Level Shift1. The second and third driving output circuits Driver2 and Driver3 are closer to the display area AA than the second and third level shift circuits Level Shift2 and Level Shift3.

[0068] The driving output circuit is closer to the display area AA, which can shorten the wiring length from the driving output circuit to the display area AA and improve the driving capability of the driving output circuit.

[0069] Figure 8 yes Figure 2 The layout of the single-stage gate drive circuit is shown.

[0070] The first direction is the connection direction between the single-stage gate driving circuit and the display area AA, and the second direction is the arrangement direction of the single-stage gate driving circuit. In this example, the first direction is perpendicular to the second direction.

[0071] Figure 8 Figure 2 shows two adjacent single-stage gate drive circuits GIP. All PMOS transistors in the single-stage gate drive circuit GIP are arranged in a row along a first direction. All NMOS transistors in the single-stage gate drive circuit GIP are arranged in a row along the first direction. The gates G of each NMOS transistor and each PMOS transistor extend along a second direction.

[0072] The substrate electrodes of all PMOS transistors in the single-stage gate drive circuit GIP are arranged in a row along the first direction and connected as a whole. The substrate electrodes of all NMOS transistors in the single-stage gate drive circuit GIP are arranged in a row along the first direction and connected as a whole. The two rows of transistors facing each other in two adjacent single-stage gate driving circuits have the same polarity and share a substrate electrode.

[0073] Such a design can shorten the size of the single-stage gate driving circuit GIP along the second direction and reduce the area of the single-stage gate driving circuit GIP.

[0074] In the embodiments of the present disclosure, continue to refer to Figure 8The size of the substrate electrode near the active area (source area, drain area, and the channel area between them) in the first direction is equal to the size of the active area in the first direction. This design can improve process uniformity.

[0075] Figure 9 yes Figure 2 The metal layer layout of the single-stage gate drive circuit is shown.

[0076] The single-stage gate driver circuit (GIP) circuit includes three layers of metal wiring: the first metal layer M1, the second metal layer M2, and the third metal layer M3, in the direction away from the substrate. Most of the wiring in the first metal layer M1 is used for interconnection between transistors, most of the wiring in the second metal layer M2 is used for interconnection between circuit modules (for example, the single-stage shift register circuit Cell1 and the logic operation circuit Cell2), and most of the wiring in the third metal layer M3 is used for interconnection between single-stage gate driver circuit GIP circuits.

[0077] Thanks to the arrangement of transistors in the single-stage gate driver circuit (GIP), only three metal layers are required for the gate driver circuit, which requires fewer wiring layers.

[0078] Thanks to the arrangement of transistors in the single-stage gate driver circuit (GIP), most of the wiring in the second metal layer M2 extends along the first direction, while most of the wiring in the second metal layer extends along the second direction. This reduces the overlap between different metal layers and reduces parasitic capacitance on the metal layers.

[0079] Figure 10 It is a partial layout diagram of the display substrate according to an embodiment of the present disclosure.

[0080] The single-stage gate driving circuits GIP1 , GIP2 , . . . GIPn are arranged along the second direction, and the single-stage gate driving circuits GIP1 , GIP2 , . . . GIPn drive the single-row pixel circuits A1 , A2 , . . . An in a one-to-one correspondence.

[0081] The size of a pair of MOS transistors in the single-stage gate driver circuits GIP1, GIP2, ..., GIPn along the second direction is 5.868 μm. Accordingly, the center-to-center distance of the pixel circuits in the display area AA along the second direction should be greater than or equal to 5.868 μm. This display substrate is suitable for display products with a 4K resolution.

[0082] Figure 11 This is a partial metal layer layout of a single-stage gate drive circuit in an embodiment of the present disclosure.

[0083] Voltage drop is significant in DC signals with long signal lines. The driver output circuit is the main circuit module that consumes power, and the DC power signal lines connected to it, such as the power lines VDD and VSS1, need to have a large driving capability. Figure 11 In the second direction, DC power signal lines VDD and VSS1 are arranged in the second metal layer M3. The width of these DC power signal lines VDD and VSS1 (the dimension in the first direction) is greater than 10 μm, which can reduce the line resistance to below 100 Ω (with little impact on circuit performance). The sheet resistance of the DC power signal lines VDD and VSS1 is sufficiently low, thereby reducing the impact of voltage drops on the DC power signal lines VDD and VSS1 on the entire column gate drive circuit. This layout design helps to improve the voltage drop on the DC power signal lines VDD and VSS1.

[0084] In one embodiment of the present disclosure, a single-stage gate-base driving circuit has a size of approximately 400 um in the first direction and 6.543 um in the second direction, and can be used for narrow-frame products as well as products with a pixel pitch greater than or equal to 6.543 um.

[0085] Figure 12 FIG. 4 is a circuit diagram of a single-stage shift register circuit according to an embodiment of the present disclosure.

[0086] In this embodiment, a single-stage shift register circuit includes: a plurality of D flip-flops numbered in sequence, and two transmission gates correspondingly connected to each D flip-flop; the input end of the D flip-flop is connected to the output end of the correspondingly numbered D flip-flop in the next single-stage shift register circuit through a transmission gate, and the output end of the D flip-flop is connected to the input end of the correspondingly numbered D flip-flop in the next single-stage shift register circuit through another transmission gate.

[0087] Specifically, refer to Figure 12 The n-th single-stage shift register circuit includes: a plurality of D flip-flops D1, D2, D3 and D4 numbered in sequence and transmission gates TG1 to TG8.

[0088] The input terminal C_Dn of the D flip-flop D3 is connected to the output terminal C_Qn+1 of the corresponding numbered D flip-flop in the next single-stage shift register circuit through a transmission gate TG1, and the output terminal C_Qn of the D flip-flop D3 is connected to the input terminal C_Dn+1 of the corresponding numbered D flip-flop in the next single-stage shift register circuit through another transmission gate TG2.

[0089] The input terminal B_Dn of the D flip-flop D2 is connected to the output terminal B_Qn+1 of the corresponding numbered D flip-flop in the next single-stage shift register circuit through a transmission gate TG3, and the output terminal B_Qn of the D flip-flop D2 is connected to the input terminal B_Dn+1 of the corresponding numbered D flip-flop in the next single-stage shift register circuit through another transmission gate TG4.

[0090] The input terminal A_Dn of the D flip-flop D1 is connected to the output terminal A_Qn+1 of the corresponding numbered D flip-flop in the next single-stage shift register circuit through a transmission gate TG5, and the output terminal A_Qn of the D flip-flop D1 is connected to the input terminal A_Dn+1 of the corresponding numbered D flip-flop in the next single-stage shift register circuit through another transmission gate TG6.

[0091] The input terminal D_Dn of the D flip-flop D4 is connected to the output terminal D_Qn+1 of the corresponding numbered D flip-flop in the next single-stage shift register circuit through a transmission gate TG7, and the output terminal D_Qn of the D flip-flop D4 is connected to the input terminal D_Dn+1 of the corresponding numbered D flip-flop in the next single-stage shift register circuit through another transmission gate TG8.

[0092] The output terminals and inverted output terminals of the D flip-flops D1, D2, D3, and D4 are logically operated in a logic operation circuit to obtain a variety of different signal waveforms.

[0093] The reset signal terminal RN of each of the D flip-flops D1 , D2 , D3 and D4 receives a global control signal LF_pulse1 .

[0094] The control terminal of each transmission gate receives global control signals: a control signal GSD_BW and a control signal GSD_FW.

[0095] Figure 13 4 is a circuit diagram of a D flip-flop according to an embodiment of the present disclosure.

[0096] The D flip-flop includes: a first NOT gate NOT1, a second NOT gate NOT2, a third NOT gate NOT3, a fourth NOT gate NOT4, a first NAND gate NAND1, a second NAND gate NAND2, a first transmission gate TG9, a second transmission gate TG10 and a third transmission gate TG11; The clock signal terminal CP of the D flip-flop is connected to the input terminal of the first NOT gate NOT1, and the output terminal of the first NOT gate NOT1 is connected to the first node CP-; An input end of the second NOT gate NOT2 is connected to the first node CP-, and an output end of the second NOT gate NOT2 is connected to the second node CP'; A first end of the first transmission gate TG9 is connected to an input end D of the D flip-flop, a second end of the first transmission gate TG9 is connected to a first input end of the first NAND gate NAND1 and an output end of the third NOT gate NOT3, a high-level active enable end of the first transmission gate TG9 is connected to a first node CP-, and a low-level active enable end of the first transmission gate TG9 is connected to a second node CP'; The second input terminal of the first NAND gate NAND1 is connected to the enable terminal RN of the D flip-flop, and the output terminal of the first NAND gate NAND1 is connected to the input terminal of the third NOT gate NOT3 and the first terminal of the second transmission gate TG10; The high level effective enable terminal of the third NOT gate NOT3 is connected to the second node CP', and the low level effective enable terminal of the third NOT gate NOT3 is connected to the first node CP-; A second end of the second transmission gate TG10 is connected to a first end of the third transmission gate TG11 and an input end of the fourth NOT gate NOT4, a high-level active enable end of the second transmission gate TG10 is connected to a second node CP′, and a low-level active enable end of the second transmission gate TG10 is connected to a first node CP−; A second end of the third transmission gate TG11 is connected to the inverting output end Q- of the D flip-flop and the output end of the second NAND gate NAND2, a high-level active enable end of the third transmission gate TG11 is connected to the first node CP-, and a low-level active enable end of the third transmission gate TG11 is connected to the second node CP'; An output terminal of the fourth NOT gate NOT4 is connected to an output terminal Q of the D flip-flop and a first input terminal of the second NAND gate NAND2; A second input terminal of the second NAND gate NAND2 is connected to the enable terminal RN of the D flip-flop.

[0097] Figure 14 is a circuit diagram of a logic operation circuit according to an embodiment of the present disclosure.

[0098] The output terminal B_Qn of the D flip-flop D2 and the output terminal C_Qn of the D flip-flop D3 are connected to the two input terminals of the third NAND gate NAN3. The output terminal of the third NAND gate NAN3 is connected to the output terminal of the fifth NOT gate NOT5. The output terminal of the fifth NOT gate NOT5 and the inverting output terminal A_Qn of the D flip-flop D1 are connected to the two output terminals of the first NOR gate NOR1. The output terminal of the first NOR gate NOR1 is connected to the input terminal of the sixth NOT gate NOT6. The output terminal of the sixth NOT gate NOT6 and the clock signal terminal CKV4 are connected to the two input terminals of the second NOR gate NOR2. The output terminal of the second NOR gate NOR2 is connected to the input terminal of the seventh NOT gate NOT7. The output terminal of the seventh NOT gate NOT7 and the output terminal A_Qn of the first D flip-flop D1 are connected to the two input terminals A and B of the multiplexer MUX2. The output terminal of the multiplexer MUX2 outputs the third gate drive signal WSn' to the third level shifter circuit LevelShift3.

[0099] The second global control signal LF_pulse2 is inverted by the eighth NOT gate NOT8 and inputted into the third NOR gate NOR3 together with the first global control signal LF_pulse1. The third NOR gate NOR3 is connected to the enable terminal C of the multiplexer MUX2.

[0100] The three input terminals of the fourth NOR gate NOR4 are respectively connected to the output terminal B_Qn of the D flip-flop D2, the output terminal C_Qn of the D flip-flop D3, and the output terminal D_Qn of the D flip-flop D4. The two input terminals of the fourth NAND gate NAN4 are respectively connected to the output terminal of the fourth NOR gate NOR4 and the global control signal LF_pulse2. The output terminal of the fourth NAND gate NAND4 is connected to the first level shift circuit Level Shift1 to provide the first gate drive signal DSn' to the first level shift circuit Level Shift1.

[0101] The third gate drive signal is buffered by the sequentially connected ninth NOT gate NOT9, tenth NOT gate NOT10, eleventh NOT gate NOT11, twelfth NOT gate NOT12, thirteenth NOT gate NOT13, and fourteenth NOT gate NOT17 before being connected to the enable terminal EN of the D latch D_latch. The input terminal D of the D latch D_latch is connected to the output terminal B_Qn of the D flip-flop D2. The output terminal Q of the D latch D_latch and the inverting output terminal D_Qn- of the D flip-flop D4 are respectively connected to the two input terminals of a fifth NOR gate NOR5. The output terminal of the fifth NOR gate NOR5 and the global control signal LF_pulse2 are respectively connected to the two input terminals of a fifth NAND gate NAND5. The output terminal of the fifth NAND gate NAND5 is connected to the second level shift circuit Level Shift2 to provide the second gate drive signal DSn' to the second level shift circuit Level Shift2.

[0102] Figure 15 4 is a block diagram of a level conversion circuit and a drive output circuit in a single-stage gate drive circuit according to an embodiment of the present disclosure.

[0103] The third level shift circuit Level Shift3 converts the low-level voltage of the third gate drive signal WSn' from 0V to a negative voltage, keeps the high-level voltage of the third gate drive signal WSn' unchanged, obtains the third gate drive signal WSn", and simultaneously outputs the third reverse gate drive signal WSn_b''. The high-level period of the third reverse gate drive signal WSn_b'' corresponds to the low-level period of the third gate drive signal WSn'', and the low-level period of the third reverse gate drive signal WSn_b'' corresponds to the high-level period of the third gate drive signal WSn''. The low-level voltage of the third reverse gate drive signal WSn_b'' is equal to the low-level voltage of the third reverse gate drive signal WSn''. The high-level voltage of the third reverse gate drive signal WSn_b'' is equal to the high-level voltage of the third reverse gate drive signal WSn''.

[0104] The first level conversion circuit Level Shift3 converts the low-level voltage of the first gate drive signal AZn' from 0V to a negative voltage, keeps the high-level voltage of the first gate drive signal AZn' unchanged, obtains the first gate drive signal AZn", and simultaneously outputs the first reverse gate drive signal AZn_b''. The high-level period of the first reverse gate drive signal AZn_b'' corresponds to the low-level period of the first gate drive signal AZn'', and the low-level period of the first reverse gate drive signal AZn_b'' corresponds to the high-level period of the first gate drive signal AZn''. The low-level voltage of the first reverse gate drive signal AZn_b'' is equal to the low-level voltage of the first reverse gate drive signal AZn''. The high-level voltage of the first reverse gate drive signal AZn_b'' is equal to the high-level voltage of the first reverse gate drive signal AZn''.

[0105] The second level shift circuit Level Shift3 converts the low-level voltage of the second gate drive signal DSn' from 0V to a negative voltage, keeps the high-level voltage of the second gate drive signal DSn' unchanged, obtains the second gate drive signal DSn", and simultaneously outputs the second reverse gate drive signal DSn_b''. The high-level period of the second reverse gate drive signal DSn_b'' corresponds to the low-level period of the second gate drive signal DSn'', and the low-level period of the second reverse gate drive signal DSn_b'' corresponds to the high-level period of the second gate drive signal DSn''. The low-level voltage of the second reverse gate drive signal DSn_b'' is equal to the low-level voltage of the second reverse gate drive signal DSn''. The high-level voltage of the second reverse gate drive signal DSn_b'' is equal to the high-level voltage of the second reverse gate drive signal DSn''.

[0106] Figure 16 FIG. 4 is a circuit diagram of a level conversion circuit according to an embodiment of the present disclosure.

[0107] The level conversion circuit includes: a fifteenth NOT gate NOT15, an N-type first transistor M1, an N-type second transistor M2, a P-type third transistor M3 and a P-type fourth transistor M4; The input terminal in of the level conversion circuit is connected to the input terminal of the fifteenth NOT gate NOT15 and the gate of the third transistor M3; An output end of the fifteenth NOT gate NOT15 is connected to the gate of the fourth transistor M4; The source of the third transistor M3 and the source of the third transistor M3 are both connected to the positive power supply terminal VDD; The drain of the third transistor M3 is connected to the inverting output terminal out_b of the level conversion circuit, the drain of the first transistor M1, and the gate of the second transistor M2; The drain of the fourth transistor M4 is connected to the output terminal out of the level conversion circuit, the gate of the first transistor M1, and the drain of the second transistor M2; Sources of the first transistor M1 and the second transistor M2 are connected to the negative power supply terminal VSS2 .

[0108] In some embodiments, the level conversion circuit further includes: a fifth transistor M5 and a sixth transistor M6, the gate, source, and drain of the fifth transistor M5 are all connected to the negative power supply terminal, the gate, source, and drain of the sixth transistor M6 are all connected to the negative power supply terminal, the fifth transistor M5 and the first transistor M1 are adjacent to each other in the layout, and the sixth transistor M6 and the second transistor M2 are adjacent to each other in the layout.

[0109] The fifth transistor and the sixth transistor are dummy transistors to improve process uniformity and consistency of the first transistor M1 and the second transistor M2 .

[0110] The negative power supply voltage connected to the second level shift circuit Level shift2 and the second driver output circuit Driver2 is -5V, and the negative power supply voltage connected to the first and third level shift circuits Level shift1, 3 and the first and third driver output circuits Driver1, 3 is -3V.

[0111] Figure 17 1 is a circuit diagram of a first drive output circuit and a second drive output circuit according to an embodiment of the present disclosure. The first drive output circuit and the second drive output circuit are Class A drive output circuits.

[0112] The Class A driving output circuit includes: a sixth NAND gate NAND6, a seventh NAND gate NAND7, a sixteenth NOT gate, a P-type seventh transistor M7, and an N-type eighth transistor M8; The input terminal in and the enable terminal EN of the class A drive output circuit are connected to the input terminal of the sixth NAND gate NAND6, the output terminal of the sixth NAND gate NAND6 is connected to the gate of the seventh transistor M7, and the source of the seventh transistor M7 is connected to the positive power supply terminal VDD; The inverting input terminal in_b and the enable terminal of the class A driver output circuit are connected to the input terminal of the seventh NAND gate NAND7, the output terminal of the seventh NAND gate NAND7 is connected to the input terminal of the sixteenth NOT gate, the output terminal of the sixteenth NOT gate is connected to the gate of the eighth transistor M8, and the source of the eighth transistor M8 is connected to the negative power supply terminal VSS; The drain of the seventh transistor M7 and the drain of the eighth transistor M8 are connected to the output end of the class A driving output circuit.

[0113] Optionally, the Class A driver output circuit further includes a normally-on third transmission gate TG11, through which the output of the sixth NAND gate NAND6 is connected to the gate of the seventh transistor M7. The third transmission gate TG11 functions as a protection circuit. The third transmission gate TG11 has an active-high enable terminal connected to a positive power supply voltage, and an active-low enable terminal connected to a negative power supply voltage.

[0114] Figure 18 FIG3 is a circuit diagram of a third drive output circuit according to an embodiment of the present disclosure. The third drive output circuit is a Class B drive output circuit.

[0115] Class B driver output circuit includes: At least one N-type transistor M13-M16, wherein the source of the at least one N-type transistor M13-M16 receives a negative power supply voltage VSS1, the drain of the at least one N-type transistor M13-M16 is connected to the output terminal out of the class-B driver output circuit, and the gate of the at least one N-type transistor M13-M16 receives a signal obtained by performing an AND operation between the inverting input terminal in_b of the class-B driver output circuit and the enable terminal EN (the operation is performed via a NAND gate NAND12 and a NOT gate NOT17); At least two P-type transistors M9 to M12, the sources of the at least two P-type transistors M9 to M12 are connected to the positive power supply terminal VDD, the drains of the at least two P-type transistors M9 to M12 are connected to the output terminal out of the class-B driver output circuit, and the gates of the at least two P-type transistors M9 to M12 receive multiple control signals in a one-to-one correspondence. The multiple control signals are obtained by performing a NOT AND operation on the input terminal in of the class-B driver output circuit and the multiple rising edge adjustment terminals trc1 to tr4.

[0116] The multiple rising edge adjustment terminals trc1 to tr4 are used to adjust the rising edge slope of the output waveform of the class B driver output circuit. The more ports among the multiple rising edge adjustment terminals trc1 to tr4 that provide high-level voltages, the steeper the rising edge of the output waveform of the class B driver output circuit.

[0117] Optionally, the plurality of control signals are transmitted to the gate of the corresponding P-type transistor via a normally-on transmission gate TG12 to TG15 , respectively. The transmission gate plays a protective role.

[0118] An embodiment of the present disclosure further provides a display substrate, comprising: the aforementioned gate driving circuit.

[0119] An embodiment of the present disclosure further provides a display device, comprising the aforementioned display substrate.

[0120] The display device is, for example, a display module, a mobile phone, a head-mounted display device, or any other product or component with a display function.

[0121] The various embodiments in the present disclosure are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0122] The scope of protection of the present disclosure is not limited to the above-described embodiments. Obviously, those skilled in the art may make various modifications and variations to the present disclosure without departing from the scope and spirit of the present disclosure. If such modifications and variations fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such modifications and variations.

Claims

1. A gate drive circuit comprising a cascaded single-stage gate drive circuit, characterized in that: The single-stage gate drive circuit includes: a single-stage shift register circuit, a logic operation circuit and a drive output circuit; The single-stage shift register circuit is used to transfer the coding sequence to the single-stage shift register circuit in the next-stage single-stage gate drive circuit; The logic operation circuit is used to map the coding sequence into multiple driving signal waveforms; The driving output circuit is used for driving a plurality of gate lines in a one-to-one correspondence according to the plurality of driving signal waveforms.

2. The gate drive circuit according to claim 1, wherein: The single-stage shift register circuit includes: a plurality of D flip-flops numbered in sequence, and two transmission gates correspondingly connected to each D flip-flop; The input end of the D flip-flop is connected to the output end of the D flip-flop with the corresponding number in the next single-stage shift register circuit through a transmission gate, and the output end of the D flip-flop is connected to the input end of the D flip-flop with the corresponding number in the next single-stage shift register circuit through another transmission gate.

3. The gate drive circuit according to claim 2, wherein: The D flip-flop includes: a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a first NAND gate, a second NAND gate, a first transmission gate, a second transmission gate and a third transmission gate; The clock signal terminal of the D flip-flop is connected to the input terminal of the first NOT gate, and the output terminal of the first NOT gate is connected to the first node; An input terminal of the second NOT gate is connected to the first node, and an output terminal of the second NOT gate is connected to the second node; A first end of the first transmission gate is connected to an input end of the D flip-flop, a second end of the first transmission gate is connected to a first input end of the first NAND gate and an output end of the third NOT gate, a high-level active enable end of the first transmission gate is connected to the first node, and a low-level active enable end of the first transmission gate is connected to the second node; The second input terminal of the first NAND gate is connected to the enable terminal of the D flip-flop, and the output terminal of the first NAND gate is connected to the input terminal of the third NOT gate and the first terminal of the second transmission gate; The active high enable terminal of the third NOT gate is connected to the second node, and the active low enable terminal of the third NOT gate is connected to the first node; The second end of the second transmission gate is connected to the first end of the third transmission gate and the input end of the fourth NOT gate, the high-level active enable end of the second transmission gate is connected to the second node, and the low-level active enable end of the second transmission gate is connected to the first node; A second end of the third transmission gate is connected to the inverting output end of the D flip-flop and the output end of the second NAND gate, a high-level active enable end of the third transmission gate is connected to the first node, and a low-level active enable end of the third transmission gate is connected to the second node; The output end of the fourth NOT gate is connected to the output end of the D flip-flop and the first input end of the second NAND gate; The second input terminal of the second NAND gate is connected to the enable terminal of the D flip-flop.

4. The gate drive circuit according to claim 1, wherein: The logic operation circuit includes: a NOT gate, a NAND gate, a NOR gate, a multiplexer and a D latch.

5. The gate driving circuit according to claim 1, wherein: The logic operation circuit includes three output terminals to output three different driving waveforms.

6. The gate drive circuit according to claim 1, wherein: The single-stage gate drive circuit further includes: a level conversion circuit, the level conversion circuit including: a fifteenth NOT gate, an N-type first transistor, an N-type second transistor, a P-type third transistor, and a P-type fourth transistor; An input end of the level conversion circuit is connected to an input end of the fifteenth NOT gate and a gate of the third transistor; An output terminal of the fifteenth NOT gate is connected to the gate of the fourth transistor; The source of the third transistor and the source of the third transistor are both connected to the first power supply terminal; The drain of the third transistor is connected to the reverse output terminal of the level conversion circuit, the drain of the first transistor, and the gate of the second transistor; The drain of the fourth transistor is connected to the output end of the level conversion circuit, the gate of the first transistor, and the drain of the second transistor; Sources of the first transistor and the second transistor are connected to a second power supply terminal.

7. The gate drive circuit according to claim 6, wherein: The level conversion circuit also includes: a fifth transistor and a sixth transistor, the gate, source and drain of the fifth transistor are all connected to the second power supply end, the gate, source and drain of the sixth transistor are all connected to the second power supply end, the fifth transistor and the first transistor are adjacent to each other in the layout, and the sixth transistor and the second transistor are adjacent to each other in the layout.

8. The gate driving circuit according to claim 1, wherein: The drive output circuit includes: at least one Class A drive output circuit; the Class A drive output circuit includes: a sixth NAND gate, a seventh NAND gate, a sixteenth NOT gate, a P-type seventh transistor and an N-type eighth transistor; The input terminal and the enable terminal of the Class A drive output circuit are connected to the input terminal of the sixth NAND gate, the output terminal of the sixth NAND gate is connected to the gate of the seventh transistor, and the source of the seventh transistor is connected to the first power supply terminal; The inverting input terminal and the enable terminal of the Class A drive output circuit are connected to the input terminal of the seventh NAND gate, the output terminal of the seventh NAND gate is connected to the input terminal of the sixteenth NAND gate, the output terminal of the sixteenth NAND gate is connected to the gate of the eighth transistor, and the source of the eighth transistor is connected to the second power supply terminal; The drain of the seventh transistor and the drain of the eighth transistor are connected to the output end of the class A driving output circuit.

9. The gate driving circuit according to claim 8, wherein: The class A drive output circuit further includes: a third transmission gate that is normally on, and the output end of the sixth NAND gate is connected to the gate of the seventh transistor via the third transmission gate.

10. The gate driving circuit according to claim 1, wherein: The drive output circuit includes: at least one Class B drive output circuit; the Class B drive output circuit includes: At least one N-type transistor, wherein a source of the at least one N-type transistor receives a second power supply voltage, a drain of the at least one N-type transistor is connected to an output terminal of the Class-B driver output circuit, and a gate of the at least one N-type transistor receives a signal obtained by performing an AND operation between an inverting input terminal and an enable terminal of the Class-B driver output circuit; At least two P-type transistors, the sources of the at least two P-type transistors are both connected to the first power supply terminal, the drains of the at least two P-type transistors are both connected to the output terminal of the Class-B driver output circuit, and the gates of the at least two P-type transistors receive multiple control signals in a one-to-one correspondence. The multiple control signals are obtained by performing a NOT operation on the input terminal of the Class-B driver output circuit and multiple rising edge adjustment terminals.

11. The gate driving circuit according to claim 10, wherein: The plurality of control signals are respectively transmitted to the gate of the corresponding P-type transistor via a normally-on transmission gate.

12. A display substrate, characterized in that: include: The gate drive circuit according to any one of claims 1 to 11.

13. A display device, characterized in that: The display substrate according to claim 12 is included.

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