Display device and driving method thereof

Abstract

The invention provides a display device and a driving method thereof, and a level shifter in the display device comprises at least one first signal line for transmitting at least one first clock signal, and at least one corresponding second signal line. A power consumption reduction module in the display device is at least used for generating a voltage signal (the amplitude of the voltage signal is between the minimum amplitude and the maximum amplitude of a first clock signal), and a second signal line forms a current path with a corresponding first signal line and the power consumption reduction module through a switch module in a time-sharing manner. The gate driver is used for generating a plurality of gate signals according to at least one second clock signal transmitted by at least one second signal line, and the gate driver is used for generating a plurality of gate signals according to at least one second clock signal transmitted by at least one second signal line, wherein a current path is formed between the gate driver and the power consumption reduction module in at least one time period in a rising edge of a first clock signal and at least one time period in a falling edge; the power consumption of the level converter and the power consumption of the driver comprising the level converter are reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display device and a driving method thereof. Background Art

[0002] Currently, reducing power consumption has become an essential step for display devices to achieve sustainable development.

[0003] Among them, the display panel in the display device is driven by the driver chip to display the picture. For the driver chip, the power consumption when charging and discharging the pixels in the display panel is relatively large. How to reduce the power consumption of the driver chip in this process becomes a particularly important issue in reducing the overall power consumption of the display device. Summary of the Invention

[0004] An object of the present invention is to provide a display device and a driving method thereof, so as to solve the problem of high power consumption when the existing driving chip charges and discharges pixels in the display panel.

[0005] An embodiment of the present invention provides a display device, including:

[0006] multiple sub-pixels;

[0007] A gate driver, configured to generate a plurality of gate signals, wherein the gate signals are configured to control the corresponding plurality of sub-pixels to turn on;

[0008] a level converter, comprising at least one first signal line, at least one corresponding second signal line, and a switch module connected between the at least one first signal line and the at least one second signal line, the level converter being configured to generate at least one first clock signal transmitted via the at least one first signal line;

[0009] a power consumption reduction module, configured to generate a voltage signal having an amplitude greater than a minimum amplitude of the first clock signal and less than a maximum amplitude of the first clock signal;

[0010] The second signal line forms a current path with the corresponding first signal line and with the power reduction module in a time-sharing manner through the switch module, and the second signal line forms a current path with the power reduction module during at least one period of the rising edge of the first clock signal and during at least one period of the falling edge of the first clock signal through the switch module;

[0011] The gate driver is configured to generate a plurality of the gate signals according to at least one second clock signal transmitted by at least one second signal line.

[0012] An embodiment of the present invention further provides a method for driving a display device, the display device comprising a plurality of sub-pixels, a gate driver, a level converter, and a power reduction module, the level converter comprising at least one first signal line, at least one corresponding second signal line, and a switch module connected between the at least one first signal line and the at least one second signal line;

[0013] The driving method of the display device includes:

[0014] controlling the level converter to generate at least one first clock signal transmitted through at least one first signal line;

[0015] Controlling, by the switch module, the second signal line to form a current path with the power reduction module during at least one period of a rising edge of the first clock signal and during at least one period of a falling edge of the first clock signal, so that a voltage signal generated by the power reduction module is transmitted to the second signal line, and an amplitude of the voltage signal is greater than a minimum amplitude of the first clock signal and less than a maximum amplitude of the first clock signal;

[0016] controlling the second signal line by the switch module to form a current path with the corresponding first signal line when no current path is formed between the second signal line and the power consumption reduction module, so that the first clock signal is transmitted to the corresponding second signal line;

[0017] The gate driver is controlled to generate a plurality of gate signals according to at least one second clock signal transmitted by at least one second signal line, wherein the gate signals are used to control the corresponding plurality of sub-pixels to turn on.

[0018] The present invention provides a display device and a driving method thereof. A level converter in the display device includes at least one first signal line, at least one corresponding second signal line (the at least one second clock signal output by the second signal line is used to generate multiple gate signals), and a switch module connected between the at least one first signal line and the at least one second signal line. The level converter is used to generate at least one first clock signal transmitted through the at least one first signal line. By providing a power reduction module for at least generating a voltage signal (whose amplitude is between the minimum amplitude and the maximum amplitude of the first clock signal), and forming a current path between the second signal line and the corresponding first signal line and the power reduction module through the switch module in a time-sharing manner, the second signal line forms a current path between the power reduction module and the corresponding first signal line through the switch module during at least one period of the rising edge and at least one period of the falling edge of the first clock signal, the duration that the first signal line drives its corresponding load is reduced, thereby reducing the power consumption of the level converter and the power consumption of the driver including the level converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 and Figure 2 This is a diagram illustrating the architecture of a display device provided by an embodiment of the present invention.

[0020] Figure 3 and Figure 4 A timing diagram of multiple first clock signals and a timing diagram of multiple second clock signals provided by an embodiment of the present invention.

[0021] Figure 5 and Figure 6 These are two connection states of the second signal line corresponding to when the power consumption reduction module includes a capacitor.

[0022] Figure 7 and Figure 8 The power consumption reduction module includes two connection states of the corresponding second signal line when the first voltage line is used.

[0023] Figures 9 to 11 The power consumption reduction module includes three connection states of the second signal line corresponding to the first voltage line and the second voltage line.

[0024] Figure 12 and Figure 13 A circuit diagram and corresponding timing diagram of a demultiplexing circuit provided in an embodiment of the present invention.

[0025] Figure 14 、 Figure 15 This is an equivalent circuit diagram and corresponding timing diagram of the level converter, power consumption reduction module and panel body provided by the embodiment of the present invention.

[0026] Figure 16 The present invention provides a flowchart of a method for driving a display device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0028] In the description of the present invention, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise clearly and specifically defined, and "electrically connected" means that the two are connected by conductive material, without limiting whether a current path is formed between the two.

[0029] In addition, it should be noted that the drawings only provide structures and steps that are closely related to the present invention, and some details that are not closely related to the invention are omitted. The purpose is to simplify the drawings and make the invention clear at a glance, rather than to indicate that the actual device is exactly the same as the attached drawings. Figure 1 The same is not a limitation of the actual device.

[0030] Embodiments of the present invention provide a display device, which may include but is not limited to the following embodiments and combinations of the following embodiments.

[0031] In some embodiments, combined Figures 1 to 4As shown, the display device 100 includes: a plurality of sub-pixels P; a gate driver 201 for generating a plurality of gate signals gate, wherein the gate signals gate are used to control the corresponding plurality of sub-pixels P to be turned on; a level converter 202, including at least one first signal line (for example, including 8 first signal lines CLKOUT1 to CLKOUT8), corresponding at least one second signal line (for example, including 8 second signal lines CLK1 to CLK8), and a switch module 2021 connected between the at least one first signal line and the at least one second signal line, wherein the level converter 202 is used to generate at least one first clock signal (for example, including 8 first clock signals clkout1 to clkout8) transmitted through the at least one first signal line; a power reduction module 203, at least for generating a voltage signal avdd, wherein the amplitude a of the voltage signal avdd is greater than the minimum amplitude a of each of the first clock signals (clkout1 to clkout8). value a1 and is less than the maximum amplitude a2 of the first clock signal; wherein, the second signal line (each of CLK1 to CLK8) forms a current path with the corresponding first signal line (the corresponding one of CLKOUT1 to CLKOUT8) through the switching module 2021 in a time-sharing manner, and forms a current path with the power reduction module 203; the second signal line forms a current path with the power reduction module 203 through the switching module 2021 within at least one time period t1 of the rising edge of the first clock signal (the corresponding one of clkout1 to clkout8) and within at least one time period t2 of the falling edge of the first clock signal; wherein, the gate driver 201 is used to generate a plurality of the gate signals gate according to at least one second clock signal (for example, including 8 second clock signals clk1 to clk8) transmitted by at least one second signal line (for example, including 8 second signal lines CLK1 to CLK8).

[0032] The display device 100 may be, but is not limited to, an organic self-luminous display device, an inorganic self-luminous direct display device, or a liquid crystal display device. The display device 100 may include a panel body 10 for displaying an image and a driver 20. The driver 20 may include the aforementioned level converter 202, the aforementioned power reduction module 203, a source driver 204, and a power manager 205. The aforementioned gate driver 201 may be integrated into the aforementioned panel body 10 or the driver 20. Figure 1 Only the former is taken as an example.

[0033] like Figure 1As shown, here, a plurality of sub-pixels are arranged as an example, for example, they can be arranged in n rows and m columns (n and m are both positive integers). Among them, the panel body 10 may include a plurality of gate lines (GL1 to GLn) and a plurality of data lines (DL1 to DLm). Each gate line is electrically connected to a plurality of sub-pixels P in a corresponding row to output a corresponding gate signal gate (including a gate pulse pg for controlling the corresponding sub-pixel to turn on) thereto. The n rows of sub-pixels P (the corresponding transistors in the corresponding pixel circuit) are turned on sequentially under the control of the n gate signals gate (the n gate pulses pg therein). Each data line is connected to a plurality of sub-pixels P in a corresponding column to output a corresponding data signal data thereto. The multiple data signals data corresponding to the plurality of columns of sub-pixels P are matched so that when the sub-pixels P in each row are turned on, the corresponding m data voltages are respectively transmitted to the corresponding m sub-pixels P through the m data lines.

[0034] In combination with the above discussion, it can be seen that in this embodiment, the n gate signals gate corresponding to the n rows of sub-pixels P are generated by the gate driver 201 according to a number of second clock signals (for example, including 8 second clock signals clk1 to clk8) generated by the level converter 202. It should be noted that since the gate driver 201 generally includes n-stage cascaded gate driving units corresponding to the n rows of sub-pixels P, and each gate driving unit includes a plurality of transistors, at least one capacitor and a plurality of connecting lines, further, each gate line is also electrically connected to m pixel circuits in the m sub-pixels, and each pixel circuit includes a plurality of transistors, at least one capacitor and a plurality of connecting lines, if no interference is added, the load of each first signal line at least includes the transistors, capacitors and connecting lines in the corresponding gate driving unit and the corresponding row of pixel circuits (which can be equivalent to Figure 2 The resistors and capacitors connected in series in the panel main body 10 result in a heavy load on each first signal line, causing a large power consumption of the level converter 202 and the driver 20 including the same.

[0035] It can be understood that in this embodiment, a power reduction module 203 for generating a voltage signal avdd is provided, and the second signal line forms a current path between the power reduction module 203 and the first clock signal (the corresponding one of clkout1 to clkout8) within at least one time period t1 of the rising edge and within at least one time period t2 of the falling edge of the first clock signal through the switch module 2021, that is, within at least one time period t1 of the rising amplitude of the first clock signal and at least one time period t2 of the falling amplitude, a voltage signal with an amplitude a between the minimum amplitude a1 and the maximum amplitude a2 of the first clock signal is provided to the second signal line through the power reduction module 203. The signal avdd is used to assist in pulling up the potential of the second signal line during the rising edge of the first clock signal and to assist in pulling down the potential of the second signal line during the falling edge of the first clock signal. Only in other time periods is the first signal line providing the first clock signal to the second signal line. Therefore, the second clock signal finally output by the second signal line is generated by being driven by the first signal line and the power consumption reduction module 203 through time-sharing. Therefore, it is possible to avoid the first clock signal that is always transmitted through the first signal line directly driving the gate driver 201 to work, thereby reducing the time length of the first signal line driving its corresponding load, thereby reducing the power consumption of the level converter 202 and the power consumption of the driver 20 including it.

[0036] In summary, combined with Figure 3 and Figure 4 As shown, the second signal line (each of CLK1 to CLK8) forms a current path (corresponding to the current path) between the power consumption reduction module 203 and the second signal line (each of CLK1 to CLK8) during the period t1 of the rising edge of the first clock signal (the corresponding one of clkout1 to clkout8) and during the period t2 of the falling edge of the first clock signal. Figure 6 ), and a current path is formed between the first signal line (one corresponding to CLKOUT1 to CLKOUT8) and the corresponding first signal line (one corresponding to CLKOUT1 to CLKOUT8) in a period other than the above two periods (t1, t2) within one cycle of the first clock signal. Figure 5 ), so that the waveform of the second clock signal (the corresponding one of clk1 to clk8) output by the second signal line in the period t1' corresponding to the period t1 on the rising edge is formed by the action of the voltage signal avdd output by the power reduction module 203, and the waveform of the second clock signal (the corresponding one of clk1 to clk8) in the period t2' corresponding to the period t2 on the falling edge is formed by the action of the voltage signal avdd output by the power reduction module 203.

[0037] In some embodiments, combined Figures 2 to 6As shown, the power consumption reduction module 203 includes: a capacitor C, the first plate of the capacitor C receives a constant voltage (so that the change of the charge stored in the capacitor C is only affected by the voltage of its second plate), and the second signal line (each of CLK1 to CLK8) forms a current path with the corresponding first signal line (the corresponding one of CLKOUT1 to CLKOUT8) through the switching module 2021 in a time-sharing manner, and forms a current path with the second plate of the capacitor C.

[0038] In this embodiment, Figure 6 As shown, when a current path is formed between the second signal line and the second plate of the capacitor C during the time period t1 of the rising edge of the first clock signal, the second plate of the capacitor C can discharge to the second signal line to assist in raising the potential of the second clock signal; when a current path is formed between the second signal line and the second plate of the capacitor C during the time period t2 of the falling edge of the first clock signal, the second signal line can discharge to the second plate of the capacitor C to assist in lowering the potential of the second clock signal, and at the same time, the capacitor C also stores a sufficiently large charge to prepare for discharging to the second signal line during the time period t1 of the rising edge of the next cycle of the first clock signal.

[0039] It should be noted that, since the charging and discharging of the capacitor C is a process of gradual charge transfer, the amplitude of the voltage signal avdd provided by the power consumption reduction module 203 in this embodiment also changes gradually.

[0040] Furthermore, in this embodiment, the capacitor C can be a variable capacitor, that is, the capacitance value of the capacitor C can be adjusted according to demand. For example, when at least one of the refresh rate and resolution of the display device 100 is higher, since the required frequencies of the first clock signal and the second clock signal are larger, the charging and discharging speed of the capacitor C needs to be faster. According to the principle that "the voltage of a small-capacity capacitor rises / falls faster", the capacitance value of the capacitor C can be adjusted to be smaller at this time.

[0041] In some embodiments, combined Figure 7 and Figure 11 As shown, the power consumption reduction module 203 includes: a first voltage line VL1, which is used to transmit the constant voltage voltage signal avdd; wherein, the second signal line (each of CLK1 to CLK8) forms a current path with the corresponding first signal line (the corresponding one of CLKOUT1 to CLKOUT8) through the switch module 2021 in a time-sharing manner, and forms a current path with the first voltage line VL1.

[0042] This embodiment and Figure 5 and Figure 6The difference between the illustrated embodiments is that at least the constant voltage signal avdd transmitted through the first voltage line VL1 assists the rise of the potential of the second clock signal output by the second signal line, and also reduces the time length for the first signal line to drive its corresponding load, thereby reducing the power consumption of the level converter 202 and the power consumption of the driver 20 including it.

[0043] Specifically, it can be divided into the following two situations:

[0044] Case 1, combined Figure 7 and Figure 8 As shown, the power consumption reduction module 203 only includes the first voltage line VL1 mentioned above. Figure 8 As shown, a current path is formed between the second signal line and the first voltage line VL1 during a period t1 on the rising edge of the first clock signal. Since the amplitude of the voltage signal avdd output by the first voltage line VL1 is greater than the current potential of the first clock signal, the voltage signal avdd output by the first voltage line VL1 can help increase the potential of the second clock signal. A current path is formed between the second signal line and the first voltage line VL1 during a period t2 on the falling edge of the first clock signal. Since the amplitude of the voltage signal avdd output by the first voltage line VL1 is less than the current potential of the first clock signal, the voltage signal avdd output by the first voltage line VL1 can help lower the potential of the second clock signal.

[0045] Case 2, combined Figures 9 to 11 As shown, the power consumption reduction module 203 further includes: a second voltage line VL2, grounded, with an amplitude of the ground voltage vss being less than the amplitude of the voltage signal avdd and less than or equal to the minimum amplitude a1 of the first clock signal; wherein, the second signal line forms a current path with the first voltage line VL1 during at least a period t1 of a rising edge of the first clock signal, and forms a current path with the second voltage line VL2 during at least a period t2 of a falling edge of the first clock signal, through the switch module 2021;

[0046] For example Figure 10 As shown, a current path is formed between the second signal line and the first voltage line VL1 during the period t1 of the rising edge of the first clock signal. Since the amplitude of the voltage signal avdd output by the first voltage line VL1 is greater than the current potential of the first clock signal, the voltage signal avdd output by the first voltage line VL1 can help increase the potential of the second clock signal. For example, Figure 11As shown, a current path is formed between the second signal line and the second voltage line VL2 during the period t2 of the falling edge of the first clock signal. Since the ground voltage vss output by the second voltage line VL2 is smaller in amplitude than the voltage signal avdd than the current potential of the first clock signal, the ground voltage vss output by the second voltage line VL2 can assist in lowering the potential of the second clock signal to a greater extent.

[0047] It can be understood that in the embodiment of the present invention, since the power consumption reduction module 203 is set independently of the level converter 202, that is, the parameters of the devices in the power consumption reduction module 203 can be set according to the requirements of the Enji display device 100, avoiding problems such as the large size of the level converter 202 and the inflexible setting of the parameters of the devices in the power consumption reduction module 203 due to integration inside the level converter 202.

[0048] In some embodiments, combined Figures 2 to 3 、 Figure 6 、 Figure 8 、 Figures 10 and 11 As shown, the second signal line (each of CLK1 to CLK8) first forms a current path with the power reduction module 203 during the rising edge of the first clock signal (the corresponding one of clkout1 to clkout8) through the switch module 2021, and then forms a current path with the corresponding first signal line (the corresponding one of CLKOUT1 to CLKOUT8); the second signal line first forms a current path with the power reduction module 203 during the falling edge of the first clock signal through the switch module 2021, and then forms a current path with the corresponding first signal line.

[0049] In combination with the above discussion, it can be seen that the time period t1 in the rising edge of the above-mentioned first clock signal can also include at least one time period t3. During the time period t3 in the rising edge of the first clock signal, a current path is formed between the second signal line and the corresponding first signal line through the switch module 2021, that is, after the switch module 2021 assists in raising the potential of the second clock signal, the first clock signal provided by the corresponding first signal line is transmitted to the second signal line so that the corresponding second clock signal gradually rises to the maximum amplitude a2 of the first clock signal within the time period t3' corresponding to the time period t3.

[0050] In combination with the above discussion, it can be seen that the time period t2 in the falling edge of the above-mentioned first clock signal can also include at least one time period t4. During the time period t4 in the falling edge of the first clock signal, a current path is formed between the second signal line and the corresponding first signal line through the switch module 2021, that is, after the switch module 2021 assists in lowering the potential of the second clock signal, the first clock signal provided by the corresponding first signal line is transmitted to the second signal line so that the corresponding second clock signal gradually decreases to the minimum amplitude a1 of the first clock signal within the time period t4' corresponding to the time period t4.

[0051] Further, combined Figure 3 and Figure 4 As shown, the second signal line (each of CLK1 to CLK8) forms a current path between the corresponding first signal line (the corresponding one of CLKOUT1 to CLKOUT8) and the corresponding first signal line (the corresponding one of CLKOUT1 to CLKOUT8) through the switch module 2021 during the period when the maximum amplitude a2 of the first clock signal (the corresponding one of clkout1 to clkout8) is located and the period when the minimum amplitude a1 of the first clock signal is located.

[0052] That is, when the potential of the first clock signal is stable at the corresponding maximum amplitude a2 or minimum amplitude a1 in each cycle of the first clock signal (that is, during the stable period after the rising edge and the stable period after the falling edge of the first clock signal), the second signal line also forms a current path with the corresponding first signal line through the switching module 2021, so that the amplitude of the second clock signal can be stabilized to the maximum amplitude a2 of the first clock signal after its rising edge and can be stabilized to the minimum amplitude a1 of the first clock signal after its falling edge.

[0053] In some embodiments, combined Figures 1 to 4 As shown, the level converter 202 includes a plurality of first signal lines (e.g., eight first signal lines CLKOUT1 to CLKOUT8) and a corresponding plurality of second signal lines (e.g., eight second signal lines CLK1 to CLK8). The level converter 202 may include a clock generation module 2023 and a plurality of buffers 2024 connected between the plurality of output terminals of the clock generation module 2023 and the corresponding plurality of first signal lines. A signal output from each output terminal of the clock generation module 2023 is amplified by the corresponding buffer 2024 to generate a corresponding first clock signal.

[0054] It should be noted that, since the first clock signals transmitted by different first signal lines have a phase difference, that is, there is a time delay between the time periods of the rising edges of different first clock signals, and there is also a time delay between the time periods of the falling edges of different first clock signals, and each second signal line needs to form a current path with the power reduction module 203 within at least one time period t1 of the rising edge and at least one time period t2 of the falling edge of the corresponding first clock signal, so the time periods for forming the current path between different second signal lines and the power reduction module 203 are also different. It is necessary to control the corresponding second signal line to form a current path with the power reduction module 203 in the corresponding time period according to the phase of each first clock signal.

[0055] like Figure 2 As shown, it can be considered that the first clock signal clkout1 transmitted by the first signal line CLKOUT1 has the earliest phase compared with the first clock signals transmitted by other first signal lines, that is, the time period of its rising edge and the time period of its falling edge are both earliest, so the switch module 2021 can first control the corresponding second signal line CLK1 to form a current path with the power reduction module 203, and at this time, the other first clock signals have not reached the corresponding time period t1 or time period t2, so the switch module 2021 can control the other second signal lines to form a current path with the corresponding first signal line.

[0056] Here, eight first signal lines CLKOUT1 to CLKOUT8 and eight second signal lines CLK1 to CLK8 are taken as an example. It can be considered that the eight second signal lines CLK1 to CLK8 are respectively transmitted to the N+1th, N+2th, N+3th, N+4th, N+5th, N+6th, N+7th, and N+8th gate driving units in the n-stage gate driving unit to generate the N+1th to N+8th gate signals gate N+1, gate N+2, gate N+3, gate N+4, gate N+5, gate N+6, gate N+7, and gate N+8, where N is 0 or an integer multiple of 8.

[0057] Among them, combined Figures 1 to 4 As shown, the same second signal line (one of CLK1 to CLK8) forms a current path with the power reduction module 203 for different proportions of time in different cycles of the corresponding first clock signal (the corresponding one of clkout1 to clkout8); and / or, different second signal lines form a current path with the power reduction module 203 for different proportions of time in one cycle of the corresponding first clock signal.

[0058] It should be noted that, in this embodiment, it is taken into account that the second clock pulse p2 in different cycles of the second clock signal corresponding to the first clock pulse p1 of the same second signal line in different cycles is used to generate different gate pulses pg corresponding to sub-pixels P in different rows, and the second clock pulse p2 in the same cycle of the second clock signal corresponding to the first clock pulse p1 of different second signal lines in one cycle is used to generate different gate pulses pg corresponding to sub-pixels P in different rows, and since sub-pixels P in different rows have different distances from the driver 20, there is a difference in the attenuation degree of at least one signal loaded by the pixel circuit in the sub-pixel P.

[0059] Therefore, this embodiment can improve the difference in signal attenuation caused by the difference in distance between sub-pixels P in different rows and the driver 20, thereby improving the uniformity of the displayed image, by at least one of "differentiated settings of the proportion of the time period during which the second signal line forms a current path with the power reduction module 203 in different cycles of the same first clock signal" and "differentiated settings of the proportion of the time period during which different second signal lines form a current path with the power reduction module 203 in one cycle of the corresponding first clock signal."

[0060] Specific, combined Figures 1 to 4 As shown, the plurality of gate signals gate include a first-type gate signal gate-1 and a second-type gate signal gate-2. The distance between the plurality of sub-pixels P corresponding to the first-type gate signal gate-1 and the level converter 202 is smaller than the distance between the plurality of sub-pixels P corresponding to the second-type gate signal gate-2 and the level converter 202. The plurality of cycles of the same first clock signal (one of clkout1 to clkout8) include a first-type cycle Tt1 corresponding to the first-type gate signal gate-1 and a second-type cycle Tt2 corresponding to the second-type gate signal gate-2. The first clock pulse p in the first clock signal located within the first-type cycle Tt1 is 1 pulse is used to generate the first-type gate signal gate-1, and the first clock pulse p1 in the first clock signal located within the second-type period Tt2 is used to generate the second-type gate signal gate-2; the multiple second clock signals include a first-type second clock signal (for example, the second clock signal clk8) corresponding to the first-type gate signal gate-1, and a second-type second clock signal (for example, the second clock signal clk7) corresponding to the second-type gate signal gate-1, the second clock pulse p2 of the first-type second clock signal is used to generate the first-type gate signal gate-1, and the second clock pulse p2 of the second-type second clock signal is used to generate the second-type gate signal gate-2.

[0061] Among them, the above-mentioned first-type gate signal gate-1 and second-type gate signal gate-2 can be understood as, among any two gate signals gate, the one corresponding to the sub-pixel P with a smaller distance from the level converter 202 and the one corresponding to the sub-pixel P with a larger distance from the level converter 202, that is, the two are respectively the gate signal gate corresponding to the near-end sub-pixel P and the gate signal gate corresponding to the far-end sub-pixel P.

[0062] Among them, taking the n gate pulses pg generated in sequence on the time axis from the far-end gate driving unit to the near-end gate driving unit in the gate driver 201 as an example, the first-type gate signal gate-1 corresponding to the near-end sub-pixel P is more delayed than the second-type gate signal gate-2 corresponding to the far-end sub-pixel P, that is, the above-mentioned first-type period Tt1 may lag behind the second-type period Tt2, and the phase of the above-mentioned first-type second clock signal may lag behind the phase of the second-type second clock signal. The above only takes the two as clk8 and clk7 as an example.

[0063] Based on the above definition, this embodiment can make at least one of the following settings:

[0064] The first one is combined Figures 2 to 4 As shown, the proportion of the time during which the same second signal line (one of CLK1 to CLK8) forms a current path with the power reduction module 203 in the corresponding first-type cycle Tt1 (i.e., the ratio of the total time of period t1 and period t2 to the time of the first-type cycle Tt1) is greater than the proportion of the time during which the same second signal line (one of CLK1 to CLK8) forms a current path with the power reduction module 203 in the corresponding second-type cycle Tt2 (i.e., the ratio of the total time of period t1 and period t2 to the time of the second-type cycle Tt2);

[0065] The second clock signal at least acted upon by the corresponding first clock signal and the voltage signal avdd also includes a first-type target period T1' corresponding to the first-type period Tt1, and the second clock signal at least acted upon by the corresponding first clock signal and the voltage signal also includes a second-type target period T2' corresponding to the second-type period Tt2. For the same second signal line, since the duration of the current path formed between the second signal line and the power consumption reduction module 203 accounts for a larger proportion in the first-type period Tt1 than in the second-type period Tt2, the longer the duration of the voltage signal avdd acts, the longer the duration of the time periods t1' and t2' in the formed second clock signal also accounts for a larger proportion;

[0066] The second is combined Figures 2 to 4As shown, the proportion of the time during which the first-type second signal line corresponding to the first-type second clock signal forms a current path with the power reduction module within one cycle of the corresponding first clock signal is greater than the proportion of the time during which the second-type second signal line corresponding to the second-type second clock signal forms a current path with the power reduction module within one cycle of the corresponding first clock signal;

[0067] Among them, since the first type second signal line (for example, corresponding to the second clock signal clk8) forms a current path with the power reduction module 203 for a longer period of time within one cycle of the first clock signal than the second type second signal line (for example, corresponding to the second clock signal clk7).

[0068] It should be noted that this embodiment takes into account that the proximal sub-pixel P (corresponding to the first-type gate signal gate-1) is closer to the level converter 202 than the distal sub-pixel P (corresponding to the second-type gate signal gate-2). Therefore, in the absence of interference, the attenuation of the first-type gate signal gate-1 is greater than the attenuation of the second-type gate signal gate-2.

[0069] Therefore, this embodiment adopts at least one of the following methods: "setting a larger proportion of the total duration of the time period t1 and the time period t2 within the first-type cycle Tt1 corresponding to the proximal sub-pixel P in the same first clock signal, thereby increasing the total duration of the time period t1' and the time period t2' within the corresponding first-type target cycle T1' in the second clock signal"; and "setting a larger proportion of the duration of the current path formed between the first-type second signal line corresponding to the proximal sub-pixel P and the power reduction module 203 within one cycle of the first clock signal, thereby increasing the total duration of the time period t1' and the time period t2' of the first-type second signal line within the corresponding one cycle". Both of these methods can achieve that the time period t1' of the second clock signal corresponding to the proximal sub-pixel P in its rising edge has a larger proportion, and the time period t2' in its falling edge has a larger proportion, so that the waveform of the first-type gate signal gate-1 generated thereby can rise and fall more slowly, so that the difference between the waveform of the first-type gate signal gate-1 and the waveform of the second-type gate signal gate-2 corresponding to the distal sub-pixel P is smaller, thereby improving the uniformity of the display screen.

[0070] In some embodiments, combined Figure 2 、 Figure 12 and Figure 13As shown, the switch module 2021 includes at least one demultiplexing circuit 2022 (for example, including 8 demultiplexing circuits) corresponding to at least one first signal line (for example, including 8 first signal lines CLKOUT1 to CLKOUT8), and the demultiplexing circuit 2022 includes: a first demultiplexing transistor Tm1, the gate of the first demultiplexing transistor Tm1 is electrically connected to the control line CON, the source of the first demultiplexing transistor Tm1 is electrically connected to the corresponding first signal line (one of CLKOUT1 to CLKOUT8), and the drain of the first demultiplexing transistor Tm1 is electrically connected to the corresponding second signal line (one of CLK1 to CLK8); a second demultiplexing transistor Tm2, the second demultiplexing transistor Tm3 is electrically connected to the control line CON, and the drain of the first demultiplexing transistor Tm1 is electrically connected to the corresponding second signal line (one of CLK1 to CLK8); The gate of the body transistor Tm2 is electrically connected to the control line CON, the source of the second demultiplexing transistor Tm2 is electrically connected to the power reduction module 203, and the drain of the second demultiplexing transistor Tm2 is electrically connected to the corresponding second signal line (one of CLK1 to CLK8); wherein, the control signal con transmitted by the control line CON is used to control the time-sharing conduction of the first demultiplexing transistor Tm1 and the second demultiplexing transistor Tm2, and the control signal con is used to control the second demultiplexing transistor Tm2 to be turned on within at least a time period t1 of the rising edge of the first clock signal (the corresponding one of clkout1 to clkout8) and within at least a time period t2 of the falling edge of the first clock signal.

[0071] Among them, the first demultiplexing transistor Tm1 can be one of an N-type transistor and a P-type transistor, and the second demultiplexing transistor Tm2 can be the other of an N-type transistor and a P-type transistor, that is, the current potential of the control signal con can control one of the first demultiplexing transistor Tm1 and the second demultiplexing transistor Tm2 to be turned on and the other to be turned off.

[0072] For example Figure 12 and Figure 13 As shown, here, the first demultiplexing transistor Tm1 and the second demultiplexing transistor Tm2 are respectively a P-type transistor and an N-type transistor as an example, then the control signal con is a corresponding high potential in the above-mentioned time period t1 and time period t2, so that the second demultiplexing transistor Tm2 is turned on in the time period t1 and time period t2, thereby forming a current path between the corresponding second signal line and the power consumption reduction module 203, so as to form the waveform of the second clock signal in the corresponding time period t1' and the corresponding time period t2'.

[0073] Specifically, the duration of the period during which the first potential c1 (for example, a corresponding low potential) in the control signal con is used to control the conduction of the first demultiplexing transistor Tm1 is shorter than the duration of the period during which the second potential c2 (for example, a corresponding high potential) in the control signal is used to control the conduction of the second demultiplexing transistor Tm2 is used. In combination with the above discussion, it can be seen that since the second signal line forms a current path with the corresponding first signal line (a corresponding one of CLKOUT1 to CLKOUT8) in the period other than the above two periods (t1 and t2) within one cycle of the first clock signal, that is, the duration of the period during which the second potential c2 in the control signal con is used to control the conduction of the second demultiplexing transistor Tm2 should be set longer.

[0074] In other embodiments, Figure 14 and Figure 15 As shown, the demultiplexing circuit 2022 includes a third transistor T3, a fourth transistor T4 to a tenth transistor T10, a first resistor R1 and a second resistor R2, and a first inverter F1 and a second inverter F2. The buffer 2024 in the level converter 202 includes a first transistor T1 and a second transistor T2. The specific connection relationship can be referred to but not limited to Figure 14 , where the solid circle in the transistor indicates that the transistor is an N-type transistor, and the hollow circle indicates that the transistor is a P-type transistor. Figure 2 The resistance value of the resistor in the panel body 10 (the resistor and capacitor connected in series) can be 3.5 kilo-ohms, the capacitance value of the capacitor can be 3 nF, and the capacitance value of the capacitor C in the power consumption reduction module 203 can be 10 nF.

[0075] Combine Figure 14 and Figure 15 As shown, the left side of the dotted line L can be considered to form a current path between the second signal line and the corresponding first signal line. At this time, since the second clock signal (one of clk1 to clk8) is not affected by the power reduction module 203, the waveform of the second clock signal is close to the waveform of the corresponding first clock signal, that is, the rising edge and the falling edge are relatively steep. The right side of the dotted line L can be analyzed as follows:

[0076] Period t1′: the CKOUT_rising signal is at a corresponding high level and the CKOUT_falling signal is at a corresponding low level, the third transistor T3, the fourth transistor T4, the ninth transistor T9, and the tenth transistor T10 are all turned on, and the capacitor C in the power reduction module 203 discharges to the second signal line;

[0077] Period t3': the CKOUT_rising signal is at a corresponding low potential, and the CKOUT_falling signal is at a corresponding low potential. The difference from period t1' is that the ninth transistor T9 and the tenth transistor T10 are turned off, and the ninth transistor T9 and the sixth transistor T6 are turned on. That is, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all turned on. The first signal line continues to charge the second signal line, so that the potential of the second clock signal rises to a value close to the maximum amplitude a2 of the first clock signal.

[0078] Period t2′: the CKOUT_rising signal is at a corresponding low level and the CKOUT_falling signal is at a corresponding high level, the ninth transistor T9, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all turned on, and the second signal line charges the capacitor C in the power reduction module 203;

[0079] Time period t4': the CKOUT_rising signal is at a corresponding low potential and the CKOUT_falling signal is at a corresponding low potential. The difference from time period t2' is that the third transistor T3 and the fourth transistor T4 are turned on, and the seventh transistor T7 and the eighth transistor T8 are turned off, that is, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all turned on, and the second signal line continues to discharge to the first signal line to cause the potential of the second clock signal to drop to a level close to the minimum amplitude a1 of the first clock signal.

[0080] Among them, the frequency of the signal output from each output end of the clock generation module 2023, the frequency of the CKOUT_rising signal, and the frequency of the CKOUT_falling signal can all be equal to the frequency of the corresponding first clock signal, for example, it can be 500 Hz. The minimum amplitude a1 and the maximum amplitude a2 of the corresponding first clock signal obtained by amplifying the signal output from each output end of the clock generation module 2023 through the corresponding buffer 2024 can be 40 V and 0 V respectively acting on the buffer 2024.

[0081] In some embodiments, as Figure 1 As shown, the display device 100 further includes: a timing controller 206 (also included in the driver 20), which is used to generate a source clock signal ck; wherein the level converter 202 is included in the power manager 205 in the display device or is independent of the power manager 205 (the latter is taken as an example here), and the power manager 205 is used to generate a first power signal vgh and a second power signal vgl; wherein the level converter 202 is used to generate at least one first clock signal according to the source clock signal ck, the first power signal vgh and the second power signal vgl.

[0082] Specifically, the level converter 202 can generate at least one first clock signal (for example, including 8 first clock signals clkout1 to clkout8) based on the timing of the source clock signal ck and the amplitude of the constant voltage first power signal vgh and the amplitude of the constant voltage second power signal vgl. The high potential and low potential corresponding to each first clock signal can be the amplitude of the first power signal vgh and the amplitude of the second power signal vgl, respectively. The period and duty cycle of each first clock signal can be the same as the period and duty cycle of the source clock signal ck. There is a phase difference between different first clock signals. For example, the phase difference between two adjacent ones of clkout1 to clkout8 is the same.

[0083] The embodiment of the present invention also provides a driving method of a display device, such as Figure 1 and Figure 2 As shown, the display device 100 includes a plurality of sub-pixels P, a gate driver 201, a level converter 202, and a power reduction module 203. The level converter 202 includes at least one first signal line (for example, including eight first signal lines CLKOUT1 to CLKOUT8), corresponding at least one second signal line (for example, including eight second signal lines CLK1 to CLK8), and a switch module 2021 connected between the at least one first signal line and the at least one second signal line.

[0084] like Figure 16 As shown, the driving method of the display device includes but is not limited to the following steps and combinations of the following steps:

[0085] S1, controlling the level converter to generate at least one first clock signal transmitted through at least one first signal line;

[0086] As can be seen from the above discussion, the level converter 202 can generate at least one first clock signal based on the source clock signal ck provided by the timing controller 206 and the first power signal vgh and the second power signal vgl provided by the power manager 205. The duty cycle, period, and amplitude of the first clock signal can be referred to the relevant description above.

[0087] S2, controlling, by the switch module, the second signal line to form a current path with the power reduction module during at least one period of a rising edge of the first clock signal and during at least one period of a falling edge of the first clock signal, so that a voltage signal generated by the power reduction module is transmitted to the second signal line, and an amplitude of the voltage signal is greater than a minimum amplitude of the first clock signal and less than a maximum amplitude of the first clock signal;

[0088] S3, controlling the second signal line through the switch module to form a current path with the corresponding first signal line when the second signal line does not form a current path with the power consumption reduction module, so that the first clock signal is transmitted to the corresponding second signal line;

[0089] As can be seen from the above discussion, during at least one period t1 when the amplitude of the first clock signal rises and during at least one period t2 when it falls, the power reduction module 203 provides the second signal line with a voltage signal avdd having an amplitude a between the minimum amplitude a1 and the maximum amplitude a2 of the first clock signal, so as to assist in pulling up the potential of the second signal line during the rising edge of the first clock signal and assist in pulling down the potential of the second signal line during the falling edge of the first clock signal. During other periods, the first signal line provides the first clock signal to the second signal line, thereby preventing the first clock signal, which is always transmitted through the first signal line, from directly driving the gate driver 201 to operate, reducing the time period during which the first signal line drives its corresponding load, and thereby reducing the power consumption of the level shifter 202 and the power consumption of the driver 20 including the same.

[0090] S4, controlling the gate driver to generate a plurality of gate signals according to at least one second clock signal transmitted by at least one second signal line, wherein the gate signals are used to control the corresponding plurality of sub-pixels to turn on;

[0091] Each second signal line can drive a corresponding multi-stage gate driving unit to generate corresponding multiple gate signals gate. For details, please refer to the above related discussion.

[0092] Specific, combined Figures 2 to 6 As shown, the power consumption reduction module 203 includes a capacitor C, and a first plate of the capacitor C receives a constant voltage;

[0093] The above step S2 includes but is not limited to the following steps:

[0094] S21, controlling the second signal line through the switch module to form a current path between the second plate of the capacitor and the second signal line during at least one period of a rising edge of the first clock signal and during at least one period of a falling edge of the first clock signal;

[0095] It can be understood that when a current path is formed between the second signal line and the second plate of the capacitor C during the time period t1 of the rising edge of the first clock signal, the second plate of the capacitor C can discharge to the second signal line to help increase the potential of the second clock signal; when a current path is formed between the second signal line and the second plate of the capacitor C during the time period t2 of the falling edge of the first clock signal, the second signal line can discharge to the second plate of the capacitor C to help lower the potential of the second clock signal. At the same time, the capacitor C also stores a sufficiently large charge to prepare for discharging to the second signal line during the time period t1 of the rising edge of the next cycle of the first clock signal.

[0096] Specific, combined Figure 7 and Figure 8 As shown, the power consumption reduction module 203 (only) includes a first voltage line VL1, and the first voltage line VL1 is used to transmit the constant voltage signal avdd;

[0097] The above step S2 includes but is not limited to the following steps:

[0098] S22, controlling the second signal line through the switch module to form a current path with the first voltage line during at least one period of a rising edge of the first clock signal and during at least one period of a falling edge of the first clock signal;

[0099] It can be understood that when the second signal line forms a current path between the first voltage line VL1 and the second signal line during the period t1 of the rising edge of the first clock signal, the voltage signal avdd output by the first voltage line VL1 helps to increase the potential of the second clock signal; when the second signal line forms a current path between the first voltage line VL1 and the first voltage line VL1 during the period t2 of the falling edge of the first clock signal, the voltage signal avdd output by the first voltage line VL1 helps to lower the potential of the second clock signal.

[0100] Specific, combined Figures 9 to 11 As shown, the power consumption reduction module 203 includes a first voltage line VL1 and a second voltage line VL2, the first voltage line VL1 is used to transmit the constant voltage signal avdd, the second voltage line VL2 is grounded, and the amplitude of the ground voltage vss is less than the amplitude of the voltage signal avdd and less than or equal to the minimum amplitude a1 of the first clock signal;

[0101] The above step S2 includes but is not limited to the following steps:

[0102] S23, controlling the second signal line through the switch module to form a current path with the first voltage line during at least one period of the rising edge of the first clock signal, and to form a current path with the second voltage line during at least one period of the falling edge of the first clock signal.

[0103] It can be understood that a current path is formed between the second signal line and the first voltage line VL1 during the time period t1 of the rising edge of the first clock signal, and the voltage signal avdd output by the first voltage line VL1 helps to increase the potential of the second clock signal; the second signal line forms a current path between the second voltage line VL2 during the time period t2 of the falling edge of the first clock signal, and the ground voltage vss output by the second voltage line VL2 helps to lower the potential of the second clock signal to a greater extent.

[0104] The above is a detailed introduction to the structure of the display device and the driving method thereof provided by the embodiments of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display device, characterized in that: include: multiple sub-pixels; A gate driver, configured to generate a plurality of gate signals, wherein the gate signals are configured to control the corresponding plurality of sub-pixels to turn on; a level converter, comprising at least one first signal line, at least one corresponding second signal line, and a switch module connected between the at least one first signal line and the at least one second signal line, the level converter being configured to generate at least one first clock signal transmitted via the at least one first signal line; a power consumption reduction module, configured to generate a voltage signal having an amplitude greater than a minimum amplitude of the first clock signal and less than a maximum amplitude of the first clock signal; The second signal line forms a current path with the corresponding first signal line and with the power reduction module in a time-sharing manner through the switch module, and the second signal line forms a current path with the power reduction module during at least one period of the rising edge of the first clock signal and during at least one period of the falling edge of the first clock signal through the switch module; The gate driver is configured to generate a plurality of the gate signals according to at least one second clock signal transmitted by at least one second signal line.

2. The display device according to claim 1, wherein The power consumption reduction module includes: A capacitor, wherein the first plate of the capacitor receives a constant voltage, and the second signal line forms a current path with the corresponding first signal line and the second plate of the capacitor in a time-sharing manner through the switch module.

3. The display device according to claim 1, wherein The power consumption reduction module includes: A first voltage line, used for transmitting the constant voltage signal; The second signal line forms a current path with the corresponding first signal line and a current path with the first voltage line in a time-sharing manner through the switch module.

4. The display device according to claim 3, wherein The power consumption reduction module further includes: a second voltage line, grounded, wherein the amplitude of the ground voltage is smaller than the amplitude of the voltage signal and smaller than or equal to the minimum amplitude of the first clock signal; Particularly, the second signal line forms a current path with the first voltage line during at least one period of the rising edge of the first clock signal and forms a current path with the second voltage line during at least one period of the falling edge of the first clock signal through the switch module.

5. The display device according to any one of claims 1 to 4, wherein: The second signal line forms a current path with the power consumption reduction module first and then forms a current path with the corresponding first signal line through the switch module at a rising edge of the first clock signal; The second signal line first forms a current path with the power consumption reduction module through the switch module during the falling edge of the first clock signal, and then forms a current path with the corresponding first signal line.

6. The display device according to claim 5, wherein The level converter includes a plurality of the first signal lines and a corresponding plurality of the second signal lines; The second signal line forms a current path with the power consumption reduction module for different periods of time in different cycles of the corresponding first clock signal; And / or, different second signal lines have different proportions of duration in which a current path is formed between the second signal line and the power consumption reduction module within the corresponding period of the first clock signal.

7. The display device according to claim 6, wherein The plurality of gate signals include a first type of gate signals and a second type of gate signals, and a distance between the plurality of sub-pixels corresponding to the first type of gate signals and the level shifter is smaller than a distance between the plurality of sub-pixels corresponding to the second type of gate signals and the level shifter; The multiple cycles of the same first clock signal include a first cycle corresponding to the first type of gate signal and a second cycle corresponding to the second type of gate signal, a first clock pulse in the first clock signal located within the first cycle is used to generate the first type of gate signal, and a first clock pulse in the first clock signal located within the second cycle is used to generate the second type of gate signal; The plurality of second clock signals include a first type of second clock signal corresponding to the first type of gate signal and a second type of second clock signal corresponding to the second type of gate signal, wherein the second clock pulse of the first type of second clock signal is used to generate the first type of gate signal, and the second clock pulse of the second type of second clock signal is used to generate the second type of gate signal; The proportion of the time during which the same second signal line forms a current path with the power consumption reduction module in the corresponding first-type cycle is greater than the proportion of the time during which the same second signal line forms a current path with the power consumption reduction module in the corresponding second-type cycle; And / or, the proportion of the time during which the first type of second signal line corresponding to the first type of second clock signal forms a current path with the power reduction module within one cycle of the corresponding first clock signal is greater than the proportion of the time during which the second type of second signal line corresponding to the second type of second clock signal forms a current path with the power reduction module within one cycle of the corresponding first clock signal.

8. The display device according to claim 5, wherein The second signal line forms a current path with the corresponding first signal line through the switch module during a period when the first clock signal has a maximum amplitude and a period when the first clock signal has a minimum amplitude.

9. The display device according to any one of claims 1 to 4, wherein: The switch module includes at least one demultiplexing circuit corresponding to at least one first signal line, and the demultiplexing circuit includes: a first demultiplexing transistor, wherein a gate of the first demultiplexing transistor is electrically connected to a control line, a source of the first demultiplexing transistor is electrically connected to the corresponding first signal line, and a drain of the first demultiplexing transistor is electrically connected to the corresponding second signal line; a second demultiplexing transistor, wherein a gate of the second demultiplexing transistor is electrically connected to the control line, a source of the second demultiplexing transistor is electrically connected to the power reduction module, and a drain of the second demultiplexing transistor is electrically connected to the corresponding second signal line; In which, the control signal transmitted by the control line is used to control the time-sharing conduction of the first demultiplexing transistor and the second demultiplexing transistor, and the control signal is used to control the conduction of the second demultiplexing transistor within at least one time period of the rising edge of the first clock signal and within at least one time period of the falling edge of the first clock signal.

10. The display device according to claim 9, wherein The duration of a period during which the first potential in the control signal is used to control the first demultiplexing transistor to be turned on is shorter than the duration of a period during which the second potential in the control signal is used to control the second demultiplexing transistor to be turned on.

11. The display device according to any one of claims 1 to 4, characterized in that: Also includes: A timing controller, for generating a source clock signal; The level converter is included in a power manager in the display device or is independent of the power manager, and the power manager is used to generate a first power signal and a second power signal; The level converter is configured to generate at least one first clock signal according to the source clock signal, the first power signal, and the second power signal.

12. A method for driving a display device, characterized in that: The display device includes a plurality of sub-pixels, a gate driver, a level converter and a power reduction module, wherein the level converter includes at least one first signal line, at least one corresponding second signal line and a switch module connected between the at least one first signal line and the at least one second signal line; The driving method of the display device includes: controlling the level converter to generate at least one first clock signal transmitted through at least one first signal line; Controlling, by the switch module, the second signal line to form a current path with the power reduction module during at least one period of a rising edge of the first clock signal and during at least one period of a falling edge of the first clock signal, so that a voltage signal generated by the power reduction module is transmitted to the second signal line, and an amplitude of the voltage signal is greater than a minimum amplitude of the first clock signal and less than a maximum amplitude of the first clock signal; controlling the second signal line by the switch module to form a current path with the corresponding first signal line when no current path is formed between the second signal line and the power consumption reduction module, so that the first clock signal is transmitted to the corresponding second signal line; The gate driver is controlled to generate a plurality of gate signals according to at least one second clock signal transmitted by at least one second signal line, wherein the gate signals are used to control the corresponding plurality of sub-pixels to turn on.

13. The method for driving a display device according to claim 12, wherein: The power consumption reduction module includes a capacitor, wherein a first plate of the capacitor receives a constant voltage; The step of controlling the second signal line through the switch module to form a current path with the power consumption reduction module within at least one period of the rising edge of the first clock signal and within at least one period of the falling edge of the first clock signal includes: The switch module controls the second signal line to form a current path with the second plate of the capacitor during at least one period of a rising edge of the first clock signal and during at least one period of a falling edge of the first clock signal.

14. The method for driving a display device according to claim 12, wherein: The power consumption reduction module includes a first voltage line, and the first voltage line is used to transmit the voltage signal of constant voltage; The step of controlling the second signal line through the switch module to form a current path with the power consumption reduction module within at least one period of the rising edge of the first clock signal and within at least one period of the falling edge of the first clock signal includes: The switch module controls the second signal line to form a current path with the first voltage line during at least one period of a rising edge of the first clock signal and during at least one period of a falling edge of the first clock signal.

15. The method for driving a display device according to claim 12, wherein: The power consumption reduction module includes a first voltage line and a second voltage line, the first voltage line is used to transmit the constant voltage voltage signal, the second voltage line is grounded, and the amplitude of the ground voltage is smaller than the amplitude of the voltage signal and smaller than or equal to the minimum amplitude of the first clock signal; The step of controlling the second signal line through the switch module to form a current path with the power consumption reduction module within at least one period of the rising edge of the first clock signal and within at least one period of the falling edge of the first clock signal includes: The switch module controls the second signal line to form a current path with the first voltage line during at least one period of the rising edge of the first clock signal, and to form a current path with the second voltage line during at least one period of the falling edge of the first clock signal.

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