Pixel circuit, driving method thereof and liquid crystal display device

Abstract

The invention discloses a pixel circuit, a driving method thereof and a liquid crystal display device. The pixel circuit comprises a data writing module, a first voltage transmission module, a second voltage transmission module and a storage module, the data write-in module is connected with the first end of the storage module, and the data write-in module is used for transmitting data voltage to the first end of the storage module; the first voltage transmission module is connected with the second end of the storage module, and the first voltage transmission module is used for transmitting the first voltage to the second end of the storage module; the second voltage transmission module is connected with the second end of the storage module, and the second voltage transmission module is used for transmitting the second voltage to the second end of the storage module. According to the invention, data voltage can be converted into higher voltage, so that driving of PDLC material display can be realized.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, and a liquid crystal display device. Background Art

[0002] In a Thin Film Transistor Liquid Crystal Display (TFT-LCD), a gate driver typically provides a gate drive signal to the gate of each thin film transistor in a pixel circuit to control the gate's on and off state. However, existing pixel circuits are unable to drive polymer dispersed liquid crystal (PDLC) materials. Summary of the Invention

[0003] The present invention provides a pixel circuit and a driving method thereof, and a liquid crystal display device, which can convert a data voltage into a higher voltage, thereby realizing the driving of a PDLC material display.

[0004] In a first aspect, a pixel circuit is provided, including: a data writing module, a first voltage transmission module, a second voltage transmission module and a storage module; the data writing module is connected to the first end of the storage module, and the data writing module is used to transmit the data voltage to the first end of the storage module; the first voltage transmission module is connected to the second end of the storage module, and the first voltage transmission module is used to transmit the first voltage to the second end of the storage module; the second voltage transmission module is connected to the second end of the storage module, and the second voltage transmission module is used to transmit the second voltage to the second end of the storage module.

[0005] Optionally, the driving stage of the pixel circuit includes alternating first driving frames and second driving frames; the first driving frame includes a first data writing stage and a first stage, and the second driving frame includes a second data writing stage and a second stage; the data writing module is used to be turned on in the first data writing stage and the second data writing stage, and turned off in the first stage and the second stage to transmit the data voltage to the first end of the storage module; the first voltage transmission module is used to be turned on in the first data writing stage, the first stage, and the second data writing stage, and turned off in the second stage to transmit the first voltage to the second end of the storage module; the second voltage transmission module is used to be turned on in the second stage, and turned off in the first data writing stage, the first stage, and the second data writing stage to transmit the second voltage to the second end of the storage module.

[0006] Optionally, the first stage is located between the first data writing stage and the second data writing stage, and the second stage is located after the second data writing stage.

[0007] Optionally, the start time of the second phase is the same as the end time of the second data writing phase, and the end time of the second phase is the same as the start time of the first data writing phase.

[0008] Optionally, the first voltage is lower than the second voltage.

[0009] Optionally, the first voltage is -15V.

[0010] Optionally, the second voltage is 15V.

[0011] Optionally, the data voltage is 0V or 10V.

[0012] Optionally, the data writing module includes a first transistor; the gate of the first transistor is connected to the first scan line, the first electrode of the first transistor is connected to the data line, and the second electrode of the first transistor is connected to the first end of the storage module.

[0013] Optionally, the first transistor is a dual-gate transistor, and the first transistor includes a first sub-transistor and a second sub-transistor; the gate of the first sub-transistor and the gate of the second sub-transistor are both connected to the first scan line, the first electrode of the first sub-transistor is connected to the data line, the second electrode of the first sub-transistor is connected to the first electrode of the second sub-transistor, and the second electrode of the second sub-transistor is connected to the first end of the storage module.

[0014] Optionally, the first voltage transmission module includes a second transistor; the gate of the second transistor is connected to the second scan line, the first electrode of the second transistor is connected to the first power line, and the second electrode of the second transistor is connected to the second end of the storage module.

[0015] Optionally, the second transistor is a dual-gate transistor, and the second transistor includes a third sub-transistor and a fourth sub-transistor; the gate of the third sub-transistor and the gate of the fourth sub-transistor are both connected to the second scan line, the first electrode of the third sub-transistor is connected to the first power line, the second electrode of the third sub-transistor is connected to the first electrode of the fourth sub-transistor, and the second electrode of the fourth sub-transistor is connected to the second end of the storage module.

[0016] Optionally, the second voltage transmission module includes a third transistor; the gate of the third transistor is connected to the third scan line, the first electrode of the third transistor is connected to the second power line, and the second electrode of the third transistor is connected to the second end of the storage module.

[0017] Optionally, the third transistor is a dual-gate transistor, and the third transistor includes a fifth sub-transistor and a sixth sub-transistor; the gate of the fifth sub-transistor and the gate of the sixth sub-transistor are both connected to the third scan line, the first electrode of the fifth sub-transistor is connected to the second power line, the second electrode of the fifth sub-transistor is connected to the first electrode of the sixth sub-transistor, and the second electrode of the sixth sub-transistor is connected to the second end of the storage module.

[0018] Optionally, the storage module includes a storage capacitor, a first end of the storage capacitor serves as the first end of the storage module, and a second end of the storage capacitor serves as the second end of the storage module.

[0019] In a second aspect, an embodiment of the present invention provides a driving method for a pixel circuit, wherein the pixel circuit includes a data writing module, a first voltage transmission module, a second voltage transmission module and a storage module; the data writing module is connected to the first end of the storage module, the first voltage transmission module is connected to the second end of the storage module, and the second voltage transmission module is connected to the second end of the storage module; the driving method includes: controlling the data writing module to be turned on to transmit the data voltage to the first end of the storage module; controlling the first voltage transmission module to be turned on to transmit the first voltage to the second end of the storage module; and controlling the second voltage transmission module to be turned on to transmit the second voltage to the second end of the storage module.

[0020] In a third aspect, an embodiment of the present invention provides a liquid crystal display device, comprising the pixel circuit provided by any embodiment of the present invention.

[0021] The pixel circuit provided by an embodiment of the present invention includes a data writing module, a first voltage transmission module, a second voltage transmission module, and a storage module. By controlling the data writing module and the first voltage transmission module to switch from an on state to an off state, and the second voltage transmission module to switch from an off state to an on state in the second phase of the second drive frame, the voltage of the first electrode can be jumped from the first voltage to the second voltage, and the jump voltage is coupled to the pixel electrode through the storage module, thereby increasing the voltage of the pixel electrode. In other words, by converting the data voltage of the pixel electrode into a voltage higher than the data voltage in the second phase of the second drive frame, a sufficiently strong electric field change can be formed between the pixel electrode and the common electrode. This electric field change is sufficient to drive the reorientation of the liquid crystal molecules of the PDLC material, change the optical properties of the liquid crystal layer such as the transmittance and refractive index of light, meet the conditions required for the PDLC material to display, and thus realize the driving of the PDLC material display.

[0022] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1is a structural schematic diagram of a liquid crystal display device provided by an embodiment of the present invention;

[0025] Figure 2 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0026] Figure 3 This is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of liquid crystal flipping provided by an embodiment of the present invention;

[0028] Figure 5 This is another liquid crystal flip schematic diagram provided by an embodiment of the present invention;

[0029] Figure 6 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0030] Figure 7 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0031] Figure 8 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0032] Figure 9 is a structural diagram of another pixel circuit provided by an embodiment of the present invention;

[0033] Figure 10 This is a simulation diagram provided by an embodiment of the present invention;

[0034] Figure 11 This is a flowchart of a driving method for a pixel circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0036] It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and the accompanying drawings are used to distinguish similar items and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present invention described herein can be implemented in sequences other than those illustrated or described herein. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0037] As described in the background art, existing pixel circuits have the problem of being unable to drive PDLC materials. The inventors have discovered that the reason for this problem is that, in order to prevent the liquid crystal material from polarizing, a data voltage must be supplied to one of the electrodes of the liquid crystal material via a driver chip to drive the liquid crystal material to rotate. When the data voltage output by the driver chip is too high, the excessively high data voltage may degrade the performance of the thin-film transistors in the pixel circuit, leading to problems such as increased leakage, thus affecting the normal operation of the pixel circuit. However, for polymer dispersed liquid crystal (PDLC) materials, the orientation change of the liquid crystal droplets within the polymer matrix depends on the electric field. If the data voltage is insufficient, the generated electric field strength is insufficient, and the optical axis orientation of the liquid crystal droplets cannot be effectively changed, thereby preventing the PDLC from achieving the transition from a scattered state to a transparent state.

[0038] In view of the above research findings of the inventors, in order to solve the problems of the prior art, the embodiments of the present invention provide a pixel circuit and a driving method thereof and a liquid crystal display device.

[0039] Figure 1 It is a structural schematic diagram of a liquid crystal display device provided by an embodiment of the present invention. Figure 2 Schematic diagram of a pixel circuit according to an embodiment of the present invention. Figure 1 and Figure 2 The liquid crystal display device includes a display panel 01 and a display driver module 02. The display driver module 02 can be a display driver chip (Display Driver Integrated Circuit, DDIC) or a touch and display driver integration (Touch and Display Driver Integration, TDDI) chip, etc.

[0040] The display panel 01 may include a display area AA and a non-display area NAA. The display area AA includes a plurality of pixels 10 arranged in an array.

[0041] The display panel 01 also includes a plurality of scan lines GL and a gate drive circuit 11. The plurality of scan lines GL extend along the first direction X and are arranged in sequence along the second direction Y. Each scan line GL is connected to the corresponding row (which may be one or more rows) of pixels 10. The gate drive circuit 11 is connected to the plurality of scan lines GL, and the gate drive circuit 11 may be located in the non-display area NAA. The display panel 01 also includes a plurality of data lines DL extending along the second direction Y and arranged along the first direction X. Each data line DL is connected to the corresponding column (which may be one or more columns) of pixel circuits 10. The first direction X (which may be the row direction) and the second direction Y (which may be the column direction) intersect, for example, may be perpendicular. A column of pixel circuits 10 may also be connected to two corresponding data lines, which is not specifically limited in the embodiments of the present invention.

[0042] The display panel 01 further includes a pixel electrode 102 and a common electrode 103. Under the control of the scan line GL signal, the pixel circuit 10 receives the data voltage Vdata from the data line DL, processes and transmits it to control the potential of the pixel electrode 102, thereby controlling the display state of the pixel.

[0043] More specifically, when the scan signal on the corresponding scan line GL is at an active level, each row of pixels receives a data signal from the data line DL. This signal, transmitted through the pixel circuit 10, ultimately changes the potential of the pixel electrode 102. After the pixel electrode 102 receives the data voltage Vdata, combined with the fixed voltage Vcom on the common electrode 103, an electric field is formed between the pixel electrode 102 and the common electrode 103. This electric field drives the liquid crystal molecules to deflect, thereby changing the display state of the pixel and displaying images or text. When the electric field strength changes, the orientation of the liquid crystal molecules also changes accordingly. For example, when a high voltage is applied to the pixel electrode 102, the liquid crystal molecules deflect more toward the direction of the electric field; conversely, when a low voltage is applied to the pixel electrode 102, the degree of deflection is also less. By controlling the orientation of the liquid crystal molecules, the optical properties of the liquid crystal layer, such as its transmittance and refractive index, can be altered, thereby achieving the display function.

[0044] Continue to refer Figure 2 The pixel circuit 10 includes: a data writing module 110, a first voltage transmission module 120, a second voltage transmission module 130 and a storage module 140.

[0045] The data writing module 110 is connected to the first end a of the storage module 140, and the data writing module 110 is used to transmit the data voltage to the first end a of the storage module 140; the first voltage transmission module 120 is connected to the second end b of the storage module 140, and the first voltage transmission module 120 is used to transmit the first voltage V1 to the second end b of the storage module 140; the second voltage transmission module 130 is connected to the second end b of the storage module 140, and the second voltage transmission module 130 is used to transmit the second voltage V2 to the second end b of the storage module 140.

[0046] Specifically, the driving phase of the pixel circuit 10 includes alternating first and second driving frames. The first driving frame includes a first data writing phase and a first phase, and the second driving frame includes a second data writing phase and a second phase.

[0047] During the first data writing phase, the data writing module 110 and the first voltage transmission module 120 are turned on, and the second voltage transmission module 130 is turned off. The data voltage Vdata on the data line Data is written to the first terminal a (i.e., the pixel electrode 102) of the storage module 140 via the data writing module 110, and the first voltage V1 on the first power line Vcom1 is written to the second terminal b (hereinafter referred to as the first electrode) of the storage module 140 via the first voltage transmission module 120. At this time, the voltage Va at the first terminal a of the storage module 140 equals Vdata, i.e., the voltage on the pixel electrode 102 is the data voltage Vdata, and the voltage Vb at the second terminal b of the storage module 140 equals V1, i.e., the voltage of the first electrode is the first voltage V1.

[0048] In the first phase, the data writing module 110 and the second voltage transmission module 130 are turned off, while the first voltage transmission module 120 remains on to maintain the voltage of the first electrode at the first voltage V1. In other words, in the first driving frame, the pixel electrode 102 is charged with the data voltage Vdata. At this time, the voltage of the pixel electrode 102 can be negative relative to the fixed voltage Vcom of the common electrode, which causes the liquid crystal molecules to be in a specific deflection state.

[0049] During the second data writing phase, the data writing module 110 and the first voltage transmission module 120 are turned on, the second voltage transmission module 130 is turned off, the data voltage Vdata on the data line Data is written to the pixel electrode 102 via the data writing module 110, and the first voltage V1 on the first power line Vcom1 is written to the first electrode via the first voltage transmission module 120. At this time, the voltage Va at the first terminal a of the storage module 140 is equal to Vdata, i.e., the voltage of the pixel electrode 102 is the data voltage Vdata, and the voltage Vb at the second terminal b of the storage module 140 is equal to V1, i.e., the voltage of the first electrode is the first voltage V1.

[0050] In the second phase, the data writing module 110 and the first voltage transmission module 120 switch from an on state to an off state, and the second voltage transmission module 130 switches from an off state to an on state. The first voltage V2 on the second power line Vcom2 is written to the first electrode via the second voltage transmission module 130, causing the voltage of the first electrode to jump from the first voltage V1 to the second voltage V2, with the jump voltage VT1 = V2 - V1. The storage module 140 couples the jump voltage VT1 to the pixel electrode 102, causing the voltage of the pixel electrode 102 to jump from the data voltage Vdata to Vdata + VT1, thereby increasing the voltage of the pixel electrode 102. In other words, in the second drive frame, the pixel electrode 102 is charged with Vdata + VT1. At this time, the voltage of the pixel electrode 102 can be positive relative to the fixed voltage Vcom of the common electrode 103, causing the liquid crystal molecules to enter a deflection state different from that in the first drive frame. By continuously alternating between the first and second drive frames, the voltage of the pixel electrode 102 continuously changes, and the deflection state of the liquid crystal molecules also changes accordingly, thereby achieving dynamic control of the liquid crystal display. Each switch of the drive frame will bring about a change in the orientation of the liquid crystal molecules, thereby causing changes in optical properties such as light transmittance and refractive index, ultimately achieving dynamic display of the picture.

[0051] Optionally, the storage module 140 includes a storage capacitor, a first end of the storage capacitor serves as a first end a of the storage module 140 , and a second end of the storage capacitor Cst serves as a second end b of the storage module 140 .

[0052] The pixel circuit provided by an embodiment of the present invention includes a data writing module, a first voltage transmission module, a second voltage transmission module, and a storage module. By controlling the data writing module and the first voltage transmission module to switch from an on state to an off state, and the second voltage transmission module to switch from an off state to an on state in the second phase of the second drive frame, the voltage of the first electrode can be jumped from the first voltage to the second voltage, and the jump voltage is coupled to the pixel electrode through the storage module, thereby increasing the voltage of the pixel electrode. In other words, by converting the data voltage of the pixel electrode into a voltage higher than the data voltage in the second phase of the second drive frame, a sufficiently strong electric field change can be formed between the pixel electrode and the common electrode. This electric field change is sufficient to drive the reorientation of the liquid crystal molecules of the PDLC material, change the optical properties of the liquid crystal layer such as the transmittance and refractive index of light, meet the conditions required for the PDLC material to display, and thus realize the driving of the PDLC material display.

[0053] Figure 3 This is a driving timing diagram of a pixel circuit provided by an embodiment of the present invention. Figure 2 and Figure 3 , the driving phase of the pixel circuit 10 includes alternating first driving frames F1 and second driving frames F2.

[0054] The first driving frame F1 includes a first data writing phase t1 and a first phase t2 , and the second driving frame F2 includes a second data writing phase t3 and a second phase t4 .

[0055] The data writing module 110 is configured to be turned on in the first data writing phase t1 and the second data writing phase t3 and turned off in the first phase t2 and the second phase t4 to transmit the data voltage Vdata to the first terminal a of the storage module 140 .

[0056] The first voltage transmission module 120 is configured to be turned on in the first data writing phase t1 , the first phase t2 , and the second data writing phase t3 , and turned off in the second phase t4 , so as to transmit the first voltage V1 to the first electrode.

[0057] The second voltage transmission module 130 is configured to be turned on in the second phase t4 and turned off in the first data writing phase t1 , the first phase t2 , and the second data writing phase t3 , so as to transmit the second voltage V2 to the first electrode.

[0058] Specifically, in the first data writing phase t1, the data writing module 110 is turned on in response to the first scan signal on the first scan line S1, the first voltage transmission module 120 is turned on in response to the second scan signal on the second scan line S2, and the second voltage transmission module 130 is turned off in response to the third scan signal on the third scan line S3. The data voltage Vdata on the data line Data is written to the pixel electrode 102 via the data writing module 110, and the first voltage V1 on the first power line Vcom1 is written to the first electrode via the first voltage transmission module 120. At this time, the voltage Va at the first terminal of the storage module 140 is equal to Vdata, i.e., the voltage of the pixel electrode 102 is the data voltage Vdata, and the voltage Vb at the second terminal of the storage module 140 is equal to V1, i.e., the voltage of the first electrode is the first voltage V1.

[0059] In the first phase t2, the data writing module 110 is turned off in response to the first scan signal on the first scan line S1, the second voltage transmission module 130 is turned off in response to the third scan signal on the third scan line S3, and the first voltage transmission module 120 is turned on in response to the second scan signal on the second scan line S2, thereby maintaining the voltage of the first electrode at the first voltage V1. In other words, in the first drive frame, the pixel electrode 102 is charged with the data voltage Vdata. At this time, the voltage of the pixel electrode 102 can be negative relative to the fixed voltage Vcom of the common electrode 103, which causes the liquid crystal molecules to be in a specific deflection state.

[0060] In the second data writing phase t3, the data writing module 110 is turned on in response to the first scan signal on the first scan line S1, the first voltage transmission module 120 is turned on in response to the second scan signal on the second scan line S2, and the second voltage transmission module 130 is turned off in response to the third scan signal on the third scan line S3. The data voltage Vdata on the data line Data is written to the pixel electrode 102 via the data writing module 110, and the first voltage V1 on the first power line Vcom1 is written to the first electrode via the first voltage transmission module 120. At this time, the voltage Va at the first terminal of the storage module 140 is equal to Vdata, i.e., the voltage of the pixel electrode 102 is the data voltage Vdata, and the voltage Vb at the second terminal of the storage module 140 is equal to V1, i.e., the voltage of the first electrode is the first voltage V1.

[0061] In the second phase t4, the first scan signal on the first scan line S1 and the second scan signal on the second scan line S2 transition from a high level to a low level, meaning that the data writing module 110 and the first voltage transmission module 120 transition from an on state to an off state. The third scan signal on the third scan line S3 transitions from a low level to a high level, and the second voltage transmission module 130 transitions from an off state to an on state. The first voltage V2 on the second power line Vcom2 is written to the first electrode via the second voltage transmission module 130, causing the voltage of the first electrode to transition from the first voltage V1 to the second voltage V2, with a transition voltage VT1 = V2 - V1. The storage module 140 couples the transition voltage VT1 to the pixel electrode 102, causing the voltage of the pixel electrode 102 to transition from the data voltage Vdata to Vdata + VT1, thereby increasing the voltage of the pixel electrode 102. That is, in the second driving frame, the pixel electrode 102 is charged with Vdata+VT1. At this time, the voltage of the pixel electrode 102 can be positive relative to the fixed voltage Vcom of the common electrode 103, so that the liquid crystal molecules are in a deflection state different from that in the first driving frame.

[0062] Optionally, continue to refer to Figure 3 The first stage t2 is located between the first data writing stage t1 and the second data writing stage t3, and the second stage t4 is located after the second data writing stage t3.

[0063] Specifically, during the first phase t2, the first voltage transmission module 120 continues to conduct to maintain the voltage of the first electrode at the first voltage V1. This voltage stability phase between the two data writing phases helps avoid voltage fluctuations that may be caused by frequent voltage switching and writing operations. Stable voltage transmission is crucial to the normal operation of the entire circuit system. It ensures that the storage module 140 and the pixel electrode 102 connected thereto can operate in a stable voltage environment, reducing display anomalies that may be caused by voltage instability.

[0064] Optionally, continue to refer to Figure 3 The starting time of the second phase t4 is the same as the ending time of the second data writing phase t3, and the ending time of the second phase t4 is the same as the starting time of the first data writing phase t1.

[0065] Specifically, when the start time of the second phase t4 coincides with the end time of the second data writing phase t3, the process from data writing to voltage transition is seamless. After the end of the second data writing phase t3, the voltage of the first electrode can immediately transition from the first voltage V1 to the second voltage V2 according to the setting of the second phase t4, with the transition voltage VT1 = V2 - V1. The storage module 140 couples the transition voltage VT1 to the pixel electrode 102, causing the voltage of the pixel electrode 102 to transition from the data voltage Vdata to Vdata + VT1. This instantaneous transition effectively avoids voltage fluctuation interference that may occur due to the intermediate interval. For example, in a liquid crystal display, if the voltage change of the pixel electrode 102 is not timely, it may cause the liquid crystal molecules to transition unstablely between two states, affecting the clarity and accuracy of the display. This seamless transition ensures that the voltage change of the pixel electrode 102 is consistent, allowing the liquid crystal molecules to quickly and stably enter the next deflection state. The end time of the second phase t4 coincides with the start time of the first data writing phase t1, ensuring efficient utilization of the entire working cycle. This tight schedule ensures that each stage is closely coordinated and reduces idle time.

[0066] Optionally, the first voltage V1 is less than the second voltage V2. Exemplarily, the first voltage V1 is -15V, and the second voltage V2 is 15V.

[0067] Optionally, the data voltage Vdata is 0V or 10V. In a liquid crystal display device, the data voltage Vdata is used to control the deflection state of the liquid crystal molecules, thereby affecting the display effect. After the input image signal is processed, the driver chip determines the data voltage Vdata of the pixel electrode 102 corresponding to each pixel based on the pixel information of the image. For example, for a black and white image, the data voltage Vdata of the pixel electrode 102 corresponding to the black pixel may be set to 0V, and the data voltage Vdata of the pixel electrode 102 corresponding to the white pixel may be set to 10V. For color images, the color information of each pixel may be converted into a corresponding data voltage value to drive the liquid crystal molecules through more complex color space conversion and brightness adjustment algorithms to achieve accurate color display.

[0068] Figure 4 This is a schematic diagram of liquid crystal flipping provided by an embodiment of the present invention. Figure 5 This is another liquid crystal flip schematic diagram provided by an embodiment of the present invention. Figure 4 As shown, in the first driving frame, when the data voltage Vdata is 10V and the fixed voltage Vcom is 20V, that is, the voltage difference between the pixel electrode 102 and the common electrode 103 is 10V, the liquid crystal molecules switch from transparent to opaque. Figure 5 As shown, in the first driving frame, when the data voltage Vdata is 0V and the fixed voltage Vcom is 20V, that is, the voltage difference between the pixel electrode 102 and the common electrode 103 is 20V, the liquid crystal molecules switch from opaque to transparent.

[0069] like Figure 4 As shown in FIG. 1 , in the second driving frame, when the data voltage Vdata is 0V, the first voltage V1 is -15V, the second voltage V2 is 15V, and the fixed voltage Vcom is 20V, that is, the voltage on the pixel electrode 102 is 30V, and the voltage difference between the pixel electrode 102 and the common electrode 103 is 10V, the liquid crystal molecules switch from transparent to opaque. Figure 5 As shown, in the second driving frame, when the data voltage Vdata is 10V, the first voltage V1 is -15V, the second voltage V2 is 15V, and the fixed voltage Vcom is 20V, that is, the voltage of the pixel electrode 102 is 40V, and the voltage difference between the pixel electrode 102 and the common electrode 103 is 20V, the liquid crystal molecules switch from opaque to transparent.

[0070] Figure 6 FIG. 1 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention. Figure 6 As shown, the data writing module 110 includes a first transistor T1 , a gate of which is connected to the first scan line S1 , a first electrode of which is connected to the data line, and a second electrode of which is connected to the first terminal a of the storage module 140 .

[0071] Specifically, the first transistor T1 can be an N-type transistor or a P-type transistor. By controlling the first scan signal on the first scan line S1, the data voltage Vdata can be written to the pixel electrode 102 row by row or pixel by pixel, thereby controlling the voltage of the pixel electrode 102 in each pixel. When the first scan signal on the first scan line S1 is at an active level, the first transistor T1 is turned on; when the first scan signal on the first scan line S1 is at an inactive level, the first transistor T1 is turned off.

[0072] Optionally, the first transistor T1 is a dual-gate transistor, comprising a first sub-transistor T1-1 and a second sub-transistor T1-2. A gate of the first sub-transistor T1-1 and a gate of the second sub-transistor T1-2 are both connected to the first scan line S1, a first electrode of the first sub-transistor T1-1 is connected to the data line Data, a second electrode of the first sub-transistor T1-1 is connected to the first electrode of the second sub-transistor T1-2, and a second electrode of the second sub-transistor T1-2 is connected to the first terminal a of the storage module 140.

[0073] Figure 7 FIG. 1 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention. Figure 7 As shown, the first voltage transmission module 120 includes a second transistor T2.

[0074] A gate of the second transistor T2 is connected to the second scan line S2 , a first electrode of the second transistor T2 is connected to the first power line Vcom1 , and a second electrode of the second transistor T2 is connected to the second end b of the storage module 140 .

[0075] Specifically, when the second scan signal on the second scan line S2 becomes a valid signal, the second transistor T2 is turned on, and the first voltage V1 on the first power line Vcom1 is transmitted from the first electrode to the second electrode of the second transistor T2 and then written into the first electrode.

[0076] Optionally, the second transistor T2 is a dual-gate transistor, and includes a third sub-transistor T2-1 and a fourth sub-transistor T2-2. The gates of the third sub-transistor T2-1 and the fourth sub-transistor T2-2 are both connected to the second scan line S2, a first electrode of the third sub-transistor T2-1 is connected to the first power line Vcom1, a second electrode of the third sub-transistor T2-1 is connected to the first electrode of the fourth sub-transistor T2-2, and a second electrode of the fourth sub-transistor T2-2 is connected to the second terminal b of the storage module 141.

[0077] Specifically, by configuring the second transistor T2 as a dual-gate transistor, leakage current from the source to the drain of the second transistor T2 can be reduced after the second transistor T2 is turned off, thereby maintaining the stability of the voltage at the second terminal of the storage module 140. Furthermore, the gates of the third sub-transistor T2-1 and the fourth sub-transistor T2-2 are connected to the same scan line (the second scan line S2), enabling the third sub-transistor T2-1 and the fourth sub-transistor T2-2 to be turned on or off simultaneously. The specific operating process can be found in the relevant description of the above technical solution and will not be repeated here.

[0078] Figure 8 FIG. 1 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention. Figure 8As shown, the second voltage transmission module 130 includes a third transistor T3 , a gate of which is connected to the third scan line S3 , a first electrode of which is connected to the second power line Vcom2 , and a second electrode of which is connected to the second terminal b of the storage module 140 .

[0079] Specifically, when the third scan signal on the third scan line S3 becomes a valid signal, the third transistor T3 is turned on, and the second voltage V2 on the second power line Vcom2 is transmitted from the first electrode to the second electrode of the third transistor T3 and then written into the first electrode.

[0080] Optionally, the third transistor T3 is a dual-gate transistor and includes a fifth sub-transistor T3-1 and a sixth sub-transistor T3-2. The gates of the fifth sub-transistor T3-1 and the sixth sub-transistor T3-2 are both connected to the third scan line S3. A first electrode of the fifth sub-transistor T3-1 is connected to the second power line Vcom2. A second electrode of the fifth sub-transistor T3-1 is connected to the first electrode of the sixth sub-transistor T3-2. A second electrode of the sixth sub-transistor T3-2 is connected to the second terminal b of the storage module 140.

[0081] Specifically, by configuring the third transistor T3 as a dual-gate transistor, leakage current from the source to the drain of the third transistor T3 can be reduced after the third transistor T3 is turned off, thereby maintaining the stability of the voltage at the second terminal of the storage module 140. Furthermore, the gates of the fifth sub-transistor T3-1 and the sixth sub-transistor T3-2 are connected to the same scan line (the third scan line S3), enabling the fifth sub-transistor T3-1 and the sixth sub-transistor T3-2 to be turned on or off simultaneously. The specific operating process can be found in the relevant description of the above technical solution and will not be repeated here.

[0082] Optionally, the storage module 140 includes a storage capacitor Cst, a first end of the storage capacitor Cst serves as a first end a of the storage module 140 , and a second end of the storage capacitor Cst serves as a second end b of the storage module 140 .

[0083] Optionally, the inactive level is a level signal that turns off the transistor; the active level is a control signal that turns on the transistor. When the transistor is an N-type transistor, the active level is greater than zero potential, that is, the voltage value of the active level is greater than 0; the inactive level is less than zero potential, that is, the voltage value of the inactive level is less than 0. When the transistor is a P-type transistor, the active level is less than zero potential, that is, the voltage value of the active level is less than 0; the inactive level is greater than zero potential, that is, the voltage value of the inactive level is greater than 0.

[0084] Figure 9 FIG. 1 is a schematic diagram of another pixel circuit provided by an embodiment of the present invention. Figure 9As shown, the pixel circuit includes: a data writing module 110 , a first voltage transmission module 120 , a second voltage transmission module 130 and a storage module 140 .

[0085] Optionally, the data writing module 110 includes a first transistor T1. The first transistor T1 is a dual-gate transistor and includes a first sub-transistor T1-1 and a second sub-transistor T1-2. The first voltage transmission module 120 includes a second transistor T2. The second transistor T2 is a dual-gate transistor and includes a third sub-transistor T2-1 and a fourth sub-transistor T2-2. The second voltage transmission module 130 includes a third transistor T3. The third transistor T3 includes a fifth sub-transistor T3-1 and a sixth sub-transistor T3-2. The storage module 140 includes a storage capacitor Cst.

[0086] Figure 10 This is a simulation diagram provided by an embodiment of the present invention. Figure 9 and Figure 10 When the data voltage Vdata is 0V or 10V, in the first drive frame F1, the voltage Vn2 of the second node n2 is 0V, and the voltage Vn3 of the third node n3 is -15V. In the second drive frame F2, the voltage Vn2 of the second node n2 is -20V, and the voltage Vn3 of the third node n3 is 20V. At the start of each frame, the voltage Vn1 of the first node n1 jumps from -5V to 25V. At the beginning of each frame, the first scan signal on the first scan line S1 connected to the first sub-transistor T1-1 and the second sub-transistor T1-2 jumps from the inactive level to the active level, causing the conduction state of the first sub-transistor T1-1 and the second sub-transistor T1-2 to change, thereby changing the voltage source connection status of the first node n1, causing the voltage of the first node n1 to jump from -5V to 25V.

[0087] Based on the same inventive concept, an embodiment of the present invention further provides a method for driving a pixel circuit, which is used to drive the pixel circuit provided by any embodiment of the present invention. Figure 11 This is a flowchart of a driving method of a pixel circuit provided by an embodiment of the present invention. Figure 11 , the driving method of the pixel circuit includes:

[0088] S110 , controlling the data writing module to be turned on to transmit the data voltage to the first terminal of the storage module.

[0089] S120 , controlling the first voltage transmission module to be turned on to transmit the first voltage to the second end of the storage module.

[0090] S130: Control the second voltage transmission module to be turned on to transmit the second voltage to the second end of the storage module.

[0091] The specific working principle of the driving method of the pixel circuit provided in this embodiment can refer to the description of the pixel circuit in any of the above embodiments, and has the same beneficial effects as described in any of the above embodiments, which will not be repeated here.

[0092] Optionally, an embodiment of the present invention further provides a liquid crystal display device, including the pixel circuit provided by any of the above embodiments, so that the liquid crystal display device also has the beneficial effects described in any of the above embodiments. In this embodiment, the liquid crystal display device can be applied to mobile phones, and can also be applied to any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiment of the present invention does not specifically limit this.

[0093] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A pixel circuit, characterized in that: include: A data writing module, a first voltage transmission module, a second voltage transmission module and a storage module; The data writing module is connected to the first end of the storage module, and the data writing module is used to transmit the data voltage to the first end of the storage module; The first voltage transmission module is connected to the second end of the storage module, and the first voltage transmission module is used to transmit the first voltage to the second end of the storage module; The second voltage transmission module is connected to the second end of the storage module, and is used to transmit a second voltage to the second end of the storage module.

2. The pixel circuit according to claim 1, wherein: The driving phase of the pixel circuit includes alternating first driving frames and second driving frames; The first driving frame includes a first data writing phase and a first phase, and the second driving frame includes a second data writing phase and a second phase; The data writing module is configured to be turned on in the first data writing phase and the second data writing phase, and turned off in the first phase and the second phase, so as to transmit the data voltage to the first end of the storage module; The first voltage transmission module is configured to be turned on during the first data writing phase, the first phase, and the second data writing phase, and turned off during the second phase, so as to transmit the first voltage to the second end of the storage module; The second voltage transmission module is configured to be turned on in the second phase and turned off in the first data writing phase, the first phase, and the second data writing phase, so as to transmit the second voltage to the second end of the storage module.

3. The pixel circuit according to claim 2, wherein: The first phase is located between the first data writing phase and the second data writing phase, and the second phase is located after the second data writing phase.

4. The pixel circuit according to claim 3, wherein: The start time of the second phase is the same as the end time of the second data writing phase, and the end time of the second phase is the same as the start time of the first data writing phase.

5. The pixel circuit according to claim 1, wherein: The first voltage is less than the second voltage; Preferably, the first voltage is -15V; Preferably, the second voltage is 15V; Preferably, the data voltage is 0V or 10V.

6. The pixel circuit according to claim 1, wherein: The data writing module includes a first transistor; The gate of the first transistor is connected to the first scan line, the first electrode of the first transistor is connected to the data line, and the second electrode of the first transistor is connected to the first end of the storage module; Preferably, the first transistor is a dual-gate transistor, and the first transistor includes a first sub-transistor and a second sub-transistor; The gate of the first sub-transistor and the gate of the second sub-transistor are both connected to the first scan line, the first electrode of the first sub-transistor is connected to the data line, the second electrode of the first sub-transistor is connected to the first electrode of the second sub-transistor, and the second electrode of the second sub-transistor is connected to the first end of the storage module.

7. The pixel circuit according to claim 1, wherein: The first voltage transmission module includes a second transistor; The gate of the second transistor is connected to the second scan line, the first electrode of the second transistor is connected to the first power line, and the second electrode of the second transistor is connected to the second end of the storage module; Preferably, the second transistor is a dual-gate transistor, and the second transistor includes a third sub-transistor and a fourth sub-transistor; The gate of the third sub-transistor and the gate of the fourth sub-transistor are both connected to the second scan line, the first electrode of the third sub-transistor is connected to the first power line, the second electrode of the third sub-transistor is connected to the first electrode of the fourth sub-transistor, and the second electrode of the fourth sub-transistor is connected to the second end of the storage module.

8. The pixel circuit according to claim 1, wherein: The second voltage transmission module includes a third transistor; The gate of the third transistor is connected to the third scan line, the first electrode of the third transistor is connected to the second power line, and the second electrode of the third transistor is connected to the second end of the storage module; Preferably, the third transistor is a dual-gate transistor, and the third transistor includes a fifth sub-transistor and a sixth sub-transistor; The gate of the fifth sub-transistor and the gate of the sixth sub-transistor are both connected to the third scan line, the first electrode of the fifth sub-transistor is connected to the second power line, the second electrode of the fifth sub-transistor is connected to the first electrode of the sixth sub-transistor, and the second electrode of the sixth sub-transistor is connected to the second end of the storage module. Preferably, the storage module includes a storage capacitor, a first end of the storage capacitor serves as the first end of the storage module, and a second end of the storage capacitor serves as the second end of the storage module.

9. A method for driving a pixel circuit, characterized in that: The pixel circuit includes a data writing module, a first voltage transmission module, a second voltage transmission module and a storage module; the data writing module is connected to the first end of the storage module, the first voltage transmission module is connected to the second end of the storage module, and the second voltage transmission module is connected to the second end of the storage module; The driving method includes: Controlling the data writing module to be turned on to transmit the data voltage to the first end of the storage module; controlling the first voltage transmission module to be turned on to transmit the first voltage to the second end of the storage module; The second voltage transmission module is controlled to be turned on to transmit the second voltage to the second end of the storage module.

10. A liquid crystal display device, characterized in that: The method comprises the pixel circuit according to any one of claims 1 to 8.

Images