Semiconductor device

Abstract

A semiconductor device includes a variable resistance memory cell array, a sense amplifier electrically connected to the variable resistance memory cell array, and a clamp voltage generation circuit electrically connected to the sense amplifier. The sense amplifier includes an amplifying unit that amplifies a voltage at a sense node, a first clamp circuit having a first NMOS transistor and a second NMOS transistor, the gate terminals of which are electrically connected, a second clamp circuit having a third NMOS transistor and a fourth NMOS transistor, the gate terminals of which are electrically connected, a fifth NMOS transistor electrically connected to the variable resistance memory cell array, a reference resistor, and a sixth NMOS transistor electrically connected to the reference resistor. The first NMOS transistor and the third NMOS transistor are connected in series between the sensing node and the fifth NMOS transistor, and the second NMOS transistor and the fourth NMOS transistor are connected in series between the sensing node and the sixth NMOS transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2024-018536 filed on February 9, 2024 (including specification, drawings and abstract) is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device, and, for example, to a semiconductor device including a memory device having a variable resistance memory cell. Background Art

[0004] The disclosed technologies are listed below.

[0005] [Non-Patent Literature 1] “A Reflow-capable, Embedded 8Mb STT-MRAM Macro with 9nS Read Access Time in 16nm FinFET Logic CMOS Process”, TSMC, IEDM 2020

[0006] A variable resistance memory cell indicates a storage element whose resistance value changes according to stored information, and an example of a memory device including such a variable resistance memory cell (hereinafter also referred to as a memory cell) includes a magnetoresistive memory (magnetoresistive random access memory, hereinafter also referred to as MRAM). For example, Non-Patent Document 1 discloses a technology related to MRAM. Summary of the Invention

[0007] The present inventors have studied technologies related to the MRAM described in Non-Patent Document 1. Their research will be described later in a comparative example and will therefore be omitted here. However, they have discovered that the technology disclosed in Non-Patent Document 1 has a problem of difficulty in achieving both high-speed operation and stable operation at high temperatures.

[0008] The following briefly describes an overview of representative embodiments of the embodiments disclosed in this application. In the following description, field effect transistors are also referred to as MOS transistors, N-channel MOS transistors are also referred to as NMOS transistors, and P-channel MOS transistors are also referred to as PMOS transistors.

[0009] A semiconductor device according to one embodiment includes a variable resistance memory cell array, a sense amplifier electrically connected to the variable resistance memory cell array, and a clamp voltage generating circuit electrically connected to the sense amplifier.

[0010] In the semiconductor device, the sense amplifier includes an amplifying unit configured to amplify a voltage at a sensing node, a first clamping circuit having a first NMOS transistor and a second NMOS transistor whose gate terminals are electrically connected to each other, a second clamping circuit having a third NMOS transistor and a fourth NMOS transistor whose gate terminals are electrically connected to each other, a fifth NMOS transistor electrically connected to the variable resistance memory cell array, a reference resistor, and a sixth NMOS transistor electrically connected to the reference resistor.

[0011] Here, a drain terminal of the third NMOS transistor is electrically connected to the amplifying unit via a first node constituting a sensing node, a drain terminal of the fourth NMOS transistor is electrically connected to the amplifying unit via a second node constituting a sensing node, a source terminal of the third NMOS transistor is electrically connected to the drain terminal of the first NMOS transistor via a third node, a source terminal of the fourth NMOS transistor is electrically connected to the drain terminal of the second NMOS transistor via a fourth node, a source terminal of the first NMOS transistor is electrically connected to the drain terminal of the fifth NMOS transistor via a fifth node, a source terminal of the second NMOS transistor is electrically connected to the drain terminal of the sixth NMOS transistor via a sixth node, a source terminal of the fifth NMOS transistor is electrically connected to the variable resistance memory cell array, a source terminal of the sixth NMOS transistor is electrically connected to a reference resistor, a clamp voltage generating circuit supplies a first clamp voltage to gate terminals of the first and second NMOS transistors and supplies a second clamp voltage to gate terminals of the third and fourth NMOS transistors, and transconductances of the third and fourth NMOS transistors are lower than transconductances of the first and second NMOS transistors.

[0012] Other issues and novel features will become clear from the description of this specification and the accompanying drawings.

[0013] According to one embodiment, a semiconductor device including a memory device capable of achieving both high-speed operation and stable operation can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1A and Figure 1B is a diagram for describing a sense amplifier according to a first embodiment;

[0015] Figure 2 is a circuit diagram illustrating the configuration of a clamp circuit and a clamp voltage generating circuit according to the first embodiment;

[0016] Figure 3 is a circuit diagram illustrating the configuration of a clamp circuit and a clamp voltage generating circuit according to the first embodiment;

[0017] Figure 4 is a circuit diagram illustrating a configuration of a current correction circuit according to a first embodiment;

[0018] Figure 5 is a diagram for describing a current correction circuit according to a first embodiment;

[0019] Figure 6 is a diagram for describing a current correction circuit according to a first embodiment;

[0020] Figure 7 is a diagram for describing an initialization circuit according to a first embodiment;

[0021] Figure 8A and Figure 8B is a waveform diagram for describing the initialization circuit according to the first embodiment;

[0022] Figure 9 is a circuit diagram illustrating an example of an initialization circuit according to the first embodiment;

[0023] Figure 10 is a circuit diagram illustrating a configuration of a reference resistor according to a second embodiment;

[0024] Figure 11 is a circuit diagram illustrating a configuration of a reference resistor according to a modification of the second embodiment;

[0025] Figure 12A and Figure 12B is a diagram for describing a semiconductor device according to a second embodiment;

[0026] Figure 13 is a block diagram illustrating a configuration of a nonvolatile memory device included in the semiconductor device according to the first embodiment;

[0027] Figure 14 is a block diagram illustrating the configuration of a semiconductor device according to a first embodiment;

[0028] Figure 15A and Figure 15B is a diagram for describing comparative examples studied by the present inventors;

[0029] Figure 16 is a diagram illustrating mathematical expressions for describing comparative examples; and

[0030] Figure 17 is a circuit diagram illustrating the configuration of a reference resistor indicating a comparative example studied by the present inventors. DETAILED DESCRIPTION

[0031] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Note that the present disclosure is merely an example, and appropriate modifications that can be easily conceived by those skilled in the art while maintaining the gist of the present invention are naturally included in the scope of the present invention.

[0032] Furthermore, in this specification and each drawing, elements similar to those previously described with respect to the previously described drawing are denoted by the same reference numerals, and detailed description thereof may be appropriately omitted.

[0033] <Comparative Example>

[0034] Hereinafter, a plurality of embodiments will be described. To facilitate understanding of the embodiments, before describing the embodiments, the technology disclosed in Non-Patent Document 1 and the problems found by the present inventors will be described using comparative examples.

[0035] <<Comparison Example Configuration and Operation>>

[0036] Figure 15A and Figure 15B is a diagram for describing comparative examples studied by the present inventors. Figure 15A and Figure 15B Similar to Non-Patent Document 1 Figure 6 The main difference is that in Figure 15A and Figure 15B In order to facilitate the description, the present inventors in the non-patent document 1 Figure 6 In the figure, additional reference numerals are added (for example, Vthn, etc.). Figure 15A and Figure 15B middle, Figure 15A A circuit diagram of a comparative example is shown. Figure 15B It is an icon Figure 15A The waveform diagram of the operation.

[0037] here, Figure 15A The circuit diagram illustrates portions related to a sense amplifier used when reading information stored in a memory cell.

[0038] The sense amplifier includes a latch unit Latch and a precharge circuit. The latch unit is connected to a pair of sensing nodes Q and QB. When activated by an activation signal LATCH, the latch unit amplifies the small potential difference between the sensing nodes Q and QB and outputs the amplified potential difference as the output DOUT. The precharge circuit is composed of PMOS transistors PP1 to PP3.

[0039] The potentials of the pair of sensing nodes Q and QB are determined by the memory cell and the reference resistor. Figure 15AIn the embodiment of the present invention, the memory cell is equivalently represented by the current source Icell, and the reference resistor is equivalently represented by the current source Iref. Depending on the stored information, the resistance value (cell resistance) of the memory cell is in a state of low resistance Rp or high resistance Rap (low resistance Rp < high resistance Rap). Therefore, the value of the current source Icell equivalently representing the memory cell changes according to the stored information. The value of the current source Iref equivalently representing the reference resistor is a value (e.g., an intermediate value) between the value of the current source Icell corresponding to the high resistance and the value of the current source Icell corresponding to the low resistance.

[0040] The clamp element is connected between a pair of sensing nodes Q and QB and a memory cell (current source Icell) and a reference resistor (current source Iref). The clamp element is composed of NMOS transistors NN1 and NN2 whose gate terminals are supplied with a clamp voltage Vclamp. Figure 15A , Vthn indicates the threshold voltage of NMOS transistors NN1 and NN2, and Vbl indicates the voltage applied to the memory cell and the reference resistor. The value of the voltage Vbl of the memory cell varies depending on the value of the cell resistance, but can be limited (clamped) to, for example, approximately 0.1 V by appropriately setting the clamping voltage Vclamp and the threshold voltage Vthn.

[0041] As a result, even in Figure 15B In the precharge period (a period during which the PMOS transistors PP1 to PP3 are in the on state) indicated by reference symbol PTH, the voltage Vbl applied to the memory cell and the reference resistor is also clamped to about 0.1 V. Thereafter, in the discharge period (a period during which the PMOS transistors PP1 to PP3 are in the off state) indicated by reference symbol DTH, a potential difference determined by the memory cell and the reference resistor is generated between the sensing nodes Q and QB, and in the sensing period indicated by reference symbol STH, the potential difference between the sensing nodes Q and QB is amplified by the latch unit Latch.

[0042] exist Figure 15AIn the present invention, NMOS transistors NN1A to NN1X and NN2A to NN2X, and switches S1A to S1X and S2A to S2X are used to correct for variations. That is, when a relative variation occurs between the clamping element (NMOS transistor NN1) corresponding to the memory cell and the clamping element (NMOS transistor NN2) corresponding to the reference resistor, and / or when an offset occurs between the inputs of the latch unit Latch due to a variation in the latch unit Latch, one of the switches S1A to S1X and S2A to S2X (e.g., S2A) is turned on. As a result, for example, NMOS transistor NN2A is connected in parallel to the clamping element (NMOS transistor NN2) corresponding to the reference resistor, and the variation can be reduced.

[0043] When no variation correction is required, the clamp element can be formed from two NMOS transistors NN1 and NN2. This can suppress an increase in the area occupied by the clamp element even when multiple sense amplifiers are provided in the memory device. Furthermore, since the clamp voltage Vclamp can be shared by the clamp elements provided in multiple sense amplifiers, an increase in the occupied area can also be suppressed in this regard.

[0044] <<Study by the present inventor>>

[0045] Typically, in a memory cell constituting an MRAM, the resistance ratio of the resistance value corresponding to the stored information deteriorates as the ambient temperature rises. That is, depending on the stored information, the cell resistance becomes a high resistance Rap or a low resistance Rp, but the TMR ratio (i.e., the resistance ratio between the high resistance Rap and the low resistance Rp) deteriorates as the ambient temperature rises. The value of the current source Iref based on the reference resistor is set between the value of the current source Icell corresponding to the high resistance Rap and the value of the current source Icell corresponding to the low resistance Rp. However, since the resistance ratio deteriorates as the temperature rises, the current difference between the current source Iref and the current source Icell decreases, and the read margin at high temperature decreases.

[0046] exist Figure 15A and Figure 15B In the configuration of the comparative example shown, the read margin at high temperature can be improved by the following two methods.

[0047] <<<First Method>>>

[0048] The first method is to increase the transconductance (Gm) of the NMOS transistors NN1 and NN2 that form the clamp element. For example, by increasing the transconductance of NMOS transistor NN1, the conversion efficiency from cell resistance to cell current (corresponding to the current source Icell) can be improved. Therefore, even when the TMR ratio degrades due to high temperatures, a sufficient read margin can be ensured.

[0049] The following will use Figure 16 The mathematical expressions shown below describe the first method in detail. Figure 16 In Expression (1), reference symbol λ indicates the channel length modulation coefficient of the NMOS transistors NN1 to NN1X, and reference symbol Vds indicates the drain-source voltage of the NMOS transistors NN1 to NN1X.

[0050] For ease of description, assuming that the channel length modulation coefficient λ is 0 and the multiplier 2 is 1, when the cell resistance is low resistance Rp, the current Ip of the memory cell (current source Icell) is expressed by expression (2), and when the cell resistance is high resistance Rap, the current Iap of the memory cell (current source Icell) is expressed by expression (3). In expressions (2) and (3), reference symbols Vbl(p) and Vbl(ap) represent the voltage of the memory cell generated when the cell resistance is low resistance Rp and the voltage of the memory cell generated when the cell resistance is high resistance Rap, as shown in expressions (4) and (5). Expressions (6) and (7) are obtained by substituting expressions (4) and (5) into expressions (2) and (3).

[0051] As can be understood from expressions (6) and (7), as the transconductance Gm increases, the ratio of the cell resistance value to the memory cell current Ip and Iap increases. That is, when the cell resistance value changes from low resistance Rp to high resistance Rap (or from Rap to Rp), the amount of change in the cell current flowing through the memory cell can be increased, and the read margin can be ensured.

[0052] <<<Second Method>>>

[0053] As reference Figure 15A As described above, the second method is to correct the variation by using NMOS transistors NN1A to NN1X and NN2A to NN2X and switches S1A to S1X and S2A to S2X. For example, by correcting the variation, the read margin can be improved by reducing the offset between the inputs of the latch unit Latch.

[0054] <<<Problems caused by the first and second methods>>>

[0055] The transconductance Gm is determined by the ratio (W / L) of the channel width W to the channel length L of the NMOS transistor. A first method is to increase the transconductance Gm by, for example, increasing the channel width W of the NMOS transistor NN1. In this case, the overlap between the drain diffusion region and the gate terminal of the NMOS transistors NN1 and NN2 connected to the sensing nodes Q and QB increases, and the drain capacitance (capacitance formed by the overlap between the drain diffusion region and the gate terminal) of the NMOS transistors NN1 and NN2 connected to the sensing nodes Q and QB increases.

[0056] When the second method is employed, the drain diffusion regions of the correction NMOS transistors NN1A to NN1X and NN2A to NN2X are connected to the drain diffusion regions of the NMOS transistors NN1 and NN2, for example, via wiring. In other words, the wiring connecting the drain diffusion regions of the correction NMOS transistors is connected to the sensing nodes Q and QB. Therefore, even when the second method is employed, parasitic capacitance (wiring capacitance, drain capacitance of the correction NMOS transistors, etc.) connected to the sensing nodes Q and QB increases.

[0057] When the parasitic capacitance (including drain capacitance) connected to the sensing nodes Q and QB increases, it takes time for the potentials of the sensing nodes Q and QB to decrease depending on the memory cell and the reference resistor. Figure 15B , Figure 15B The discharge period DTH shown becomes long, and it becomes difficult to achieve high-speed operation of the read operation.

[0058] That is, it has been found that, in the case of achieving stable operation of MRAM by ensuring or improving the read margin at high temperature, high-speed operation is difficult to achieve, and a problem arises in that it is difficult to achieve both stable operation at high temperature and high-speed operation.

[0059] (First embodiment)

[0060] <Configuration of Semiconductor Device>

[0061] Figure 14 1 is a block diagram illustrating the configuration of a semiconductor device according to a first embodiment. Figure 14 In FIG, reference numeral 1000 indicates a semiconductor device. The semiconductor device 1000 includes an internal bus 1001 and a plurality of circuit blocks connected to the internal bus 1001. Figure 14 , as examples of a plurality of circuit blocks, a processor 1002, a volatile memory device (RAM) 1003, a nonvolatile memory device 1004, a timer 1005, an analog-to-digital conversion circuit (ADC) 1006, a digital-to-analog conversion circuit (DAC) 1007, a communication interface circuit (communication IF) 1008, and a peripheral circuit 1009 are indicated. Note that Figure 14The circuit blocks shown are examples and are not limited thereto.

[0062] For example, when the processor 1002 operates according to a program, predetermined functions are implemented by the semiconductor device 1000. To implement the predetermined functions, when the processor 1002 operates, circuit blocks connected to the internal bus 1001 (e.g., the nonvolatile memory device 1004, the peripheral circuit 1009, etc.) are accessed by the processor 1002 through the internal bus 1001.

[0063] <<Configuration of Nonvolatile Memory Devices>>

[0064] Figure 13 This is a block diagram illustrating the configuration of a nonvolatile memory device (hereinafter also referred to as a memory device) included in a semiconductor device according to the first embodiment. The nonvolatile memory device 1004 according to the first embodiment is an MRAM. The nonvolatile memory device 1004 according to the first embodiment includes a memory cell array (variable resistance memory cell array) 1100 (in which a plurality of memory cells MC11 to MCnm, etc., constituting the MRAM, are arranged in an array), an address decoder 1101, a word line driver 1102, a plurality of input / output circuits 1103_1 to 1103_k, and a control circuit 1104.

[0065] The memory cell array 1100 includes unit memory cell arrays 1100_1 to 1100_k corresponding to the input / output circuits 1103_1 to 1103_k. Since the unit memory cell arrays 1100_1 to 1100_k have the same configuration as each other, Figure 13 , only the unit memory cell array 1100_1 corresponding to the input / output circuit 1103_1 is clearly illustrated, in which the memory cells MC11 to MCnm are arranged in an array, and for other unit memory cell arrays, the memory cells, etc. are omitted. Similarly, in the unit memory cell array 1100_1, since a plurality of memory cells are arranged in an array, the unit memory cell array can also be regarded as a memory cell array.

[0066] In the memory cell array 1100, common word lines WL1 to WLn are arranged in corresponding rows, and the memory cells arranged in the same row are connected. In addition, bit lines BL1 to BLm are arranged in corresponding columns of the unit memory cell array 1100_1, and the memory cells arranged in the same column are connected. Figure 13 Although not shown in the figure, write (high resistance state) source lines SL are provided in columns to correspond to the bit lines BL1 to BLm.

[0067] Row address signals and column address signals (not shown) are received from Figure 14 The internal bus 1001 shown is supplied to the address decoder 1101, the row address signal is decoded, and the decoding result Sw1 is supplied to the word line driver 1102. In addition, the address decoder 1101 decodes the column address signal and supplies the decoding result Sbl to the input / output circuits 1103_1 to 1103 — k.

[0068] The word line driver 1102 supplies a selection voltage (e.g., a high level) to the word line indicated by the decoding result Sw1 (i.e., the word line selected by the row address signal), and supplies a non-selection voltage (e.g., a low level) to the other word lines. As a result, a plurality of memory cells connected to the word line supplied with the selection voltage are selected and electrically connected to the bit lines.

[0069] The input / output circuit 1103_1 includes a column selector CSEL, a write system circuit IBF & WTD, and a read system circuit SA & OBF. The column selector CSEL is connected to the bit lines BL1 to BLm arranged in the corresponding unit memory cell array 1100_1, selects the bit line indicated by the decoding result Sbl, that is, the bit line selected by the column address signal, sets the selected bit line as the common bit line GBL, and is connected to the write system circuit IBF & WTD and the read system circuit SA & OBF.

[0070] The write system circuits IBF and WTD, the read system circuits SA and OBF, and the control circuit 1104 are connected to Figure 14 The internal bus 1001 is shown. For example, when a write operation to the memory device 1004 is instructed from the processor 1002 via the internal bus 1001, the control circuit 1104 operates the write system circuits IBF & WTD. As a result, information from the internal bus 1001 is supplied to the bit line selected by the column address signal via the write system circuits IBF & WTD and the common bit line GBL, and is written into the memory cell connected to the bit line.

[0071] Furthermore, when a read operation on the memory device 1004 is instructed by the processor 1002, for example, via the internal bus 1001, the control circuit 1104 operates the read system circuits SA and OBF. The read system circuits SA and OBF are composed of a sense amplifier SA and an output buffer circuit OBF. Information on the common bit line GBL is amplified by the sense amplifier SA and output to the internal bus 1001 via the output buffer circuit OBF.

[0072] <<Sense Amplifier>>

[0073] Figure 1A and Figure 1B is a diagram for describing a sense amplifier according to a first embodiment. Figure 1Ais a circuit diagram illustrating the configuration of a sense amplifier, and Figure 1B is a waveform diagram illustrating the operation of the sense amplifier.

[0074] Figure 1A In addition to the sense amplifier SA, Figure 13 The main part of the control circuit 1104 is shown. In addition, Figure 1A An example is shown in the figure, in which the column selector CSEL is provided in the sense amplifier SA, but it is not limited thereto. Figure 13 As shown, the column selector CSEL may be provided between the unit memory cell array 1100_1 and the sense amplifier SA. Figure 3 As shown, a plurality of memory cells MC11 to MCnm are arranged in an array in the unit memory cell array 1100_1, but Figure 1A , one memory cell MC11 among a plurality of memory cells is drawn as a representative memory cell.

[0075] <<<Memory Cell Configuration>>>

[0076] From the representative memory cell Figure 1A The configuration of the memory cell MC11 shown can be understood as follows: the memory cell resistance element (MRAM resistance element) RM is composed of an NMOS transistor NM connected in series between the bit line BL and the wiring SL supplied with the ground voltage Vss. The resistance value of the resistance element RM changes to high resistance or low resistance depending on the stored information. The gate terminal of the NMOS transistor NM is connected to the word line WL, and when a high level indicating selection is supplied to the word line WL, the memory cell MC11 is selected, and the resistance element having a resistance value corresponding to the stored information is connected between the bit line BL and the wiring SL supplied with the ground voltage Vss via the NMOS transistor NM.

[0077] <<<Configuration of Sense Amplifier>>>

[0078] The sense amplifier SA includes PMOS transistors P1 and P2, NMOS transistors N1 to N8, a noise cancellation circuit NCC, an amplification unit SAP, a reference resistor Rref, a current correction circuit TCP, a correction information storage circuit TCP_O, and a column selector CSEL. Furthermore, the sense amplifier SA includes a cell-side sensing line SAC, a reference-side sensing line SAR, a cell-side bit line BLC, a reference-side bit line BLR, a first clamping voltage line VL1, a second clamping voltage line VL2, a correction current line TLC, a correction current line TLR, and an initial voltage line VLI.

[0079] The source terminal of PMOS transistor P1 is connected to the power supply voltage Vdd, and its drain terminal is connected to the cell-side sensing line SAC. The source terminal of PMOS transistor P2 is connected to the power supply voltage Vdd, and its drain terminal is connected to the reference-side sensing line SAR. A precharge signal / PC is supplied to the gate terminals of PMOS transistors P1 and P2, and PMOS transistors P1 and P2 form a precharge circuit PCK. That is, when the precharge signal / PC is at a low level, PMOS transistors P1 and P2 are turned on, and the cell-side sensing line SAC and the reference-side sensing line SAR are precharged at the power supply voltage Vdd.

[0080] The amplification unit SAP includes a pair of sensing nodes NI1 and NI2. When the activation signal SAE goes high, the amplification unit SAP amplifies the potential difference between the pair of sensing nodes NI1 and NI2 and outputs the amplified potential difference as output Dout to the output buffer circuit OBF (not shown). Of the pair of sensing nodes in the amplification unit SAP, one sensing node NI1 is connected to the cell-side sensing line SAC, and the other sensing node NI2 is connected to the reference-side sensing line SAR.

[0081] Each of the NMOS transistors N1 to N4 functions as a clamping element, and the NMOS transistors N1 to N4 constitute a clamping circuit CLP. Specifically, the clamping circuit CLP includes an NMOS transistor N3 having a drain terminal connected to the cell-side sense line SAC and a source terminal connected to the connection node CLC, and an NMOS transistor N4 having a drain terminal connected to the reference-side sense line SAR and a source terminal connected to the connection node CLR. Furthermore, the clamping circuit CLP includes an NMOS transistor N1 having a drain terminal connected to the connection node CLC and a source terminal connected to the cell-side bit line BLC, and an NMOS transistor N2 having a drain terminal connected to the connection node CLR and a source terminal connected to the reference-side bit line.

[0082] In other words, the clamping circuit CLP can be regarded as including NMOS transistors N3 and N1 and NMOS transistors N4 and N2, wherein the source-drain paths of the NMOS transistors N3 and N1 are connected in series between the cell-side sensing line SAC and the cell-side bit line BLC, and the source-drain paths of the NMOS transistors N4 and N2 are connected in parallel between the reference-side sensing line SAR and the reference-side bit line BLR.

[0083] In the clamp circuit CLP, the gate terminals of the NMOS transistors N1 and N2 are commonly connected to a first clamp voltage line VL1, and the gate terminals of the NMOS transistors N3 and N4 are commonly connected to a second clamp voltage line VL2. Therefore, the clamp circuit CLP can also be considered to be composed of a first clamp circuit including the NMOS transistors N1 and N2, and a second clamp circuit including the NMOS transistors N3 and N4.

[0084] In the first embodiment, the transconductance Gm of the NMOS transistors N3 and N4 constituting the second clamp circuit is set to be smaller than the transconductance Gm of the NMOS transistors N1 and N2 constituting the first clamp circuit. To set the transconductance Gm in this manner, for example, when the channel lengths L of the NMOS transistors N1 to N4 are the same, the channel widths W of the NMOS transistors N1 and N2 are set to be longer (larger) than the channel widths W of the NMOS transistors N3 and N4. When the channel widths W of the NMOS transistors N1 to N4 are the same, the channel lengths L of the NMOS transistors N1 and N2 are set to be shorter (smaller) than the channel lengths L of the NMOS transistors N3 and N4. When the ratio (W / L) between the channel widths W and the channel lengths L of the NMOS transistors is the size of the NMOS transistors, the sizes of the NMOS transistors N3 and N4 are set to be smaller than the sizes of the NMOS transistors N1 and N2.

[0085] NMOS transistors N5 to N8 form a switching switch for initializing the cell-side bit line BLC and the reference-side bit line BLR. The drain terminals of NMOS transistors N5 and N7 are connected to the cell-side bit line BLC, the source terminal of NMOS transistor N5 is connected to the column selector CSEL, and the source terminal of NMOS transistor N7 is connected to the initialization voltage line VLI. The drain terminals of NMOS transistors N6 and N8 are connected to the reference-side bit line BLR, the source terminal of NMOS transistor N6 is connected to the ground voltage Vss via the reference resistor Rref, and the source terminal of NMOS transistor N8 is connected to the initialization voltage line VLI.

[0086] The gate terminal of NMOS transistor N5 and the gate terminal of NMOS transistor N6 are commonly connected, and a read signal READ is supplied. Furthermore, the gate terminal of NMOS transistor N7 and the gate terminal of NMOS transistor N8 are commonly connected, and a read signal / READ is supplied. Since the read signal / READ is an inverted signal (inverted read signal) of the read signal READ, NMOS transistors N5 and N7 are complementarily turned on (off), and NMOS transistors N6 and N8 are also complementarily turned on (off).

[0087] Correction information storage circuit TCP_O, for example, stores correction information for correcting offset at the input of amplifier unit SAP. The correction information stored in correction information storage circuit TCP_O is supplied to current correction circuit TCP. When read signal READ is high, current correction circuit TCP generates a correction current using the supplied correction information and a bias signal (correction current bias signal) VTRM. The correction current is then supplied to connection nodes CLC and / or CLR via correction current lines TLC and TLR.

[0088] <<<<Noise Cancellation Circuit>>>

[0089] The noise cancellation circuit NCC includes NMOS transistors N11 to N15 , a noise cancellation side (hereinafter also referred to as NC side) sensing line SANC, and an NC side bit line BLNC.

[0090] The drain terminal of the NMOS transistor N15 is connected to the power supply voltage Vdd, its source terminal is connected to the NC-side sense line SANC, and its gate terminal is supplied with a read signal READ. The drain terminal of the NMOS transistor N12 is connected to the NC-side sense line SANC, and its source terminal is connected to the connection node CLNC. The drain terminal of the NMOS transistor N11 is connected to the connection node CLNC, and its source terminal is connected to the NC-side bit line BLNC. The gate terminal of the NMOS transistor N11 (its source-drain paths are connected in series) is connected to the first clamp voltage line VL1, and the gate terminal of the NMOS transistor N12 is connected to the second clamp voltage line VL2.

[0091] Similar to NMOS transistors N5 to N8, NMOS transistors N13 and N14 function as switching switches when initializing the NC-side bit line BLNC. The drain terminals of NMOS transistors N13 and N14 are connected to the NC-side bit line BLNC, the source terminal of NMOS transistor N13 is connected to the ground voltage Vss, and the source terminal of NMOS transistor N14 is connected to the initialization voltage line VLI. The inverted read signal / READ and the read signal READ are supplied to the gate terminals of NMOS transistors N13 and N14. As a result, NMOS transistors N13 and N14 are complementarily turned on (off).

[0092] <<Control Circuit>>

[0093] Although the control circuit 1104 includes a plurality of circuit blocks, Figure 1A Only circuit blocks necessary for the description are shown in FIG. That is, the control circuit 1104 includes a timing control circuit TCNT, a clamp voltage generation circuit CLPG, and an initialization circuit VBLG.

[0094] The timing control circuit TCNT is based on the internal bus 1001 ( Figure 14 ) provides instructions to output the precharge signal / PC, the activation signal SAE, the read signal READ and the inverted read signal / READ.

[0095] The clamp voltage generation circuit CLPG generates a first clamp voltage VCL1 and a second clamp voltage VCL2 having predetermined voltage values, and supplies the first clamp voltage VCL1 and the second clamp voltage VCL2 to first and second clamp voltage lines VL1 and VL2. Furthermore, when performing current correction, the clamp voltage generation circuit CLPG supplies a bias signal VTRM having a predetermined voltage value to the current correction circuit TCP. As will be described in detail later, the voltage values of the first clamp voltage VCL1 and the second clamp voltage VCL2 are lower than the power supply voltage Vdd, and the voltage value of the first clamp voltage VCL1 is also lower than the voltage value of the second clamp voltage VCL2.

[0096] In addition, the initialization circuit VBLG generates an initialization voltage VINI having a predetermined voltage value and supplies the initialization voltage VINI to the initialization voltage line VLI during the standby period. As will be described in detail later, the voltage value of the initialization voltage VINI is lower than the power supply voltage Vdd.

[0097] In the following description, the PMOS transistors P1 and P2 may be referred to as the first PMOS transistor and the second PMOS transistor. Similarly, the NMOS transistors N1 to N8 and N11 to N15 may be referred to as the first to eighth NMOS transistors and the eleventh to fifteenth NMOS transistors.

[0098] <<Overview of Nonvolatile Memory Device Operation>>

[0099] Will use Figure 1B The waveform diagram shown here is used to describe the Figure 1A and Figure 1B An overview of a read operation of a nonvolatile memory device is shown with the sense amplifier SA.

[0100] During a standby period SBH prior to time t0 when a read operation begins, the read signal READ is at a low level. Consequently, NMOS transistors N5 and N6 are turned off, while NMOS transistors N7 and N8 are turned on. Initialization voltage VINI, which is lower than power supply voltage Vdd, is supplied to cell-side bit line BLC and reference-side bit line BLR. Consequently, during the standby period SBH, cell-side bit line BLC, reference-side bit line BLR, and connection nodes CLC and CLR have voltages lower than power supply voltage Vdd.

[0101] During the standby period SBH and the precharge period PTH from time t0 to time t1, the precharge signal / PC becomes a low level, whereby the PMOS transistors P1 and P2 of the precharge circuit PCK are turned on, and the cell-side sensing line SAC, the reference-side sensing line SAR, and the pair of sensing nodes NI1 and NI2 of the amplification unit SAP are precharged to the power supply voltage Vdd.

[0102] Furthermore, during the precharge period PTH, since the read signal READ becomes high, the NMOS transistors N5 and N6 are turned on. As a result, the memory cell is connected to the cell-side bit line BLC via the column selector CSEL, and the reference resistor Rref is connected to the reference-side bit line BLR. The voltages of the cell-side bit line BLC, the reference-side bit line BLR, and the connection nodes CLC and CLR during the precharge period PTH are clamped by the first clamp voltage VCL1 and the second clamp voltage VCL2 and become lower than the power supply voltage Vdd, as shown in FIG. Figure 1B shown.

[0103] At time t1, when the precharge signal / PC goes high, PMOS transistors P1 and P2 are turned off, precharging the cell-side sensing line SAC and the reference-side sensing line SAR ends, and a discharge period DTH begins. During the discharge period DTH from time t1 to time t2, the voltage of the cell-side sensing line SAC decreases according to the cell current flowing through the selected memory cell, and the voltage of the reference-side sensing line SAR decreases according to the reference current flowing through the reference resistor. As a result, a potential difference is generated between the pair of sensing nodes NI1 and NI2 of the amplification unit SAP.

[0104] At time t2 , when the activation signal SAE becomes a high level, the amplification unit SAP amplifies the potential difference between the pair of sensing nodes NI1 and NI2 , and outputs the amplified potential difference as an output Dout.

[0105] In the noise cancellation circuit NCC, the NMOS transistor N13 is turned on in the standby period SBH, and when the transition is made to the precharge period PTH, the NMOS transistor N14 is turned on. As a result, when the transition is made from the standby period SBH to the precharge period PTH, as shown in FIG. Figure 1B As shown, the voltage of the NC side bit line BLNC and the connection node CLNC rises from the ground voltage Vss to a voltage determined by the first clamp voltage VCL1 and the second clamp voltage VCL2. That is, when the standby period SBH transitions to the precharge period PTH, as shown in FIG. Figure 1BAs shown, the voltages of the NC-side bit line BLNC and the connection node CLNC change in opposite directions to the voltages of the cell-side bit line BLC, the reference-side bit line BLR, and the connection nodes CLC and CLR. As a result, voltage changes of opposite phases can be applied to the first and second clamp voltage lines VL1 and VL2 via, for example, the gate capacitances of the NMOS transistors N11 and N12, and noise can be eliminated.

[0106] Next, the following will be described in more detail with reference to the accompanying drawings. Figure 1A Characteristic portions in the configuration according to the first embodiment are shown.

[0107] <<Clamp Circuit and Clamp Voltage Generation Circuit>>

[0108] Figure 2 is a circuit diagram illustrating the configuration of a clamp circuit and a clamp voltage generating circuit according to the first embodiment. Figure 2 Similar to Figure 1A The main difference is that Figure 2 Only shown Figure 1A The portion of the circuit diagram shown is related to the clamping circuit CLP.

[0109] exist Figure 1A In the embodiment, it has been described that the clamp voltage generating circuit CLPG generates voltages lower than the power supply voltage Vdd as the first clamp voltage VCL1 and the second clamp voltage VCL2, but as a more specific example, in Figure 2 , generating the first clamp voltage VCL1 and the second clamp voltage VCL2 having the following voltage values will be described.

[0110] That is, the clamp voltage generation circuit CLPG generates a voltage as a first clamp voltage VCL1, having a voltage value obtained by adding the threshold voltage Vthn of the NMOS transistors N1 and N2 serving as clamp elements to the voltages set for the cell-side bit line BLC and the reference-side bit line BLR. Here, the voltage set for the cell-side bit line BLC and the reference-side bit line BLR is the voltage Vbl (e.g., approximately 0.1V) applied to the selected memory cell (e.g., MC11). As a result, the clamp voltage generation circuit CLPG generates the first clamp voltage VCL1, having a voltage value (=Vbl+Vthn) obtained by adding the threshold voltage Vthn to the voltage Vbl. Furthermore, the clamp voltage generation circuit CLPG generates a voltage as a second clamp voltage VCL2, having a voltage value (=Vcnd+Vth) obtained by adding the threshold voltage Vthn of the NMOS transistors N3 and N4 serving as clamp elements to the voltage Vcnd set for the connection nodes CLC and CLR. The voltage Vcnd has a voltage value higher than the voltage Vbl by a DC saturation margin of the NMOS transistors N1 and N2, and is approximately 0.3 V, for example.

[0111] As a result, Figure 1B During the period from time t0 to time t3 shown, that is, when the cell-side bit line BLC and the reference-side bit line BLR are connected to the memory cell MC11 and the reference resistor Rref via the NMOS transistors N5 and N6, the voltages of the cell-side bit line BLC and the reference-side bit line BLR are limited (clamped) to the voltage Vbl (approximately 0.1 V), and the voltage of the connection nodes CLC and CLR is limited (clamped) to the voltage Vcnd (approximately 0.3 V). Here, for ease of explanation, the case where the threshold voltages of the NMOS transistors N1 and N2 and the threshold voltages of the NMOS transistors N3 and N4 are the same threshold voltage Vthn is taken as an example, but the present invention is not limited thereto.

[0112] The clamp circuit CLP includes two groups (one group N1 and N3 and one group N2 and N4) of two cascode connected NMOS transistors. Figure 1A As shown, the NMOS transistors N3 and N4 have a smaller channel width W than the NMOS transistors N1 and N2 , and the transconductance Gm thereof is set to be smaller than the transconductance of the NMOS transistors N1 and N2 .

[0113] Since the transconductance Gm of the NMOS transistors N1 and N2 is set to be large, the clamping accuracy can be improved when the voltage of the cell side bit line BLC and the reference side bit line BLR to which their source terminals are connected is controlled to the voltage Vbl. In addition, by increasing the transconductance Gm, the read margin can be improved, as shown in FIG. Figure 16 as shown in the description.

[0114] On the other hand, the NMOS transistors N3 and N4 connected to a pair of sensing nodes via the cell-side sensing line SAC and the reference-side sensing line SAR have a shorter channel width W than the NMOS transistors N1 and N2 (for example, 1 / 4 of the channel width W of the NMOS transistors N1 and N2). Therefore, the parasitic capacitance connected to the pair of sensing nodes (for example, the drain capacitance of the NMOS transistors N3 and N4) can be reduced to, for example, 1 / 4. As a result, since the channel width W of the NMOS transistors N1 and N2 can be shortened, the parasitic capacitance can be reduced to 1 / 4. Figure 1B The discharge period DTH and the sensing period STH are shown, and thus a high-speed operation of a read operation can be achieved.

[0115] Note that the reduced transconductance Gm of NMOS transistors N3 and N4 reduces the clamping accuracy when clamping connection nodes CLC and CLR to voltage Vcnd. However, the voltage fluctuations at connection nodes CLC and CLR caused by this reduction in clamping accuracy are fluctuations caused by NMOS transistors N1 and N2 operating in the saturation region, so read margin is not degraded. Conversely, the cascode connection improves the channel length modulation factor λ and improves current fluctuations when the voltages of cell-side sense line SAC and reference-side sense line SAR fluctuate.

[0116] Furthermore, since the two NMOS transistors N1 and N3 are connected to the connection node CLC, and the two NMOS transistors N2 and N4 are also connected to the connection node CLR, the parasitic capacitance connected to the connection nodes CLC and CLR increases. However, since the voltage of the connection nodes CLC and CLR is limited to the voltage Vcnd by the NMOS transistors N3 and N4, the discharge time associated with the connection nodes CLC and CLR does not increase.

[0117] <<<Example of Clamp Voltage Generation Circuit>>>

[0118] Figure 3 is a circuit diagram illustrating the configuration of a clamp circuit and a clamp voltage generating circuit according to the first embodiment. Figure 3 Similar to Figure 2 The main difference is that Figure 3 The figure shows a detailed configuration example of the clamp voltage generating circuit CLPG. Figure 3 In the case of a sensor amplifier SA, the configuration of the sensor amplifier SA is similar to that of the Figure 2 , and thus the description of the sense amplifier PA is omitted.

[0119] The clamp voltage generating circuit CLPG includes PMOS transistors P3 and P4 , NMOS transistors N16 to N18 , a reference resistor Rref_CL, a resistance element Rclamp2 , a current source Iclamp2 , and a reference current source Iref_CL.

[0120] The source terminals of the PMOS transistors P3 and P4 are connected to the power supply voltage Vdd, and the drain terminal of the PMOS transistor P3 is connected to the gate terminals of the PMOS transistors P3 and P4. The drain terminal of the PMOS transistor P3 is connected to the ground voltage Vss via the reference current source Iref_CL. Thus, a current mirror circuit is formed by the PMOS transistors P3 and P4, and a reference current corresponding to the reference current Iref_CL is output from the drain terminal of the PMOS transistor P4.

[0121] The drain terminal of NMOS transistor N18 is connected to the drain terminal of PMOS transistor P4, the drain terminal of NMOS transistor N16 is connected to the source terminal of NMOS transistor N18, and the source terminal of NMOS transistor N16 is connected to ground voltage Vss via reference resistor Rref_CL. The gate terminal of NMOS transistor N16 is connected to the drain terminal of PMOS transistor P4. Here, NMOS transistor N16 is a replica element simulating NMOS transistors N1 and N2 used as clamping elements. NMOS transistor N18 is a replica element simulating NMOS transistors N3 and N4 used as clamping elements. Therefore, for example, NMOS transistor N16 is set to have characteristics similar to those of NMOS transistor N1, and for example, NMOS transistor N18 is set to have characteristics similar to those of NMOS transistor N3.

[0122] In addition, the reference resistor Rref_CL is a replica element of the analog reference resistor Rref. Therefore, the reference resistor Rref_CL is set to have characteristics similar to those of the reference resistor Rref.

[0123] The reference current output from the drain terminal of PMOS transistor P4 is supplied to a series circuit consisting of NMOS transistors N18 and N16 and a reference resistor Rref_CL. As a result, a voltage corresponding to the voltage Vbl (approximately 0.1V) applied to the memory cell is generated at the source terminal of NMOS transistor N16. Since the first clamp voltage line VL1 is connected to the gate terminal of NMOS transistor N16, the value of the first clamp voltage VCL1 supplied to the first clamp voltage line VL1 from the clamp voltage generation circuit CLPG is a voltage obtained by adding the threshold voltage Vthn of the NMOS transistor to the voltage Vbl (approximately 0.1V) at the source terminal of NMOS transistor N16 (=Vbl + Vthn).

[0124] The gate terminal of the NMOS transistor N17 is connected to the drain terminal of the NMOS transistor N17 and the gate terminal of the NMOS transistor N18, and the drain terminal of the NMOS transistor N17 is connected to the power supply voltage Vdd via the current source Iclamp2. Furthermore, the source terminal of the NMOS transistor N17 is connected to the ground voltage Vss via the resistor element Rclamp2. Here, the NMOS transistor N17 is a replica element that simulates the NMOS transistors N3 and N4 used as clamping elements. Therefore, for example, the NMOS transistor N17 is configured to have characteristics similar to those of the NMOS transistor N3.

[0125] The current source Iclamp2 and the resistance element Rclamp2 are configured so that the voltage generated in the resistance element Rclamp2 by the current supplied from the current source Iclamp2 to the resistance element Rclamp2 via the NMOS transistor N17 is equal to the voltage Vcnd at the connection nodes CLC and CLR. As a result, the voltage at the source terminal of the NMOS transistor N17 has a value equal to the voltage Vcnd (approximately 0.3V). Since the second clamp voltage line VL2 is connected to the gate terminal of the NMOS transistor N17, the second clamp voltage VCL2 becomes a value obtained by adding the threshold voltage Vthn of the NMOS transistor N17 to a voltage value equal to the voltage Vcnd (approximately 0.3V) (=Vcnd + Vthn).

[0126] As reference Figure 1A As described above, since parasitic capacitance connected to the cell-side sensing line SAC and the reference-side sensing line SAR can be reduced, both stable operation and high-speed operation can be achieved.

[0127] also, Figure 2 The illustrated clamp voltage generation circuit CLPG generates a first clamp voltage VCL1 and a second clamp voltage VCL2 using replica elements of NMOS transistors N1 to N4 and a replica element of a reference resistor Rref serving as clamp elements. Therefore, even when the characteristics of the NMOS transistors N1 to N4 and the reference resistor Rref fluctuate, such as during manufacturing, the clamp voltage generation circuit CLPG can generate the first clamp voltage VCL1 and the second clamp voltage VCL2 in accordance with the fluctuations, further improving operational stability.

[0128] <<Current Correction Circuit>>

[0129] Figure 4 is a circuit diagram illustrating the configuration of a current correction circuit according to the first embodiment. Figure 4 Similar to Figure 2 The main difference is that in Figure 4 The part related to the current correction circuit is added to Figure 2 middle.

[0130] Due to characteristic variations between clamping elements constituting the clamping circuit CLP (e.g., characteristic variations between NMOS transistors N1 and N2) and / or characteristic variations between elements constituting the amplifying unit SAP (e.g., MOS transistors), an input offset may occur in the amplifying unit SAP.

[0131] For example, when an input offset occurs due to a characteristic variation between the NMOS transistors N1 and N2, a potential difference may occur between the pair of sensing nodes NI1 and NI2 even if the cell resistance and the reference resistor have the same value. Furthermore, when an input offset occurs due to, for example, an element constituting the amplification unit SAP, the amplification unit SAP may output an undesired output Dout even if there is no potential difference between the pair of sensing nodes NI1 and NI2, thereby reducing a read margin during a read operation of a memory cell at high resistance and / or a read operation of a memory cell at low resistance.

[0132] In the first embodiment, a current correction circuit TCP is provided in the sense amplifier SA. Although not particularly limited, the sense amplifier SA is further provided with a correction information storage circuit TCP_O. Correction information storage circuit TCP_O pre-stores correction information. The correction information is supplied from correction information storage circuit TCP_O to the current correction circuit TCP. Based on the supplied correction information and a bias signal VTRM supplied from a clamp voltage generation circuit CLPG, the current correction circuit TCP generates a minute correction current and supplies the generated correction current to the connection node CLC and / or the connection node CLR via correction current lines TLC and TLR.

[0133] By supplying correction current to the connection node CLC and / or the connection node CLR, the cell current flowing through the cell side sensing line SAC and / or the reference current flowing through the reference side sensing line SAR during the read operation can be corrected, and the input offset can be reduced and the read margin can be improved.

[0134] By connecting the correction current lines TLC and TLR to the connection nodes CLC and CLR, the parasitic capacitance connected to the connection nodes CLC and CLR increases. However, since the NMOS transistors N3 and N4 serving as clamping elements clamp the voltage of the connection nodes CLC and CLR to the voltage Vcnd (approximately 0.3 V), the discharge time for discharging the connection nodes CLC and CLR does not increase.

[0135] Correction current lines TLC and TLR are connected to, for example, a cell-side sensing line SAC and a reference-side sensing line SAR, and correction current is supplied to the sensing lines SAC and SAR, thereby reducing input offset. However, in this case, parasitic capacitance generated by correction current lines TLC, TLR, and the like is connected to the sensing lines SAC and SAR, and the parasitic capacitance connected to the pair of sensing nodes increases, which increases the discharge time of the sensing lines SAC and SAR, and limits high-speed read operations.

[0136] Furthermore, correction current lines TLC and TLR are connected to, for example, the cell-side bit line BLC and the reference-side bit line BLR, and correction current is supplied to the bit lines BLC and BLR, thereby reducing input offset. However, in this case, a current correction circuit TCP is required to generate the correction current at the very low voltage Vbl (approximately 0.1V) applied to the memory cell, and it is difficult to configure the current correction circuit TC.

[0137] Therefore, if Figure 4 As shown, the correction current lines TLC and TLR to which the correction current is supplied are ideally connected to the connection nodes CLC and CLR.

[0138] <<<Example of Current Correction Circuit>>>

[0139] Figure 5 and Figure 6 is a diagram for describing a current correction circuit according to a first embodiment. Here, Figure 5 Illustrated is a configuration of a clamp voltage generation circuit that generates a bias signal to be supplied to a current correction circuit. Figure 6 It is an icon Figure 5 The configuration of the current correction circuit is shown in the circuit diagram.

[0140] Figure 5 Similar to Figure 4 The main difference is that Figure 5 The detailed configuration of the clamp voltage generating circuit CLPG is illustrated. Figure 5 The clamping voltage generating circuit CLPG shown is similar to Figure 3 The clamping voltage generation circuit shown in Figure 2 is different from the Figure 5 A configuration for generating a bias signal to be supplied to a current correction circuit is illustrated.

[0141] In order to generate the bias signal VTRM supplied to the current correction circuit TCP, Figure 5 In the clamp voltage generating circuit CLPG shown in FIG. 1 , a PMOS transistor P5 and NMOS transistors N19 and N20 are added to the Figure 3 In the clamping voltage generating circuit CLPG.

[0142] The source terminal of the PMOS transistor P5 is connected to the power supply voltage Vdd, and its gate terminal is connected to the gate terminal of the PMOS transistor P3. The drain terminal of the PMOS transistor P5 is connected to the drain terminal of the NMOS transistor N20, and the source terminal of the NMOS transistor N20 is connected to the drain terminal of the NMOS transistor N19. The source terminal of the NMOS transistor N19 is also connected to the ground voltage Vss. The gate terminal of the NMOS transistor N19 is connected to the drain terminal of the PMOS transistor P5, and the gate terminal of the NMOS transistor N20 is connected to the gate terminal of the NMOS transistor N17. The bias signal VTRM is extracted from the gate terminal of the NMOS transistor N19 (the drain terminal of the PMOS transistor P5).

[0143] Similar to the NMOS transistors N17 and N18 , the NMOS transistor N20 is a replica element simulating the NMOS transistors N3 and N4 used as clamping elements.

[0144] The current mirror circuit is composed of PMOS transistors P3 to P5, and a current mirror current corresponding to the reference current Iref_CL is supplied from the PMOS transistor P5 to the NMOS transistors N20 and N19 connected in series. As a result, the bias signal VTRM is output from the gate terminal of the NMOS transistor N19.

[0145] Figure 6 The current correction circuit TCP shown includes NMOS transistors N21 to N25 and N31 to N37.

[0146] The source terminals of the NMOS transistors N21 to N25 are connected to the ground voltage Vss, and the gate terminals thereof are connected to Figure 5 The gate terminal of the NMOS transistor N19 is shown so that the bias signal VTRM is supplied. As a result, the NMOS transistors N19 and N21 to N25 constitute a current mirror circuit, and the NMOS transistors N21 to N25 function as current sources.

[0147] In the first embodiment, with the size of the NMOS transistor N21 as a reference (×1), the sizes of the NMOS transistors N22 to N25 are set to twice (×2), four times (×4), eight times (×8), and 16 times (×16) the size of the reference (×1). Figure 5 The size of the NMOS transistor N19 shown is set to N times (×N) the reference (×1).

[0148] The drain terminals of the NMOS transistors N21 to N25 are connected to the source terminals of the NMOS transistors N31 to N35, and the drain terminals of the NMOS transistors N31 to N35 are connected to the source terminals of the NMOS transistors N36 and N37. The drain terminal of the NMOS transistor N36 is connected to the connection node CLC via the correction current line TLC, and the drain terminal of the NMOS transistor N37 is connected to the connection node CLR via the correction current line TLR.

[0149] The gate terminals of the NMOS transistors N31 to N35 and the gate terminals of the NMOS transistors N36 and N37 are connected to the correction information storage circuit TCP_O. The correction information stored in the correction information storage circuit TCP_O is supplied to the gate terminals of the NMOS transistors N31 to N35, N36, and N37 as switch signals CHS1 to CHS5 and select signals SLS1 and SLS2. The NMOS transistors N31 to N35 and N36 and N37 have the same size. The NMOS transistors N31 to N35 function as switches that are turned on by setting the switch signals CHS1 to CHS5 to a high level, and the NMOS transistors N36 and N37 function as switches that are turned on by setting the select signals SLS1 and SLS2 to a high level.

[0150] By combining the high levels of the switch signals CHS1 to CHS5, 32 different settings can be made, and the size can be adjusted from 0 times to 31 times. For example, in the case where the size N of the NMOS transistor N19 is set to 256 (N=256), by combining the high levels of the switch signals CHS1 to CHS5, a range from 0 to 1 / 256× the reference current Iref_CL ( Figure 5 ) to a minute correction current of 31 / 256×reference current Iref_CL. The generated correction current can be supplied to, for example, connection node CLC or CLR through selection signals SLS1 and SLS2 to perform correction.

[0151] In the case where the read margin when the memory cell has a low resistance is reduced due to input offset, the selection signal SLS1 is set to a high level so that a small correction current is applied to the connection node CLC. Therefore, the cell current Icell can be increased during the read operation. On the other hand, in the case where the read margin when the memory cell has a high resistance is small due to input offset, the selection signal SLS2 is set to a high level so that a small correction current is applied to the connection node CLR. As a result, the reference resistor Rref ( Figure 5) By supplying a minute correction current to the connection node, the read margin can be improved by equalizing the read margin when the memory cell has a high resistance and the read margin when the memory cell has a low resistance.

[0152] exist Figure 5 The clamp voltage generating circuit CLPG shown in Figure 6 In the current correction circuit TCP shown, a current mirror is formed by NMOS transistors N19 and N20, N21 to N25, and N3 and N4, and even when the characteristics of the NMOS transistors fluctuate, such as at the time of manufacturing, a correction current can be generated according to the fluctuation, and the stability of operation can be improved.

[0153] <<Initialization Circuit>>

[0154] Figure 7 is a diagram for describing an initialization circuit according to the first embodiment. Figure 7 Similar to Figure 4 The difference is that in Figure 7 The part related to the initialization circuit is added to Figure 4 In other words, Figure 7 , an initialization circuit VBLG, an initialization voltage line VLI supplied with an initialization voltage VINI generated by the initialization circuit VBLG, and NMOS transistors N7 and N8 are illustrated as portions related to the initialization circuit.

[0155] Figure 8A and Figure 8B is a waveform diagram for describing the initialization circuit according to the first embodiment. Figure 8A and Figure 8B Similar to Figure 1B The difference is that in Figure 8A and Figure 8B The waveforms of the NC side sense line and the NC side bit line are omitted. Here, for example, Figure 8A Pictured Figure 4 The operation of the circuit shown, and Figure 8B Pictured Figure 7 operation of the circuit shown.

[0156] The initialization circuit VBLG generates an initialization voltage VINI and supplies the initialization voltage VINI to the initialization voltage line VLI. The voltage of the initialization voltage VINI is lower than the power supply voltage Vdd and is, for example, approximately voltage Vbl (approximately 0.1V)+0.2V.

[0157] like Figure 7As shown, the NMOS transistor N7 is connected between the initial voltage line VLI and the cell side bit line BLC, and the NMOS transistor N8 is connected between the initial voltage line VLI and the reference side bit line BLR. The inverted read signal / READ is supplied to the gate terminals of the NMOS transistors N7 and N8. Therefore, in the standby period SBH ( Figure 8A and Figure 8B ), the NMOS transistors N7 and N8 are turned on. As a result, in the standby period SBH, the voltages of the cell-side bit line BLC and the reference-side bit line BLR have voltage values determined by the initialization voltage VINI.

[0158] During the standby period SBH, since the read signal READ becomes low level, the NMOS transistors N5 and N6 are turned off. Therefore, when the initialization voltage VINI is not supplied through the NMOS transistors N7 and N8, the cell side bit line BLC and the reference side bit line BLR are in a floating state, and Figure 8A As shown, for example, the voltage rises toward the power supply voltage Vdd to become the power supply voltage Vdd. Thereafter, at time t0 when the read operation begins, the voltages of the cell-side bit line BLC and the reference-side bit line BLR change from the power supply voltage Vdd to a voltage Vbl determined by the first clamp voltage VCL1. That is, when the read operation transitions from the standby period, the amount of change in the voltages of the cell-side bit line BLC and the reference-side bit line BLR increases. The voltage change in the bit lines is transmitted to the first clamp voltage line VL1, for example, via the gate capacitance (capacitance between the source and gate terminals) of NMOS transistors N1 and N2, and becomes noise, for example.

[0159] On the other hand, Figure 7 In the configuration of FIG. 5 , in the standby period SBH, the initialization voltage VINI of a voltage lower than the power supply voltage Vdd (voltage Vbl (about 0.1V) + 0.2V) is supplied to the cell side bit line BLC and the reference side bit line BLR. Figure 8B As shown, when transitioning from the standby period to the read operation, the voltage variation of the cell side bit line BLC and the reference side bit line BLR can be reduced (to about 0.2 V). As a result, noise transmitted to the first clamp voltage line VL1 via the gate capacitance can be reduced.

[0160] exist Figure 7 In the configuration in which the initialization voltage VINI having a voltage lower than the power supply voltage Vdd (voltage Vbl (about 0.1V)+0.2V) is supplied to the cell-side bit line BLC and the reference-side bit line BLR during the standby period SBH, the voltage at the connection nodes CLC and CLR transitions from about 0.5V (standby period SBH) to about 0.3V (read operation period), as shown Figure 8BThat is, the voltage variation at the connection nodes CLC and CLR can also be reduced, and noise can be reduced.

[0161] Since the time required to wait for noise convergence can be shortened by reducing noise, for example, the precharge period PTH from time t0 to time t1 can be shortened, thereby achieving high-speed operation. Alternatively, since the fluctuations of the first clamping voltage VCL1 and the second clamping voltage VCL2 due to noise can be reduced, the read margin can be improved by suppressing the fluctuations of the cell current after time t1.

[0162] <<<Configuration Example of Initialization Circuit>>>

[0163] Figure 9 is a circuit diagram illustrating an example of an initialization circuit according to the first embodiment. Figure 9 Similar to Figure 7 The difference is that the initialization circuit VBLG is configured in Figure 9 Clearly shown in.

[0164] Initialization circuit VBLG includes a current source I_VB and NMOS transistors N41 and N42. The source terminal of NMOS transistor N42 is connected to ground voltage Vss, and its drain terminal is connected to power supply voltage Vdd via current source I_VB. The source terminal of NMOS transistor N41 is connected to ground voltage Vss, and its drain terminal is connected to initialization voltage line VLI. In addition, the gate terminals of NMOS transistors N41 and N42 are connected to the drain terminal of NMOS transistor N42. Therefore, NMOS transistors N41 and N42 form a current mirror circuit.

[0165] In the first embodiment, the initialization circuit VBLG is shared by a plurality of sense amplifiers. Figure 13 In the example shown, one initialization circuit VBLG is provided for k input / output circuits 1103_1 to 1103 — k.

[0166] When NMOS transistors N7 and N8 are turned on, current flows from the power supply voltage Vdd to the initial voltage line VLI via PMOS transistors P1 and P2, NMOS transistors N3 and N4, NMOS transistors N1 and N2, and NMOS transistors N7 and N8, and further, current flows to the ground voltage Vss via NMOS transistor N41.

[0167] For example, NMOS transistor N41 functions as a current source through which a current of 4 μA flows. Therefore, for example, assuming that one initialization circuit VBLG is shared by 256 sense amplifiers, a current of 7 nA is distributed to one NMOS transistor serving as a clamping element. Even in the standby period SBH before time t0, the first clamping voltage VCL1 is applied to NMOS transistors N1 and N2, and by allowing a current of 7 nA to flow, approximately 0.3 V (which is the initialization voltage VINI) is automatically generated in the initialization voltage line VLI to which the source terminals of NMOS transistors N1 and N2 are connected.

[0168] As described above, the initialization circuit VBLG can be implemented by adding a current source and an NMOS transistor without adding a complex circuit, and can be shared by multiple sense amplifiers. Therefore, it is possible to suppress increases in occupied area and power consumption.

[0169] <<Noise Cancellation Circuit>>

[0170] Next, we will refer to Figure 7 as well as Figure 8A and Figure 8B describe Figure 1A and Figure 1B The noise cancellation circuit NCC shown in FIG. Figure 1A As shown, the noise cancellation circuit NCC includes NMOS transistors N11 to N15. Here, NMOS transistors N11 and N12 are replicas of NMOS transistors N1 and N2, and N3 and N4, which are used as clamping elements. Therefore, for example, NMOS transistors N11 and N12 are configured to have characteristics similar to those of NMOS transistors N1 and N3.

[0171] like Figure 7 as well as Figure 8A and Figure 8B As described above, at time t0 when the standby period SBH transitions to the read operation, the voltages of the cell-side bit line BLC and the reference-side bit line BLR transition from approximately 0.3 V (= voltage Vbl (approximately 0.1 V) + approximately 0.2 V) to approximately 0.1 V (= power supply Vbl). Furthermore, at time t0, the voltage of the connection nodes CLC and CLR transitions from approximately 0.5 V to approximately 0.3 V. The voltage transitions in the cell-side bit line BLC and the reference-side bit line BLR propagate to the first clamping voltage line VL1 via the gate capacitances of the NMOS transistors N1 and N2, and the voltage transitions in the connection nodes CLC and CLR propagate to the second clamping voltage line VL2 via the NMOS transistors N3 and N4.

[0172] Since the voltage transition at time t0 is a negative change from a high voltage value to a low voltage value, as Figure 8A and Figure 8BAs shown, the voltage transition thus acts as a negative noise application to the first clamping voltage VCL1 and the second clamping voltage VCL2.

[0173] Meanwhile, in the noise cancellation circuit NCC, at time t0, when the read operation transitions from the standby period SBH, the NMOS transistor N13 switches to an OFF state, and the NMOS transistors N14 and N15 switch to an ON state. As a result, the voltages of the NC-side bitline BLNC and the connection node CLNC rise from the ground voltage Vss to a voltage determined by the initialization voltage VINI. Specifically, the voltage of the connection node CLNC transitions from the ground voltage Vss to approximately 0.5V, and the voltage of the NC-side bitline BLNC also transitions from the ground voltage Vss to approximately 0.3V.

[0174] The transition of the voltage at the NC-side bit line BLNC is transmitted to the first clamp voltage line VL1 via the gate capacitance of the NMOS transistor N11, and the transition of the current at the connection node CLNC is transmitted to the second clamp voltage line VL1 via the gate capacitance of the NMOS transistor N12. Since the transition at time t0 is a positive change from a low voltage value to a high voltage value, as shown in FIG. Figure 8A and Figure 8B As shown, the voltage transition thus acts as a forward noise application to the first clamping voltage VCL1 and the second clamping voltage VCL2.

[0175] Since both the negative noise and the positive noise are applied to the first and second clamping voltage lines VL1 and VL2 , the noises may be canceled.

[0176] Since the noise is reduced by the cancellation, the time to wait for the noise to converge can be shortened, and thus the precharge period PTH from time t0 to time t1 can be shortened, for example, to achieve high-speed operation. Alternatively, since the fluctuation of the first clamp voltage VCL1 and the second clamp voltage VCL2 due to noise can be reduced, the read margin can be improved by suppressing the fluctuation of the cell current after time t1.

[0177] In addition, since the NMOS transistors N11 and N12 are replica elements of the NMOS transistors N1 to N4, for example, when the gate capacitances of the NMOS transistors N1 to N4 vary due to fluctuations at the time of manufacturing, the gate capacitances of the NMOS transistors N11 and N12 also vary in a similar manner, and therefore, the amount of noise to be canceled can be prevented from being reduced due to fluctuations at the time of manufacturing.

[0178] NMOS transistors N5 to N8 and N13 and N14 can be considered to constitute a selection circuit that changes connections with the cell-side bit line BLC, reference-side bit line BLR, and NC-side bit line BLNC between standby time and read time.

[0179] According to the first embodiment, a semiconductor device including an MRAM capable of both high-speed and stable operation at high temperatures can be provided. This can expand the application range of the semiconductor device and enhance its commercial value. For example, endpoint devices that communicate with the cloud often need to perform high-speed data processing in harsh environments. The semiconductor device including the MRAM according to the first embodiment can also be used in such endpoint devices.

[0180] (Second embodiment)

[0181] In the second embodiment, a method of performing a multi-processing operation in a sense amplifier SA (eg, Figure 1A ) is a preferred example of a reference resistor Rref used in a memory cell (e.g., MC11). The reference resistor Rref is set to have an intermediate resistance value between a resistance value when a memory cell (e.g., MC11) has a high resistance and a resistance value when the memory cell has a low resistance. To enable this setting, the reference resistor Rref includes an adjustment function unit that adjusts the resistance value.

[0182] The present inventors have studied a reference resistor including such an adjustment function unit. First, the inventors' study will be described using a comparative example.

[0183] <Comparison example of reference resistors>

[0184] Figure 17 : is a circuit diagram illustrating a comparative example of a reference resistor studied by the present inventors. Figure 17 As shown, the reference resistor Rref of the comparative example is composed of a resistance value fixing unit Rref_fx and five resistance value adjusting units Rref_ad1 to Rref_ad5 connected in series between terminal nodes RT1 and RT2 of the reference resistor Rref. The adjusting function unit is realized by the five resistance value adjusting units.

[0185] The resistance value fixing unit Rref_fx and the resistance value adjusting units Rref_ad1 to Rref_ad5 are basically composed of the resistance element RM ( Figure 1A ) are composed of polysilicon resistors (hereinafter also referred to as polysilicon resistors) with substantially the same characteristics as the basic resistors. The sheet resistance of the polysilicon resistor is relatively large, approximately 1 kΩ. Each of the resistance value adjustment units Rref_ad1 to Rref_ad5 is composed of a resistor constructed using a basic resistor R and a short-circuit switch. Hereinafter, a case will be described in which the basic resistor R is composed of a 1 kΩ polysilicon resistor.

[0186] In the resistance adjustment unit Rref_ad1, resistor R11 is composed of eight elementary resistors R connected in parallel. This results in a resistor R11 with a resistance value of approximately 125Ω. To achieve an adjustment function with a resolution of 125Ω, resistor R11 and an NMOS transistor N51 are connected in parallel. A short-circuiting switch is formed by NMOS transistor N51, and is turned on and off by a switching signal 11 supplied to the gate terminal of NMOS transistor N51. Consequently, whether a resistance value with a resolution of 125Ω is added to or not added to the reference resistor Rref is determined by the switching signal 11.

[0187] Similarly, in the resistance value adjustment unit Rref_ad2, the resistor R12 is composed of four basic resistors R connected in parallel, and the NMOS transistor N52 constituting the short-circuit switch is connected in parallel with the resistor R12. Hereinafter, in the resistance value adjustment unit Rref_ad3, the resistor R13 is composed of two basic resistors R connected in parallel, and the resistor R13 and the NMOS transistor N53 constituting the short-circuit switch are connected in parallel. In the resistance value adjustment unit Rref_ad4, the resistor R14 is composed of one basic resistor R, and the resistor R14 and the NMOS transistor N54 constituting the short-circuit switch are connected in parallel. Furthermore, in the resistance value adjustment unit Rref_ad5, the resistor R15 is composed of two basic resistors R connected in series, and the resistor R15 and the NMOS transistor N55 constituting the short-circuit switch are connected in parallel.

[0188] By connecting these resistance value adjustment units Rref_ad1 to Rref_ad5 in series with a resistance value fixing unit Rref_fx having a base resistance value of resistor R16, a reference resistor Rref having a resistance value resolution of 125Ω can be implemented. In this case, by combining the high and low levels of the switching signals 11 to 15, a reference resistor Rref is implemented in which the resistance value can be adjusted within a range of +0Ω to +3.875kΩ relative to the base resistance value.

[0189] On-resistance is generated in the NMOS transistors N51 to N55 when in the on state. This on-resistance causes an error in the resistance value of the reference resistor Rref. In order to suppress the error in the reference resistor Rref caused by the error in the NMOS transistors N51 to N55 to 10%, for example, the on-resistance of the NMOS transistors N51 to N55 needs to be set to 12.5Ω, 25Ω, 50Ω, 100Ω, and 200Ω, which is 10% of the resistance value of the resistors R11 to R15.

[0190] For example, to achieve an on-resistance of less than 100Ω, the sizes of NMOS transistors N51 to N53 need to be increased, and in particular, to achieve an on-resistance of 12.5Ω, the size of NMOS transistor N51 needs to be increased. In other words, there is a problem of increasing the occupied area of the NMOS transistors constituting the short-circuiting switch.

[0191] <Configuration of Reference Resistors>

[0192] Figure 10 : is a circuit diagram illustrating the configuration of a reference resistor according to the second embodiment. Figure 10 In FIG, reference symbol Rref indicates a reference resistor. Figure 17 In the comparative example shown, the reference resistor Rref is configured by a fixed resistance unit Rref_fx and five resistance adjustment units Rref_ad1 through Rref_ad5 connected in series between terminal nodes RT1 and RT2. The fixed resistance unit Rref_fx includes a resistor R17 having a base resistance value. The resistance values of the resistance adjustment units Rref_ad1 through Rref_ad5, controlled by switch signals 11 through 15, are added to the base resistance value to form the resistance value of the reference resistor Rref. The resolution of the resistance value added to the base resistance value decreases as the resistance adjustment units Rref_ad1 through Rref_ad5 are added in order.

[0193] Here, the description will be made of the Figure 17 The case where the resistors constituting the resistance value adjustment units Rref_ad1 to Rref_ad5 are constituted by the basic resistor R having a resistance value of 1 kΩ described in the foregoing description is not limited thereto. Furthermore, a case where the reference resistor Rref includes five resistance value adjustment units will be described, but the number is not limited to five.

[0194] The resistance value adjustment unit Rref_ad1 includes resistors R21 and R22, which constitute a short-circuit switch, and an NMOS transistor N51. Resistor R22 and NMOS transistor N51 are connected in series, and resistor R21 is connected in parallel with the series-connected resistor R22 and NMOS transistor N51. Here, resistor R22 has two resistor groups (3×R), in which three basic resistors R are connected in series. Resistor R22 is implemented by connecting the two resistor groups (3×R) in parallel (3×R / 2). Resistor R21 is implemented by connecting two basic resistors R in parallel (R / 2).

[0195] As described in the comparative example, since the basic resistor R is 1 kΩ, the resistance value of the resistor R22 is 1.5 kΩ, and the resistance value of the resistor R21 is 0.5 kΩ. Therefore, when the NMOS transistor N51 is turned on by the switch signal I1, the resistance value of the resistance value adjustment unit Rref_ad1 is 0.375 kΩ, and when the NMOS transistor N51 is turned off, the resistance value of the resistance value adjustment unit Rref_ad1 is 0.5 kΩ. Therefore, as in the comparative example, the difference in the resistance value of the resistance value adjustment unit Rref_ad1 generated by turning on / off the short-circuiting switch is set to 125 Ω. In addition, the number of elements constituting the resistance value adjustment unit Rref_ad1 (the number of NMOS transistors and the number of basic resistors) is the same as the number of elements of the resistance value adjustment unit of the comparative example (the number of NMOS transistors is 1 and the number of basic resistors is 8).

[0196] The resistance value adjustment unit Rref_ad2 includes resistors R23 and R24, which constitute a short-circuit switch, and an NMOS transistor N52. In the resistance value adjustment unit Rref_ad2, the resistor R24 and the NMOS transistor N52 are connected in series, and the resistor R23 is connected in parallel with the series-connected resistor R24 and NMOS transistor N52. Here, the resistor R24 is composed of three basic resistors R connected in series, and the resistor R23 is composed of one basic resistor R.

[0197] Therefore, when the NMOS transistor N52 is turned on by the switching signal I2, the resistor R23 with a resistance value of 1kΩ and the resistor R24 with a resistance value of 3kΩ are connected in parallel, and the resistance value of the resistance value adjustment unit Rref_ad2 is 0.75kΩ. When the NMOS transistor N52 is turned off, the resistance value of the resistance value adjustment unit Rref_ad2 is 1kΩ. Therefore, as in the comparative example, the difference in the resistance value of the resistance value adjustment unit Rref_ad2 generated by turning on / off the short-circuit switch is set to 250Ω. In addition, the number of elements constituting the resistance value adjustment unit Rref_ad2 (the number of NMOS transistors and the number of basic resistors) is the same as the number of elements of the resistance value adjustment unit of the comparative example (the number of NMOS transistors is 1 and the number of basic resistors is 4).

[0198] Since the resistance value adjusting units Rref_ad3 to Rref_ad5 are similar to Figure 17 The resistance value adjusting units Rref_ad3 to Rref_ad5 are not shown, and thus a description thereof will be omitted.

[0199] The value of the resistor R17 constituting the resistance value fixing unit Rref_fx is set to a value approximately 1 kΩ lower than the resistance value of the resistor R16 described in the comparative example. This is because, in the comparative example, when the NMOS transistors N51 and N52 are turned on by the switching signals 11 and 12, the resistance values of the resistance value adjusting units Rref_ad1 and Rref_ad2 become 0Ω, while in the case of the second embodiment, the resistance values of the resistance value adjusting units Rref_ad1 and Rref_ad2 become 0.375 kΩ and 0.75 kΩ, respectively.

[0200] The reference resistor Rref according to the second embodiment can adjust the resistance value with almost the same resolution (125Ω) and range as the comparative example by controlling the short-circuit switches (NMOS transistors N51 to N55) with switch signals 11 to 15. Similar to the comparative example, when the error generated by the on-resistance of the NMOS transistors constituting the short-circuit switches is suppressed to 10%, the resistance values of the resistors R22 and R24 connected in series to the NMOS transistors N51 and N52 are relatively large, 1.5kΩ and 3kΩ, respectively, and therefore, the allowable on-resistance values of the NMOS transistors N51 and N52 can be increased to 150Ω (=1.5kΩ×10%) and 300Ω (=3kΩ×10%). As a result, the size of the NMOS transistors N51 and N52 can be reduced. In addition, since the resistance value of the resistor R17 is reduced, the size of the resistor R17 can also be reduced. In other words, the increase in the occupied area can be suppressed.

[0201] In order to suppress the error to 10%, the values of the allowable on-resistances of the NMOS transistors N53 to N55 are the same as those in the comparative example, and are 50Ω, 100Ω, and 200Ω, respectively.

[0202] <Edit>

[0203] Figure 10 The reference resistor Rref including the resistance value adjustment unit is illustrated, wherein the basic resistor R constituting the resistor (R11) is divided into 1:3 (1 to 3), the basic resistor R having a ratio of 3 is changed from parallel connection to series connection, a short-circuit switch is connected in series to the basic resistors connected in series, and the basic resistor R having a ratio of 1 is changed relative to Figure 17 In the comparative example shown, a resistance value adjustment unit (eg, Rref_ad1) including resistors in which four or more basic resistors R are connected in parallel is connected in parallel. Figure 17 , the resistance value adjusting units having a configuration in which four or more basic resistors R are connected in parallel are Rref_ad1 and Rref_ad2. Figure 17 The resistance value adjustment unit Rref_ad2 shown in FIG. Figure 17In the example, the resistor R12 composed of four basic resistors R connected in parallel is divided into Figure 10 In the circuit, the resistor R24 is composed of three basic resistors R connected in series and the resistor R23 is composed of one basic resistor R, the resistor R24 is connected in series with the NMOS transistor N52 constituting the short-circuit switch, and the resistor R23 is connected in parallel with the NMOS transistor N52 and the resistor R24 connected in series.

[0204] On the other hand, in this modification, Figure 17 In the comparative example shown, a reference resistor can be formed by dividing a resistor formed by connecting N basic resistors R of two or more basic resistors in parallel into 1:N-1 (1 to N-1) and changing the basic resistors R with the N-1 ratio from parallel connection to series connection.

[0205] Figure 11 : is a circuit diagram illustrating a configuration of a reference resistor according to a modification of the second embodiment. Figure 10 and Figure 17 The reference resistor Rref is composed of a fixed resistance unit Rref_fx and five resistance adjustment units Rref_ad1 to Rref_ad5 connected in series between terminal nodes RT1 and RT2. The fixed resistance unit Rref_fx includes a resistor R18 having a base resistance value, and the resistance values of the resistance adjustment units Rref_ad1 to Rref_ad5, which are controlled by switching signals 11 to 15, are added to the base resistance value to form the resistance value of the reference resistor Rref.

[0206] exist Figure 17 In the comparative example of , the resistance value adjustment unit Rref_ad1 includes a resistor R11 including eight (N) basic resistors R connected in parallel. Figure 11 In the modification shown, the resistor R11 is divided into a resistor R25 including one basic resistor R and a resistor R26 including seven (N-1) basic resistors R connected in series. In the resistance value adjustment unit Rref_ad1, an NMOS transistor N51 is connected in series to the resistor R26, and the resistor R25 is connected in parallel to a series circuit consisting of the resistor R26 and the NMOS transistor N51. Since the resistance value adjustment unit Rref_ad1 according to the modification is composed of eight basic resistors R and one NMOS transistor, the resistance value adjustment unit Rref_ad1 has the same Figure 17 The resistance value adjustment unit Rref_ad1 shown has the same number of elements.

[0207] When the NMOS transistor N51 is turned on by the switching signal 11, the seven basic resistors R connected in series and the one basic resistor R are connected in parallel, so that the resistance value of the resistance value adjustment unit Rref_ad1 is 0.875kΩ. On the other hand, when the NMOS transistor N51 is turned off, the resistance value of the resistance value adjustment unit Rref_ad1 is 1kΩ. By turning on / off the NMOS transistor N51, the difference in the resistance value of the resistance value adjustment unit Rref_ad1 is 125Ω, similar to Figure 10 and comparative examples.

[0208] exist Figure 11 In the example, the resistance value adjustment units Rref_ad2, Rref_ad4 and Rref_ad5 are similar to Figure 10 In the case of the resistance value adjustment unit Rref_ad2, Figure 17 The number of basic resistors R connected in parallel is four, and Figure 10 The ratio is 1:3 and Figure 11 The same result is obtained by dividing into 1:N-1. In the case of the resistance value adjustment units Rref_ad4 and Rref_ad5, Figure 17 The basic resistor R is not connected in parallel. Next, we will describe Figure 17 The resistance value adjustment unit Rref_ad3 in which the basic resistors R are connected in parallel and can be divided into 1:N-1.

[0209] exist Figure 17 In the comparative example of , the resistance value adjustment unit Rref_ad3 includes a resistor R13 including two (N) basic resistors R connected in parallel. Figure 11 In the modification shown, the resistor R13 is divided into a resistor R27 including one basic resistor R and a resistor R28 including one (N-1) basic resistor R. In the resistance value adjustment unit Rref_ad3, an NMOS transistor N53 is connected in series to the resistor R28, and the resistor R27 is connected in parallel to a series circuit consisting of the resistor R28 and the NMOS transistor N53. Since the resistance value adjustment unit Rref_ad3 according to the modification is composed of two basic resistors R and one NMOS transistor, the resistance value adjustment unit Rref_ad3 has the same Figure 17 The resistance value adjustment unit Rref_ad3 shown has the same number of elements.

[0210] When the NMOS transistor N53 is turned on by the switching signal 13, the two basic resistors R are connected in parallel, so that the resistance value of the resistance value adjustment unit Rref_ad3 is 0.500 kΩ. On the other hand, when the NMOS transistor N53 is turned off, the resistance value of the resistance value adjustment unit Rref_ad1 is 1 kΩ. By turning on / off the NMOS transistor N53, the difference in the resistance value of the resistance value adjustment unit Rref_ad2 is 500 Ω, similar to Figure 10 and comparative examples.

[0211] When the NMOS transistors N51 to N53 are turned on, the resistance value added to the resistance value fixing unit Rref_fx by the resistance value adjustment unit increases to 0.875 kΩ, 0.750 kΩ, and 0.500 kΩ, so that the resistance value of the resistor R18 constituting the resistance value fixing unit Rref_fx is set to be approximately 2 kΩ smaller than the resistor R16 shown in the comparative example.

[0212] According to the modified reference resistor Rref, the resistance value can be adjusted with almost the same resolution (125Ω) and range as the comparative example by controlling the short-circuit switches (NMOS transistors N51 to N55) using switch signals 11 to 15. Similar to the comparative example, while the error generated by the on-resistance of the NMOS transistors constituting the short-circuit switches is suppressed to 10%, the resistance values of the resistors R26, R24, and R28 connected in series to the NMOS transistors N51, N52, and N53 are relatively large, namely 7kΩ, 3kΩ, and 1kΩ, respectively. Therefore, the allowable on-resistance values of the NMOS transistors N51, N52, and N53 can be increased to 700Ω (=7kΩ×10%), 300Ω (=3kΩ×10%), and 100Ω (=1kΩ×10%). As a result, the sizes of the NMOS transistors N51, N52, and N53 can be reduced (by approximately 1 / 50 times, approximately 1 / 10 times, and approximately 1 / 2 times, compared to the comparative example). Furthermore, since the resistance value of the resistor R18 is reduced, the size of the resistor R18 can also be reduced. That is, an increase in the occupied area can be suppressed.

[0213] In order to suppress the error to 10%, the values of the allowable on-resistances of the NMOS transistors N54 and N55 are the same as those in the comparative example, and are 100Ω and 200Ω, respectively.

[0214] <Configuration of Semiconductor Device>

[0215] Figure 12A and Figure 12B is a diagram for describing a semiconductor device according to a second embodiment. Here, Figure 12A is a circuit diagram illustrating a configuration of a semiconductor device according to a second embodiment, Figure 12B is a circuit diagram illustrating the configuration of a reference resistor.

[0216] Figure 12A Similar to Figure 1A The main difference is that in Figure 12A , a resistance value information storage circuit REF_O for setting the resistance value of the reference resistor Rref is indicated. Switch signals 11 to 15 for setting the resistance value of the reference resistor to an appropriate value are pre-stored in the resistance value information storage circuit REF_O. In the second embodiment, the reference resistor Rref is provided in each of the clamp voltage generation circuit and the plurality of sense amplifiers SA, and the output of the resistance value information storage circuit REF_O is supplied to the reference resistor Rref in the clamp voltage generation circuit and the plurality of sense amplifiers SA. As a result, the resistance value of each reference resistor Rref can be set to an appropriate value while suppressing an increase in the occupied area of the resistance value information storage circuit REF_O.

[0217] The terminal node RT1 of the reference resistor Rref is connected to Figure 12A The source terminal of the NMOS transistor N6 is shown, and the terminal node RT2 is connected to the ground voltage Vss. The switching signals 11 to 15 are supplied from the resistance value information storage circuit REF_O to the resistance value adjustment units Rref_ad1 to Rref_ad5. Figure 10 and Figure 11 As described above, the resistance value of the reference resistor Rref is adjusted to an appropriate value by the switching signals 11 to 15 .

[0218] When it is considered that the adjustment function unit for adjusting the resistance value is composed of the resistance value adjustment units Rref_ad1 to Rref_ad5, the adjustment function unit can be regarded as consisting of a coarse adjustment unit (first adjustment unit) and a resistance value fine adjustment unit (second adjustment unit), wherein the coarse adjustment unit (first adjustment unit) roughly adjusts the resistance value, and the resistance value fine adjustment unit (second adjustment unit) finely adjusts the resistance value so as to adjust a certain range of the resistance value with high resolution.

[0219] Figure 12B Corresponding to Figure 10 The reference resistor Rref is shown and Figure 12B , the resistance value adjusting units Rref_ad1 to Rref_ad2 correspond to resistance value fine adjustment units, and the resistance value adjusting units Rref_ad3 to Rref_ad5 correspond to resistance value coarse adjustment units. Figure 12BAs shown, the resistance value coarse adjustment unit (first adjustment unit) is composed of a resistance element (first resistance element: 2×R) composed of a basic resistor R and a MOS transistor (N55) used as a short-circuit switch connected in parallel with the first resistance element, and the resistance value fine adjustment unit (second adjustment unit) is composed of an adjustment unit composed of a resistance element (second resistance element: 3×R), a short-circuit switch (N52) connected in series with the second resistance element, and a resistance element (third resistance element: R) connected in parallel with the adjustment unit.

[0220] In the first and second embodiments, the MRAM is described as an example of the nonvolatile memory device, but is not limited thereto, and for example, a variable resistance memory such as a resistance random access memory (ReRAM) may be used.

[0221] Although the invention made by the present inventors has been specifically described based on the embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the gist of the present invention.

Claims

1. A semiconductor device comprising: a variable resistance memory cell array; a sense amplifier electrically connected to the variable resistance memory cell array; as well as a clamp voltage generating circuit, electrically connected to the sense amplifier, The sense amplifier comprises: an amplifying unit configured to amplify a voltage at the sensing node; A first clamp circuit including a first NMOS transistor and a second NMOS transistor whose gate terminals are electrically connected to each other; a second clamp circuit including a third NMOS transistor and a fourth NMOS transistor whose gate terminals are electrically connected to each other; a fifth NMOS transistor electrically connected to the variable resistance memory cell array; a reference resistor; and a sixth NMOS transistor electrically connected to the reference resistor, wherein a drain terminal of the third NMOS transistor is electrically connected to the amplification unit via a first node configuring the sensing node, wherein a drain terminal of the fourth NMOS transistor is electrically connected to the amplification unit via a second node configuring the sensing node, wherein a source terminal of the third NMOS transistor is electrically connected to a drain terminal of the first NMOS transistor via a third node, wherein the source terminal of the fourth NMOS transistor is electrically connected to the drain terminal of the second NMOS transistor via a fourth node, wherein the source terminal of the first NMOS transistor is electrically connected to the drain terminal of the fifth NMOS transistor via a fifth node, wherein the source terminal of the second NMOS transistor is electrically connected to the drain terminal of the sixth NMOS transistor via a sixth node, wherein a source terminal of the fifth NMOS transistor is electrically connected to the variable resistance memory cell array, wherein a source terminal of the sixth NMOS transistor is electrically connected to the reference resistor, wherein the clamp voltage generating circuit supplies a first clamp voltage to the gate terminals of the first NMOS transistor and the second NMOS transistor, and supplies a second clamp voltage to the gate terminals of the third NMOS transistor and the fourth NMOS transistor, The transconductance of the third NMOS transistor and the fourth NMOS transistor is lower than the transconductance of the first NMOS transistor and the second NMOS transistor.

2. The semiconductor device according to claim 1, The channel lengths of the first NMOS transistor and the second NMOS transistor are shorter than the channel lengths of the third NMOS transistor and the fourth NMOS transistor, and / or the channel widths of the first PMOS transistor and the second NMOS transistor are longer than the channel widths of the third NMOS transistor and the fourth NMOS transistor.

3. The semiconductor device according to claim 2, wherein the sense amplifier includes a current correction circuit electrically connected to the third node and the fourth node, and The current correction circuit applies a correction current to the third node and / or the fourth node based on a correction current bias signal input from the clamp voltage generation circuit.

4. The semiconductor device according to claim 1 , further comprising: a VBL initialization circuit configured to generate an initialization potential to be supplied to the fifth node and the sixth node, The sense amplifier further comprises: a seventh NMOS transistor having a drain terminal electrically connected to the fifth node and a source terminal electrically connected to the VBL initialization circuit; and an eighth NMOS transistor having a drain terminal electrically connected to the sixth node and a source terminal electrically connected to the VBL initialization circuit, and wherein during standby, the seventh NMOS transistor and the eighth NMOS transistor are turned on and the fifth NMOS transistor and the sixth NMOS transistor are turned off.

5. The semiconductor device according to claim 4, The sense amplifier further comprises: a first PMOS transistor; a second PMOS transistor; as well as Noise cancellation circuit, The noise cancellation circuit comprises: an eleventh NMOS transistor; a twelfth NMOS transistor; a thirteenth NMOS transistor; a fourteenth NMOS transistor; and The fifteenth NMOS transistor, wherein a gate terminal of the eleventh NMOS transistor is electrically connected to the clamp voltage generating circuit so that the first clamp voltage is supplied, wherein a gate terminal of the twelfth NMOS transistor is electrically connected to the clamp voltage generating circuit so that the second clamp voltage is supplied, wherein the drain terminal of the eleventh NMOS transistor is electrically connected to the source terminal of the twelfth NMOS transistor, wherein the source terminal of the eleventh NMOS transistor is electrically connected to the drain terminal of the thirteenth NMOS transistor and the drain terminal of the fourteenth NMOS transistor, wherein a source terminal of the fourteenth NMOS transistor is electrically connected to the VBL initialization circuit, wherein the first PMOS transistor is electrically connected to the first node, wherein the second PMOS transistor is electrically connected to the second node, wherein the fifteenth NMOS transistor is electrically connected to the drain terminal of the twelfth NMOS transistor, and During the standby period, the thirteenth NMOS transistor and the fifteenth NMOS transistor are turned on and the fourteenth NMOS transistor is turned off.

6. The semiconductor device according to claim 1, The reference resistor comprises: a first regulating unit; as well as A second regulating unit is connected in series with the first regulating unit, Wherein, in the first regulating unit, a first resistance element and a first transistor used as a short-circuit switch are connected in parallel, and In the second regulating unit, the regulating unit and the third resistance element are connected in parallel, wherein in the regulating unit, the second resistance element and the second transistor serving as a short-circuit switch are connected in series.

7. The semiconductor device according to claim 1, The variable resistance memory cell array is a magnetoresistive memory cell array.

8. A semiconductor device comprising: a memory cell array in which a plurality of variable resistance memory cells are arranged; a sense amplifier connected to the memory cell array; as well as a clamp voltage generating circuit configured to generate a clamp voltage that clamps a voltage applied to a variable resistance memory cell selected from the plurality of variable resistance memory cells during a read operation, The sense amplifier comprises: an amplifying unit configured to amplify a potential difference between a pair of sensing nodes; a precharge circuit configured to supply a predetermined voltage to the pair of sensing nodes during a standby period prior to the read operation; Reference resistor; a first MOS transistor and a second MOS transistor having source-drain paths connected in series between one of the pair of sensing nodes and the selected variable resistance memory cell; and A third MOS transistor and a fourth MOS transistor, source-drain paths of which are connected in series between the other sensing node of the pair of sensing nodes and the reference resistor, wherein the clamp voltage is applied to gate terminals of the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor, wherein the size of the first MOS transistor connected to one sensing node of the first MOS transistor and the second MOS transistor is smaller than the size of the second MOS transistor, and The size of the third MOS transistor connected to the other sensing node of the third MOS transistor and the fourth MOS transistor is smaller than that of the fourth MOS transistor.

9. The semiconductor device according to claim 8, The sense amplifier includes a current correction circuit that supplies a correction current to a node connecting the first MOS transistor and the second MOS transistor and a node connecting the third MOS transistor and the fourth MOS transistor.

10. The semiconductor device according to claim 9, wherein the clamp voltage generating circuit generates a first clamp voltage and a second clamp voltage different from the first clamp voltage as the clamp voltage, wherein a gate terminal of the first MOS transistor and a gate terminal of the third MOS transistor are connected to a first wiring to which the first clamp voltage is applied, wherein a gate terminal of the second MOS transistor and a gate terminal of the fourth MOS transistor are connected to a second wiring to which the second clamp voltage is applied, wherein the semiconductor device further includes an initialization circuit configured to generate an initialization voltage having a value lower than the predetermined voltage supplied by the precharge circuit, and The sense amplifier includes a selection circuit that supplies the initialization voltage generated by the initialization circuit to the third MOS transistor and the fourth MOS transistor during the standby period.

11. The semiconductor device according to claim 10, wherein the sense amplifier includes a noise cancellation circuit having a fifth MOS transistor and a sixth MOS transistor whose source-drain paths are connected in series, wherein the gate terminal of the fifth MOS transistor is connected to the first wiring, and the gate terminal of the sixth MOS transistor is connected to the second wiring, and The initialization voltage is supplied to the sixth MOS transistor by the selection circuit during the standby period.

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