Selective read perturbation sampling

Abstract

The invention relates to selective read perturbation sampling. A processing device in a memory system maintains a counter to track a number of read operations performed on a data block of a memory device, and determines that the number of read operations performed on the data block satisfies a first threshold criterion. The processing device further determines whether a number of scan operations performed on the data block satisfies a scan threshold criterion. In response to the number of scan operations performed on the data block satisfying the scan threshold criterion, the processing device performs a first data integrity scan to determine one or more first error rates of the data block, each of the one or more first error rates corresponding to a first set of word lines of the data block, the first group includes a first alternating pair of adjacent word lines.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application. The parent application is an invention patent application filed on December 17, 2020, with application number 202011496084.4 and title “Selective Read Disturbance Sampling.” Technical Field

[0003] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to selective read disturb sampling in memory subsystems. Background Art

[0004] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally speaking, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0005] In one aspect, the present disclosure relates to a system comprising: a memory device; and a processing device operatively coupled to the memory device to perform operations comprising: maintaining a counter to track a number of read operations performed on a data block of the memory device; determining whether the number of read operations performed on the data block satisfies a read threshold criterion; determining whether the number of scan operations performed on the data block satisfies a scan threshold criterion; and in response to the number of scan operations performed on the data block satisfying the scan threshold criterion, performing a first data integrity scan to determine one or more first error rates for the data block, each of the one or more first error rates corresponding to a first group of word lines of the data block, the first group comprising a first alternating pair of adjacent word lines.

[0006] In another aspect, the present disclosure relates to a method comprising: initiating a first data integrity scan of a first group of multiple word lines of a data block, the multiple word lines comprising a first pair of adjacent word lines, a second pair of adjacent word lines, and a third pair of adjacent word lines; selecting the first pair of adjacent word lines and the third pair of adjacent word lines to be included in the first group; omitting the second pair of adjacent word lines from the first group, wherein the first pair of adjacent word lines and the third pair of adjacent word lines are physically separated in the data block by the second pair of adjacent word lines; and determining one or more reliability statistics corresponding to the first pair of adjacent word lines and the third pair of adjacent word lines as part of the first data integrity scan of the first group of the multiple word lines.

[0007] In yet another aspect, the present disclosure relates to a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: maintain a counter to track a number of read operations performed on a data block of the memory device; determine that the number of read operations performed on the data block satisfies a first threshold criterion; and in response to the number of read operations performed on the data block satisfying the first threshold criterion, perform a first data integrity scan to determine one or more first error rates for the data block, each of the one or more first error rates corresponding to a first group of word lines of the data block, the first group comprising a first alternating pair of adjacent word lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure will be more fully understood from the detailed description provided below and the accompanying drawings of various embodiments of the present disclosure.

[0009] Figure 1 An example computing system including a memory subsystem according to some embodiments of the present disclosure is shown.

[0010] Figure 2 is a block diagram illustrating selective read disturb sampling in a data block of a memory device in a memory subsystem according to some embodiments of the present disclosure.

[0011] Figure 3 is a flow chart of an example method for selective read disturb sampling in a data block of a memory device according to some embodiments of the present disclosure.

[0012] Figures 4A to 4B is a flow chart of an example method of selecting different sets of word lines during subsequent read disturbance scan operations performed on a block of data of a memory device, according to some embodiments of the present disclosure.

[0013] Figure 5 is a block diagram illustrating stress patterns identified from selective read disturb sampling that warrant supplemental read disturb scanning of certain word lines of a data block of a memory device in a memory subsystem, according to some embodiments of the present disclosure.

[0014] Figure 6 is a flow chart of an example method for identifying stress patterns from selective read disturb sampling that warrant supplemental read disturb scanning of certain word lines of a data block in a memory subsystem according to some embodiments of the present disclosure.

[0015] Figure 7 is a flow chart of an example method for identifying stress patterns from selective read disturb sampling that warrant supplemental read disturb scanning of certain word lines of a data block in a memory subsystem according to some embodiments of the present disclosure.

[0016] Figure 8 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0017] Aspects of the present disclosure relate to selective read disturbance sampling in a memory subsystem. The memory subsystem may be a memory device, a memory module, or a mixture of a memory device and a memory module. Figure 1 Examples of storage devices and memory modules are described. Generally speaking, a host system can utilize a memory subsystem that includes one or more components (e.g., memory devices) that store data. The host system can provide data to be stored at the memory subsystem and can request data to be retrieved from the memory subsystem.

[0018] The memory device may be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. Each die may be composed of one or more planes. The planes may be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane is composed of a set of physical blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Hereinafter, a data block refers to a cell of a memory device used to store data and may include a group of memory cells, a word line group, a word line, or an individual memory cell. A memory page (also referred to herein as a "page") stores one or more bits of binary data corresponding to data received from a host system. The memory cells of a data block may be arranged along several individual word lines. When data is written to a memory cell of a memory device for storage, a voltage is applied to the word line on which the memory cell is located, causing the memory cell on the word line to deteriorate. Therefore, the memory cells of each word line of a memory device can handle a limited number of write operations performed before the memory cell can no longer reliably store data. Data stored at memory cells of a memory device can be read from the memory component and transferred to a host system. When data is read from a memory cell on a given word line of a memory device, memory cells on all other word lines on the memory device may experience so-called read disturb. Read disturb is the result of continuously reading from a memory cell without an intervening erase operation, causing other memory cells on other nearby word lines to change (e.g., become programmed) over time. Word lines closer to (e.g., adjacent to) the word line being read may experience higher levels of read disturb than other word lines located further away. If too many read operations are performed on memory cells of a given word line, data stored at memory cells on nearby or adjacent word lines of the memory device may become corrupted or incorrectly stored at the memory cells. This can result in a higher error rate for the data stored at the memory cells and can increase the use of error detection and correction operations (e.g., error control operations) in subsequent operations (e.g., reads and / or writes) performed on the memory cells. The increased use of error control operations can lead to reduced performance of conventional memory subsystems. Furthermore, as the error rate of a memory cell or data block continues to increase, it may even exceed the error correction capability of the memory subsystem, resulting in irreparable loss of data. Furthermore, as more resources of the memory subsystem are used to perform error control operations, fewer resources are available to perform other read or write operations.

[0019] The error rate associated with data stored at a data block may increase due to read disturbance. Therefore, after performing a threshold number of read operations on the data block, the memory subsystem may perform a data integrity check (also referred to herein as a "scan") to verify whether the errors of the data stored at the data block are within acceptable limits. During the data integrity check, one or more reliability statistics are determined for the data stored at the data block. One example of a reliability statistic is the raw bit error rate (RBER). The RBER corresponds to the number of bit errors encountered per sample size (e.g., per page or per codeword) by the data stored at the data block.

[0020] Conventionally, if the reliability statistics for a data block exceed a threshold, indicating a high error rate associated with the data stored at the data block (at least in part due to read disturb), the data stored at the data block is relocated to a new data block in the memory subsystem (also referred to herein as "folding"). Folding the data stored at the data block to other data blocks may include writing the data to the other data blocks to refresh the data stored by the memory subsystem. Doing so can counteract the effects of the read disturb associated with the data and erase the data at the data block. However, as previously discussed, read disturb has a more severe effect on word lines adjacent to the word line performing the read operation than on other word lines located further away. Therefore, if memory cells on a particular word line are read more frequently, read disturb can induce uneven stress on the memory cells of the data block. For example, memory cells of a data block adjacent to a word line from which memory cells are frequently read may have a high error rate, while memory cells not adjacent to the word line may have a lower error rate due to the lesser effect of read disturb on these memory cells.

[0021] Depending on the data access activity of the host system of a particular memory subsystem, the effects of read disturbance can be concentrated on one or more specific memory pages in a block, or more evenly distributed across the entire memory pages of the block. If the read stress is concentrated on a single memory page, then, for example, the block can be considered to be experiencing single word line (SWL) read disturbance (also known as "row hammer" read disturbance). Single word line read disturbance can occur when a certain data segment stored in the memory subsystem is read significantly more frequently than the rest of the data in the same block. However, if the read stress is evenly distributed across multiple memory pages, then the block can be considered to be experiencing uniform read disturbance (also known as "full block" read disturbance). Uniform read disturbance can occur when each data segment in the block is read at approximately the same frequency (for example, for a block storing video file data, where the playback of the video file will trigger the reading of each page of the block).

[0022] Conventional memory subsystems perform data integrity checks using scan operations at the block level. Because scan operations are performed at the block level, the memory subsystem monitors the number of read operations performed on a particular data block and performs a scan operation when the read count (i.e., the number of read operations) meets or exceeds a certain read threshold. Depending on the implementation, the memory subsystem may maintain one or more read counters that track the number of read operations performed on segments of the memory device. For example, some systems may maintain a separate read counter for each physical block, while other systems may maintain a read counter for a superblock (i.e., a collection of multiple physical blocks). In many cases, available memory space (e.g., RAM) is insufficient to support the use of a read counter for each individual wordline of a memory block. Memory subsystem controller firmware typically cannot distinguish between SWL read disturbance stress and uniform read disturbance stress, so it utilizes conservative read threshold settings based on SWL read disturbance stress. Even so, because the read operation count is maintained at the block level, the memory subsystem controller cannot determine which wordlines of a data block are experiencing or may be experiencing SWL read disturbance, and therefore, performs a scan operation on every wordline of the data block. This is often unnecessary because the data block may only be experiencing uniform read disturbance stress, and even in the presence of SWL read disturbance stress, it is likely that only a small percentage of the word lines in the data block are affected. Therefore, performing scans in this manner can cause the memory subsystem to perform excessive memory management operations. This can result in decreased performance of the memory subsystem and increased power consumption of the memory subsystem. System bandwidth and other resources can also be tied up for extended periods, preventing those resources from being used for other functions.

[0023] Aspects of the present disclosure address the above and other deficiencies by performing selective read disturbance sampling. When a data integrity scan is triggered in a data block, a block scan component selectively identifies a first group of word lines of the data block for scanning. Instead of scanning all word lines of the data block, the block scan component may scan approximately 50% of the word lines. The word lines selected for inclusion in the first group may include alternating pairs of adjacent word lines (e.g., every other pair of two adjacent word lines). For example, the block scan component may select a first pair of adjacent word lines, omit a second pair of adjacent word lines, select a third pair of adjacent word lines, and so on, where the first pair of adjacent word lines and the third pair of adjacent word lines are physically separated by the second pair of adjacent word lines. As part of the data integrity scan, the block scan component may determine an error rate or some other reliability statistic for the word lines included in the first group and use the data to determine whether the data block is to be refreshed.

[0024] In the event that a data block experiences an SWL read disturbance, typically, the two word lines immediately adjacent to the word line targeted by the repeated read operation (i.e., the selected word line) experience a higher stress level. Because these two word lines are separated by the selected word line, at least one of the two word lines will be scanned when the block scan component selects to include alternating pairs of adjacent word lines in the word line set. Because the stress levels on each of the two word lines adjacent to the selected word line are approximately equal, either word line can represent the worst-case stress level. Therefore, if the block scan component determines that the stress level warrants a refresh of the data block, the data can be relocated before irreversible damage is caused to the data block. If a block refresh is not required, then in response to a subsequent trigger, the block scan component can perform another data integrity scan on a second set of word lines that includes those word lines that were not scanned during the first data integrity scan. Thus, the set of word lines evaluated during each consecutive data integrity scan can alternate.

[0025] By selecting a specific set of wordlines of a data block for scanning, the sample size for a given data integrity scan can be reduced by approximately 50%. This smaller sample size reduces the time used to perform each data integrity scan, thereby increasing performance, reducing power consumption, and freeing up system resources for other functions. As a result, the memory subsystem controller is occupied less time when performing data integrity scans, allowing the controller more time to handle other data access operations (e.g., host access operations) in the memory subsystem. These benefits are magnified when using higher-density memory (e.g., QLC memory with lower read disturbance capabilities), or as the size of the data block and the corresponding number of wordlines contained therein increase.

[0026] Figure 1 An example computing system 100 is shown that includes a memory subsystem 110, according to some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices.

[0027] The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0028] Computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation), a device with Internet of Things (IoT) capabilities, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or networked commercial device), or such a computing device that includes a memory and a processing device.

[0029] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., with no intervening components), whether wired or wireless, including electrical, optical, magnetic, etc.

[0030] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0031] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket that supports Double Data Rate (DDR)), and the like. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. The host system 120 can further utilize an NVM Express (NVMe) interface to access memory components (e.g., memory device 130) when the memory subsystem 110 is coupled to the host system 120 via a PCIe interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. As an example, Figure 1Shown is a memory subsystem 110. In general, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0032] Memory devices 130 and 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0033] Some examples of nonvolatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. Cross-point arrays of nonvolatile memory can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. In addition, compared to many flash-based memories, cross-point nonvolatile memory can perform write-in-place operations, where nonvolatile memory cells can be programmed even if they have been previously erased. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0034] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of, for example, SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, and an MLC portion, a TLC portion, or a QLC portion of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. In some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0035] Although nonvolatile memory components such as a 3D cross-point nonvolatile memory cell array and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 can be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selected memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), non-OR (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM).

[0036] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130 and other such operations. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0037] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0038] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 is shown as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0039] Generally speaking, the memory subsystem controller 115 may receive commands or operations from the host system 120 and convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions for accessing the memory device 130 and convert responses associated with the memory device 130 into information for the host system 120.

[0040] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0041] In some embodiments, memory device 130 includes a local media controller 135 that, in conjunction with memory subsystem controller 115, performs operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device that is combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0042] In one embodiment, the memory subsystem 110 includes a block scan component 113 that can be used to perform selective read disturb sampling during a scan or other data integrity check of data blocks of the memory devices 130 and 140. In one embodiment, for example, the block scan component 113 maintains one or more counters to track the number of read operations performed on each block of the memory device 130. In response to determining that the number of read operations performed on the data block meets a first threshold criterion, the block scan component can perform a first data integrity scan to determine one or more first error rates for the data block, each of the one or more first error rates corresponding to a first group of word lines of the data block. In one embodiment, the first group of word lines includes alternating pairs of adjacent word lines of the data block (i.e., every other pair of two adjacent word lines). If at least one of the one or more first error rates meets the first error threshold criterion, the block scan component 113 can relocate the data stored in the data block to another data block on the memory device 130 and reset the read counter for the original data block.

[0043] If at least one of the first one or more error rates does not meet the first error threshold criteria, the block scan component 113 may determine whether the number of read operations performed on the data block meets the second threshold criteria. In response to the number of read operations performed on the data block meeting the second threshold criteria, the block scan component 113 may perform a second data integrity scan to determine one or more second error rates for the data block, each of the second one or more error rates corresponding to a second group of word lines of the data block. In one embodiment, the second group of word lines includes second alternating pairs of adjacent word lines (i.e., pairs of adjacent word lines not included in the first group used for the first data integrity scan). If at least one of the one or more second error rates meets the first error threshold criteria, the block scan component 113 may relocate the data stored in the data block to another data block on the memory device 130 and reset the read counter of the original data block.

[0044] In one embodiment, a data block includes a first pair of adjacent word lines, a second pair of adjacent word lines, a third pair of adjacent word lines, and a fourth pair of adjacent word lines. The first pair of adjacent word lines and the third pair of adjacent word lines may be physically separated by the second pair of adjacent word lines, and the second pair of adjacent word lines and the fourth pair of adjacent word lines may be physically separated by the third pair of adjacent word lines. For example, a first group of word lines used for a first data integrity scan may include the first pair of adjacent word lines and the third pair of adjacent word lines, and a second group of word lines used for a second data integrity scan may include the second pair of adjacent word lines and the fourth pair of adjacent word lines.

[0045] In one embodiment, in addition to a first threshold criterion that can trigger a refresh of the associated data block if met or exceeded, the block scan component 113 can also track a second threshold criterion that is less than the first threshold criterion. If, for example, in a first data integrity scan, the block scan component 113 determines that the error rate of at least one word line in a first pair of adjacent word lines meets the second error threshold criterion, and at least one word line error rate in a third pair of adjacent word lines meets the second error threshold criterion, the block scan component 113 can perform a supplemental data integrity scan to determine one or more error rates corresponding to the second pair of adjacent word lines, thereby determining whether a refresh of the data block is appropriate. Similarly, if, in a second data integrity scan, the block scan component 113 determines that the error rate of at least one word line in a second pair of adjacent word lines meets the second error threshold criterion, and at least one word line error rate in a fourth pair of adjacent word lines meets the second error threshold criterion, the block scan component 113 can perform a supplemental data integrity scan to determine one or more error rates corresponding to the third pair of adjacent word lines, thereby determining whether a refresh of the data block is appropriate. This ensures that, in the event that the SWL read disturbance stress is distributed among two or more word lines of a data block, the identified footprint of moderate stress (i.e., stress that meets the lower second error threshold criteria but does not meet the higher first error threshold criteria) among the set of word lines examined during a given data integrity scan can indicate that higher stress may exist on unscanned word lines, which may trigger a refresh of the data block. Therefore, the block scan component 113 can scan those word lines to be checked indicated by the identified footprint, rather than scanning every unscanned word line of the data block. Further details regarding the operation of the block scan component 113 are described below.

[0046] Figure 2is a block diagram illustrating selective read disturb sampling in a data block 200 of a memory device in a memory subsystem according to some embodiments of the present disclosure. In one embodiment, data block 200 represents any of the data blocks comprising memory device 130 or memory device 140. As shown, data block 200 includes several individual word lines, such as word lines WLn+4, WLn+3, WLn+2, WLn+1, WLn, WLn-1, WLn-2, and WLn-2. This number and arrangement of word lines is merely an example, and in other embodiments, data block 200 may include any other number of word lines (e.g., tens or hundreds of word lines). During a memory access operation, such as a read operation, different word lines of data block 200 may experience different voltage levels. For example, when reading data from a memory cell arranged on a particular word line (e.g., WLn), a corresponding read voltage (e.g., VSELECT) is applied to that word line. A pass voltage (e.g., VPASSR) can be applied to other word lines in data block 200 that are not being read. However, in one embodiment, due to the read operation, two word lines (e.g., WLn+1 and WLn-1) adjacent to the read word line (e.g., WLn) are known to experience some capacitive coupling, which can affect the voltage levels on those two adjacent word lines. Therefore, to account for the coupling, and to ensure that those word lines are not activated during the read operation on word line WLn, a higher pass voltage can be applied to those two word lines. As a result, in one embodiment, pass voltage VPASSR is applied to word lines WLn+4, WLn+3, WLn+2, WLn-2, and WLn-2, higher pass voltages VPASSR+Vx and VPASSR+Vy are applied to word lines WLn+1 and WLn-1, respectively, and read voltage VSELECT is applied to word line WLn. If these voltages are repeatedly applied in this manner, the two word lines WLn+1 and WLn-1 will experience higher stress due to the repeated application of higher pass voltages VPASSR+Vx and VPASSR+Vy.

[0047] Thus, in one embodiment, the block scan component 113 can perform selective read disturb sampling in the data block 200. For example, the block scan component 113 can maintain a counter to track the number of read operations performed on the data block 200 and can determine whether the number of read operations satisfies a first threshold criterion (e.g., meets or exceeds a certain threshold). In one embodiment, the counter is maintained at the block level and incremented each time a read operation is performed on any word line of the data block 200. In response to the number of read operations (i.e., the value of the counter) satisfying the first threshold criterion, the block scan component 113 can perform a first data integrity scan to determine one or more error rates for the data block. In one embodiment, the block scan component 113 selects a first group of word lines to be included in the first data integrity scan (e.g., Scan N), where the first group includes alternating pairs of adjacent word lines (e.g., every other pair of adjacent word lines). For example, in one embodiment, the first group of word lines includes a first pair of adjacent word lines (i.e., WLn+4 and WLn+3), omits a second pair of adjacent word lines (i.e., WLn+2 and WLn+1), includes a third pair of adjacent word lines (i.e., WLn and WLn-1), and omits a fourth pair of adjacent word lines (i.e., WLn-2 and WLn-3).

[0048] As described above, WLn+1 and WLn-1 will typically experience higher stress levels due to the application of higher pass voltages VPASSR+Vx and VPASSR+Vy. However, because these two word lines are separated by the selected word line WLn, at least one of the two word lines will be included in the first group. For example, in the illustrated embodiment, WLn-1 is included in the first group, while WLN+1 is not. If the block scan component 113 determines that the stress level on WLn-1 warrants refreshing the data block 200, the data can be relocated before the data block is irreversibly damaged. If a block refresh is not required, then in response to a subsequent trigger, the block scan component 113 can perform another data integrity scan (e.g., Scan N+1) on a second group of word lines that includes those word lines not scanned during the first data integrity scan. For example, in one embodiment, the second group of word lines omits the first pair of adjacent word lines (i.e., WLn+4 and WLn+3), includes the second pair of adjacent word lines (i.e., WLn+2 and WLn+1), omits the third pair of adjacent word lines (i.e., WLn and WLn-1), and includes the fourth pair of adjacent word lines (i.e., WLn-2 and WLn-3). Thus, in this embodiment, WLn+1 is included in the second group, while WLn-1 is not. Because the stress levels on each of the two word lines, WLn+1 and WLn-1, are substantially equal, any one word line can represent the worst stress level in data block 200, and only one of the two word lines need be included in any one data integrity scan.

[0049] Figure 3 is a flow chart of an example method for selective read disturbance sampling in a data block of a memory device according to some embodiments of the present disclosure. Method 300 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 300 is performed by Figure 1 The block scanning component 113 is executed. Although shown in a specific order or sequence, the order of the processes described may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0050] At operation 305, processing logic maintains a counter to track the number of read operations performed on the data block 200 of the memory device 130. In one embodiment, the counter is maintained at the block level and incremented each time a read operation is performed on any word line of the data block 200. In one embodiment, the counter is initialized to an initial value (e.g., 0) and incremented in response to a read operation. In another embodiment, the initial value is some other number, and the value of the counter may be decremented in response to a read operation.

[0051] At operation 310, processing logic determines whether the number of read operations performed on data block 200 (e.g., the value of a counter) meets a read threshold criterion. In one embodiment, the read threshold criterion is met when the number of read operations meets or exceeds a defined threshold. For example, when a data integrity scan is suitable for determining an error level or other reliability metric for data block 200, the threshold may be set to a certain level based on testing or other diagnostics. In one embodiment, block scan component 113 compares the value of the counter to the threshold to determine whether the read threshold criterion is met. If the read count does not meet or exceed the defined threshold, processing logic returns to operation 305 and continues to monitor the read count value of the data block.

[0052] In response to determining that the number of read operations performed on the data block meets the read threshold criteria, at operation 315, processing logic determines whether the number of scan operations performed is even or odd. In one embodiment, the block scan component maintains a separate counter that is incremented each time a scan operation is performed. The number of scan operations performed or the scan operation to be performed next may affect which word lines are included in the set of word lines for the next scan operation. For example, if the number of scan operations performed is even, then the scan threshold criteria may be met. Conversely, if the number of scan operations performed is odd, then the scan threshold criteria is not met. In one embodiment, if the number of scan operations performed is even, then processing logic proceeds to operation 320, and if the number of scan operations performed is not even (i.e., is odd), then processing logic proceeds to operation 325.

[0053] At operation 320, processing logic may perform a first data integrity scan to determine one or more first error rates for the data block 200, each of the one or more first error rates corresponding to a first group of word lines of the data block. In one embodiment, the first group of word lines includes alternating pairs of adjacent word lines of the data block 200 (i.e., every other pair of two adjacent word lines). For example, in one embodiment, the first group of word lines includes a first pair of adjacent word lines (i.e., WLn+4 and WLn+3), omits a second pair of adjacent word lines (i.e., WLn+2 and WLn+1), includes a third pair of adjacent word lines (i.e., WLn and WLn-1), and omits a fourth pair of adjacent word lines (i.e., WLn-2 and WLn-3). During the scan, the block scan component 113 identifies one or more reliability statistics, such as a raw bit error rate (RBER), which represents the number of bit errors per unit time experienced by the data stored at the block. In one embodiment, during the scan, the scan determination component 113 reads a raw codeword (i.e., a series of a fixed number of bits) from a selected word line of the data block 200. The block scan component 113 may apply the codeword to an error correction code (ECC) decoder to generate a decoded codeword and compare the decoded codeword to the original codeword. The block scan component 113 may count the number of flipped bits between the decoded codeword and the original codeword, where the ratio of the number of flipped bits to the total number of bits in the codeword represents the RBER. The block scan component 113 may repeat this process for additional codewords on other selected wordlines until a complete set of wordlines has been scanned.

[0054] At operation 325, processing logic may perform a second data integrity scan to determine one or more second error rates for the data block 200, each of the one or more second error rates corresponding to a second group of word lines of the data block. In one embodiment, the second group of word lines includes alternating pairs of adjacent word lines that are not included in the first group of word lines (i.e., every other pair of two adjacent word lines). For example, in one embodiment, the second group of word lines omits the first pair of adjacent word lines (i.e., WLn+4 and WLn+3), includes the second pair of adjacent word lines (i.e., WLn+2 and WLn+1), omits the third pair of adjacent word lines (i.e., WLn and WLn-1), and includes the fourth pair of adjacent word lines (i.e., WLn-2 and WLn-3). Depending on the embodiment, the second data integrity scan need not be performed after the first data integrity scan and may instead be performed before the first data integrity scan.

[0055] At operation 330, processing logic determines whether the error rate of the block satisfies the error threshold criteria (i.e., meets or exceeds the error threshold). In one embodiment, the block scan component 113 compares the error rate to an error threshold representing the error correction capability of the memory device. If the error rate does not meet or exceed the error threshold, the processing device proceeds to operation 335.

[0056] At operation 335, processing logic increments a counter that tracks the number of scan operations performed and updates the read threshold criteria. For example, because the error rate has not met or exceeded the error threshold and the data block has not been refreshed, the block scan component 113 can lower the read threshold criteria so that a subsequent scan operation can be performed after a fewer number of read operations than the number of read operations that occurred before the previous scan operation was performed. Furthermore, processing returns to operation 305, where processing logic continues to monitor the read count value of the block on the memory component and increments the counter in response to a new read operation.

[0057] If the error threshold criteria are met, then at operation 340, processing logic relocates the data from data block 200 to another block and resets the read count value of the read counter (e.g., to zero or some other initial value). In one embodiment, block scan component 113 reads the data stored in data block 200 (i.e., the block whose error rate meets or exceeds the error threshold) and writes the data to another block. Once the data is written to the other block, the data stored in the initial data block 200 is erased and the initial block is available for programming with the new data. Depending on the embodiment, the data is relocated to another block in the same plane of the same memory device, to another plane on the same memory device, or to a different memory device of the memory subsystem 110. In addition, block scan component 113 also increments a counter that tracks the number of scan operations performed.

[0058] Figures 4A to 4B is a flow chart of an example method for selecting different sets of word lines during subsequent read disturbance scan operations performed on a data block of a memory device according to some embodiments of the present disclosure. Method 400 may be performed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 400 is performed by Figure 1 The block scanning component 113 is executed. Although shown in a specific order or sequence, the order of the processes described may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0059] At operation 410, processing logic determines whether a first read count of the data block 200 satisfies a read threshold criterion, the first read count indicating the number of read operations performed on the data block 200. In response to determining that the first read count of the data block does not satisfy the read threshold criterion, processing logic returns to operation 410 and continues to monitor the read count of the data block 200.

[0060] In response to determining that the first read count of data block 200 satisfies the read threshold criteria, at operation 415, processing logic initiates a first data integrity scan of a first plurality of word lines of data block 200. At operation 420, processing logic selects a first pair of adjacent word lines (e.g., WLn+4 and WLn+3) and a third pair of adjacent word lines (e.g., WLn and WLn-1) to include in the first group, while omitting a second pair of adjacent word lines (e.g., WLn+2 and WLn+1), wherein the first pair of adjacent word lines and the third pair of adjacent word lines are physically separated by the second pair of adjacent word lines in data block 200. At operation 425, as part of the first data integrity scan of the first plurality of word lines, processing logic determines one or more reliability statistics (e.g., error rates) corresponding to the first pair of adjacent word lines and the third pair of adjacent word lines.

[0061] At operation 430, processing logic determines whether at least one of the one or more reliability statistics of the block satisfies an error threshold criterion (i.e., meets or exceeds an error threshold). In one embodiment, the block scan component 113 compares the determined reliability statistics for each word line to an error threshold representing the error correction capability of the memory device. If the error rate does not meet or exceed the error threshold, the processing device proceeds to operation 440, as shown in FIG. Figure 4B (see box "A").

[0062] If the error threshold criteria are met, then at operation 435, processing logic relocates the data from the data block 200 to another block and resets the read count value of the read counter (e.g., to zero or some other initial value). In one embodiment, the block scan component 113 reads the data stored in the data block 200 (i.e., the block whose reliability statistics meet or exceed the error threshold) and writes the data to the other block. Once the data is written to the other block, the data stored in the initial data block 200 is erased and the initial block is available for programming with new data.

[0063] See Figure 4B At operation 440 , processing logic determines whether the read count of data block 200 satisfies the second read threshold criteria. In response to determining that the read count of the data block does not satisfy the second read threshold criteria, processing logic returns to operation 440 and continues to monitor the read count of data block 200 .

[0064] In response to determining that the read count of data block 200 satisfies the second read threshold criteria, at operation 445, processing logic initiates a second data integrity scan of a second plurality of word lines of data block 200. At operation 450, processing logic selects a second pair of adjacent word lines (e.g., WLn+2 and WLn+1) for inclusion in the second group, while omitting the first pair of adjacent word lines (e.g., WLn+4 and WLn+3) and the third pair of adjacent word lines (e.g., WLn and WLn-1). At operation 455, as part of the second data integrity scan of the second plurality of word lines, processing logic determines one or more reliability statistics (e.g., error rates) corresponding to the second pair of adjacent word lines.

[0065] At operation 460, processing logic determines whether at least one of the one or more reliability statistics of the block satisfies an error threshold criterion (i.e., meets or exceeds an error threshold). In one embodiment, the block scan component 113 compares the determined reliability statistics for each word line to an error threshold representing the error correction capability of the memory device. If the error rate does not meet or exceed the error threshold, the processing device proceeds to operation 470 and continues processing.

[0066] If the error threshold criteria are met, then at operation 465, processing logic relocates the data from the data block 200 to another block and resets the read count value of the read counter (e.g., to zero or some other initial value). In one embodiment, the block scan component 113 reads the data stored in the data block 200 (i.e., the block whose reliability statistics meet or exceed the error threshold) and writes the data to the other block. Once the data is written to the other block, the data stored in the initial data block 200 is erased and the initial block is available for programming with new data.

[0067] Figure 5 is a block diagram illustrating a stress pattern identified from selective read disturb sampling that warrants a supplemental read disturb scan of certain word lines of a data block of a memory device in a memory subsystem, according to some embodiments of the present disclosure. In one embodiment, data block 500 represents data block 200 or any of the other data blocks comprising memory device 130 or memory device 140. As shown, data block 500 includes several individual word lines, such as word lines WLn+4, WLn+3, WLn+2, WLn+1, WLn, WLn-1, WLn-2, and WLn-3. This number and arrangement of word lines is merely an example, and in other embodiments, data block 500 may include any other number of word lines (e.g., tens or hundreds of word lines). During a memory access operation, such as a read operation, different word lines of data block 200 may experience different voltage levels. In one embodiment, a certain pattern of read operations performed on data block 500 may exist. For example, a certain percentage (e.g., approximately 50% or some other percentage) of read operations can be directed to WLn. As a result, in one embodiment, pass voltage VPASSR is applied to word lines WLn+4, WLn+3, WLn+2, WLn-2, and WLn-2, higher pass voltages VPASSR+Vx and VPASSR+Vy are applied to word lines WLn+1 and WLn-1, respectively, and read voltage VSELECT is applied to word line WLn, accounting for approximately 50% of read operations. Furthermore, another percentage (e.g., approximately 50% or some other percentage) of read operations can be directed to WLn+2. As a result, in one embodiment, pass voltage VPASSR is applied to word lines WLn+4, WLn, WLn-1, WLn-2, and WLn-2, higher pass voltages VPASSR+Vx and VPASSR+Vy are applied to word lines WLn+3 and WLn+1, respectively, and read voltage VSELECT is applied to word line WLn+2, accounting for approximately 50% of the read operation.

[0068] Thus, in one embodiment, the block scan component 113 can perform selective read disturbance sampling in the data block 500, as described above. For example, the block scan component 113 can maintain a counter to track the number of read operations performed on the data block 500, and can determine whether the number of read operations meets a first threshold criterion (e.g., meets or exceeds a certain threshold). In one embodiment, the counter is maintained at the block level and incremented each time a read operation is performed on any word line of the data block 500. In response to the number of read operations (i.e., the value of the counter) meeting the first threshold criterion, the block scan component 113 can perform a first data integrity scan to determine one or more error rates for the data block. In one embodiment, the block scan component 113 selects a first group of word lines to be included in the first data integrity scan (e.g., Scan N), where the first group includes alternating pairs of adjacent word lines (e.g., every other pair of adjacent word lines). For example, in one embodiment, the first group of word lines includes a first pair of adjacent word lines (i.e., WLn+4 and WLn+3), omits a second pair of adjacent word lines (i.e., WLn+2 and WLn+1), includes a third pair of adjacent word lines (i.e., WLn and WLn-1), and omits a fourth pair of adjacent word lines (i.e., WLn-2 and WLn-3).

[0069] As described above, WLn+3, WLn+1, and WLn-1 will typically experience higher stress levels due to the application of higher pass voltages VPASSR+Vx and VPASSR+Vy during corresponding read operations. In one embodiment, the stress experienced by each word line is Figure 5 5 is shown in graphical form 510. In one embodiment, WLn+3 and WLn-1 experience a moderate stress level because the higher pass voltages VPASSR+Vx and VPASSR+Vy are only applied to those word lines that account for approximately 50% of the read operations, while WLn+1 experiences a higher stress level because the higher pass voltage is applied to that word line that accounts for approximately 100% of the read operations.

[0070] Because WLn+3 and WLn-1 are included in the first set of word lines used for the first scan operation, and WLn+1 is omitted from the first set, the high stress level on WLn+1 may not be detected in the first scan operation. Therefore, in one embodiment, in addition to the first threshold criterion that can trigger a refresh of the associated data block if met or exceeded, the block scan component 113 can also track a second threshold criterion that is less than the first threshold criterion. If, during the first data integrity scan, for example, the block scan component 113 determines that the error rate of at least one word line in the first pair of adjacent word lines (e.g., WLn+3) meets (e.g., meets or exceeds) the second error threshold criterion, and the error rate of at least one word line in the third pair of adjacent word lines (e.g., WLn-1) meets the second error threshold criterion, the block scan component 113 can perform a supplemental data integrity scan to determine one or more error rates corresponding to the second pair of adjacent word lines (e.g., WLn+2 and WLn+1) to determine whether it is appropriate to refresh the data block. This ensures that, in the event that the SWL read disturbance stress is spread across two or more word lines of a data block, the identified footprint of moderate stress (i.e., stress that satisfies the lower second error threshold criterion but does not satisfy the higher first error threshold criterion) among the set of word lines examined during a given data integrity scan can indicate that higher stress may exist on the unscanned word line (i.e., WLn+1), which may trigger a refresh of the data block. Therefore, the block scan component 113 can scan those word lines to be inspected (i.e., WLn+2 and WLn+1) indicated by the identified footprint, rather than scanning every unscanned word line of the data block.

[0071] Figure 6 is a flow chart of an example method for identifying stress patterns from selective read disturbance sampling that warrant supplemental read disturbance scanning of certain word lines of a data block in a memory subsystem according to some embodiments of the present disclosure. Method 600 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 600 is performed by Figure 1 The block scanning component 113 is executed. Although shown in a specific order or sequence, the order of the processes described may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0072] At operation 605, processing logic determines that at least one error rate or other reliability statistic determined from the data integrity scan does not meet a first error threshold criterion associated with refreshing data block 500. At operation 610, processing logic determines whether the error rate of at least one word line in a first pair of adjacent word lines (e.g., WLn+4 and WLn+3) meets a second error threshold criterion that is lower than the first threshold criterion, and whether the error rate of at least one word line in a third pair of adjacent word lines (e.g., WLn and WLn-1) meets a second, lower error threshold criterion. If not, processing logic returns to operation 605. However, if so, then at operation 615, processing logic performs a supplemental data integrity scan to determine one or more error rates corresponding to a second pair of adjacent word lines (e.g., WLn+2 and WLn+1), the second pair of adjacent word lines being physically located between the first and second pairs of adjacent word lines in data block 500.

[0073] At operation 620, processing logic determines whether one or more error rates corresponding to the second pair of adjacent word lines meet the first higher error threshold criteria. If so, then at operation 625, processing logic relocates data from data block 500 to another block and resets the read count value of the read counter (e.g., to zero or some other initial value). If not, then at operation 630, processing logic continues processing.

[0074] Figure 7 is a flow chart of an example method for identifying stress patterns from selective read disturbance sampling that warrant supplemental read disturbance scanning of certain word lines of a data block in a memory subsystem according to some embodiments of the present disclosure. Method 700 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 700 is performed by Figure 1 The block scanning component 113 is executed. Although shown in a specific order or sequence, the order of the processes described may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0075] At operation 705, processing logic determines that at least one error rate or other reliability statistic determined from the data integrity scan does not meet a first error threshold criterion associated with refreshing data block 500. At operation 710, processing logic determines whether the error rate of at least one word line in a second pair of adjacent word lines (e.g., WLn+2 and WLn+1) meets a second error threshold criterion that is lower than the first threshold criterion, and whether the error rate of at least one word line in a fourth pair of adjacent word lines (e.g., WLn-2 and WLn-3) meets a second lower error threshold criterion. If not, processing logic returns to operation 705. However, if so, then at operation 715, processing logic performs a supplemental data integrity scan to determine one or more error rates corresponding to a third pair of adjacent word lines (e.g., WLn and WLn-1), the third pair of adjacent word lines being physically located between the second and fourth pairs of adjacent word lines in data block 500.

[0076] At operation 720, processing logic determines whether one or more error rates corresponding to the second pair of adjacent word lines meet the first higher error threshold criteria. If so, then at operation 725, processing logic relocates data from data block 500 to another block and resets the read count value of the read counter (e.g., to zero or some other initial value). If not, then at operation 730, processing logic continues processing.

[0077] Figure 8 An example machine of a computer system 800 is shown within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 800 may correspond to a host system (e.g., Figure 1 host system 120) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 110), or can be used to perform operations of the controller (for example, to execute an operating system to execute the corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client user machine in server-client user network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0078] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or collectively execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0079] The example computer system 800 includes a processing device 802, a main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 806 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 818, which communicate with each other via a bus 830.

[0080] The processing device 802 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 802 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 802 is configured to execute instructions 826 for performing the operations and steps discussed herein. The computer system 800 may further include a network interface device 808 that communicates via a network 820.

[0081] The data storage system 818 may include a machine-readable storage medium 824 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 826 or software embodying any one or more of the methodologies or functions described herein. The instructions 826 may also reside completely or at least partially within the main memory 804 and / or within the processing device 802 during execution by the computer system 800, the main memory 804, and the processing device 802, which also constitute the machine-readable storage medium. The machine-readable storage medium 824, the data storage system 818, and / or the main memory 804 may correspond to Figure 1 Memory subsystem 110.

[0082] In one embodiment, instructions 826 include implementing instructions corresponding to Figure 1The block scanning component 113 of the embodiment of the present invention may include instructions for the functionality of the block scanning component 113. Although the machine-readable storage medium 824 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0083] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the most effective means for those skilled in the art of data processing to convey their work to others skilled in the art. Here, and generally speaking, an algorithm is conceived to be a self-consistent sequence of operations that produces a desired result. The operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0084] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0085] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the desired purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored on a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0086] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods described. Structures for various such systems will be presented in the following description. Furthermore, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein can be implemented using a variety of programming languages.

[0087] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, or the like.

[0088] In the foregoing description, the embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. The description and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system comprising: memory device; and a processing device operatively coupled with the memory device to perform operations comprising: determining an occurrence of a triggering event for a segment of the memory device; determining a number of scan operations performed on the segment of the memory device; as well as Based on the number of scan operations performed on the segment of the memory device, a first group of word lines of the segment is identified and a first data integrity scan is performed to determine one or more first error rates corresponding to the first group of word lines, the first group of word lines comprising first alternating pairs of adjacent word lines.

2. The system of claim 1 , wherein determining the occurrence of the triggering event for the segment of the memory device comprises: maintaining a counter to track a number of read operations performed on the segment of the memory device; It is determined that the number of read operations performed on the segment satisfies a read threshold criterion.

3. The system of claim 1 , wherein the processing device is configured to perform operations further comprising: determining whether at least one of the first one or more error rates satisfies a first error threshold criterion; and Responsive to at least one of the first one or more error rates satisfying the first error threshold criterion, relocating data stored in the segment to another segment on the memory device.

4. The system of claim 3, wherein the first set of word lines of the segment comprises a first alternating pair of adjacent word lines in the memory device, and wherein the first set of word lines is interleaved with but does not include a second set of word lines.

5. The system of claim 4 , wherein the segment comprises a first pair of adjacent word lines, a second pair of adjacent word lines, a third pair of adjacent word lines, and a fourth pair of adjacent word lines, the first group of word lines comprises the first pair of adjacent word lines and the third pair of adjacent word lines, the second group of word lines comprises the second pair of adjacent word lines and the fourth pair of adjacent word lines, wherein the first pair of adjacent word lines and the third pair of adjacent word lines are physically separated by the second pair of adjacent word lines, and wherein the second pair of adjacent word lines and the fourth pair of adjacent word lines are physically separated by the third pair of adjacent word lines.

6. The system of claim 5, wherein the processing device is configured to perform operations further comprising: determining that an error rate of at least one word line in the first pair of adjacent word lines satisfies a second error threshold criterion and an error rate of at least one word line in the third pair of adjacent word lines satisfies the second error threshold criterion, wherein the second error threshold criterion is less than the first error threshold criterion; and A supplemental data integrity scan is performed to determine one or more error rates corresponding to the second pair of adjacent word lines.

7. The system of claim 6, wherein the processing device is configured to perform operations further comprising: determining whether at least one of the one or more error rates corresponding to the second pair of adjacent word lines satisfies the first error threshold criterion; and In response to at least one of the one or more error rates corresponding to the second pair of adjacent word lines satisfying the first error threshold criterion, data stored in the segment is relocated to another segment on the memory device.

8. A method comprising: determining an occurrence of a triggering event for a segment of a memory device; determining a number of scan operations performed on the segment of the memory device; as well as Based on the number of scan operations performed on the segment of the memory device, a first group of word lines of the segment is identified and a first data integrity scan is performed to determine one or more first error rates corresponding to the first group of word lines, the first group of word lines comprising first alternating pairs of adjacent word lines.

9. The method of claim 8, wherein determining the occurrence of the triggering event for the segment of the memory device comprises: maintaining a counter to track a number of read operations performed on the segment of the memory device; It is determined that the number of read operations performed on the segment satisfies a read threshold criterion.

10. The method according to claim 8, further comprising: determining whether at least one of the first one or more error rates satisfies a first error threshold criterion; as well as Responsive to at least one of the first one or more error rates satisfying the first error threshold criterion, relocating data stored in the segment to another segment on the memory device.

11. The method of claim 10, wherein the first set of word lines of the segment comprises a first alternating pair of adjacent word lines in the memory device, and wherein the first set of word lines is interleaved with but does not include a second set of word lines.

12. The method of claim 11 , wherein the segment comprises a first pair of adjacent word lines, a second pair of adjacent word lines, a third pair of adjacent word lines, and a fourth pair of adjacent word lines, the first group of word lines comprises the first pair of adjacent word lines and the third pair of adjacent word lines, the second group of word lines comprises the second pair of adjacent word lines and the fourth pair of adjacent word lines, wherein the first pair of adjacent word lines and the third pair of adjacent word lines are physically separated by the second pair of adjacent word lines, and wherein the second pair of adjacent word lines and the fourth pair of adjacent word lines are physically separated by the third pair of adjacent word lines.

13. The method according to claim 12, further comprising: determining that an error rate of at least one word line in the first pair of adjacent word lines satisfies a second error threshold criterion and an error rate of at least one word line in the third pair of adjacent word lines satisfies the second error threshold criterion, wherein the second error threshold criterion is less than the first error threshold criterion; as well as A supplemental data integrity scan is performed to determine one or more error rates corresponding to the second pair of adjacent word lines.

14. The method according to claim 13, further comprising: determining whether at least one of the one or more error rates corresponding to the second pair of adjacent word lines satisfies the first error threshold criterion; as well as In response to at least one of the one or more error rates corresponding to the second pair of adjacent word lines satisfying the first error threshold criterion, data stored in the segment is relocated to another segment on the memory device.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: determining an occurrence of a triggering event for a segment of a memory device; determining a number of scan operations performed on the segment of the memory device; and Based on the number of scan operations performed on the segment of the memory device, a first group of word lines of the segment is identified and a first data integrity scan is performed to determine one or more first error rates corresponding to the first group of word lines, the first group of word lines comprising first alternating pairs of adjacent word lines.

16. The non-transitory computer-readable storage medium of claim 15, wherein the instructions cause the processing device to perform operations further comprising: determining whether at least one of the first one or more error rates satisfies a first error threshold criterion; and Responsive to at least one of the first one or more error rates satisfying the first error threshold criterion, relocating data stored in the segment to another segment on the memory device.

17. The non-transitory computer-readable storage medium of claim 16, wherein the first set of word lines of the segment comprises a first alternating pair of adjacent word lines in the memory device, and wherein the first set of word lines is interleaved with but does not include a second set of word lines.

18. The non-transitory computer-readable storage medium of claim 17 , wherein the segment comprises a first pair of adjacent word lines, a second pair of adjacent word lines, a third pair of adjacent word lines, and a fourth pair of adjacent word lines, the first group of word lines comprises the first pair of adjacent word lines and the third pair of adjacent word lines, the second group of word lines comprises the second pair of adjacent word lines and the fourth pair of adjacent word lines, wherein the first pair of adjacent word lines and the third pair of adjacent word lines are physically separated by the second pair of adjacent word lines, and wherein the second pair of adjacent word lines and the fourth pair of adjacent word lines are physically separated by the third pair of adjacent word lines.

19. The non-transitory computer-readable storage medium of claim 18, wherein the instructions cause the processing device to perform operations further comprising: determining that an error rate of at least one word line in the first pair of adjacent word lines satisfies a second error threshold criterion and an error rate of at least one word line in the third pair of adjacent word lines satisfies the second error threshold criterion, wherein the second error threshold criterion is less than the first error threshold criterion; and A supplemental data integrity scan is performed to determine one or more error rates corresponding to the second pair of adjacent word lines.

20. The non-transitory computer-readable storage medium of claim 19, wherein the instructions cause the processing device to perform operations further comprising: determining whether at least one of the one or more error rates corresponding to the second pair of adjacent word lines satisfies the first error threshold criterion; and In response to at least one of the one or more error rates corresponding to the second pair of adjacent word lines satisfying the first error threshold criterion, data stored in the segment is relocated to another segment on the memory device.

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