Method for forming bonded wafer

Abstract

The invention provides a method for forming a bonded wafer, and the method comprises the steps: enabling a difference value between the bending degree of a device substrate and the bending degree of a supporting substrate to be within a preset range through controlling the bending degree of the device substrate and / or the bending degree of the supporting substrate. Therefore, in the process of bonding the device substrate and the supporting substrate, the stress of the bonding interface of the supporting substrate and the device substrate can be regulated and controlled, so that the stress of the bonding interface is in a proper range. Therefore, the problem that the bonding strength between the device substrate and the supporting substrate is not enough due to the fact that the bending difference between the device substrate and the supporting substrate is too large can be avoided, and then bonding defects are reduced or avoided; meanwhile, the problem that the stress of the bonding interface of the device substrate and the supporting substrate is small due to the fact that the bending difference value between the device substrate and the supporting substrate is too small can be solved, the problem that planarization driving force is insufficient in the subsequent heat treatment planarization process is solved, and then the roughness of the surface of a bonded wafer is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a method for forming a bonded wafer. Background Art

[0002] Silicon on insulator (SOI) technology has now become one of the mainstream products in most electronic materials fields. With the rapid development of new energy vehicles, the integration of automotive-grade SOI wafer-based chips has gradually increased, and therefore the quality requirements for the device layer in the SOI wafer are becoming increasingly higher.

[0003] In current SOI wafer formation methods, a device substrate and a supporting substrate are typically bonded to form a bonded wafer (i.e., an SOI wafer). After the bonded wafer is formed, the device substrate serves as the device layer of the bonded wafer. However, current device layers suffer from high surface roughness and numerous particle defects, resulting in low device layer quality. This low device layer quality can lead to issues such as photolithography overlay failure, increased threshold voltage, and leakage current, thus impacting device manufacturing process and performance. Summary of the Invention

[0004] The object of the present invention is to provide a method for forming a bonded wafer to improve the roughness and defects of the bonded wafer surface.

[0005] To solve the above technical problems, the present invention provides a method for forming a bonded wafer, comprising:

[0006] Providing a device substrate and a support substrate, wherein the device substrate has a first set curvature, and the support substrate has a second set curvature, and a difference between the first set curvature and the second set curvature is within a preset range;

[0007] The device substrate and the support substrate are bonded to form a bonded wafer.

[0008] Optionally, in the method for forming a bonded wafer, the preset range is 0 μm to 20 μm.

[0009] Optionally, in the method for forming a bonded wafer, the curvature of the support substrate is -5 μm to 30 μm.

[0010] Optionally, in the method for forming a bonded wafer, the curvature of the device substrate is -5 μm to 10 μm.

[0011] Optionally, in the method for forming a bonded wafer, before bonding the device substrate and the support substrate, the method further includes:

[0012] An oxide layer of a preset thickness is formed on the surface of the device substrate and / or the surface of the support substrate. After the device substrate and the support substrate are bonded, part of the oxide layer is located between the device substrate and the support substrate to form a buried oxide layer.

[0013] Optionally, in the method for forming a bonded wafer, the thickness of the oxide layer on the surface of the device substrate and / or the thickness of the oxide layer on the surface of the support substrate is less than or equal to 0.4 μm.

[0014] Optionally, in the method for forming a bonded wafer, the buried oxide layer has a thickness of 0.01 μm to 1 μm.

[0015] Optionally, in the method for forming a bonded wafer, before bonding the device substrate and the support substrate, the method further includes:

[0016] Ion implantation is performed on the device substrate to form an ion implantation layer, wherein the depth of the ion implantation layer is 100 nm to 600 nm, and the width of the ion implantation layer is 10 nm to 100 nm.

[0017] Optionally, in the method for forming a bonded wafer, after bonding the device substrate and the support substrate, the method further includes:

[0018] A thermal treatment planarization process is performed on the bonded wafer.

[0019] Optionally, in the method for forming a bonded wafer, after bonding the device substrate and the support substrate and before performing a heat treatment and planarization process on the bonded wafer, the method for forming a bonded wafer further includes:

[0020] The bonded wafer is subjected to a reinforcement heat treatment.

[0021] In the method for forming a bonded wafer provided by the present invention, the device substrate has a first set curvature, the support substrate has a second set curvature, the difference between the first set curvature and the second set curvature is within a preset range, and by controlling the curvature of the device substrate and / or the curvature of the support substrate, the difference between the curvature of the device substrate and the curvature of the support substrate is made within a preset range. In this way, in the process of bonding the device substrate and the support substrate, the stress of the bonding interface between the support substrate and the device substrate can be regulated so that the stress of the bonding interface is within an appropriate range. This can avoid the problem of insufficient bonding strength between the device substrate and the support substrate due to the large difference in curvature between the device substrate and the support substrate, thereby reducing or avoiding the generation of bonding defects; at the same time, it can also avoid the problem of small stress at the bonding interface between the device substrate and the support substrate due to the small difference in curvature between the device substrate and the support substrate, thereby avoiding the problem of insufficient flattening driving force in the subsequent heat treatment flattening process, thereby improving the roughness of the bonded wafer surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic flow chart of a method for forming a bonded wafer according to an embodiment of the present invention;

[0023] Figures 2 to 12 is a schematic diagram of a structure formed in a method for forming a bonded wafer according to an embodiment of the present invention; Figure 13 Schematic diagram of the relationship between the curvature difference between the support substrate and the device substrate and the surface roughness in the method for forming a bonded wafer according to an embodiment of the present invention;

[0024] Figures 14 to 28 2 is a schematic diagram of a surface after heat treatment and flattening in a method for forming a bonded wafer according to an embodiment of the present invention.

[0025] The description of the accompanying drawings is as follows:

[0026] 100 - bonding wafer; 102 - device substrate; 101 - supporting substrate; 103 - oxide layer; 104 - ion implantation layer. DETAILED DESCRIPTION

[0027] The following is a detailed description of the bonded wafer forming method proposed by the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0028] Figure 1 Schematic diagram of the process of forming a bonded wafer according to an embodiment of the present invention. Figure 1As shown, the method for forming a bonded wafer provided in this embodiment includes:

[0029] Step S1: providing a device substrate and a support substrate, wherein the device substrate has a first set curvature, and the support substrate has a second set curvature, and a difference between the first set curvature and the second set curvature is within a preset range;

[0030] Step S2: bonding the device substrate and the support substrate to form a bonded wafer.

[0031] Figures 2 to 12 This is a schematic diagram of the structure formed in the method for forming a bonded wafer provided by an embodiment of the present invention. Figures 2 to 12 The method for forming the bonded wafer provided in this embodiment is described in more detail.

[0032] First, execute step S1, as Figure 2 and Figure 3 A support substrate 101 and a device substrate 102 are provided. The device substrate 102 has a first predetermined curvature, and the support substrate 101 has a second predetermined curvature. The difference between the first predetermined curvature and the second predetermined curvature is within a preset range. The material of the device substrate 102 is the same as that of the support substrate 101, and both the material of the device substrate 102 and the material of the support substrate 101 can be silicon.

[0033] In this embodiment, the method for preparing the device substrate 102 and the support substrate 101 includes: first, providing a silicon ingot grown by the Czochralski method, wherein the crystal growth direction of the silicon ingot can be <100> 、 <110> or <111> Then, the silicon ingot is subjected to edge grinding to reach the target diameter, and is segmented to form crystal segments, with the notch direction being <110> Next, the crystal segment is sliced, polished, and cleaned in sequence to form a device substrate 102. The thickness of the device substrate 102 may be 500 μm to 800 μm.

[0034] Next, another crystal segment is sliced, polished, and cleaned to form a support substrate 101. The thickness of the support substrate 101 can be 500 μm to 800 μm. In other words, the method for forming the support substrate 101 is the same as the method for forming the device substrate 102, and the thickness of the support substrate 101 can be the same as that of the device substrate 102.

[0035] Next, the curvature of the device substrate 102 and / or the curvature of the support substrate 101 are adjusted so that the device substrate 102 has a first set curvature and the support substrate 101 has a second set curvature, and the difference between the first set curvature and the second set curvature is within a preset range. This allows the stress at the bonding interface between the support substrate 101 and the device substrate 102 to be controlled during the subsequent bonding process, ensuring that the stress at the bonding interface is within an appropriate range. This can avoid the problem of insufficient bonding strength between the device substrate 102 and the supporting substrate 101 due to the large difference in curvature between the device substrate 102 and the supporting substrate 101, thereby reducing or avoiding the occurrence of bonding defects; at the same time, it can also avoid the problem of small bonding interface stress between the device substrate 102 and the supporting substrate 101 due to the small difference in curvature between the device substrate 102 and the supporting substrate 101, thereby avoiding the problem of insufficient flattening driving force in the subsequent heat treatment flattening process, thereby improving the roughness of the surface of the bonded wafer 100.

[0036] In this embodiment, the preset range may be 0 μm to 20 μm, that is, the difference between the first set curvature of the device substrate 102 and the second set curvature of the support substrate 101 may be 0 μm to 20 μm.

[0037] In some embodiments, the curvature of the device substrate 102 is adjusted to provide the device substrate 102 with a first set curvature, such that the difference between the curvature of the device substrate 102 and the curvature of the support substrate 101 is within a preset range.

[0038] In one embodiment, the method for adjusting the curvature of the device substrate 102 includes: Figure 5 As shown, an oxide layer 103 of a preset thickness is formed on the surface of the device substrate 102 , and the curvature of the device substrate 102 is adjusted by the oxide layer 103 of the preset thickness so that the curvature of the device substrate 102 is within a set range.

[0039] Specifically, the oxide layer 103 can be formed by combining a dry oxidation process with a wet oxidation process. That is, a dry oxidation process is first performed on the device substrate 102 to form a partial thickness of the oxide layer 103 on the surface of the device substrate 102, and then a wet oxidation process is performed on the device substrate 102 to increase the thickness of the oxide layer 103 to a predetermined thickness. In this way, the finally formed oxide layer 103 can have good density and uniformity (achieved by the dry oxidation process) and can achieve rapid growth of the oxide layer 103 (achieved by the wet oxidation process). The material of the oxide layer 103 is silicon oxide.

[0040] Exemplarily, the dry oxidation process utilizes an oxidation furnace or a rapid thermal annealing chamber to oxidize the surface of the device substrate 102 under the conditions that the process gas is oxygen and the temperature is 850°C to 1050°C, thereby forming an oxide layer 103 of partial thickness, and the oxygen gas flow rate is 1slm to 10slm.

[0041] Exemplarily, the wet oxidation process is an in-situ steam generation (ISSG) process, in which hydrogen and oxygen are introduced into a rapid thermal annealing chamber to form water vapor in situ. The water vapor then chemically reacts with silicon on the surface of the device substrate 102 to form the oxide layer 103. The water vapor flow rate can be 0 slm to 20 slm.

[0042] In this embodiment, the thickness of the oxide layer 103 on the surface of the device substrate 102 is less than or equal to 0.4 μm and greater than 0 μm, for example, 0.3 μm, 0.2 μm or 0.1 μm, so as to regulate the curvature of the device substrate 102 so that the curvature of the device substrate 102 is within a set range.

[0043] In another embodiment, if Figure 6 As shown, the method for adjusting the curvature of the device substrate 102 includes: performing ion implantation on the device substrate 102 to form an ion implantation layer 104, wherein the depth of the ion implantation layer 104 is 100 nm to 600 nm, and the width of the ion implantation layer 104 is 10 nm to 100 nm. That is, the curvature of the device substrate 102 is adjusted by adjusting the depth and width of the ion implantation layer 104, so that the curvature of the device substrate 102 is within a set range. The energy of the ion implantation can be 20 keV to 80 keV.

[0044] In this embodiment, the first set curvature of the device substrate 102 may be set in a range of -5 μm to 10 μm, such as -4 μm, 1 μm or 5 μm.

[0045] In some embodiments, the curvature of the support substrate 101 is adjusted so that the support substrate 101 has a second set curvature, so that the difference between the curvature of the device substrate 102 and the curvature of the support substrate 101 is within a preset range.

[0046] For example, Figure 4As shown, the method for adjusting the curvature of the support substrate 101 includes: forming an oxide layer 103 of a preset thickness on the surface of the support substrate 101, and adjusting the curvature of the support substrate 101 through the oxide layer 103 of the preset thickness so that the support substrate 101 has a second set curvature. The method for forming the oxide layer 103 on the surface of the support substrate 101 can be the same as the method for forming the oxide layer 103 on the surface of the device substrate 102 described above, that is, forming the oxide layer 103 on the surface of the support substrate 101 by combining a dry oxidation process and a wet oxidation process.

[0047] In this embodiment, the thickness of the oxide layer 103 on the surface of the support substrate 101 is less than or equal to 0.4 μm and greater than 0 μm, for example 0.3 μm, 0.2 μm or 0.1 micrometer, so as to regulate the curvature of the support substrate 101 so that the curvature of the device substrate 102 is within a set range.

[0048] In this embodiment, the curvature of the support substrate 101 may be set in a range of -5 μm to 30 μm, for example, -4 μm, 1 μm, 10 μm or 20 μm.

[0049] It should be noted that the curvature of the support substrate 101 and the curvature of the device substrate 102 can be the same or different. It is only necessary to ensure that the difference between the curvature of the device substrate 102 (i.e., the first set curvature) and the curvature of the support substrate 101 (i.e., the second set curvature) is within a preset range.

[0050] In some embodiments, the curvature of the device substrate 102 and the curvature of the support substrate 101 are adjusted so that the device substrate 102 has a first predetermined curvature and the support substrate 101 has a second predetermined curvature, thereby ensuring that the difference between the curvature of the device substrate 102 and the curvature of the support substrate 101 is within a preset range. When the difference between the curvature of the device substrate 102 and the curvature of the support substrate 101 is large and it is impossible to achieve the difference between the curvature of the device substrate 102 and the curvature of the support substrate 101 within the preset range by adjusting either the curvature of the device substrate 102 or the curvature of the support substrate 101 alone, the curvature of the device substrate 102 and the curvature of the support substrate 101 can be adjusted so that the difference between the curvature of the device substrate 102 and the curvature of the support substrate 101 is within the preset range.

[0051] Specifically, an oxide layer 103 of a preset thickness is formed on the surface of the device substrate 102 and the surface of the support substrate 101, and the curvature of the device substrate 102 is adjusted by the oxide layer 103 of the preset thickness so that the device substrate 102 has a first set curvature. The preset thickness can be less than or equal to 0.4 μm, that is, the thickness of the oxide layer 103 on the surface of the device substrate 102 and / or the thickness of the oxide layer 103 on the surface of the support substrate 101 is less than or equal to 0.4 μm. The total thickness of the oxide layer 103 on the surface of the device substrate 102 and the oxide layer 103 on the surface of the support substrate 101 (i.e., the thickness of the buried oxide layer) can be 0.01 μm to 1 μm.

[0052] In this embodiment, the oxide layer 103 on the surface of the device substrate 102 and the surface of the supporting substrate 101 can be formed by combining a dry oxidation process and a wet oxidation process, so that the oxide layer 103 has good density and uniformity (achieved by the dry oxidation process) and can achieve rapid growth of the oxide layer 103 (achieved by the wet oxidation process).

[0053] In a further embodiment, after the oxide layer 103 is formed on the surface of the device substrate 102 and the surface of the support substrate 101, ion implantation may be performed on the device substrate 102 to form an ion implantation layer 104. The ion implantation layer 104 has a depth of 100 nm to 600 nm and a width of 10 nm to 100 nm, so as to adjust the curvature of the device substrate 102. If the difference between the curvature of the device substrate 102 and the curvature of the support substrate 101 exceeds a preset range, the curvature of the device substrate 102 may be adjusted by adjusting the depth and width of the ion implantation layer 104, so that the difference between the curvature of the device substrate 102 and the curvature of the support substrate 101 is within the preset range.

[0054] In this embodiment, the second set curvature of the support substrate 101 may be -5 μm to 30 μm, for example, 10 μm or 20 μm. Figure 7 and Figure 8 As shown, Figure 7 is a schematic diagram of the surface when the curvature of the supporting substrate 101 is a negative value (less than 0); Figure 7 FIG. 1 is a schematic diagram of a surface when the curvature of the supporting substrate 101 is positive (greater than 0).

[0055] In this embodiment, the first set curvature of the device substrate 102 may be -5 μm to 10 μm, for example, 5 μm. Figure 9 and Figure 10 As shown, Figure 9 is a surface schematic diagram of the device substrate 102 when the first set curvature is a positive value (greater than 0); Figure 10 FIG. 1 is a schematic diagram of a surface of the device substrate 102 when the first set curvature is a negative value (less than 0).

[0056] It should be noted that in Figures 7 to 10 In the description, the case where the oxide layer 103 is formed on the surfaces (i.e., the upper and lower opposite surfaces) and side surfaces of the support substrate 101 and the device substrate 102 is used as an example. In other embodiments, the oxide layer 103 may be formed only on any surface of the support substrate 101 and / or the device substrate 102.

[0057] Then, execute step S2, as Figure 11 As shown, the device substrate 102 and the support substrate 101 are bonded to form a bonded wafer 100. After bonding, a portion of the oxide layer 103 is located between the device substrate 102 and the support substrate 101 to form a buried oxide layer, that is, the portion of the oxide layer 103 serves as the buried oxide layer of the bonded wafer 100, and the device substrate 102 serves as the device layer of the bonded wafer 100.

[0058] in, Figure 11 In the figure, an example is shown in which an oxide layer is formed on one surface of the device substrate 102 or the support substrate 101 , that is, there is only one oxide layer between the device substrate 102 and the support substrate 101 .

[0059] In other embodiments, an oxide layer may be formed on a surface of the device substrate 102 and a surface of the support substrate 101. When the device substrate 102 and the support substrate 101 are bonded, the oxide layer on the surface of the device substrate 102 faces the oxide layer on the surface of the support substrate 101, that is, there may be two oxide layers between the device substrate 102 and the support substrate 101, and the two oxide layers together constitute the buried oxide layer of the bonded wafer 100.

[0060] In this embodiment, the device substrate 102 and the support substrate 101 can be bonded by concave-to-convex bonding, concave-to-concave bonding, or convex-to-convex bonding. That is, when the first set curvature of the device substrate 102 and / or the second set curvature of the support substrate 101 is greater than zero or less than zero, the concave surface of the device substrate 102 can be bonded to the concave surface of the support substrate 101, the concave surface of the device substrate 102 can be bonded to the convex surface of the support substrate 101, or the convex surface of the device substrate 102 can be bonded to the convex surface of the support substrate 101.

[0061] Since the difference between the first set curvature of the device substrate 102 and the second set curvature of the support substrate 101 is within a preset range, the stress at the bonding interface between the support substrate 101 and the device substrate 102 can be regulated during the bonding process between the device substrate 102 and the support substrate 101, so that the stress at the bonding interface is within an appropriate range. This can avoid the problem of insufficient bonding strength between the device substrate 102 and the support substrate 101 due to an excessively large difference in curvature between the device substrate 102 and the support substrate 101, thereby reducing or avoiding the occurrence of bonding defects; at the same time, it can also avoid the problem of low stress at the bonding interface between the device substrate 102 and the support substrate 101 due to an excessively small difference in curvature between the device substrate 102 and the support substrate 101.

[0062] Then, a heat treatment and flattening process is performed on the bonded wafer 100. Specifically, the method for performing a heat treatment and flattening process on the bonded wafer 100 includes: first, performing a reinforcement heat treatment on the bonded wafer 100 to enhance the bonding strength between the support substrate 101 and the device layer; then, Figure 12 As shown, the bonded wafer 100 is subjected to a peeling process, and the ion implantation layer 104 of the device substrate is peeled and split, that is, a portion of the device substrate is left on the supporting substrate.

[0063] Afterwards, a heat treatment flattening process is performed on the bonded wafer 100. The heat treatment flattening process is a high-temperature heat treatment. At high temperatures, the surface silicon atoms will migrate to reach the lowest energy state. Driven by this mechanism, the silicon surface appears to be flatter. In the process of performing the heat treatment flattening process, since the difference between the curvature of the device substrate 102 and the curvature of the support substrate 101 is within a preset range, the problem of small stress at the bonding interface between the support substrate 101 and the device substrate 102 can be avoided, thereby avoiding the problem of insufficient flattening driving force in the heat treatment flattening process, so that the surface roughness that can be achieved under the same heat load is better, thereby improving the roughness of the surface of the bonded wafer 100.

[0064] Table 1 Relationship between the curvature difference between the support substrate and the device substrate and the number of surface particles

[0065]

[0066] In the first embodiment, reference Figure 13 and combined Figures 14 to 16 , Figure 14 is a schematic diagram of particles on the surface of the bonding wafer 100, Figure 15 Schematic diagram of the haze value on the bonded wafer surface. Figure 16 Schematic diagram of the roughness of the bonded wafer surface. Figure 13As shown, the curvature difference between the supporting substrate 101 and the device substrate 102 (i.e., the difference between the first set curvature and the second set curvature) is 21.4 μm. After performing the heat treatment flattening process, the surface roughness of the bonded wafer (i.e., the roughness of the device substrate surface) is 0.666 nm, the number of surface particles is 10038, the haze value (Haze) is 9.48 ppm, and the GOI yield (yield) is 34.5%.

[0067] In Example 2, refer to Figure 13 and combined Figures 17 to 19 , Figure 17 is a schematic diagram of particles on the surface of the bonding wafer 100, Figure 18 Schematic diagram of the haze value on the bonded wafer surface. Figure 19 Figure 1 shows the roughness of the bonded wafer surface. The difference in curvature between the support substrate 101 and the device substrate 102 is 19.7 μm. After thermal planarization, the surface roughness of the bonded wafer is 0.139 nm, with 38 surface particles, a haze value of 4.44 ppm, and a GOI yield of 97.5%.

[0068] In Example 3, refer to Figure 13 and combined Figures 20 to 22 , Figure 20 is a schematic diagram of particles on the surface of the bonding wafer 100, Figure 21 Schematic diagram of the haze value on the bonded wafer surface. Figure 22 Figure 1 shows the roughness of the bonded wafer surface. The difference in curvature between the support substrate 101 and the device substrate 102 is 10.1 μm. After thermal planarization, the surface roughness of the bonded wafer is 0.152 nm, the number of surface particles is 52, the haze value is 4.71 ppm, and the GOI yield is 94.5%.

[0069] In Example 4, reference Figure 13 and combined Figures 23 to 25 , Figure 23 is a schematic diagram of particles on the surface of the bonding wafer 100, Figure 24 Schematic diagram of the haze value on the bonded wafer surface. Figure 25 Figure 1 shows the roughness of the bonded wafer surface. The difference in curvature between the support substrate 101 and the device substrate 102 is 0.05 μm. After thermal planarization, the surface roughness of the bonded wafer is 0.206 nm, with 389 surface particles, a haze value of 5.4 ppm, and a GOI yield of 81.4%.

[0070] In Example 5, reference Figure 9 and combined Figures 26 to 28 , Figure 26 is a schematic diagram of particles on the surface of the bonding wafer 100, Figure 27 Schematic diagram of the haze value on the bonded wafer surface. Figure 28 Figure 1 shows the roughness of the bonded wafer surface. The difference in curvature between the support substrate 101 and the device substrate 102 is -4.01 μm. After thermal planarization, the surface roughness of the bonded wafer is 0.239 nm, the number of surface particles is 541, the haze value is 6.11 ppm, and the GOI yield is 72.4%.

[0071] In combination with Example 1, Example 2, Example 3, Example 4 and Example 5 in Table 1, it can be seen that when the difference in curvature between the supporting substrate 101 and the device substrate 102 is within a preset range of 0μm to 20μm, after performing the heat treatment flattening process, the roughness of the bonded wafer surface can be improved, so that the surface roughness of the bonded wafer (5μm*5μm sampling area) is less than or equal to 0.206nm, the surface light scattering haze value is less than or equal to 5.4ppm, and the number of surface particles of the bonded wafer is less than or equal to 389, thereby reducing the roughness of the bonded wafer surface and reducing the number of particles on the bonded wafer surface.

[0072] In addition, it should be noted that in the above-mentioned Examples 1, 2, 3, 4 and 5, the roughness of the bonded wafer surface is the roughness of the device substrate surface in the bonded wafer, and the number of particles on the bonded wafer surface is the number of particles on the device substrate surface in the bonded wafer.

[0073] In summary, in the method for forming a bonded wafer provided in an embodiment of the present invention, the device substrate has a first set curvature, the supporting substrate has a second set curvature, and the difference between the first set curvature and the second set curvature is within a preset range. By controlling the curvature of the device substrate and / or the curvature of the supporting substrate, the difference between the curvature of the device substrate and the curvature of the supporting substrate is made within a preset range, that is, 0μm to 20μm, for example, the values of Examples 2, 3, and 4 are all acceptable. In this way, in the process of bonding the device substrate and the supporting substrate, the stress at the bonding interface between the supporting substrate and the device substrate can be regulated so that the stress at the bonding interface is within an appropriate range. This can avoid the problem of insufficient bonding strength between the device substrate and the supporting substrate due to excessively large difference in curvature between the device substrate and the supporting substrate, thereby reducing or avoiding bonding defects; at the same time, it can also avoid the problem of low bonding interface stress between the device substrate and the supporting substrate due to excessively small difference in curvature between the device substrate and the supporting substrate, thereby avoiding the problem of insufficient flattening driving force in the subsequent heat treatment flattening process, thereby improving the roughness of the bonded wafer surface.

[0074] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for forming a bonded wafer, characterized in that: include: Providing a device substrate and a support substrate, wherein the device substrate has a first set curvature, and the support substrate has a second set curvature, and a difference between the first set curvature and the second set curvature is within a preset range; The device substrate and the support substrate are bonded to form a bonded wafer.

2. The method for forming a bonded wafer according to claim 1, wherein: The preset range of the difference between the first set curvature and the second set curvature is 0 μm to 20 μm.

3. The method for forming a bonded wafer according to claim 1, wherein: The curvature of the support substrate is -5 μm to 30 μm.

4. The method for forming a bonded wafer according to claim 1, wherein: The curvature of the device substrate is -5 μm to 10 μm.

5. The method for forming a bonded wafer according to claim 1, wherein: Before bonding the device substrate and the support substrate, the method further includes: An oxide layer of a preset thickness is formed on the surface of the device substrate and / or the surface of the support substrate. After the device substrate and the support substrate are bonded, part of the oxide layer is located between the device substrate and the support substrate to form a buried oxide layer.

6. The method for forming a bonded wafer according to claim 5, wherein: The thickness of the oxide layer on the surface of the device substrate and / or the thickness of the oxide layer on the surface of the support substrate is less than or equal to 0.4 μm.

7. The method for forming a bonded wafer according to claim 5, wherein: The thickness of the buried oxide layer is 0.01 μm to 1 μm.

8. The method for forming a bonded wafer according to claim 1, wherein: Before bonding the device substrate and the support substrate, the method further includes: Ion implantation is performed on the device substrate to form an ion implantation layer, wherein the depth of the ion implantation layer is 100 nm to 600 nm, and the width of the ion implantation layer is 10 nm to 100 nm.

9. The method for forming a bonded wafer according to claim 1, wherein: After bonding the device substrate and the support substrate, the method further includes: A thermal treatment planarization process is performed on the bonded wafer.

10. The method for forming a bonded wafer according to claim 9, wherein: After bonding the device substrate and the support substrate, and before performing a heat treatment and planarization process on the bonded wafer, the method for forming the bonded wafer further includes: The bonded wafer is subjected to a reinforcement heat treatment.

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