Wafer room temperature bonding method and application thereof

Abstract

The invention discloses a wafer room temperature bonding method and application thereof, and belongs to the technical field of semiconductor advanced packaging and three-dimensional integration. The method comprises the following steps: providing a first wafer, and sequentially preparing a metal plane layer and an oxide layer on the surface of one side of the first wafer to form a metal / oxide composite layer; selectively etching the metal / oxide composite layer to remove the oxide layer and form a metal nanowire array layer on the metal plane layer; providing a second wafer, and preparing a metal material layer on the surface of one side of the second wafer; and aligning the surface, with the metal nanowire array layer, of the first wafer with the surface, with the metal material layer, of the second wafer, and then bonding. According to the invention, the metal nanowire array is introduced into the bonding interface, so that the nanowires are subjected to plastic deformation and local surface diffusion under the action of external pressure, that is, compact and reliable metal-metal bonding can be realized in a room temperature environment, and the requirements of a low-temperature process window and high strength are both considered.

Description

Technical Field

[0001] This application relates to a wafer room temperature bonding method and its application, belonging to the field of advanced semiconductor packaging and three-dimensional integration technology. Background Technology

[0002] Wafer bonding technology is a core process for achieving three-dimensional integration and heterogeneous material integration, playing an irreplaceable role in improving chip performance and reducing device size. Traditional metal diffusion bonding typically requires high temperatures (e.g., gold-gold bonding usually requires ≥300℃), which easily induces thermal mismatch stress in large-size wafers, leading to warping, cracking, and thermal damage to internal devices. Existing room-temperature bonding methods mostly rely on surface activation treatment to increase surface energy, which is extremely sensitive to the roughness / cleanliness of the bonding surface. Surface-activated room-temperature bonding requires atomic-level cleanliness, low roughness, and a high-vacuum environment, which leads to problems such as limited bonding strength and stability in large-size wafers, and high bonding and equipment costs, making it difficult to meet the industrial application requirements of large-size wafers. Metal bonding is widely used in wafer bonding due to its excellent electrical and thermal conductivity. However, atomic migration and diffusion in metal planar films are extremely limited at room temperature, making it difficult to form high-strength atomic-level contacts. Therefore, high temperatures are usually required to promote atomic diffusion, but the easy oxidation of metal surfaces can also lead to bonding defects. Thus, developing a method to achieve high-strength bonding of large-size wafers at room temperature to realize large-size, high-strength, and mass-producible metal-metal bonding within the room temperature or near-room temperature window, while also exhibiting higher tolerance to surface conditions and vacuum conditions and ensuring long-term environmental reliability, has become a key technical challenge to be solved in the semiconductor manufacturing field. Summary of the Invention

[0003] To address at least one of the problems in existing wafer room temperature bonding methods, namely, damage to the wafer caused by high-temperature bonding and insufficient bonding strength and high cost at room temperature, this application proposes a wafer room temperature bonding technology solution. By introducing a "metal nanowire array" at the bonding interface, high-strength bonding under low temperature and low pressure is achieved, which significantly improves the actual contact area and surface activity of the interface microstructure. Under external pressure, the nanowires undergo plastic deformation and local surface diffusion, thus achieving dense and reliable metal-metal bonding at room temperature, thereby balancing the low-temperature process window and high strength requirements.

[0004] The technical solution adopted in this application is as follows: According to a first aspect of this application, a wafer room temperature bonding method is provided, comprising: A first wafer is provided, and a metal planar layer and an oxide layer are sequentially formed on one side surface of the first wafer to form a metal / oxide composite layer; The metal / oxide composite layer is selectively etched to remove the oxide layer and form a metal nanowire array layer from the metal planar layer; A second wafer is provided, and a metal material layer is prepared on one side surface of the second wafer; The side of the first wafer with the metal nanowire array layer is aligned with the side of the second wafer with the metal material layer and then bonded together.

[0005] Optionally, the metal material layer is the same as the metal planar layer; Alternatively, the metal material layer may be the same as the metal nanowire array layer.

[0006] Optionally, the thickness of the metal / oxide composite layer is 0.2~5 μm; Optionally, the in-plane thickness uniformity of the metal / oxide composite layer is -5% to 5%; Optionally, before sequentially forming the metal planar layer and the oxide layer on one side surface of the first wafer, the method further includes: An adhesion / diffusion barrier layer is formed on the surface of the first wafer facing the metal planar layer.

[0007] Optionally, after forming the metal / oxide composite layer, the method further includes: The metal / oxide composite layer is patterned to remove portions of the non-bonded areas on the metal / oxide composite layer.

[0008] Optionally, before selectively etching the metal / oxide composite layer, the method further includes: The metal / oxide composite layer is annealed.

[0009] Optionally, the diameter of the metal nanowire array layer is 50~500 nm; The areal density of the metal nanowire array layer is 10. 8 ~10 11 root / cm 2 .

[0010] Optionally, the bonding conditions include: Bonding is performed in a vacuum environment; And / or, the bonding pressure is 2~8 MPa; And / or, the bonding time is 15~180 min.

[0011] Optionally, after forming the metal planar layer into a metal nanowire array layer, the method further includes: The metal nanowire array layer is then subjected to tempering treatment.

[0012] According to a second aspect of this application, an application of the above-described wafer room temperature bonding method in advanced semiconductor packaging and three-dimensional integration is also provided.

[0013] The beneficial effects of this application include: (1) Achieve room temperature bonding: Utilizing the high surface activity of metal nanowires, bonding can be completed at 20-30℃, completely avoiding the problems of large-size wafer warpage and device damage caused by high temperature; (2) High bonding strength: The metal nanowires are in close contact under pressure and form high-strength bonds through surface diffusion (bonding strength is expected to be ≥150MPa), which is superior to traditional room temperature bonding methods; (3) Excellent stability: Au and Ag metals that are not easily oxidized are selected. Combined with the vacuum bonding environment, metal oxidation is effectively suppressed. It is expected that the strength retention rate of the bonding interface will be ≥90% after aging at 35℃ / 50%RH for 100 hours. (4) Applicable to large-size wafers: The magnetron sputtering process ensures the uniformity of the composite layer, and the patterning and precise alignment technology can meet the large-area bonding requirements of 8-inch and larger wafers, enabling industrial mass production. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the wafer room temperature bonding method of this application; Figure 2 This is a schematic diagram of the steps and structure in a wafer room temperature bonding method according to this application; Figure 3 This is a schematic diagram of the steps and structure in another wafer room temperature bonding method of this application.

[0015] Attached Figure Labels 1. Wafer; 2. Metal planar layer; 3. Oxide layer; 4. Photoresist template; 5. Oxide nanowire array layer; 6. Metal nanowire array layer; 7. Second bonding wafer; 8. Bonding layer. Detailed Implementation

[0016] The present application is described in detail below with reference to the embodiments, but the present application is not limited to these embodiments.

[0017] Unless otherwise specified, all raw materials used in the embodiments of this application were purchased through commercial channels.

[0018] Unless otherwise specified, all test methods are standard and all instrument settings are those recommended by the manufacturer.

[0019] Explanation of key terms in this application: Room-temperature bonding: A wafer bonding process performed at approximately 20-30°C, avoiding thermal stress and device damage caused by high temperatures.

[0020] Magnetron sputtering (PVD): A physical vapor deposition method that uses plasma to bombard a target, causing atoms to be deposited onto the substrate surface to form a thin film.

[0021] Nanoimprinting (NIL): A forming technology that uses a hard mold to "press" nanoscale patterns onto a polymer or inorganic film and then transfers them to a functional layer. It is suitable for large-area nanostructures.

[0022] Reactive ion etching (RIE): Anisotropic etching is achieved through plasma chemical reaction and physical bombardment. Commonly used gases include CHF3 / Ar and BCl3 / Cl2.

[0023] Ion beam etching (IBE): This etching method mainly relies on physical sputtering to remove materials (without obvious chemical selectivity), and is suitable for metals that are difficult to wet etch (such as Pt, Au, Ag).

[0024] Selective etching: The etching agent has a "different" rate for different materials, which can remove one layer without damaging another layer (such as BOE for SiO2, hot phosphoric acid for Al2O3).

[0025] Large-size wafers: This application emphasizes wafer sizes of ≥8 inches.

[0026] Metal nanowire array layer: a metal pillar / wire structure with a diameter of about 50~500 nm (preferably 80~200 nm) and a length of 0.7~1.6 μm.

[0027] BOE (Buffered Oxide Etch): Hydrofluoric acid buffer solution, commonly used for selective etching of SiO2 (inert to Ag / Au).

[0028] CHF3 / Ar: Commonly used RIE atmosphere, suitable for etching oxide-containing materials such as SiO2 / HfO2.

[0029] BCl3 / Cl2: RIE atmosphere, suitable for etching oxides such as Al2O3 or certain metals.

[0030] Plastic deformation / plastic interlocking: Under external pressure, the nanowires undergo permanent deformation and interlock with the nanowires on the opposite side, increasing the actual contact area.

[0031] Surface diffusion: the process of atoms migrating on a surface; the diffusion barrier decreases at the nanoscale (small radius of curvature).

[0032] Cold welding: an atomic-level bonding phenomenon that occurs when clean metal surfaces come into close contact without significant temperature rise.

[0033] Metal diffusion / hot pressing bonding: A traditional bonding method that forms a metallurgical bond through atomic interdiffusion under external pressure at ≥300 ℃; it has high strength but high thermal stress.

[0034] Surface activated bonding (SAB): Room temperature bonding is achieved by activating the metal surface with ions / atomic beams in UHV and bonding it instantly; it is extremely sensitive to surface flatness / cleanliness and has a narrow window.

[0035] The typical existing technologies for wafer bonding are metal diffusion bonding and surface activation bonding. Metal diffusion bonding typically involves first depositing a thin metal film (such as Au) on the surface of the wafer to be bonded, then precisely aligning it before applying pressure and setting it at a relatively high temperature (≥300°C). Hot pressing or diffusion treatment at ℃ causes interfacial metal atoms to diffuse and form bonds. This method is mature and can achieve high strength and low interfacial resistance, but it requires high process temperature and long holding time. Under large-size wafer conditions, it is prone to thermal mismatch stress, resulting in warping, cracking, and thermal impact on the completed device. Surface activation bonding method uses ion / atom beams to activate and decontaminate the metal surface in high / ultra-high vacuum to obtain an atomically clean and chemically active flat interface, followed by immediate bonding. This method has low temperature and can theoretically achieve room temperature bonding, but it is extremely sensitive to surface roughness and cleanliness, has a narrow process window, and often relies on high-level vacuum and special activation equipment, which is complex and costly. In the mass production of ≥8-inch large-size wafers, stability and yield are limited by surface condition, re-adsorption, and alignment consistency, making it difficult to engineer.

[0036] To address the aforementioned problems in existing technologies, and in order to achieve high-strength and mass-producible metal-metal bonding at large-size wafer scale within a room temperature or near-room temperature window, while also exhibiting higher tolerance to surface conditions and vacuum conditions and ensuring long-term environmental reliability, this application provides a large-size wafer room temperature bonding method. This method involves preparing a metal / oxide composite layer on the surface of the wafer to be bonded, and then constructing a high-area-density metal nanowire array through patterning and selective etching. The nanowires are then aligned and bonded under medium vacuum and moderate external pressure, causing plastic deformation under pressure accompanied by surface diffusion / cold welding. This allows for the formation of a dense, low-void metal-metal interface at 20-30 °C. Unlike room-temperature bonding of planar films that relies on UHV activation, this application utilizes the high specific surface area and nano-curvature of nanowire arrays to significantly amplify the actual contact area, bridge gaps caused by microscopic particles / roughness, and reduce dependence on ultra-high vacuum and atomic-level flatness. Compared with high-temperature diffusion bonding, this method avoids thermal mismatch warpage and device thermal damage, making it more suitable for the consistency and yield requirements of large-size wafers. Furthermore, this route is based on mature mass production processes such as sputtering, photolithography / nanoimprinting, RIE / IBE, and BOE / thermal phosphoric acid, ensuring controllable uniformity in nanowire fabrication and enabling stable implementation and large-scale production on 8-12 inch production lines.

[0037] According to one embodiment of this application, a wafer room temperature bonding method includes: A first wafer is provided, and a metal planar layer and an oxide layer are sequentially formed on one side surface of the first wafer to form a metal / oxide composite layer; The metal / oxide composite layer is selectively etched to remove the oxide layer and form a metal nanowire array layer from the metal planar layer; A second wafer is provided, and a metal material layer is prepared on one side surface of the second wafer; The side of the first wafer with the metal nanowire array layer is aligned with the side of the second wafer with the metal material layer and then bonded together.

[0038] The processing and bonding equipment for metal nanowire array layers are mature mass-production equipment, which is easy to implement in the whole line. Moreover, the room temperature bonding process does not rely on UHV activation and atomic-level mirrors. The nanowire array can ignore the influence of particles / micro-roughness on the wafer surface under pressure, and it is easier to establish real contact than planar films. Therefore, it has a wider tolerance for roughness, cleanliness and vacuum fluctuations, and is suitable for large-size mass production.

[0039] In one embodiment, the metal material layer is the same as the metal planar layer; Alternatively, the metal material layer may be the same as the metal nanowire array layer. Surface-activated room-temperature bonding requires atomically clean, low-roughness, and high-vacuum environments, which leads to problems such as low bonding strength, high bonding costs, and high equipment costs for large-size wafers. This application uses a metal nanowire array layer for bonding. Under external pressure, the nanowires undergo permanent deformation and interlock with opposite nanowires, increasing the actual contact area. This reduces the dependence on atomically flatness and ultra-high vacuum, improving the yield and consistency of large-size wafers.

[0040] In one embodiment, the large-size wafer has a size greater than or equal to 8 inches.

[0041] In one embodiment, providing the first wafer includes: ultrasonically cleaning and drying the surfaces of the first wafer to be bonded to provide a clean first wafer. Exemplarily, the ultrasonic cleaning process includes sequentially cleaning with deionized water, anhydrous ethanol, and acetone under ultrasonic conditions for 5-20 minutes each; exemplarily, the drying method is nitrogen blowing or vacuum drying.

[0042] In one embodiment, before sequentially preparing the metal planar layer and the oxide layer on one side surface of the first wafer, the method further includes: activating the surface of the first wafer with O2 or Ar plasma for 30-300 s to remove organic residues and improve wettability.

[0043] In one embodiment, the thickness of the metal / oxide composite layer is 0.2~5 μm.

[0044] In one embodiment, the metal / oxide composite layer can be prepared by magnetron sputtering, which uses plasma to bombard the target material to deposit atoms onto the substrate surface to form a thin film.

[0045] In one embodiment, the in-plane thickness uniformity of the metal / oxide composite layer is -5% to 5%.

[0046] In one embodiment, the metal layer is made of at least one of Ag, Au, Pt, and Pd; noble metals are resistant to oxidation, have high surface energy and good plasticity, and have higher room temperature surface diffusion / cold welding activity at the nanoscale.

[0047] In one embodiment, the oxide layer is made of at least one of SiO2, Al2O3, HfO2, and MgO; the oxide layer is suitable as a subsequent sacrificial template to form a nanostructure.

[0048] In one embodiment, before sequentially forming the metal planar layer and the oxide layer on one side surface of the first wafer, the method further includes: An adhesion / diffusion barrier layer is formed on the surface of the first wafer facing the metal planar layer. The adhesion / diffusion barrier layer is designed to improve adhesion and inhibit metal diffusion to the substrate, and the material of the adhesion / diffusion barrier layer is selected from at least one of Ti, Cr, TiW, or TaN.

[0049] In one embodiment, after forming the metal / oxide composite layer, the method further includes: The metal / oxide composite layer is patterned to remove non-bonded areas. Based on the bonding area design requirements, photolithography is used to pattern the composite layer, forming a pre-defined metal / oxide composite structure. Patterning precisely defines the bonding area, reduces material waste in non-bonded areas, and improves bonding alignment accuracy (alignment error ≤ 1 μm). Patterning methods include nanoimprinting, lift-off processes, and reactive ion etching. Nanoimprinting uses a hard mold to "press" nanoscale patterns onto a polymer or inorganic film, which are then transferred to a functional layer; this technique is suitable for large-area nanostructures. Reactive ion etching achieves anisotropic etching through plasma chemical reaction and physical bombardment, commonly using gases such as CHF3 / Ar and BCl3 / Cl2.

[0050] In one embodiment, prior to the selective etching of the metal / oxide composite layer, the method further includes: The metal / oxide composite layer is annealed. Annealing aims to reduce sputtering stress, improve metal crystallinity, and enhance the metal / oxide interfacial adhesion, laying the foundation for subsequent etching to form a stable nanowire structure.

[0051] In one embodiment, the annealing conditions include annealing at 100–350 °C for 20–150 min under an inert atmosphere or vacuum. Preferably, the annealing process is a slow heating annealing.

[0052] In one embodiment, the diameter of the metal nanowire array layer is 50-500 nm; the length of the metal nanowire array layer is equal to the thickness of the metal / oxide composite layer.

[0053] The areal density of the metal nanowire array layer is 10. 8 ~10 11 root / cm 2 The small diameter and high surface density of metal nanowires give them a high specific surface area, which can significantly enhance surface activity, lower the atomic diffusion barrier, and provide impetus for room temperature bonding. This allows them to yield / flatten and interlock under lower pressure, rapidly eliminating microscopic voids and improving interface density and bonding strength.

[0054] In one embodiment, the diameter of the metal nanowire array layer is 80-200 nm.

[0055] In one embodiment, the length of the metal nanowire array layer is 0.7-1.6 μm.

[0056] In one embodiment, the selective etching method is not strictly limited, and is intended to remove oxides from the composite layer while retaining the metal portion to form a metal nanowire array layer.

[0057] In one embodiment, the selective etching method is either wet etching or dry etching. For example, wet etching uses an etchant with a "different" rate for different materials, removing one layer while essentially not damaging another (e.g., BOE for SiO2, hot phosphoric acid for Al2O3). For instance, BOE / HF solution is used to etch SiO2, hot phosphoric acid is used to etch Al2O3, and a mild acidic solution is used to etch MgO. Dry etching is an etching method that mainly relies on physical sputtering to remove materials (without obvious chemical selectivity). For example, fluorine-based gases such as CF4 are used to etch SiO2, and CHF3 / Ar or BCl3 / Cl2 reactive ion etching is used to etch HfO2. It is suitable for metals that are difficult to wet etch (such as Pt, Au, Ag).

[0058] In one embodiment, the specific surface area of ​​the metal nanowire array layer is 10 to 100 times that of the metal layer. The high specific surface area of ​​the metal nanowires can significantly enhance surface activity, lower the atomic diffusion barrier, and provide impetus for room-temperature bonding.

[0059] In one embodiment, the bonding conditions include: Bonding is performed in a vacuum environment; And / or, the bonding pressure is 2~8 MPa; And / or, the bonding temperature is 20~500°C; the preferred bonding temperature is 20~30°C. Traditional metal diffusion bonding requires high temperature (such as gold-gold bonding, which is usually ≥300°C). High temperature can easily cause the wafer to warp, crack, or even damage internal devices due to thermal stress. Wafer bonding processes completed at room temperature (20~30°C) avoid thermal stress and device damage caused by high temperature.

[0060] And / or, the bonding time is 15~180 min. The vacuum environment can avoid oxidation and bubble generation of nanowires, and the pressure causes plastic deformation of nanowires, achieving close contact and forming atomic-level bonds through surface diffusion.

[0061] In one embodiment, the vacuum level of the vacuum environment is ≥5×10⁻⁶. -3 Pa.

[0062] Compared to existing technologies, metal diffusion / hot pressing bonding is prone to causing thermal mismatch stress on wafers and thermal damage to devices at ≥300 ℃. While surface activation bonding can be performed at room temperature, it is highly dependent on wafer surface treatment, extremely sensitive to atomic-level flatness and cleanliness, has a narrow process window, low bonding strength, and is limited in yield and cost. The technical solution of this application creatively constructs a high areal density metal nanowire array using "metal / oxide composite layer → annealing (optional) → selective etching", and performs the process in a medium vacuum (≥5×10⁻⁶). -3 By aligning nanowires face-to-face under moderate external pressure (2-8 MPa) and moderate external pressure (2-8 MPa), plastic interlocking is achieved, significantly increasing the actual contact area. This, combined with the surface diffusion / cold welding effect induced by nano-curvature, allows for the attainment of a dense interface and high bonding strength at 20-30 °C. Simultaneously, this approach reduces the dependence on atomic-level flatness and ultra-high vacuum, improves the yield and consistency of large-size wafers, and facilitates stable mass production on 8-12 inch lines using mature processes such as sputtering, photolithography, and etching.

[0063] In one embodiment, after forming the metal planar layer into a metal nanowire array layer, the method further includes: The metal nanowire array layer is tempered to further densify the interface.

[0064] In one embodiment, the tempering conditions include: tempering temperature ≤150 ℃ and tempering time of 10~60 min.

[0065] In the technical solution of this application, the composite layer structure and metal / oxide type of the metal / oxide composite layer can be adjusted within the above range to meet the selective etching and reliability requirements of different material systems (Si, glass, compound semiconductor, piezoelectric / ferroelectric materials, etc.) and production lines.

[0066] According to another embodiment of this application, the aforementioned wafer room temperature bonding method is applied to advanced semiconductor packaging and three-dimensional integration.

[0067] The core principles of this application's technical solution in solving the problems of existing technologies mainly include: 1. High specific surface area and amplified actual contact area: A large number of micro-protrusions are formed at the tip of the nanowire. Under external pressure, the contact evolves rapidly from "point-line-surface" multi-scale, and the initial porosity (porosity refers to the percentage of area or volume occupied by unbonded voids, bubbles or defects in the bonding interface region after bonding is completed) is significantly reduced.

[0068] 2. Higher surface activity than metal films: The small radius of curvature at the tip of the nanowire and the high surface chemical potential can reduce the migration barrier of metal atoms, promoting surface diffusion and cold bonding at room temperature.

[0069] 3. Metal plasticity: Metal nanowires with diameters of 50-500 nm yield / flatten and interlock with each other under 2-8 MPa, rapidly eliminating microscopic voids and improving interface density and bonding strength.

[0070] Based on the aforementioned principles, this application achieves high-strength metal-metal bonding of large-size wafers at room temperature without relying on high-temperature diffusion or UHV activation planes, and has a higher tolerance for fluctuations in surface roughness / cleanliness and vacuum level.

[0071] Example 18: Room Temperature Bonding of 18-inch Silicon Wafers The steps of the wafer room temperature bonding method in this embodiment are as follows: Figure 2 As shown, it includes: (a) Formation of a metal / oxide composite layer Step 1, Substrate preparation: Two 8-inch monocrystalline silicon wafers (725 μm thick, Ra≤0.5 nm) were sequentially subjected to ultrasonic treatment with deionized water → ethanol → acetone for 10 min each; rinsed with deionized water for 2 min; dried with N2; and removed organic residues with O2 plasma at 100 W × 60 s.

[0072] Step 2, Metal Planar Layer Deposition: Sputter Au 1.0 μm in 0.3 Pa Ar atmosphere; rotate substrate at 15 rpm; thickness uniformity ±4%. Optionally, deposit Cr or Ti 10 nm between the substrate and Au first to enhance adhesion.

[0073] One of the 8-inch monocrystalline silicon wafers with the metal planar layer deposited in step 2 is processed in steps 3-6: Step 3, Oxide layer deposition: Sputter SiO2 0.35 μm at no temperature or ≤80 ℃ to form a “Au (bottom) / SiO2 (top)” bilayer composite structure, that is, to form a metal / oxide composite layer.

[0074] (b) Formation of a metal nanowire array layer Step 4, low-temperature annealing: Anneal at 2200 ℃ for 30 min to reduce the internal stress of the film.

[0075] Step 5, Oxide layer patterning (template formation): A photoresist pattern with a period of 500 nm and a pore size of 100 nm is formed on the SiO2 surface using a lift-off process. The pattern is then transferred to SiO2 using a CHF3Ar ion etching process (100 / 50 sccm, 100 W) to obtain the SiO2 oxide layer nanopore array layer; the photoresist is then removed and cleaned.

[0076] Step 6, Metal nanowire etching and oxide layer removal: Using the above-mentioned SiO2 nanopores as a hard mask, Ar ion beam etching (IBE, 600 V, 10 mA / cm) is performed. 2 Au is anisotropically etched, and the Au below the hole is "pillared"; then the SiO2 mask is selectively removed in BOE (6:1) to expose the Au nanowire array (diameter 100 nm, length ≈1.0 μm), thus forming a metal nanowire array layer.

[0077] (c) Room temperature bonding Step 7, Room Temperature Bonding: Align the bonding surfaces of the two wafers (one single-crystal silicon with a metal nanowire array layer and the other single-crystal silicon with a metal layer) (error ≤ 3 μm) and place them in a vacuum chamber (vacuum degree 8 × 10⁻⁶). - 3 Pa); apply 4 MPa pressure and hold at room temperature for 60 min to form a bonding layer, then slowly release the pressure and remove the wafer to complete the bonding.

[0078] Example 2: 12-inch silicon wafer room temperature bonding The steps of the wafer room temperature bonding method in this embodiment are the same as those in Embodiment 1, the only difference being that the size of the two silicon wafers is 12 inches.

[0079] Example 38: Room Temperature Bonding of Silicon Wafers In this embodiment, the steps of the wafer room temperature bonding method are the same as in Embodiment 1, except that: two 8-inch single-crystal silicon wafers are processed according to steps 3-6, and the metal surface of the other wafer to be bonded is also processed according to the metal nanowire process, i.e. Figure 3 As shown, the bonding surfaces of the two single-crystal silicon wafers are both nanowire arrays.

[0080] Example 48: Room temperature bonding of 8-inch silicon wafers and LiNbO3 wafers The steps of the wafer room temperature bonding method in this embodiment are similar to those in Embodiment 1, except that: (a) Formation of a metal / oxide composite layer Step 1, Substrate preparation: One 8-inch LiNbO3 wafer and one 8-inch Si wafer (725 μm thick, Ra≤0.5 nm) were sequentially subjected to ultrasonic treatment with deionized water → ethanol → acetone for 10 min each; rinsed with deionized water for 2 min; dried with N2; and removed organic residues by O2 plasma at 100 W × 60 s.

[0081] Step 2, Metal Planar Layer Deposition: Sputter 0.9 μm Pt in an Ar atmosphere of 0.4 Pa; rotate the substrate at 15 rpm; thickness uniformity ±4%. Optionally, deposit 10 nm TaN between the substrate and Pt to improve adhesion / block diffusion.

[0082] Step 3, Oxide layer deposition: Sputter HfO2 0.3 μm without heating or at ≤80 ℃ to form a “Pt (bottom) / HfO2 (top)” bilayer composite structure, that is, to form a metal / oxide composite layer.

[0083] (b) Formation of a metal nanowire array layer Step 4, Low-temperature annealing: Slowly heat to 2200 ℃ and anneal for 30 min to reduce the internal stress of the film.

[0084] Step 5, Oxide layer patterning (template formation): A photoresist pattern with a 150 nm aperture and a 500 nm period is formed on the HfO2 surface using nanoimprinting; the pattern is transferred to the HfO2 using CHF3 / Ar plasma etching process (100 / 50 sccm, 120 W) to form an HfO2 hard mask hole array, and the photoresist is removed and cleaned to obtain the HfO2 oxide layer nanopore array layer.

[0085] Step 6, Metal nanowire etching and oxide layer removal: Using the HfO2 pores as a mask, Ar ion beam etching (IBE, 700 V, 10 mA / cm) was performed. 2 Anisotropic etching is performed on Pt, and the Pt below the hole is "pillared". Then, CHF3 / Ar is used to lightly etch away the HfO2 mask, exposing the Pt nanowire array (diameter 150 nm, length ≈0.9 μm), thus forming a metal nanowire array layer.

[0086] (c) Room temperature bonding Step 7, Room Temperature Bonding: Align the bonding faces of the two wafers (error ≤ 3 μm) and place them in a vacuum chamber (vacuum degree 8 × 10⁻⁶). -3 Pa); apply 4 MPa pressure and hold at room temperature for 60 min to form a bonding layer, then slowly release the pressure and remove the wafer to complete the bonding.

[0087] Comparative example: Au film hot-press diffusion bonding on an 18-inch silicon wafer Based on the substrate and cleaning process of Example 1, instead of fabricating nanowires, a 1.0 μm planar Au film (optionally with a 10 nm TiN metal diffusion barrier layer underneath) was sputtered onto two silicon wafers; after alignment, a bonding machine was used at 5 × 10⁻⁶ Å. -3 Hot-press diffusion bonding of 8-inch Si–Si Au–Au was achieved by applying 6 MPa and 300 °C for 60 min. While high-temperature diffusion can achieve bond strength, it introduces significant thermal stress and risks, which are detrimental to large-size yield and compatibility with downstream processes. Comparative example: Au room temperature SAB bonding on a 26-inch silicon wafer Based on the substrate and cleaning process of Example 1, a 300 nm planar Au film was sputtered onto a 6-inch single-crystal silicon wafer; under ultra-high vacuum (~1×10⁻⁶) -6 After bombarding / activating the two metal surfaces with Ar ions (~0.8-1.2 keV, 30-60 s) in the cavity, they are immediately bonded; a holding pressure of 0.5-1 MPa is applied for 30-60 min to complete the 6-inch Si-Si Au-Au room temperature SAB bonding. This process has extremely high requirements for surface flatness and cleanliness, and is sensitive to the environment and equipment. When scaled up to ≥8-inch and larger wafers, the challenges of alignment and uniformity become more pronounced, resulting in high yield and cost pressures.

[0088] The above description is merely a few embodiments of this application and is not intended to limit this application in any way. Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any changes or modifications made by those skilled in the art without departing from the scope of the technical solution of this application using the disclosed technical content are equivalent to equivalent implementation cases and fall within the scope of the technical solution.

Claims

1. A wafer room temperature bonding method, characterized in that, include: A first wafer is provided, and a metal planar layer and an oxide layer are sequentially formed on one side surface of the first wafer to form a metal / oxide composite layer; The metal / oxide composite layer is selectively etched to remove the oxide layer and form a metal nanowire array layer from the metal planar layer; A second wafer is provided, and a metal material layer is prepared on one side surface of the second wafer; The side of the first wafer with the metal nanowire array layer is aligned with the side of the second wafer with the metal material layer and then bonded together.

2. The wafer room temperature bonding method according to claim 1, characterized in that, The metal material layer is the same as the metal planar layer; Alternatively, the metal material layer may be the same as the metal nanowire array layer.

3. The wafer room temperature bonding method according to claim 1, characterized in that, The thickness of the metal / oxide composite layer is 0.2~5 μm; The in-plane thickness uniformity of the metal / oxide composite layer is -5% to 5%.

4. The wafer room temperature bonding method according to claim 1, characterized in that, Before sequentially fabricating the metal planar layer and the oxide layer on one side surface of the first wafer, the process further includes: An adhesion / diffusion barrier layer is formed on the surface of the first wafer facing the metal planar layer.

5. The wafer room temperature bonding method according to claim 1, characterized in that, After forming the metal / oxide composite layer, the method further includes: The metal / oxide composite layer is patterned to remove portions of the non-bonded areas on the metal / oxide composite layer.

6. The wafer room temperature bonding method according to claim 1, characterized in that, Before selectively etching the metal / oxide composite layer, the method further includes: The metal / oxide composite layer is annealed.

7. The wafer room temperature bonding method according to claim 1, characterized in that, The diameter of the metal nanowire array layer is 50~500 nm; The areal density of the metal nanowire array layer is 10. 8 ~10 11 root / cm 2 .

8. The wafer room temperature bonding method according to claim 1, characterized in that, The conditions for bonding include: Bonding is performed in a vacuum environment; And / or, the bonding pressure is 2~8 MPa; And / or, the bonding time is 15~180 min.

9. The wafer room temperature bonding method according to claim 1, characterized in that, After forming the metal planar layer into a metal nanowire array layer, the method further includes: The metal nanowire array layer is then subjected to tempering treatment.

10. The application of the large wafer room temperature bonding method according to any one of claims 1 to 9 in advanced semiconductor packaging and three-dimensional integration.

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