Anti-Kirkendall effect metal layer structure for Micro LED bonding

Abstract

The utility model discloses an anti-Kirkendall effect metal layer structure for Micro LED bonding, which comprises a CMOS side first metal layer and an epitaxial side second metal layer, and the CMOS side first metal layer and the epitaxial side second metal layer are connected through eutectic bonding to form an integral structure. The CMOS side first metal layer comprises a silicon-based CMOS, a substrate protection layer, a first adhesion protection lamination layer, a first phase change alloy layer and a surface enhancement layer; the epitaxial side second metal layer comprises an epitaxial wafer, a conductive layer, a barrier protection layer, a second adhesion protection lamination layer and a second phase change alloy layer; through the pre-phase-change treatment, the voidage of the bonding interface is greatly higher than that of the traditional single-layer Au-Sn bonding, the thermal resistance is also greatly reduced, and the heat dissipation of the device is effectively improved; the multi-layer structure design is combined with the laser cleaning effect, so that the bonding yield of Micro LEDs below 20 microns is greatly improved, and the mass production requirement is met; and the thickness of each layer and the deposition process can be flexibly adjusted to adapt to Micro LED chips with different sizes and bonding equipment, so that the method has wide engineering application value.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor device structure, specifically to a Kirkendall effect-resistant metal layer structure for Micro LED bonding. Background Technology

[0002] In silicon-based Micro LED microdisplay technology, eutectic bonding (wafer to wafer) is a key technology for integrating CMOS driving circuits with GaN epitaxial wafers. Currently, the mainstream solder is gold-tin (Au-Sn) alloy. However, during the bonding process, the Kirkendall effect caused by the difference in diffusion rates between gold and tin atoms can form void defects at the metal interface. These voids not only increase thermal resistance (leading to significant device temperature rise) and contact resistance (causing uneven current distribution), but also affect the light emission uniformity of MicroLEDs. Especially when the chip size is reduced to below 20μm, a single void can affect the light emission characteristics of a large area of ​​LEDs, seriously reducing product yield.

[0003] The Kirkendall effect originally referred to the formation of defects during the diffusion process of two metals with different diffusion rates. It has now become a method for preparing hollow nanoparticles. If the total number of lattice points remains constant, then every plane in the diffusion region must move. This phenomenon is called the Kirkendall effect.

[0004] In existing technologies, optimizing welding process parameters (such as temperature, pressure, and time) or surface cleaning can only partially improve the void problem. However, for the physical mechanism problem of the Kirkendall effect, there is a lack of effective structural-level solutions. Traditional single-layer Au-Sn alloy bonding layers have uneven atomic migration at high temperatures, making it difficult to avoid void formation. It is urgent to fundamentally suppress the Kirkendall effect through metal layer structure design. Utility Model Content

[0005] The purpose of this invention is to provide a Kirkendall effect-resistant metal layer structure for Micro LED bonding. Through pre-phase change induction and interface optimization design, Au-Sn atom diffusion is promoted in advance to form a stable alloy phase, suppressing void generation during the bonding process and improving the reliability of the Micro LED bonding interface.

[0006] To achieve the above objectives, the technical solution adopted by this utility model is: a Kirkendall effect-resistant metal layer structure for Micro LED bonding, comprising a first metal layer on the CMOS side and a second metal layer on the epitaxial side, wherein the two are connected by eutectic bonding to form an integral structure;

[0007] The first metal layer on the CMOS side includes a silicon-based CMOS, a substrate protective layer, a first adhesion protective stack, a first phase change alloy layer, and a surface enhancement layer;

[0008] The substrate protective layer is deposited on the upper surface of the silicon-based CMOS.

[0009] The first adhesion protective stack is deposited on the upper surface of the substrate protective layer;

[0010] The first phase change alloy layer is deposited on the upper surface of the first adhesion protective stack;

[0011] The surface reinforcement layer is vapor-deposited onto the upper surface of the first phase change alloy layer;

[0012] The second metal layer on the epitaxial side includes an epitaxial wafer, a conductive layer, a barrier protective layer, a second adhesion protective stack, and a second phase change alloy layer;

[0013] The conductive layer is deposited on the upper surface of the epitaxial wafer by vapor deposition;

[0014] The barrier protective layer is deposited on the upper surface of the conductive layer;

[0015] The second adhesion protective layer is disposed on the upper surface of the barrier protective layer;

[0016] The second phase change alloy layer is deposited on the upper surface of the second adhesion protective stack.

[0017] In a preferred embodiment, both the substrate protective layer and the barrier protective layer are chromium layers with a thickness of 80-120 nm.

[0018] In a preferred embodiment, both the first and second adhesive protective layers are composed of a "titanium layer-platinum layer" as a repeating unit, wherein the thickness of the titanium layer and the platinum layer is 15-50 nm; the repeating unit is a single-layer or multi-layer structure.

[0019] In a preferred embodiment, the first phase change alloy layer is formed by laser-induced phase change of multiple "gold-tin layers", wherein the thickness of the gold layer is 3-10 nm, the thickness of the tin layer is 8-30 nm, and the multiple "gold-tin layers" are repeatedly deposited ≥ 1 time.

[0020] In a preferred embodiment, the laser-induced phase transition is performed under the following conditions: a Yb glass fiber laser with a wavelength of 1062 nm and a pulse width of 200-300 ns is used, processed by grating scanning, with a spot diameter of 10-50 μm and a pulse repetition frequency of 60-100 kHz.

[0021] In a preferred embodiment, the surface enhancement layer is a gold layer with a thickness of 80-120 nm.

[0022] In a preferred embodiment, the conductive layer is an indium tin oxide film with a thickness of 150-250 nm, and the indium tin oxide film is subjected to annealing treatment.

[0023] In a preferred embodiment, the epitaxial wafer in the second metal layer on the epitaxial side has a "substrate / N-GaN / quantum well / P-GaN" structure, wherein the substrate is a sapphire substrate or a silicon substrate.

[0024] Due to the application of the above technical solution, the beneficial effects of this application compared with the prior art are as follows:

[0025] This application presents an anti-Kirkendall effect metal layer structure for Micro LED bonding. Through pre-phase change treatment, the void ratio at the bonding interface is significantly reduced compared to traditional single-layer Au-Sn bonding, and the thermal resistance is also significantly reduced, effectively improving device heat dissipation. The multi-layer structure design combined with the laser cleaning effect greatly improves the bonding yield of Micro LEDs below 20μm, meeting mass production requirements. The thickness of each layer and the deposition process can be flexibly adjusted to adapt to Micro LED chips of different sizes and bonding equipment, and has broad engineering application value. Attached Figure Description

[0026] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Appendix Figure 1 This is a schematic diagram of the Kirkendall effect-resistant metal layer structure for Micro LED bonding according to the present invention.

[0028] Appendix Figure 2 This is a schematic diagram of the first metal layer on the CMOS side of this utility model;

[0029] Appendix Figure 3 This is a schematic diagram of the second metal layer on the epitaxial side of this utility model;

[0030] Wherein: 1. First metal layer on the CMOS side; 2. Second metal layer on the epitaxial side; 3. Silicon-based CMOS; 4. Substrate protection layer; 5. First adhesion protection stack; 6. First phase change alloy layer; 7. Surface enhancement layer; 8. Epitaxial wafer; 9. Conductive layer; 10. Barrier protection layer; 11. Second adhesion protection stack; 12. Second phase change alloy layer. Detailed Implementation

[0031] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0032] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0033] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing the present invention and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0034] Furthermore, in addition to indicating direction or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this utility model according to the specific circumstances.

[0035] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this utility model based on the specific circumstances.

[0036] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0037] Example 1

[0038] Appendix Figure 1-3 The present invention provides a Kirkendall effect-resistant metal layer structure for Micro LED bonding, comprising a first metal layer 1 on the CMOS side and a second metal layer 2 on the epitaxial side, which are connected by eutectic bonding to form an integral structure.

[0039] The first metal layer 1 on the CMOS side includes:

[0040] Silicon-based CMOS3: As a carrier of driving circuits, it provides the basis for electrical connections.

[0041] Substrate protective layer 4: deposited on the upper surface of silicon-based CMOS3, is a chromium layer with a thickness of 80-120nm. The high chemical stability of chromium is used to block metal interdiffusion and prevent the circuit of silicon-based CMOS3 from being contaminated by bonding metals.

[0042] First adhesive protective layer 5: disposed on the upper surface of the substrate protective layer 4, composed of "titanium layer-platinum layer" as a stacked repeating unit (single stack or multi stack structure), wherein the titanium layer is 15-50nm thick, utilizing the strong adhesion between titanium and chromium to enhance the interlayer bonding force; the platinum layer is 15-50nm thick, serving as an anti-oxidation protective layer to prevent internal metal oxidation.

[0043] First phase change alloy layer: deposited on the upper surface of the first adhesion protective stack 5, formed by laser-induced phase change of multiple "gold-tin layers", with a single gold layer thickness of 3-10nm (limiting infrared laser attenuation) and a tin layer thickness of 8-30nm, and repeated deposition times ≥1; laser treatment causes the "gold-tin layer" to form island-shaped alloy phase in advance, and pre-diffused atoms to reduce migration differences during bonding.

[0044] Surface reinforcement layer 7: deposited on the upper surface of the first phase change alloy layer, is a gold layer with a thickness of 80-120nm, which optimizes the flatness of the bonding interface and enhances mechanical strength.

[0045] The second metal layer 2 on the epitaxial side includes:

[0046] Epitaxial wafer 8: It has a "substrate / N-GaN / quantum well / P-GaN" structure. The substrate is made of sapphire or silicon and provides an LED light-emitting functional layer.

[0047] Conductive layer 9: It is a 150-250nm thick indium tin oxide (ITO) film deposited on the upper surface of epitaxial wafer 8 and annealed (e.g., annealed at 475℃ in an oxygen atmosphere for 3 minutes) to activate charge carriers and form a good conductive path.

[0048] Barrier protective layer 10: deposited on the upper surface of conductive layer 9, is a chromium layer with a thickness of 80-120nm, which prevents conductive layer 9 from reacting with the upper metal layer and blocks ion diffusion.

[0049] The second adhesive protective layer 11 is disposed on the upper surface of the barrier protective layer 10. Its structure is the same as that of the first adhesive protective layer 5. It is composed of a "titanium layer-platinum layer" stack unit to achieve reliable adhesion to the conductive layer 9 and metal protection.

[0050] The second phase change alloy layer 12 is deposited on the upper surface of the second adhesion protective stack 11. Its structure is the same as that of the first phase change alloy layer. It is formed by laser-induced phase change of multiple "gold-tin layers" and is connected to the first phase change alloy layer on the CMOS side through eutectic bonding.

[0051] Eutectic bonding process compatibility:

[0052] Bonding conditions: In a vacuum environment, heat to 200-300℃ at 8-10℃ / min, apply 25-35KN pressure and hold for 8-15min, simultaneously apply 60-80kHz ultrasonic vibration for 8-15min, and finally cool down to room temperature.

[0053] Structural adaptability: The total thickness of the first metal layer 1 on the CMOS side and the second metal layer 2 on the epitaxial side can be adapted to subsequent processes such as bonding time and IBE etching depth by adjusting the thickness of each single layer (such as the number of phase change layer repetitions and the number of titanium-platinum layer stacks).

[0054] To better improve the stability of interface adhesion, the structure of the first adhesion protection stack 5 and the second adhesion protection stack 11 is optimized: a double stack structure is preferred, such as a titanium layer-platinum layer as the stack repeating unit, such as a titanium layer 20nm+platinum layer 20nm+titanium layer 20nm+platinum layer 20nm.

[0055] Preparation of the first phase change alloy layer and the second phase change alloy layer 12: A Yb glass fiber laser with a wavelength of 1062nm and a pulse width of 200-300ns is used to process the gold layer by grating scanning (spot diameter 10-50μm, pulse repetition frequency 60-100kHz) to ensure uniform phase change of the gold layer to the tin layer.

[0056] Design of the first phase change alloy layer and the second phase change alloy layer 12: The first phase change alloy layer and the second phase change alloy layer 12 are preferably formed by 3-5 "gold layer-tin layer" deposition and laser processing, with the total thickness controlled at 45-60nm, so that the bonding interface void ratio is <5%.

[0057] This invention suppresses the Kirkendall effect through the following mechanism:

[0058] Pre-phase transformation induced mechanism: Laser treatment causes the gold-tin layer to undergo a solid-state phase transformation in advance, forming island-like structures of intermetallic compounds such as AuSn2. During bonding, these pre-formed alloy phases can act as a "buffer medium" for atomic diffusion, reducing the difference in diffusion rates between gold and tin at high temperatures, and fundamentally reducing void formation.

[0059] Multi-layer interface synergistic mechanism: Chromium acts as a barrier protective layer 10 to cut off the metal interdiffusion path; the first adhesion protective layer 5 and the second adhesion protective layer 11 enhance the interface bonding force and prevent oxidation through the dual action of "adhesion-protection"; gold acts as a surface reinforcement layer 7 to fill the micro-voids through plastic deformation and form a uniform bonding interface.

[0060] Ultrasonic-assisted densification mechanism: Ultrasonic vibration during the bonding process can break the oxide film on the surface of the first phase change alloy layer and the second phase change alloy layer 12, promote the flow of liquid alloy phase, further fill potential voids, and improve the density of the bonding interface.

[0061] Example 2

[0062] An anti-Kirkendall effect metal layer structure for Micro LED bonding, specifically a bonding metal layer structure for 20μm MicroLEDs, comprising:

[0063] Fabrication of the first metal layer 1 on the CMOS side:

[0064] A 100 nm chromium substrate protective layer 4 was deposited on the surface of a silicon-based CMOS 3 by magnetron sputtering.

[0065] A double-layer stack of “20nm titanium layer + 20nm platinum layer + 20nm titanium layer + 20nm platinum layer” was sequentially sputtered as the first adhesion protective stack 5.

[0066] The gold-tin layer was stacked in three layers by electron beam evaporation deposition of 5nm gold layer + 10nm tin layer. After each deposition, a Yb laser with a wavelength of 1062nm and a pulse width of 230ns was used to perform grating scanning with a spot size of 38μm and a frequency of 80kHz to form the first phase change alloy layer with a total thickness of about 45nm.

[0067] Finally, a 100nm gold surface enhancement layer 7 is deposited, forming the structure: silicon-based CMOS 3 / chromium substrate protective layer 4 100nm / titanium layer 20nm + platinum layer 20nm + titanium layer 20nm + platinum layer 20nm / first phase change alloy layer / gold surface enhancement layer 7 100nm.

[0068] Fabrication of the second metal layer 2 on the epitaxial side:

[0069] A 200 nm ITO thin film was electron beam evaporated on the surface of epitaxial wafer 8 (sapphire / N-GaN / quantum well / P-GaN) on a sapphire substrate and then annealed at 475 °C in an oxygen atmosphere for 3 min.

[0070] Sputtering a 100nm chromium barrier protective layer 10.

[0071] Deposited double-layer structure: "20nm titanium layer + 20nm platinum layer + 20nm titanium layer + 20nm platinum layer".

[0072] The "5nm gold layer + 10nm tin layer" stack was evaporated four times and laser-treated to form a second phase change alloy layer 12 with a total thickness of about 60nm. The structure is: 200nm sapphire-GaN / ITO thin film / 10100nm chromium barrier protective layer / 20nm titanium layer + 20nm platinum layer + 20nm titanium layer + 20nm platinum layer / second phase change alloy layer 12.

[0073] Eutectic bonding process:

[0074] Two metal layers were placed opposite each other and heated to 250°C at 10°C / min in a vacuum chamber. A pressure of 30KN was applied and maintained for 10 min, while ultrasonic vibration at 70kHz was applied for 10 min. After cooling, the void ratio at the bonding interface was found to be <3%, and the thermal resistance was reduced by 25% compared with the traditional process.

[0075] This application presents an anti-Kirkendall effect metal layer structure for Micro LED bonding. Through pre-phase change treatment, the void ratio at the bonding interface is significantly reduced compared to traditional single-layer Au-Sn bonding, and the thermal resistance is also significantly reduced, effectively improving device heat dissipation. The multi-layer structure design combined with the laser cleaning effect greatly improves the bonding yield of Micro LEDs below 20μm, meeting mass production requirements. The thickness of each layer and the deposition process can be flexibly adjusted to adapt to Micro LED chips of different sizes and bonding equipment, and has broad engineering application value.

[0076] Finally, it should be noted that the above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Although the present utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A Kirkendall effect-resistant metal layer structure for Micro LED bonding, characterized in that: It includes a first metal layer on the CMOS side and a second metal layer on the epitaxial side, and the two are connected by eutectic bonding to form an integral structure; The first metal layer on the CMOS side includes a silicon-based CMOS, a substrate protective layer, a first adhesion protective stack, a first phase change alloy layer, and a surface enhancement layer; The substrate protective layer is deposited on the upper surface of the silicon-based CMOS. The first adhesion protective stack is deposited on the upper surface of the substrate protective layer; The first phase change alloy layer is deposited on the upper surface of the first adhesion protective stack; The surface reinforcement layer is vapor-deposited onto the upper surface of the first phase change alloy layer; The second metal layer on the epitaxial side includes an epitaxial wafer, a conductive layer, a barrier protective layer, a second adhesion protective stack, and a second phase change alloy layer; The conductive layer is deposited on the upper surface of the epitaxial wafer by vapor deposition; The barrier protective layer is deposited on the upper surface of the conductive layer; The second adhesion protective layer is disposed on the upper surface of the barrier protective layer; The second phase change alloy layer is deposited on the upper surface of the second adhesion protective stack. 2.The anti-cockcroft-lungley effect metal layer structure for Micro LED bonding of claim 1, wherein, Both the base protective layer and the barrier protective layer are chromium layers with a thickness of 80-120 nm. 3.The anti-cockcroft-lungley effect metal layer structure for Micro LED bonding of claim 1, wherein, Both the first and second adhesion protective layers are composed of a "titanium layer-platinum layer" as a repeating unit, wherein the thickness of the titanium layer and the platinum layer is 15-50 nm; the repeating unit is a single-layer or multi-layer structure. 4.The anti-cockcroft-lungley effect metal layer structure for Micro LED bonding of claim 1, wherein, The first phase change alloy layer is formed by laser-induced phase change of multiple "gold-tin layers". The thickness of the gold layer is 3-10 nm, the thickness of the tin layer is 8-30 nm, and the multiple "gold-tin layers" are repeatedly deposited ≥ 1 time.

5. The anti-cockcroft-lungis effect metal layer structure for Micro LED bonding according to claim 4, wherein, The conditions for the laser-induced phase transition are as follows: a Yb glass fiber laser with a wavelength of 1062nm and a pulse width of 200-300ns is used, processed by grating scanning, with a spot diameter of 10-50μm and a pulse repetition frequency of 60-100kHz.

6. The anti-cockcroft-lungis effect metal layer structure for Micro LED bonding according to claim 1, wherein The surface enhancement layer is a gold layer with a thickness of 80-120 nm.

7. The anti-cockcroft-lungis effect metal layer structure for micro LED bonding according to claim 1, wherein, The conductive layer is an indium tin oxide film with a thickness of 150-250 nm, and the indium tin oxide film is annealed. 8.The anti-cockcroft-lungley effect metal layer structure for Micro LED bonding of claim 1, wherein, The epitaxial wafer in the second metal layer on the epitaxial side has a "substrate / N-GaN / quantum well / P-GaN" structure, and the substrate is a sapphire substrate or a silicon substrate.

Images