Semiconductor device and method of manufacturing the same
Through the hybrid bonding process of magnetic materials, magnetic bonding of semiconductor wafers is used to solve the problem of dielectric film rupture caused by thermal and pressure processes, and the quality of semiconductor devices is improved.
Patent Information
- Application Number
- CN202410433284.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-02-11
- Filing Date
- 2024-04-11
- Publication Date
- 2025-08-12
AI Technical Summary
Existing hybrid bonding processes usually include thermal and pressure processes, which may cause the dielectric film to rupture and affect the quality of semiconductor devices.
The hybrid bonding process of magnetic materials is adopted, and the first semiconductor wafer and the second semiconductor wafer are magnetically bonded, and the thermal and pressure processes are avoided, and the bonding is achieved by mutual attraction of the magnetic structure.
The cracks in the dielectric film are reduced and the quality of semiconductor devices is improved.
Smart Images
Figure CN120473459A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a hybrid bonding process using magnetic materials. Background Art
[0002] Generally speaking, hybrid bonding processes involve bonding metal and dielectric films. Furthermore, hybrid bonding processes often involve thermal and pressure processes, which may change the thermal budget and may also cause dielectric film cracking.
[0003] Therefore, the present invention provides a semiconductor device and a method for manufacturing the same, wherein a hybrid bonding process does not include a thermal process and / or a pressure process. Summary of the Invention
[0004] According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes a first semiconductor wafer and a second semiconductor wafer. The first semiconductor wafer includes a first substrate, a first metallization layer disposed on the top surface of the first substrate, a first dielectric layer disposed on the first metallization layer, a first magnetic structure embedded in the first dielectric layer, and a first metal pad embedded in the first dielectric layer. The first metal pad connects to a first interconnect structure in the first metallization layer. A second semiconductor wafer is disposed on the first semiconductor wafer. The second semiconductor wafer includes a second substrate, a second metallization layer disposed on the top surface of the second substrate, a second dielectric layer disposed on the second metallization layer, a second magnetic structure embedded in the second dielectric layer, and a second metal pad embedded in the second dielectric layer. The second metal pad connects to a second interconnect structure in the second metallization layer. The first magnetic structure is aligned with and in direct contact with the second magnetic structure, and the top surface of the first dielectric layer is in direct contact with the top surface of the second dielectric layer.
[0005] According to some embodiments of the present invention, the first magnetic structure and the second magnetic structure include a material selected from the group consisting of iron oxide, iron-cobalt alloy, iron-nickel alloy, or a combination thereof.
[0006] According to some embodiments of the present invention, the first magnetic structure and the second magnetic structure have opposite polarities.
[0007] According to some embodiments of the present invention, the method further includes: a packaging structure covering the first semiconductor wafer and the second semiconductor wafer.
[0008] According to some embodiments of the present invention, the second semiconductor wafer comprises: a conductive via extending from the bottom surface of the second substrate to the second interconnect structure in the second metallization layer.
[0009] According to some embodiments of the present invention, a top surface of the first metal pad is coplanar with a top surface of the first magnetic structure, and a top surface of the second metal pad is coplanar with a top surface of the second magnetic structure.
[0010] According to some embodiments of the present invention, the first metal pad and the second metal pad are aligned with each other and in direct contact.
[0011] According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided. The method includes the following steps: providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first substrate and a first metallization layer disposed on a top surface of the first substrate; forming a first magnetic layer on a top surface of the first metallization layer; patterning the first magnetic layer to form a first magnetic structure; forming a first dielectric layer on the first magnetic structure, wherein the first magnetic structure is embedded in the first dielectric layer; forming a first metal pad in the first dielectric layer; performing a planarization process to expose the top surface of the first magnetic structure; and performing a magnetization process on the first magnetic structure.
[0012] According to some embodiments of the present invention, patterning the first magnetic layer includes forming a hard mask layer on the first magnetic layer, forming a photoresist layer on the hard mask layer, and patterning the photoresist layer and the hard mask layer to define a pattern of the first magnetic structure.
[0013] According to some embodiments of the present invention, the photoresist layer is stripped before forming the first dielectric layer on the first magnetic structure.
[0014] According to some embodiments of the present invention, before forming the first metal pad, a planarization process is performed on the first dielectric layer.
[0015] According to some embodiments of the present invention, forming the first metal pad includes: removing a portion of the first dielectric layer to form a channel, and filling the channel with a conductive pad material to form the first metal pad.
[0016] According to some embodiments of the present invention, the method further includes the following steps: providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second substrate and a second metallization layer disposed on a top surface of the second substrate; forming a second magnetic layer on a top surface of the second metallization layer; patterning the second magnetic layer to form a second magnetic structure; forming a second dielectric layer on the second magnetic structure, wherein the first magnetic structure is embedded in the second dielectric layer; forming a second metal pad in the second dielectric layer; performing a planarization process to expose the top surface of the second magnetic structure; and performing a magnetization process on the second magnetic structure.
[0017] According to some embodiments of the present invention, the first magnetic structure and the second magnetic structure have opposite polarities.
[0018] According to some embodiments of the present invention, providing the second semiconductor wafer includes forming a conductive via in the second metallization layer, wherein the conductive via extends from the bottom surface of the second substrate to an interconnection structure of the second metallization layer.
[0019] According to some embodiments of the present invention, the method further includes aligning the first magnetic structure and the second magnetic structure to bond the first semiconductor wafer and the second semiconductor wafer, wherein the first magnetic structure and the second magnetic structure are in direct contact with each other.
[0020] According to some embodiments of the present invention, after bonding the first semiconductor wafer and the second semiconductor wafer, the method includes forming a packaging structure on the second semiconductor wafer, such that the packaging structure covers the first semiconductor wafer and the second semiconductor wafer.
[0021] It is to be understood that both the foregoing general description and the following detailed description are by way of example, and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The present invention may be more fully understood by reading the following detailed description of the embodiments in conjunction with the accompanying drawings:
[0023] Figures 1 to 10 is a schematic cross-sectional view of an intermediate stage of forming a first semiconductor wafer according to some embodiments.
[0024] Figure 11 is a schematic cross-sectional view of a second semiconductor wafer according to some embodiments.
[0025] Figure 12 is a schematic cross-sectional view of a semiconductor device according to some embodiments. DETAILED DESCRIPTION
[0026] Reference will now be made in detail to the embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.
[0027] It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific embodiments or examples of components and configurations are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the following description may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present invention may repeat reference numerals and / or symbols in various examples. This repetition is for the purpose of simplicity and clarity and does not itself dictate the relationship between the various embodiments and / or configurations discussed.
[0028] Furthermore, for ease of description, the present invention may use spatially relative terms, such as "below," "beneath," "lower," "above," and "upper," to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.
[0029] It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly connected or coupled to the other element or layer or intervening elements or layers may be present.
[0030] Figure 1 FIG1 is a schematic cross-sectional view of a first semiconductor wafer 100 according to some embodiments. The first semiconductor wafer 100 includes a first substrate 102 and a first metallization layer 104 disposed on a top surface of the first substrate 102. The first metallization layer 104 includes a transistor 106 and a first interconnect structure 108.
[0031] In some embodiments, the first substrate 102 may be a semiconductor substrate, such as a bulk semiconductor substrate, a silicon-on-insulator (SOI) substrate, etc., wherein the insulator may be a buried oxide (BOX) layer, a silicon oxide layer, etc. In some embodiments, the first substrate 102 may be doped (e.g., containing p-type or n-type dopants) or undoped. In some embodiments, the semiconductor material of the first substrate 102 may include silicon, germanium, a compound semiconductor (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), an alloy semiconductor, or a combination thereof. The first substrate 102 may also be formed of other materials, such as sapphire, indium tin oxide, etc.
[0032] In some embodiments, the first metallization layer 104 may include one or more active devices, such as transistors 106. In some embodiments, a first interconnect structure 108 is embedded in the first metallization layer 104. The first interconnect structure 108 may include a conductive material such as a metal, a metal alloy, a metal nitride, or the like. For example, the first interconnect structure 108 may include copper, tungsten, or other suitable conductive materials.
[0033] refer to Figure 1, a first magnetic layer 110 is formed on a top surface of the first metallization layer 104. In some embodiments, the first magnetic layer 110 is formed by a ferroelectric deposition process. In some embodiments, the first magnetic layer 110 may include iron oxide, such as Fe3O4. In some embodiments, the first magnetic layer 110 may include an iron-cobalt alloy, an iron-nickel alloy, an iron-aluminum alloy, or a combination thereof.
[0034] refer to Figure 2 A hard mask layer 120 is formed on the first magnetic layer 110. The hard mask layer 120 includes a dielectric material such as tetraethylorthosilicate (TEOS), a low-k dielectric material, doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), etc.), and / or other suitable dielectric materials. In some embodiments, the hard mask layer 120 can be formed using a suitable deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.
[0035] refer to Figure 3 , a photoresist layer 130 is formed on the hard mask layer 120. In some embodiments, the photoresist layer 130 may include carbon and hydrogen. In some embodiments, the photoresist layer 130 may be formed by any suitable deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). The photoresist layer 130 is then patterned to protect and define the pattern of the first magnetic structure 112, as will be discussed in Question 4. The photoresist layer 130 may be patterned by a suitable method, such as photolithographic patterning and etching.
[0036] refer to Figure 4, a portion of the first magnetic layer 110 is removed to form the first magnetic structure 112. In some embodiments, a portion of the hard mask layer 120 and a portion of the first magnetic layer 110 are removed using a suitable dry etching process, such as a reactive ion etching (RIE) process or other suitable anisotropic etching process. In other words, the portion of the first magnetic layer 110 located below the photoresist layer 130 is retained to form the first magnetic structure 112.
[0037] refer to Figure 5 , remove the photoresist layer 130. In some embodiments, a suitable stripping process is used to remove the photoresist layer 130. After removing the photoresist layer 130, the hard mask layer 120 is exposed.
[0038] refer to Figure 6 A first dielectric layer 122 is formed on the first magnetic structure 112, wherein the first magnetic structure 112 is embedded in the first dielectric layer 122. The first dielectric layer 122 includes a dielectric material such as tetraethyl orthosilicate (TEOS), a low-k dielectric material, doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), etc.), and / or other suitable dielectric materials. In some embodiments, the first dielectric layer 122 can be formed using a suitable deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.
[0039] In some embodiments, the first dielectric layer 122 and the hard mask layer 120 may comprise the same material. Figure 6 In some embodiments, the first dielectric layer 122 and the hard mask layer 120 include the same material. In some embodiments, the first dielectric layer 122 and the hard mask layer 120 may include different materials. In some embodiments, the hard mask layer 120 is removed before forming the first dielectric layer 122.
[0040] refer to Figure 7 A planarization process is performed on the first dielectric layer 122. In some embodiments, the planarization process is a chemical mechanical planarization (CMP) process.
[0041] refer to Figure 8, a portion of the first dielectric layer 122 is removed to form a channel T. The channel T exposes a portion of the top surface of the first interconnect structure 108. In some embodiments, a suitable dry etching process is used to remove the portion of the first dielectric layer 122, such as a reactive ion etching (RIE) process or other suitable anisotropic etching process.
[0042] refer to Figure 9 , a conductive material is filled in the channel T to form a first metal pad 140. The first metal pad 140 may cover the top surface of the first dielectric layer 122. The first metal pad 140 may include a conductive material such as a metal, a metal alloy, a metal nitride, etc. For example, the first metal pad 140 may include copper, tungsten, or other suitable conductive materials. In some embodiments, the first metal pad 140 may be formed using a suitable deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), etc.
[0043] refer to Figure 10 A planarization process is performed on the first metal pad 140. In some embodiments, the planarization process may be a chemical mechanical planarization (CMP) process. In some embodiments, the planarization process also includes a grinding process. After the planarization process, the top surface of the first magnetic structure 112 is exposed. After the first magnetic structure 112 is exposed, a magnetization process is performed on the first magnetic structure 112. Specifically, a magnetic field is applied to the first magnetic structure 112.
[0044] refer to Figure 11 , with Figures 1 to 10 Similar steps are followed to form a second semiconductor wafer 200. A second substrate 202 and a second metallization layer 204 disposed on the top surface of the second substrate 202 are provided. A second magnetic layer is then formed on the top surface of the second metallization layer 204. The second magnetic layer is patterned to form a second magnetic structure 212. Next, a second dielectric layer 222 is formed on the second magnetic structure 212, wherein the second magnetic structure 212 is embedded in the second dielectric layer 222. A second metal pad 242 is formed in the second dielectric layer 222. A planarization process is performed to expose the top surface of the second magnetic structure 212, and a magnetization process is then performed on the second magnetic structure 212.
[0045] The second metallization layer 204 includes transistors 206 and a second interconnect structure 208. The second semiconductor wafer 200 includes conductive vias 250 extending from the bottom surface of the second substrate 202 to the second interconnect structure 208 of the second metallization layer 204.
[0046] refer to Figure 12The semiconductor device 300 includes a first semiconductor wafer 100 and a second semiconductor wafer 200. The semiconductor device 300 can be applied to an integrated circuit (IC) or a portion thereof, such as a logic circuit, a resistor, a capacitor, an inductor, a memory (such as a dynamic random access memory (DRAM), etc. It should be understood that in order to simplify the drawings, Figure 12 Some elements of the semiconductor device 300 are not shown, and additional elements may be included in other embodiments of the semiconductor device 300. The semiconductor device 300 may include a package structure 310 covering the first semiconductor wafer 100 and the second semiconductor wafer 200.
[0047] The first semiconductor wafer 100 and the second semiconductor wafer 200 are bonded by aligning the first magnetic structure 112 and the second magnetic structure 212. The first magnetic structure 112 and the second magnetic structure 212 have opposite polarities. For example, the top surface of the first magnetic structure 112 is a north pole, and the top surface of the second magnetic structure 212 is a south pole. The first magnetic structure 112 is in direct contact with the second magnetic structure 212. The top surface of the first metal pad 142 is coplanar with the top surface of the first magnetic structure 112, and the top surface of the second metal pad 242 is coplanar with the top surface of the second magnetic structure 212. The top surfaces of the first dielectric layer 122 and the second dielectric layer 222 are in direct contact.
[0048] In the present invention, a first semiconductor wafer and a second semiconductor wafer are joined magnetically without thermal and / or pressure processes. Therefore, the method provided by the present invention can reduce cracks in dielectric films and improve the quality of semiconductor devices.
[0049] Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
[0050] It will be apparent to those skilled in the art that various modifications and variations may be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover modifications and variations of the present invention that fall within the scope of the appended claims.
[0051]
Explanation of symbols
[0052] 100: First semiconductor wafer
[0053] 102: first substrate
[0054] 104: first metallization layer
[0055] 106: Transistor
[0056] 108: First interconnection structure
[0057] 110: first magnetic layer
[0058] 112: First magnetic structure
[0059] 120: Hard mask layer
[0060] 122: first dielectric layer
[0061] 130: Photoresist layer
[0062] 140: First metal pad
[0063] 142: First metal pad
[0064] 200: second semiconductor wafer
[0065] 202: Second substrate
[0066] 204: Second metallization layer
[0067] 206: Transistor
[0068] 208: Second interconnect structure
[0069] 212: Second magnetic structure
[0070] 222: second dielectric layer
[0071] 242: Second metal pad
[0072] 250: conductive through hole
[0073] 300:Semiconductor device
[0074] 310: packaging structure.
Claims
1. A semiconductor device, characterized in that: include: A first semiconductor wafer comprising: a first substrate; a first metallization layer disposed on the top surface of the first substrate; a first dielectric layer disposed on the first metallization layer; a first magnetic structure embedded in the first dielectric layer; and a first metal pad embedded in the first dielectric layer, wherein the first metal pad is connected to a first interconnect structure in the first metallization layer; and A second semiconductor wafer is disposed on the first semiconductor wafer, wherein the second semiconductor wafer comprises: a second substrate; a second metallization layer disposed on the top surface of the second substrate; a second dielectric layer disposed on the second metallization layer; a second magnetic structure embedded in the second dielectric layer; and a second metal pad embedded in the second dielectric layer, wherein the second metal pad is connected to a second interconnect structure in the second metallization layer; The first magnetic structure is aligned with and directly contacts the second magnetic structure, and the top surface of the first dielectric layer is directly contacted with the top surface of the second dielectric layer.
2. The semiconductor device according to claim 1, wherein The first magnetic structure and the second magnetic structure include a material selected from the group consisting of iron oxide, iron-cobalt alloy, iron-nickel alloy, or a combination thereof.
3. The semiconductor device according to claim 1, wherein The first magnetic structure and the second magnetic structure have opposite polarities.
4. The semiconductor device according to claim 1, wherein Further including: The packaging structure covers the first semiconductor wafer and the second semiconductor wafer.
5. The semiconductor device according to claim 1, wherein The second semiconductor wafer includes: A conductive via extends from the bottom surface of the second substrate to the second interconnect structure in the second metallization layer.
6. The semiconductor device according to claim 1, wherein The top surface of the first metal pad is coplanar with the top surface of the first magnetic structure, and the top surface of the second metal pad is coplanar with the top surface of the second magnetic structure.
7. The semiconductor device according to claim 1, wherein The first metal pad and the second metal pad are aligned with each other and directly contact each other.
8. A method for manufacturing a semiconductor device, characterized in that: include: Providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first substrate and a first metallization layer disposed on a top surface of the first substrate; forming a first magnetic layer on a top surface of the first metallization layer; patterning the first magnetic layer to form a first magnetic structure; forming a first dielectric layer on the first magnetic structure, wherein the first magnetic structure is embedded in the first dielectric layer; forming a first metal pad in the first dielectric layer; performing a planarization process to expose a top surface of the first magnetic structure; and A magnetization process is performed on the first magnetic structure.
9. The method according to claim 8, characterized in that The patterning of the first magnetic layer comprises: forming a hard mask layer on the first magnetic layer; forming a photoresist layer on the hard mask layer; and The photoresist layer and the hard mask layer are patterned to define a pattern of the first magnetic structure.
10. The method according to claim 9, characterized in that Further including: Before forming the first dielectric layer on the first magnetic structure, the photoresist layer is stripped off.
11. The method according to claim 8, characterized in that Further including: Before forming the first metal pad, a planarization process is performed on the first dielectric layer.
12. The method according to claim 8, characterized in that The forming of the first metal pad comprises: removing a portion of the first dielectric layer to form a channel; and The channel is filled with a conductive material to form the first metal pad.
13. The method according to claim 8, characterized in that Further including: Providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second substrate and a second metallization layer disposed on a top surface of the second substrate; forming a second magnetic layer on a top surface of the second metallization layer; patterning the second magnetic layer to form a second magnetic structure; forming a second dielectric layer on the second magnetic structure, wherein the first magnetic structure is embedded in the second dielectric layer; forming a second metal pad in the second dielectric layer; performing a planarization process to expose a top surface of the second magnetic structure; and A magnetization process is performed on the second magnetic structure.
14. The method according to claim 13, characterized in that The first magnetic structure and the second magnetic structure have opposite polarities.
15. The method according to claim 13, characterized in that Before providing the second semiconductor wafer, the method includes: A conductive via is formed in the second metallization layer, wherein the conductive via extends from the bottom surface of the second substrate to the interconnect structure of the second metallization layer.
16. The method according to claim 13, characterized in that Further including: The first magnetic structure and the second magnetic structure are aligned to bond the first semiconductor wafer and the second semiconductor wafer, wherein the first magnetic structure and the second magnetic structure are in direct contact with each other.
17. The method according to claim 16, characterized in that After bonding the first semiconductor wafer and the second semiconductor wafer, the method further comprises: A packaging structure is formed on the second semiconductor wafer, so that the packaging structure covers the first semiconductor wafer and the second semiconductor wafer.