Digital power amplifier for reducing signal peak-to-average ratio, related method and device

Abstract

According to the digital power amplifier capable of reducing the signal peak-to-average ratio, the related method and the related device, different signal amplification modes can be selected based on the power of digital signals, and the signal peak-to-average ratio can be reduced. Specifically, the low-power digital signal is amplified through the CMOS complementary metal oxide semiconductor amplification module, so that the output power of the low-power input digital signal is improved, the peak-to-average ratio of the output signal is reduced, and the communication quality of the terminal equipment is improved.

Description

Technical Field

[0001] The present application relates to the field of communications, and in particular to a digital power amplifier, a method and a device for reducing a signal peak-to-average ratio. Background Art

[0002] With the continuous advancement of mobile communication technology, signal modulation methods have become increasingly complex, resulting in increasingly higher peak-to-average ratios (PARs) of communication signals. Based on existing knowledge, a higher PAR is more likely to cause nonlinear distortion in communication signals, leading to significant spectrum spread interference and in-band signal distortion, severely degrading the performance of the entire communication system. Summary of the Invention

[0003] In a first aspect, the present application provides a digital power amplifier, related methods, and devices for reducing the peak-to-average ratio of a signal, wherein the digital power is applied to a terminal device, and the digital power amplifier may include: a power distribution module, a low-power amplification module, and a high-power amplification module;

[0004] Power distribution module, coupled with low power amplifier module and high power amplifier module:

[0005] Can be used to receive digital signals, the digital signals including a first digital signal and a second digital signal;

[0006] It can be used to transmit a first digital signal to a low-power amplification module, where the first digital signal has a power less than a preset value;

[0007] It can be used to transmit a second digital signal to the high-power amplification module, where the second digital signal has a power greater than or equal to a preset value;

[0008] The low-power amplification module is connected in parallel with the high-power amplification module and can be used to perform a first amplification process on the first digital signal to generate a first analog signal;

[0009] The high-power amplification module can be used to perform a second amplification process on the second digital signal to generate a second analog signal.

[0010] By implementing the digital power amplifier provided in the first aspect, the digital signal amplifier can transmit digital signals in different power ranges to the corresponding amplification modules for amplification processing based on the power of the digital signals, which helps to make the digital signals in the low power range output higher power output signals, thereby reducing the peak-to-average ratio of the output signal, improving the linear stability of the output signal, and enabling the terminal equipment to have good communication quality.

[0011] In some embodiments of the digital power amplifier provided by the first aspect, the low-power amplification module is a CMOS complementary metal oxide semiconductor amplification module;

[0012] The high power amplifier module is a switching type power amplifier module.

[0013] The digital power amplifier provided in the above embodiment is a heterogeneous integrated digital power amplifier composed of a low-power amplifier module and a high-power amplifier module made of different manufacturing processes and materials, which helps to improve the amplification efficiency of different amplifier modules for digital signals in different power ranges, thereby reducing the peak-to-average ratio of the output signal and improving the communication stability of the terminal equipment.

[0014] In some embodiments of the digital power amplifier provided in the first aspect, the power distribution module may include a power determination module and a switch;

[0015] The power judgment module is coupled to the switch and can be used to receive a digital signal, generate power based on the digital signal, and send a control signal to the switch; the control signal can be used to control the switch to conduct a first path between the power distribution module and the low-power amplification module, or can be used to control the switch to conduct a second path between the power distribution module and the high-power amplification module.

[0016] By implementing the digital power amplifier provided in the above-described embodiment, the digital power amplifier can determine whether a digital signal exceeds a preset threshold value and, based on the determination result, transmit the input digital signal to the corresponding amplification module. Specifically, the digital power amplifier in the embodiment of the present application can achieve the purpose of transmitting the digital signal to the corresponding amplification module by providing two amplification modules and adjusting the operating state of the two amplification modules using a switch. It can be seen that the digital power amplifier in the embodiment of the present application can achieve the purpose of using different amplification processing for digital signals of different power levels with a simple circuit structure.

[0017] In some embodiments, the digital power amplifier provided in the first aspect may be configured to generate and send a first control signal to the switch when the digital signal is a first digital signal;

[0018] The first control signal may be used to control the switch to conduct a first path, and the first path may be used to transmit the first digital signal to the low-power amplification module;

[0019] The power determination module may also be configured to generate and send a second control signal to the switch when the digital signal is a second digital signal;

[0020] The second control signal can be used to control the switch to conduct the second path, and the second path can be used to transmit the second digital signal to the high power amplification module.

[0021] When implementing the digital power amplifier provided in the above embodiment, the digital power amplifier can, when the power of the digital signal is less than a preset value (the digital signal can be considered as the first digital signal), turn on the low-power amplification module, thereby transmitting the first digital signal to the low-power amplification module; and when the power of the digital signal is greater than or equal to the preset value (the digital signal can be considered as the second digital signal), turn on the high-power amplification module, thereby transmitting the second digital signal to the high-power amplification module. It can be seen that the digital power amplifier of the embodiment of the present application can achieve the goal of using different amplification processing for digital signals of different powers with a simple circuit structure.

[0022] In some embodiments of the digital power amplifier provided in the first aspect, the power distribution module may include a coupler, and the coupler may include an input port and a first output port;

[0023] The coupler receives the digital signal through the input port and couples with the low-power amplification module through the first output port.

[0024] When implementing the digital power amplifier provided in the above embodiment, the digital power amplifier can further distribute digital signals to different amplification modules through a coupler, thereby achieving the purpose of using different amplification processes for digital signals of different powers.

[0025] In some embodiments of the digital power amplifier provided in the first aspect, the high power amplification module may include a first high power amplification module and a second high power amplification module;

[0026] The coupler may further include a second output port and a third output port;

[0027] The coupler is coupled to the first high-power amplifying module through the second output port and is coupled to the second high-power amplifying module through the third output port.

[0028] When implementing the digital power amplifier provided in the above embodiment, the digital power amplifier can further distribute digital signals to different amplification modules through a coupler, thereby achieving the purpose of using different amplification processes for digital signals of different powers.

[0029] In some embodiments of the digital power amplifier provided in the first aspect, when the digital signal is a first digital signal, the coupler divides the first digital signal into a first sub-digital signal, a second sub-digital signal, and a third sub-digital signal according to a first preset ratio;

[0030] The first sub-digital signal is transmitted to the low-power amplification module through the first output port;

[0031] The second sub-digital signal is transmitted to the first high-power amplification module through the second output port, and the third sub-digital signal is transmitted to the second high-power amplification module through the third output port;

[0032] The second sub-digital signal and the third sub-digital signal enter the low-power amplification module through the first high-power amplification module and the second high-power amplification reflection.

[0033] In implementing the digital power amplifier provided in the above embodiment, the coupler can divide the digital signal into a first sub-digital signal, a second sub-digital signal, and a third sub-digital signal according to a first preset ratio, and transmit each sub-digital signal to a corresponding amplification module. Due to the mismatch between the impedance of the digital signal and the impedance of the amplification module circuit, the sub-digital signal entering the high-power amplification module can be reflected and enter the low-power amplification module, thereby achieving the purpose of transmitting the entire first digital signal to the low-power amplification module.

[0034] In some embodiments of the digital power amplifier provided in the first aspect, when the digital signal is a second digital signal, the coupler divides the second digital signal into a fourth sub-digital signal and a fifth sub-digital signal according to a second preset ratio;

[0035] The fourth sub-digital signal is transmitted to the first high-power amplification module through the second output port, and the fifth sub-digital signal is transmitted to the second high-power amplification module through the third output port.

[0036] In implementing the digital power amplifier provided by the above embodiment, due to the characteristics of the coupler, when the digital signal is the second digital signal, the second digital signal can be fully input into the high-power amplification module, thereby achieving the purpose of using the high-power amplification module to amplify the higher-power digital signal and ensuring the efficiency of digital signal amplification. Specifically, the coupler can divide the digital signal into a fourth sub-digital signal and a fifth sub-digital signal according to a second preset ratio, and transmit the fourth sub-digital signal to the first high-power amplification module via the second output port, and transmit the fifth sub-digital signal to the second high-power amplification module via the third output port.

[0037] In some embodiments of the digital power amplifier provided in the first aspect, the digital power amplifier may further include a power combining module, and the terminal device may include a transmitting antenna;

[0038] The power synthesis module is coupled with the low-power amplification module and the high-power amplification module, and can be used to generate an output signal based on the first analog signal generated by the low-power amplification module and the second analog signal generated by the high-power amplification module, and transmit the output signal to the transmitting antenna, and the output signal is transmitted to the target terminal via the transmitting antenna.

[0039] The digital power amplifier provided in the above embodiment can also include a power synthesis module, which can receive the first analog signal generated by the low-power amplification module and the second analog signal generated by the high-power amplification module, and generate an output signal based on the first analog signal and the second analog signal, and finally transmit the output signal to the transmitting antenna, thereby realizing communication with the target terminal.

[0040] In some embodiments of the digital power amplifier provided in the first aspect, the power synthesis module can also be used to perform harmonic control processing on the first analog signal and the second analog signal before generating an output signal based on the first analog signal generated by the low-power amplification module and the second analog signal generated by the high-power amplification module, so as to ensure the subsequent communication quality of the output signal.

[0041] In a second aspect, an embodiment of the present application provides a terminal device, which may include a digital power amplifier, a signal generating module, and a transmitting antenna;

[0042] The signal generating module is coupled to the digital power amplifier and can be used to generate a digital signal and transmit the digital signal to the digital power amplifier;

[0043] The transmitting antenna is coupled to the digital power amplifier and can be used to receive the output signal sent by the digital power amplifier and send the output signal to the target terminal.

[0044] In a third aspect, an embodiment of the present application provides a method for reducing a signal peak-to-average ratio based on a digital power amplifier, which can be applied to a digital power amplifier. The digital power amplifier may include a power distribution module, a low-power amplification module, and a high-power amplification module. The method may include:

[0045] receiving a digital signal through a power distribution module, the digital signal including a first digital signal and a second digital signal;

[0046] The first digital signal is transmitted to the low-power amplification module through the power distribution module, and the first analog signal is generated by the low-power amplification module, where the first digital signal has a power less than a preset value;

[0047] The second digital signal is transmitted to the high power amplification module through the power distribution module, and a second analog signal is generated through the high power amplification module. The second digital signal is a digital signal with power greater than or equal to a preset value.

[0048] In implementing the method provided in the third aspect, the digital power amplifier may further include a power synthesis module; and the method may further include:

[0049] An output signal is generated based on the first analog signal and the second analog signal through a power synthesis module, and the output signal is transmitted to a transmitting antenna through the power synthesis module.

[0050] In a fourth aspect, the present application provides a terminal device comprising one or more processors and one or more memories; wherein the one or more memories are coupled to the one or more processors, and the one or more memories are used to store computer program code, and the computer program code comprises computer instructions. When the one or more processors execute the computer instructions, the method described in the third aspect and any possible implementation method of the third aspect is executed.

[0051] In a fifth aspect, the present application provides a computer-readable storage medium comprising instructions, which, when executed on a target terminal, execute the method described in the third aspect and any possible implementation of the third aspect.

[0052] In a sixth aspect, the present application provides a computer program product comprising instructions, which, when the computer program product is run on a terminal device, enables the terminal device to execute the method described in the third aspect and any possible implementation of the third aspect.

[0053] It is understandable that the terminal devices provided in the second and fourth aspects, the computer-readable storage medium provided in the fifth aspect, and the computer program product provided in the sixth aspect are all related to the digital power amplifier provided in the first aspect and can be used to perform the method provided in this application. Therefore, the beneficial effects achievable by these devices can be referenced to the beneficial effects of the digital power amplifier in the first aspect, and will not be further elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1a This is a schematic diagram of the structure of a power amplifier in the prior art;

[0055] Figure 1b This is a graph showing the amplification effect of a high-power amplifier on a digital signal in the prior art;

[0056] Figure 2 1 is a schematic diagram of the composition of a digital power amplifier for reducing the peak-to-average ratio of a signal provided by an embodiment of the present application;

[0057] Figure 3 1 is a schematic diagram of another digital power amplifier for reducing the peak-to-average ratio of a signal provided in an embodiment of the present application;

[0058] Figure 4 is an amplification efficiency curve diagram of a digital power amplifier provided in an embodiment of the present application;

[0059] Figure 51 is a schematic diagram of another digital power amplifier for reducing the peak-to-average ratio of a signal provided in an embodiment of the present application;

[0060] Figure 6a This is a schematic diagram of a digital signal transmission path provided by an embodiment of the present application;

[0061] Figure 6b This is a schematic diagram of another digital signal transmission path provided by an embodiment of the present application;

[0062] Figure 7 is an amplification efficiency curve diagram of another digital power amplifier provided in an embodiment of the present application;

[0063] Figure 8 1 is a schematic diagram of another digital power amplifier for reducing the peak-to-average ratio of a signal provided in an embodiment of the present application;

[0064] Figure 9 1 is a flow chart of a method for reducing a signal peak-to-average ratio based on a digital power amplifier provided in an embodiment of the present application;

[0065] Figure 10 This is a schematic diagram of the structure of a terminal device provided in an embodiment of the present application;

[0066] Figure 11 This is a hardware structure diagram of a terminal device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0067] The following is a clear and detailed description of the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in the text is only a description of the association relationship between related objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0068] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to imply or suggest relative importance or implicitly indicate the number of the technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

[0069] The term "user interface (UI)" in the following embodiments of this application refers to a medium interface for interaction and information exchange between an application or operating system and a user, which realizes the conversion between the internal form of information and the form acceptable to the user. The user interface is a source code written in a specific computer language such as Java and extensible markup language (XML). The interface source code is parsed and rendered on the terminal device and finally presented as content that the user can recognize. The commonly used form of user interface is graphical user interface (GUI), which refers to a user interface related to computer operations that is displayed in a graphical manner. It can be a visual interface element such as text, icons, buttons, menus, tabs, text boxes, dialog boxes, status bars, navigation bars, widgets, etc. displayed on the display screen of the terminal device.

[0070] To make the description of the following embodiments clear and concise, a brief introduction to the related technologies is first given:

[0071] Peak-to-Average Ratio (PAR): The Peak-to-Average Ratio (PAR) is a statistic used to describe signal power in wireless communication systems. It represents the ratio of the highest peak power to the average power in a signal. PAR can help assess the dynamic range of a signal. A high PAR indicates the presence of high peak power, which increases the system's dynamic range, leading to greater nonlinear distortion and loss of power amplifier efficiency. Therefore, system design often requires consideration of PAR control to reduce power amplifier requirements and lower equipment costs.

[0072] Impedance matching: When two transmission lines with different characteristic impedances are connected, or when the load impedance is not equal to the transmission line characteristic impedance, the impedance mismatch causes reflections, which reduces the power capacity and transmission efficiency of the transmission system. Therefore, it is necessary to add a matching circuit between the two transmission lines, or between the load or transmission line, to perform impedance matching and reduce the reflections caused by the impedance mismatch.

[0073] See Figure 1a , Figure 1a The figure is a schematic diagram of the structure of a power amplifier in the prior art.

[0074] like Figure 1a As shown, the power amplifier 10 in the prior art can implement high-power amplification of digital signals.

[0075] Further, see Figure 1b , Figure 1bThe figure is a graph showing the amplification effect of a high power amplifier on a digital signal in the prior art. Figure 1b As shown, the high-power amplifier does not have a significant amplification effect on digital signals with low input power. The high-power amplifier can mainly have better amplification efficiency for digital signals with higher input power (compared with the low-power amplifier, the high-power amplifier has a higher saturation power and can amplify digital signals in a wider power range). Therefore, it can be considered that the digital signal after amplification by the high-power amplifier will easily have a "peak-to-average ratio difference of the output signal is too large", which will cause the output signal to be prone to nonlinear distortion, thereby reducing the communication quality of the terminal equipment.

[0076] The embodiment of the present application can provide a digital power amplifier that reduces the peak-to-average ratio of the signal. It can select different amplification methods to amplify the digital signal based on the power of the digital signal. This helps to ensure the overall amplification efficiency of the digital signal while reducing the power difference between the output signal after amplification of the digital signal in the low power range and the output signal after amplification of the digital signal in the high power range, thereby reducing the peak-to-average ratio of the output signal of the terminal device and helping to improve the communication quality of the terminal device.

[0077] See Figure 2 , Figure 2 A schematic diagram of the composition of a digital power amplifier for reducing the peak-to-average ratio of a signal provided in an embodiment of the present application.

[0078] like Figure 2 As shown, the digital power amplifier 20 may include a power distribution module 21, a low power amplification module 22 and a high power amplification module 23;

[0079] The power distribution module 21 is coupled with the low power amplification module 22 and the high power amplification module 23:

[0080] The power distribution module 21 may be configured to receive a digital signal, the digital signal including a first digital signal and a second digital signal;

[0081] The power distribution module 21 may also be used to transmit a first digital signal to the low-power amplification module 22 , where the first digital signal is a digital signal having a power less than a preset value;

[0082] The power distribution module 21 may be configured to transmit the second digital signal to the high power amplification module 23 , where the second digital signal is a digital signal having a power greater than or equal to a preset value;

[0083] The low-power amplifying module 22 is connected in parallel with the high-power amplifying module 23 and can be used to perform a first amplification process on the first digital signal to generate a first analog signal;

[0084] The high-power amplification module 23 can be used to perform a second amplification process on the second digital signal to generate a second analog signal.

[0085] The digital signal can be generated by the signal generating module 61 in the terminal device 30. For details, see Figure 10 The related embodiments are not described in detail here.

[0086] Optionally, the preset value can be set and adjusted by technicians based on the gain and / or linearity corresponding to the digital power amplifier, etc., and this application does not limit this.

[0087] Optionally, the low-frequency amplification module may be composed of a radio frequency integrated circuit (RFIC), and the high-frequency amplification module may be composed of a front-end module circuit (Front-end Modules, FEM).

[0088] In some possible implementations, the low-power amplifier module 22 is a CMOS complementary metal oxide semiconductor amplifier module;

[0089] The high power amplifier module 23 is a switch-type power amplifier module.

[0090] Specifically, the low-power amplifier module 22 may be an amplifier using a silicon-based complementary metal oxide semiconductor (CMOS) process and an inverter design. The high-power amplifier module 23 may be a switching power amplifier (such as a class E, class F, or inverse class F power amplifier) using a compound semiconductor process (such as gallium arsenide (GaAs) or gallium nitride (GaN)).

[0091] In some possible implementations, the digital power amplifier may further include a power combining module 24, and the terminal device may include a transmitting antenna;

[0092] The power synthesis module 24 is coupled with the low-power amplification module 22 and the high-power amplification module 23, and can be used to generate an output signal based on the first analog signal generated by the low-power amplification module 22 and the second analog signal generated by the high-power amplification module 23, and transmit the output signal to the transmitting antenna, and the output signal is transmitted to the target terminal via the transmitting antenna.

[0093] In some possible embodiments, the power synthesis module 24 can also be used to perform harmonic control processing on the first analog signal and the second analog signal before generating an output signal based on the first analog signal generated by the low-power amplification module 22 and the second analog signal generated by the high-power amplification module 23, so as to ensure the subsequent communication quality of the output signal.

[0094] For some possible implementations, see Figure 3 , Figure 3 A schematic diagram of the composition of another digital power amplifier for reducing the peak-to-average ratio of a signal provided in an embodiment of the present application.

[0095] like Figure 3 As shown, the power distribution module 21 may include a power determination module 211 and a switch 212;

[0096] The power judgment module 211 is coupled to the switch 212 and can be used to receive a digital signal, generate power based on the digital signal and send a control signal to the switch 212; the control signal can be used to control the switch 212 to conduct a first path between the power distribution module 21 and the low-power amplification module 22, or can be used to control the switch 212 to conduct a second path between the power distribution module 21 and the high-power amplification module 23.

[0097] The low-power amplification module 22 may include one or more low-power amplification circuits; similarly, the high-power amplification module 23 may include one or more high-power amplification circuits.

[0098] In some possible implementations, it may be configured to generate and send a first control signal to the switch 212 when the digital signal is a first digital signal;

[0099] The first control signal may be used to control the switch 212 to conduct a first path, and the first path may be used to transmit the first digital signal to the low power amplification module 22;

[0100] The power determination module 211 may also be configured to generate and send a second control signal to the switch 212 when the digital signal is a second digital signal;

[0101] The second control signal can be used to control the switch 212 to conduct the second path, and the second path can be used to transmit the second digital signal to the high power amplification module 23.

[0102] Exemplarily, the switch 212 can respond to a first control signal and throw the switch chip to the interface 31, thereby opening a first path between the signal input line and the low-power amplifier module 22, thereby achieving the purpose of transmitting the first digital signal to the low-power amplifier module 22; the switch 212 can respond to a second control signal and throw the switch chip to the interface 32, thereby opening a second path between the signal input line and the high-power amplifier module 23, thereby achieving the purpose of transmitting the second digital signal to the high-power amplifier module 23.

[0103] For example, see Figure 4 , Figure 4This is a graph showing the amplification efficiency of a digital power amplifier provided in an embodiment of the present application.

[0104] like Figure 4 As shown, curve 401 represents the amplification efficiency curve when only the low-power amplification module is used to amplify the digital signal. Point P1 can represent the saturation power point of the low-power amplification module, that is, the low-power amplification module can only effectively amplify the digital signal with a power less than or equal to the power value corresponding to point P1; curve 402 represents the amplification efficiency curve when the high-power amplification module is used to amplify the digital signal. Point P2 can represent the saturation power point of the high-power amplification module, that is, the high-power amplification module can only effectively amplify the digital signal with a power less than or equal to the power value corresponding to point P2. It can be seen that the low-power amplifier module has a better amplification effect on digital signals with lower power, while the high-power amplifier module has a better amplification effect on digital signals with higher power, and the power range covered by the power amplifier module is smaller than that of the high-power amplifier module (for example, the low-power amplifier module can only amplify and process digital signals below 200dBm, while the high-power amplifier module can amplify and process digital signals below 10,000dBm. It should be noted that the above examples of the power processing upper limits of the low-power amplifier module and the high-power amplifier module are only for more detailed explanation of the embodiment method of the present application, and do not mean that the amplifier module in the present application can only process digital signals below 10,000dBm, and should not constitute a limitation to the present application).

[0105] Furthermore, curve 403 represents an amplification efficiency curve corresponding to the digital power amplifier 20 provided in an embodiment of the present application. It can be seen that the digital power amplifier 20 provided in an embodiment of the present application can achieve good amplification efficiency for both low-power input digital signals and high-power input digital signals, thereby ensuring the quality of the communication signal output by the terminal device while also reducing the peak-to-average ratio of the communication signal, further improving the stability of the communication signal. Point P3 can represent a preset threshold, and the power determination module 211 can switch the power amplification module when the power of the input digital signal reaches P3.

[0106] Optionally, the switch 212 can be a single-pole double-throw switch, which ensures that only one amplifier module is in operation at a time. The above example of the switch 212 is merely for the purpose of illustrating the method of the present embodiment in more detail. The specific type and form of the switch 212 can be adjusted by technicians based on actual conditions and is not limited by the present application.

[0107] It should be noted that the above preset values are set by technical personnel according to actual conditions, and this application does not impose any restrictions thereon.

[0108] For some possible implementations, see Figure 5 , Figure 5 A schematic diagram of the composition of another digital power amplifier for reducing the peak-to-average ratio of a signal provided in an embodiment of the present application.

[0109] like Figure 5 As shown, the power distribution module 21 may include a coupler 213 , and the coupler 213 may include an input port 51 and a first output port 52 ;

[0110] The coupler 213 receives the digital signal through the input port 51 and is coupled to the low power amplification module 22 through the first output port 52 .

[0111] In some possible implementations, the high power amplification module 23 may include a first high power amplification module 231 and a second high power amplification module 232 ;

[0112] The coupler 213 may further include a second output port 53 and a third output port 54;

[0113] The coupler 213 is coupled to the first high power amplification module 231 through the second output port 53 , and is coupled to the second high power amplification module 232 through the third output port 54 .

[0114] In some possible implementations, when the digital signal is a first digital signal, the coupler 213 divides the first digital signal into a first sub-digital signal, a second sub-digital signal, and a third sub-digital signal according to a first preset ratio;

[0115] The first sub-digital signal is transmitted to the low-power amplification module 22 through the first output port 52;

[0116] The second sub-digital signal is transmitted to the first high-power amplification module 231 through the second output port 53 , and the third sub-digital signal is transmitted to the second high-power amplification module 232 through the third output port 54 ;

[0117] The second sub-digital signal and the third sub-digital signal enter the low-power amplification module 22 through the first high-power amplification module 231 and the second high-power amplification reflection.

[0118] For example, see Figure 6a , Figure 6a This is a schematic diagram of a digital signal transmission path provided by an embodiment of the present application. Figure 6aAs shown, for a digital signal with power less than a preset value (which can be considered a first digital signal), the coupler 213 can split the first digital signal into a first sub-digital signal, a second sub-digital signal, and a third sub-digital signal according to a first preset ratio, and transmit the first sub-digital signal to the low-power amplification module 22 through the first output port 52, transmit the second sub-digital signal to the first high-power amplification module 231 through the second output port 53, and transmit the third sub-digital signal to the second high-power amplification module 232 through the third output port 54. Since lower-power digital signals (such as the second and third sub-digital signals) experience impedance mismatch with the circuits of the high-power amplification modules, the second and third sub-digital signals are reflected back to the input port 51 by the first and second high-power amplification modules 231 and 232. After multiple reflections, the first digital signal is fully reflected through the first output port 52 and enters the low-power amplification module 22.

[0119] In some possible implementations, when the digital signal is the second digital signal, the coupler 213 divides the second digital signal into a fourth sub-digital signal and a fifth sub-digital signal according to a second preset ratio;

[0120] The fourth sub-digital signal is transmitted to the first high-power amplification module 231 through the second output port 53 , and the fifth sub-digital signal is transmitted to the second high-power amplification module 232 through the third output port 54 .

[0121] Among them, the low-power amplifier module 22 may include one or more low-power amplifier circuits; similarly, the first high-power amplifier module 231 may include one or more high-power amplifier circuits, and the second high-power amplifier module 232 may include one or more high-power amplifier circuits.

[0122] For example, see Figure 6b , Figure 6b This is another schematic diagram of a digital signal transmission path provided by an embodiment of the present application. Figure 6b As shown, for a digital signal having a power greater than or equal to a preset value (which can be considered as the second digital signal), the coupler 213 can divide the second digital signal into a fourth sub-digital signal and a fifth digital signal according to a second preset ratio, and transmit the fourth sub-digital signal to the first high-power amplification module 231 through the second output port 53, and transmit the fifth sub-digital signal to the second high-power amplification module 232 through the third output port 54. It should be noted that the first preset ratio and the second preset ratio are set by technicians based on actual conditions and are not limited in this application.

[0123] For example, see Figure 7 , Figure 7This is a graph showing the amplification efficiency of another digital power amplifier provided in an embodiment of the present application.

[0124] like Figure 7 As shown, curve 701 is the corresponding amplification efficiency curve when the power distribution module 21 is a coupler 213, and the power value corresponding to point P3 can be considered as the above-mentioned preset value; point P2 can represent the saturation power point of the high-power amplification module, that is, the high-power amplification module can only effectively amplify digital signals whose power is less than or equal to the power value corresponding to point P2.

[0125] For other possible implementations, see Figure 8 , Figure 8 This is a schematic diagram of another digital power amplifier for reducing the peak-to-average ratio of a signal provided in an embodiment of the present application. Figure 8 As shown, when the power distribution module 21 is a coupler 213, the low-power amplification module 22 may include a first low-power amplification module 221 and a second low-power amplification module 222. For example, for a digital signal with a power less than a preset value (which can be considered as a first digital signal), the coupler 213 can divide the first digital signal into a sixth sub-digital signal, a seventh sub-digital signal, and an eighth sub-digital signal according to a third preset ratio, and transmit the sixth sub-digital signal to the first low-power amplification module 221, the seventh sub-digital signal to the second low-power amplification module 222, and the eighth sub-digital signal to the high-power amplification module 23. In this case, since the digital signal with lower power (such as the eighth sub-digital signal) will have an impedance mismatch with the circuit of the high-power amplification module, the eighth sub-digital signal will be reflected back to the input port 51 by the high-power amplification module 23. After multiple reflections, all the first digital signals will enter the first low-power amplification module 221 and the second low-power amplification module 222 respectively. It should be noted that the third preset ratio is set by technicians according to actual conditions and is not limited by this application.

[0126] Furthermore, for a digital signal whose power is greater than or equal to a preset value (the digital signal can be considered as a second digital signal), the coupler 213 transmits the second digital signal to the high power amplification module 23 .

[0127] Among them, the first low-power amplification module 221 may include one or more low-power amplification circuits, and the second low-power amplification module 222 may include one or more low-power amplification circuits; similarly, the high-power amplification module 23 may include one or more high-power amplification circuits.

[0128] See Figure 9 , Figure 9 A flowchart of a method for reducing the peak-to-average ratio of a signal based on a digital power amplifier is provided in an embodiment of the present application.

[0129] like Figure 9 As shown, the method may include the following steps:

[0130] S901: Receive a digital signal through a power distribution module.

[0131] The digital signal includes a first digital signal and a second digital signal. Specifically, the first digital signal is a digital signal whose power is less than a preset value, and the second digital signal is a digital signal whose power is greater than or equal to the preset value.

[0132] It should be noted that the method of the embodiment of the present application is applied to Figure 2 、 Figure 3 as well as Figure 5 The digital power amplifier 20 in the corresponding embodiment can be applied to a terminal device 30 .

[0133] Among them, see Figure 10 , Figure 10 This is a schematic diagram of the structure of a terminal device provided in an embodiment of the present application. Figure 10 As shown, the terminal device 30 may include a digital power amplifier 20, a signal generating module 61, and a transmitting antenna 62. Specifically, the digital power amplifier 20 is coupled to the signal generating module 61 and the transmitting antenna 62. The digital power amplifier 20 can generate an output signal after amplifying the digital signal generated by the signal generating module 61, and transmit the output signal to the transmitting antenna 62. The transmitting antenna 62 can send the output signal to the target terminal, thereby enabling communication between the terminal device 30 and the target terminal.

[0134] S902: Transmit the first digital signal to the low-power amplification module through the power distribution module, and generate a first analog signal through the low-power amplification module.

[0135] S903: Transmit the second digital signal to the high power amplification module through the power distribution module, and generate a second analog signal through the high power amplification module.

[0136] In some possible implementations, the digital power amplifier 20 may further generate an output signal based on the first analog signal and the second analog signal through the power combining module 24 , and transmit the output signal to the transmitting antenna through the power combining module 24 .

[0137] In some possible implementations, the digital power amplifier 20 can utilize a power determination module 211 and a switch 212 to achieve the purpose of transmitting digital signals of different powers to corresponding amplification modules. Specifically, the power determination module 211 can be used to determine the power value of the digital signal received by the digital power amplifier and determine whether the power value is greater than a preset value. Furthermore, when the power of the digital signal is less than the preset value (the digital signal can be considered to be a first digital signal), the power determination module 211 can generate and send a first control signal to the switch 212. The switch 212 can, based on the first control signal, conduct a first path between the signal input circuit and the low-power amplification module 22, thereby achieving the purpose of transmitting the first digital signal to the low-power amplification module 22. Furthermore, when the power of the digital signal is greater than or equal to the preset value (the digital signal can be considered to be a second digital signal), the power determination module 211 can generate and send a second control signal to the switch 212. The switch 212 can, based on the second control signal, conduct a second path between the signal input circuit and the high-power amplification module 23, thereby achieving the purpose of transmitting the second digital signal to the high-power amplification module 23.

[0138] In some other possible implementations, the digital power amplifier 20 can use the coupler 213 to achieve the purpose of transmitting digital signals of different powers to corresponding amplification modules. Figure 5 In the embodiment thereof, the coupler 213 includes an input port 51, a first output port 52, a second output port 53, and a third output port 54. The input port 51 of the coupler 213 can be equivalent to the input port of the digital power amplifier 20, and the input port 51 can be used to receive the digital signal generated by the terminal device 30; the first output port 52 is coupled to the low-power amplifier module 22, and the second output port 53 and the third output port 54 are coupled to the high-power amplifier module 23. It should be noted that, in combination with Figure 5 In this embodiment, the high power amplification module 23 may include a first high power amplification module 231 and a second high power amplification module 232. Furthermore, the second output port 53 is coupled to the first high power amplification module 231, and the third output port 54 is coupled to the second high power amplification module 232.

[0139] The coupler 213 can transmit the digital signal to different amplification modules according to a preset ratio. For example, for a digital signal with a power less than a preset value (which can be considered as a first digital signal), the coupler 213 can divide the first digital signal into a first sub-digital signal, a second sub-digital signal, and a third sub-digital signal according to a first preset ratio, and transmit the first sub-digital signal to the low-power amplification module 22, the second sub-digital signal to the first high-power amplification module 231, and the third sub-digital signal to the second high-power amplification module 232. Since the low-power digital signals (such as the second sub-digital signal and the third sub-digital signal) will have an impedance mismatch with the circuit of the high-power amplification module, the second sub-digital signal and the third sub-digital signal will be reflected back to the input port 51 by the first high-power amplification module 231 and the second high-power amplification module 232. After multiple reflections, the first digital signal will enter the low-power amplification module 22 in its entirety.

[0140] Furthermore, for a digital signal having a power greater than or equal to a preset value (this digital signal can be considered to be a second digital signal), the coupler 213 can divide the second digital signal into a fourth sub-digital signal and a fifth digital signal according to a second preset ratio, and transmit the fourth sub-digital signal to the first high-power amplification module 231, and transmit the fifth sub-digital signal to the second high-power amplification module 232. It should be noted that the first preset ratio and the second preset ratio are set by technicians based on actual conditions and are not limited herein.

[0141] It can be seen that the method of the embodiment of the present application can select different signal amplification methods based on the power of the digital signal. Specifically, the low-power digital signal is amplified by the CMOS complementary metal oxide semiconductor amplifier module, which helps to improve the output power of the low-power input digital signal and reduce the peak-to-average ratio of the output signal, thereby improving the communication quality of the terminal device.

[0142] See Figure 11 , Figure 11 This is a schematic diagram of the hardware structure of another terminal device provided in an embodiment of the present application. The terminal device 30 is used to execute the image recommendation method provided in the above method embodiment.

[0143] The terminal device 30 may include a processor 101, a memory 102, a wireless communication module 103, a mobile communication module 104, an antenna 103A, an antenna 104A, a power switch 105, a sensor module 106, a focus motor 107, a camera 108, a display screen 109, and the like. The sensor module 106 may include a gyroscope sensor 106A, an acceleration sensor 106B, an ambient light sensor 106C, an image sensor 106D, a distance sensor 106E, and the like. The wireless communication module 103 may include a WLAN communication module, a Bluetooth communication module, and the like. These multiple components may transmit data via a bus.

[0144] The processor 101 may include one or more processing units. For example, the processor 101 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). The different processing units may be independent devices or integrated into one or more processors.

[0145] The memory 102 can be used to store computer executable program code, which can include instructions. The processor 101 executes various functional applications and data processing of the terminal device 30 by running the instructions stored in the memory 102. The memory 102 can include a program storage area and a data storage area. In a specific implementation, the memory 102 can include a high-speed random access memory and can also include a non-volatile memory, such as one or more disk storage devices, flash memory devices, or other non-volatile solid-state storage devices.

[0146] The wireless communication function of the terminal device 30 can be implemented through the antenna 103A, the antenna 104A, the mobile communication module 104, the wireless communication module 103, the modem processor and the baseband processor.

[0147] Antenna 103A and antenna 104A can be used to transmit and receive electromagnetic wave signals. Each antenna in terminal device 30 can be used to cover a single or multiple communication frequency bands. Different antennas can also be reused to improve antenna utilization.

[0148] The mobile communication module 104 can provide solutions for wireless communications including 2G / 3G / 4G / 5G, etc., applied to the terminal device 30. The mobile communication module 104 may include at least one filter, a switch, a power amplifier, a low noise amplifier (LNA), etc. The mobile communication module 104 can receive electromagnetic waves through the antenna 104A, and filter, amplify, and process the received electromagnetic waves, and transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 104 can also amplify the signal modulated by the modulation and demodulation processor, and convert it into electromagnetic waves for radiation through the antenna 104A. Furthermore, the above-mentioned digital power amplifier 20 can be set in the mobile communication module 104 to realize mobile communication between the terminal device 30 and the target terminal.

[0149] The modem processor may include a modulator and a demodulator. The modulator is used to modulate the low-frequency baseband signal to be transmitted into a medium- or high-frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. The demodulator then transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After processing by the baseband processor, the low-frequency baseband signal is passed to the application processor. The application processor outputs audio signals through an audio device or displays images or videos on the display screen 109.

[0150] The wireless communication module 103 can provide wireless communication solutions including wireless local area networks (WLAN), Bluetooth (BT), global navigation satellite system (GNSS), frequency modulation (FM), near field communication (NFC), infrared (IR), etc. applied to the terminal device 30. The wireless communication module 103 can be one or more devices integrating at least one communication processing module. The wireless communication module 103 receives electromagnetic waves via the antenna 103A, frequency modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 101. The wireless communication module 103 can also receive the signal to be sent from the processor 101, frequency modulate it, amplify it, and convert it into electromagnetic waves for radiation through the antenna 103A. Furthermore, the wireless communication module 103 can also be provided with the above-mentioned digital power amplifier 20 to realize wireless communication between the terminal device 30 and the target terminal.

[0151] Optionally, the antenna 103A and the antenna 104A may be considered as Figure 10 and the transmitting antenna 62 in its related embodiments.

[0152] The power switch 105 may be used to control the supply of power to the terminal device 30 .

[0153] The gyroscope sensor 106A can be used to determine the motion posture of the terminal device 30. In some embodiments, the angular velocity of the terminal device 30 around three axes (i.e., x, y, and z axes) can be determined by the gyroscope sensor 106A. The gyroscope sensor 106A can be used for anti-shake shooting. For example, when the shutter is pressed, the gyroscope sensor 106A detects the angle of the terminal device 30 shaking, calculates the distance that the lens module needs to compensate based on the angle, and allows the lens to offset the shaking of the terminal device 30 through reverse movement to achieve anti-shake. The gyroscope sensor 106A can also be used for navigation and somatosensory game scenes.

[0154] The accelerometer 106B can detect the magnitude of acceleration of the terminal device 30 in all directions (generally three axes). When the terminal device 30 is stationary, it can detect the magnitude and direction of gravity. It can also be used to identify the user's terminal posture. For example, the accelerometer 106B can be used in applications such as landscape and portrait screen switching and pedometers.

[0155] The ambient light sensor 106C is used to sense the brightness of the ambient light. The terminal device 30 can adaptively adjust the brightness of the display screen 109 based on the sensed ambient light brightness. The ambient light sensor 106C can also be used to automatically adjust the white balance when taking pictures.

[0156] Image sensor 106D, also known as a photosensitive element, utilizes the photoelectric conversion function of a photoelectric device to convert the light image on the photosensitive surface into an electrical signal proportional to the light image. The image sensor can be a charge coupled device (CCD) sensor or a complementary metal oxide semiconductor (CMOS) sensor.

[0157] The distance sensor 106E can be used to measure distance. The terminal device 30 can measure distance using infrared or laser. In some shooting scenarios, the terminal device 30 can use the distance sensor 106E to measure distance to achieve fast focusing.

[0158] The focus motor 107 can be used for fast focusing. The terminal device 30 can control the movement of the lens through the focus motor 107 to achieve automatic focusing.

[0159] The terminal device 30 can realize the shooting function through the ISP, camera 108, video codec, GPU, display screen 109 and application processor.

[0160] The ISP processes data fed back by camera 108. For example, when taking a photo, the shutter is opened, and light is transmitted through the lens to the camera's photosensitive element. The light signal is converted into an electrical signal, which is then passed to the ISP for processing and transformed into a visible image. The ISP can also perform algorithmic optimization for image noise and brightness. It can also optimize parameters such as exposure and color temperature of the captured scene. In some embodiments, the ISP can be located within camera 108.

[0161] The camera 108 can be used to capture still images or videos. The lens generates an optical image of an object and projects it onto the image sensor. The image sensor converts the optical signal into an electrical signal, which is then transmitted to the ISP for conversion into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in a standard format such as RGB or YUV. In some embodiments, the terminal device 30 may include one or N cameras 108, where N is a positive integer greater than one.

[0162] Video codecs are used to compress or decompress digital images. The terminal device 30 may support one or more video codecs. In this way, the terminal device 30 can open or save pictures or videos in multiple encoding formats.

[0163] The terminal device 30 can implement display functions through a GPU, display screen 109, and an application processor. The GPU is a microprocessor for image processing that connects the display screen 109 and the application processor. The GPU is used to perform mathematical and geometric calculations for graphics rendering. The processor 101 may include one or more GPUs that execute program instructions to generate or change display information.

[0164] The display screen 109 is used to display images, videos, etc. The display screen 109 includes a display panel. The display panel can be a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a MiniLED, a MicroLED, a Micro-oLed, or a quantum dot light-emitting diode (QLED). In some embodiments, the terminal device 30 may include one or N display screens 109, where N is a positive integer greater than one.

[0165] It should be understood that the structure illustrated in the embodiment of the present invention does not constitute a specific limitation on the terminal device 30. In other embodiments of the present application, the terminal device 30 may include more or fewer components than shown, or may combine or separate certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0166] The operations performed by each component in the terminal device 30 may be specifically referred to the relevant description of the method embodiment above, and will not be elaborated here.

[0167] The software system of the terminal device 30 can adopt a layered architecture, an event-driven architecture, a micro-kernel architecture, a micro-service architecture, or a cloud architecture. In the embodiment of the present application, a mobile operating system with a layered architecture is used as an example to illustrate the software structure of the terminal device 30.

[0168] It should be understood that each step in the above method embodiment can be completed by hardware integrated logic circuits in a processor or by software instructions. The method steps disclosed in the embodiments of the present application can be directly embodied as being executed by a hardware processor, or by a combination of hardware and software modules in a processor.

[0169] The present application also provides a user terminal, which may include: a memory and a processor. The memory may be used to store a computer program; the processor may be used to call the computer program in the memory to enable the user terminal to execute the method executed on the user terminal side in any of the above embodiments.

[0170] The present application also provides a user terminal, which may include: a memory and a processor. The memory may be used to store a computer program; the processor may be used to call the computer program in the memory to enable the user terminal to execute the method executed on the user terminal side in any of the above embodiments.

[0171] The present application also provides a chip system, which includes at least one processor for implementing the functions involved in the user terminal side in any of the above embodiments.

[0172] In one possible design, the chip system further includes a memory, which is used to store program instructions and data, and the memory is located inside or outside the processor.

[0173] The chip system can be composed of chips, or can include chips and other discrete devices.

[0174] Optionally, there may be one or more processors in the chip system. The processor may be implemented in hardware or software. When implemented in hardware, the processor may be a logic circuit, an integrated circuit, etc. When implemented in software, the processor may be a general-purpose processor implemented by reading software code stored in a memory.

[0175] Optionally, the memory in the chip system may be one or more. The memory may be integrated with the processor or may be provided separately from the processor, which is not limited in the embodiments of the present application. For example, the memory may be a non-transient processor, such as a read-only memory (ROM), which may be integrated with the processor on the same chip or provided on different chips. The embodiments of the present application do not specifically limit the type of memory or the configuration of the memory and the processor.

[0176] Exemplarily, the chip system can be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD) or other integrated chips.

[0177] The present application also provides a computer program product, which includes: a computer program (also referred to as code, or instructions), which, when executed, enables a computer to execute the method executed by the user terminal side in any of the above embodiments.

[0178] The present application also provides a computer-readable storage medium storing a computer program (also referred to as code or instruction). When the computer program is executed, the computer executes the method executed by the user terminal side in any of the above embodiments.

[0179] The various implementation modes of this application can be combined arbitrarily to achieve different technical effects.

[0180] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described herein are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated therein. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

[0181] Those skilled in the art will appreciate that all or part of the process steps in the above-described method embodiments can be implemented by a computer program instructing the relevant hardware. The program can be stored in a computer-readable storage medium, and when executed, the program can include the process steps in the above-described method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM or random access memory (RAM), magnetic disks, or optical disks.

[0182] In short, the above description is only an embodiment of the technical solution of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent replacements, improvements, etc. made based on the disclosure of this application should be included in the scope of protection of this application.

Claims

1. A digital power amplifier for reducing a signal peak-to-average ratio, characterized in that: The digital power amplifier includes: a power distribution module, a low power amplification module and a high power amplification module; The power distribution module is coupled with the low power amplification module and the high power amplification module: Used to receive a digital signal, wherein the digital signal includes a first digital signal and a second digital signal; used to transmit the first digital signal to the low-power amplification module, where the first digital signal is a digital signal with power less than a preset value; used to transmit the second digital signal to the high-power amplification module, where the second digital signal is a digital signal with a power greater than or equal to the preset value; The low-power amplification module is connected in parallel with the high-power amplification module, and is configured to perform a first amplification process on the first digital signal to generate a first analog signal; The high-power amplification module is used to perform a second amplification process on the second digital signal to generate a second analog signal.

2. The digital power amplifier according to claim 1, wherein: The low-power amplifier module is a CMOS complementary metal oxide semiconductor amplifier module; The high power amplifier module is a switch type power amplifier module.

3. The digital power amplifier according to claim 2, wherein: The power distribution module includes a power judgment module and a switch; The power judgment module is coupled to the switch, and is used to receive the digital signal, generate power based on the digital signal, and send a control signal to the switch; the control signal is used to control the switch to conduct a first path between the power distribution module and the low-power amplification module, or to control the switch to conduct a second path between the power distribution module and the high-power amplification module.

4. The digital power amplifier according to claim 3, wherein: The power determination module is configured to generate and send a first control signal to the switch when the digital signal is the first digital signal; The first control signal is used to control the switch to conduct the first path, and the first path is used to transmit the first digital signal to the low-power amplification module; The power determination module is further configured to generate and send a second control signal to the switch when the digital signal is the second digital signal; The second control signal is used to control the switch to turn on the second path, and the second path is used to transmit the second digital signal to the high power amplification module.

5. The digital power amplifier according to claim 2, wherein: The power distribution module includes a coupler, the coupler including an input port and a first output port; The coupler receives the digital signal through the input port and is coupled to the low-power amplification module through the first output port.

6. The digital power amplifier according to claim 5, characterized in that: The high power amplification module includes a first high power amplification module and a second high power amplification module; The coupler further includes a second output port and a third output port; The coupler is coupled to the first high-power amplification module through the second output port, and is coupled to the second high-power amplification module through the third output port.

7. The digital power amplifier according to claim 6, wherein: In the case where the digital signal is a first digital signal, the coupler divides the first digital signal into a first sub-digital signal, a second sub-digital signal and a third sub-digital signal according to a first preset ratio; The first sub-digital signal is transmitted to the low-power amplification module through the first output port; The second sub-digital signal is transmitted to the first high-power amplification module through the second output port, and the third sub-digital signal is transmitted to the second high-power amplification module through the third output port; The second sub-digital signal and the third sub-digital signal are reflected into the low-power amplification module through the first high-power amplification module and the second high-power amplification module.

8. The digital power amplifier according to claim 6 or 7, characterized in that: In the case where the digital signal is a second digital signal, the coupler divides the second digital signal into a fourth sub-digital signal and a fifth sub-digital signal according to a second preset ratio; The fourth sub-digital signal is transmitted to the first high-power amplification module through the second output port, and the fifth sub-digital signal is transmitted to the second high-power amplification module through the third output port.

9. The digital power amplifier according to any one of claims 1 to 8, characterized in that: The digital power amplifier further includes a power synthesis module, and the terminal device includes a transmitting antenna; The power synthesis module is coupled with the low-power amplification module and the high-power amplification module, and is used to generate an output signal based on the first analog signal generated by the low-power amplification module and the second analog signal generated by the high-power amplification module, and transmit the output signal to the transmitting antenna. The output signal is transmitted to the target terminal via the transmitting antenna.

10. The digital power amplifier according to claim 9, wherein: The power synthesis module is also used to perform harmonic control processing on the first analog signal and the second analog signal before generating the output signal based on the first analog signal generated by the low-power amplification module and the second analog signal generated by the high-power amplification module, so as to ensure the subsequent communication quality of the output signal.

11. A terminal device, characterized in that: The terminal device comprises the digital power amplifier, signal generating module and transmitting antenna according to any one of claims 1 to 10; The signal generating module is coupled to the digital power amplifier and is used to generate a digital signal and transmit the digital signal to the digital power amplifier; The transmitting antenna is coupled to the digital power amplifier, and is configured to receive an output signal sent by the digital power amplifier and send the output signal to a target terminal.

12. A method for reducing the peak-to-average ratio of a signal based on a digital power amplifier, characterized in that: Applied to a digital power amplifier, the digital power amplifier includes a power distribution module, a low-power amplification module, and a high-power amplification module, the method includes: receiving a digital signal through the power distribution module, wherein the digital signal includes a first digital signal and a second digital signal; Transmitting the first digital signal to the low-power amplification module through the power distribution module, and generating a first analog signal through the low-power amplification module, wherein the first digital signal is a digital signal with power less than a preset value; The second digital signal is transmitted to the high power amplification module through the power distribution module, and a second analog signal is generated by the high power amplification module. The second digital signal is a digital signal with power greater than or equal to the preset value.

13. The method according to claim 12, characterized in that The digital power amplifier further includes a power synthesis module; and the method further includes: An output signal is generated based on the first analog signal and the second analog signal by the power synthesis module, and the output signal is transmitted to a transmitting antenna by the power synthesis module.

14. A terminal device, characterized in that: The terminal device includes one or more processors and one or more memories; wherein the one or more memories are coupled to the one or more processors, and the one or more memories are used to store computer program code, and the computer program code includes computer instructions, and when the one or more processors execute the computer instructions, the method according to claim 12 or 13 is executed.

15. A computer-readable storage medium comprising instructions, characterized in that: When the instruction is executed on the terminal device, the method according to claim 12 or 13 is executed.

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