Signal processing method, chip and electronic equipment

Abstract

The invention relates to the field of signal processing, in particular to a signal processing method, a chip and electronic equipment, the electronic equipment comprises at least one subsystem, and the method comprises the following steps: inputting a first to-be-processed signal into the at least one subsystem according to a preset sequence to obtain a first output signal; obtaining a total delay time based on the delay time of the at least one subsystem; performing delay processing on the first to-be-processed signal based on the total delay time to obtain a second to-be-processed signal, wherein the second to-be-processed signal comprises a plurality of sampling points; zero input detection is carried out on the second to-be-processed signal; judging amplitudes of a plurality of sampling points of the second to-be-processed signal based on the zero input detection result; and if the amplitudes of the plurality of sampling points of the second to-be-processed signal are smaller than the first amplitude threshold and the number of the plurality of sampling points is greater than or equal to the first threshold, reducing the amplitude of the first output signal to obtain a final output signal. Therefore, the system stability is improved, limit cycle processing is performed only once, and the limit cycle processing efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of signal processing, and in particular to a signal processing method, chip, and electronic device. Background Art

[0002] An infinite impulse response (IIR) filter is a digital filter, or an IIR discrete-time system. Ideally, an IIR filter uses infinite precision (i.e., floating-point numbers). Its output is a weighted sum of the current input signal and the previous output signal. Therefore, when the input signal is zero, the output signal is also zero. This means that the filter will not self-oscillate in the absence of an input signal, demonstrating its stability.

[0003] In practical applications, to reduce system resource consumption or adapt to specific hardware environments, IIR filters convert floating-point numbers to fixed-point numbers before using finite register length operations to generate the output signal. However, when the input signal is continuously zero, finite register length operations can produce rounding errors. These errors can cause the IIR filter to enter a non-zero stable state, known as a limit cycle. In this limit cycle state, the output signal continuously oscillates within a certain range or becomes a DC signal, rather than decaying to zero, affecting the stability of the IIR filter.

[0004] In addition, some digital signal systems include multiple IIR filters. If the input signal is zero, each IIR filter needs to be subjected to zero input detection and limit cycle processing to improve the stability of the IIR filter, which results in relatively low processing efficiency. Summary of the Invention

[0005] The illustrative embodiments of the present application provide a signal processing method, a chip, and an electronic device.

[0006] In a first aspect, the present application provides a signal processing method, which is applied to an electronic device, wherein the electronic device includes at least one subsystem; the method includes: inputting a first signal to be processed into at least one subsystem in a preset order to obtain a first output signal; obtaining a total delay time based on the delay time of at least one subsystem; performing delay processing on the first signal to be processed based on the total delay time to obtain a second signal to be processed, wherein the second signal to be processed includes multiple sampling points; performing zero input detection on the second signal to be processed; based on the zero input detection result, judging the amplitude of multiple sampling points of the second signal to be processed; if the amplitude of multiple sampling points of the second signal to be processed is less than a first amplitude threshold, and the number of multiple sampling points is greater than or equal to the first threshold, reducing the amplitude of the first output signal to obtain a final output signal.

[0007] It is understood that the first signal to be processed may refer to the input signal x[n] of the digital signal processing system mentioned in the embodiments of the present application, and the first output signal may refer to y1[n] mentioned in the embodiments of the present application. In addition, the first signal to be processed may refer to the input signal of the digital signal processing system, and the second signal to be processed may refer to the signal after the first signal to be processed is delayed by the total delay time in the digital signal processing system.

[0008] It can be understood that the signal processing method provided in the embodiments of the present application can be executed by an electronic device or a digital signal processing system in an electronic device, and is not specifically limited here.

[0009] It can be understood that the first subsystem may refer to the second-order IIR filter mentioned in the embodiment of the present application, and the second subsystem may refer to the pure delay system mentioned in the embodiment of the present application, and no limitation is made here.

[0010] Based on the above method, a digital signal processing system including at least one subsystem can determine that the second signal to be processed is a zero-input signal by detecting that the number of sampling points in the second signal to be processed whose amplitudes are less than a first amplitude threshold is greater than or equal to the first threshold. Furthermore, based on the determination that the second signal to be processed is a zero-input signal, limit cycle processing can be directly performed on the first output signal. This improves the stability of the digital signal processing system and only requires a single limit cycle processing step, significantly increasing the efficiency of limit cycle processing.

[0011] In a possible implementation of the first aspect above, based on the zero-input detection result, the amplitudes of multiple sampling points of the second signal to be processed are judged, including: if the amplitudes of the multiple sampling points of the second signal to be processed are greater than or equal to a first amplitude threshold, increasing the amplitude of the first output signal to obtain a final output signal.

[0012] Based on the above method, when the first output signal is in a limit cycle state, the amplitude of the second output signal is reduced by reducing the gain of the second output signal to improve the limit cycle state of the second output signal, thereby improving the stability of the system.

[0013] In a possible implementation of the first aspect above, the method also includes: at least one subsystem also includes a first subsystem and a second subsystem; the method also includes: inputting the first signal to be processed into at least one subsystem in a preset order to obtain a first output signal output by the first subsystem; obtaining a total delay time based on the delay time of at least one subsystem; performing delay processing on the first signal to be processed based on the total delay time to obtain a second signal to be processed; performing zero input detection on the second signal to be processed; obtaining a second output signal output by the second subsystem based on the first output signal output by the first subsystem; judging the amplitude of multiple sampling points of the second signal to be processed based on the zero input detection result; if the amplitude of the multiple sampling points of the second signal to be processed is less than the first amplitude threshold, and the number of the multiple sampling points is greater than or equal to the first threshold, reducing the amplitude of the second output signal to obtain the final output signal.

[0014] It can be understood that the second output signal may refer to y2[n] mentioned in the embodiment of the present application.

[0015] In a possible implementation of the first aspect, at least one subsystem is an infinite impulse response subsystem; or at least one subsystem includes an infinite impulse response subsystem and a non-infinite impulse response subsystem.

[0016] Based on this, when the second signal to be processed is a zero input signal, for a digital signal processing system including different types of subsystems, the signal processing method provided in the embodiment of the present application can be used to efficiently process the output signal limit cycle problem caused by the zero input signal to improve system stability.

[0017] In a possible implementation of the first aspect above, a second output signal output by the second subsystem is obtained based on the first output signal output by the first subsystem, including: processing the first signal to be processed based on the first differential equation of the first subsystem to obtain the first output signal, and sending the first output signal to the second subsystem; processing the first output signal based on the second differential equation of the second subsystem to obtain the second output signal.

[0018] It can be understood that the first differential equation may refer to formula (3) mentioned in the embodiment of the present application, and the second differential equation may refer to formula (4) mentioned in the embodiment of the present application.

[0019] It can be understood that in other embodiments of the present application, the first differential equation and the second differential equation can also be expressed in other forms, which are not limited here.

[0020] In a possible implementation of the first aspect above, the first output signal is processed based on the second differential equation of the second subsystem to obtain the second output signal, including: determining the delay time of the second subsystem, and obtaining the second output signal based on the delay time of the second subsystem, the first output signal and the second differential equation.

[0021] It can be understood that if the second subsystem is a pure delay system, the delay may affect the phase and timing of the second output signal, thereby affecting the accuracy of signal processing. Therefore, by considering the delay time of the second subsystem, the second differential equation can be used more accurately to calculate the second output signal, that is, the second output signal has higher accuracy.

[0022] In a possible implementation of the first aspect above, if the amplitudes of multiple sampling points of the second signal to be processed are less than a first amplitude threshold, and the number of the multiple sampling points is greater than or equal to the first threshold, reducing the amplitude of the second output signal to obtain a final output signal includes: if the amplitudes of multiple sampling points of the second signal to be processed are less than the first amplitude threshold, and the number of the multiple sampling points is greater than or equal to the first threshold, determining that the second output signal is in a limit cycle state; and reducing the gain of the second output signal to reduce the amplitude of the second output signal to obtain the final output signal.

[0023] Based on the above method, when the second output signal is in a limit cycle state, the amplitude of the second output signal is reduced by reducing the gain of the second output signal to improve the limit cycle state of the second output signal, thereby improving the stability of the system.

[0024] In a possible implementation of the first aspect above, based on the zero-input detection result, the amplitudes of multiple sampling points of the second signal to be processed are judged, including: if the amplitudes of the multiple sampling points of the second signal to be processed are greater than or equal to a first amplitude threshold, determining that the second output signal is not in a limit cycle state; and increasing the gain of the second output signal to increase the amplitude of the second output signal to obtain a final output signal.

[0025] Based on the above method, when the second output signal is not in a limit cycle state, the amplitude of the second output signal can be increased by increasing the gain of the second output signal, so that when the second signal to be processed is not zero, the amplitude of the second output signal is effectively amplified to improve the visibility of the second output signal and the stability of the system.

[0026] In a possible implementation of the first aspect above, at least one subsystem also includes a third subsystem; the method also includes: obtaining a third output signal output by the third subsystem based on the second output signal output by the second subsystem; performing zero-input detection on the second signal to be processed; based on the zero-input detection result, judging the amplitudes of multiple sampling points of the second signal to be processed; if the amplitudes of the multiple sampling points of the second signal to be processed are less than a first amplitude threshold, and the number of the multiple sampling points is greater than or equal to the first threshold, reducing the amplitude of the third output signal to obtain a final output signal.

[0027] It can be understood that the third subsystem may refer to the 64-order FIR filter mentioned in the embodiment of the present application, etc., and is not limited here.

[0028] In a possible implementation of the first aspect above, the first subsystem is an IIR filter, the second subsystem is a pure delay system, and the third subsystem is an FIR filter.

[0029] It can be understood that the first subsystem, the second subsystem and the third subsystem can be any one of the IIR filters, pure delay systems and FIR filters mentioned above, and can also be other types of filters or delay systems, etc., which are not limited here.

[0030] In a second aspect, the present application provides a chip for executing the signal processing method provided by the first aspect and various possible implementations of the first aspect.

[0031] In a third aspect, the present application provides an electronic device, which includes the signal processing method in the above-mentioned first aspect and various possible implementations of the above-mentioned first aspect.

[0032] The beneficial effects of the second to third aspects mentioned above can be found in the relevant descriptions of the first aspect and various possible implementations of the first aspect, and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic flow chart of a signal processing method is shown;

[0034] Figure 2 A schematic diagram of input signal delay processing is shown;

[0035] Figure 3 A flow chart of another signal processing method is shown;

[0036] Figure 4 A schematic flow chart of zero input detection and limit cycle processing is shown. DETAILED DESCRIPTION

[0037] The illustrative embodiments of the present application include, but are not limited to, a signal processing method, a chip, and an electronic device.

[0038] The specific implementation process of the technical solution provided in the embodiments of the present application is described in detail below with reference to the accompanying drawings.

[0039] As mentioned above, in practical applications, to reduce resource consumption or adapt to specific hardware environments, IIR filters convert floating-point numbers to fixed-point numbers (i.e., from floating-point numbers to fixed-point numbers) before using finite register length operations to obtain the output signal. However, when the input signal is continuously zero, finite register length operations will produce rounding errors. These errors will cause the IIR filter to enter a non-zero stable state, namely the limit cycle state. In the limit cycle state, the output signal continues to oscillate or be DC within a certain range, rather than decaying to zero, which affects the stability of the IIR filter. In addition, some digital signal systems include multiple IIR filters, and each IIR filter requires zero input detection and limit cycle processing to improve the stability of the IIR filter, which is relatively inefficient.

[0040] In order to solve the above-mentioned problem of low processing efficiency, an embodiment of the present application provides a signal processing method, which is applied to an electronic device, and the electronic device includes at least one subsystem; the method includes: inputting a first signal to be processed into at least one subsystem in a preset order, and calculating a total delay time based on the delay time of at least one subsystem, wherein the at least one subsystem includes a first subsystem and a second subsystem; based on the first output signal output by the first subsystem, obtaining a second output signal output by the second subsystem; delay processing is performed on the first signal to be processed based on the total delay time to obtain a second signal to be processed; zero input detection is performed on the second signal to be processed; according to the zero input detection result, the number of sampling points with amplitudes less than a first amplitude threshold among multiple sampling points of the second signal to be processed is greater than or equal to the first threshold, and the amplitude of the second output signal is reduced to obtain a final output signal.

[0041] It can be understood that in the embodiment of the present application, the first signal to be processed may refer to the input signal of the digital signal processing system, and the second signal to be processed may refer to the signal after the first signal to be processed is delayed by the total delay time in the digital signal processing system.

[0042] It is understood that the electronic device may include a digital signal processing system, and the digital signal processing system may include at least one of the above subsystems. In addition, at least one of the at least one subsystem may be connected in series in sequence, which is not specifically limited here.

[0043] Based on the above method, a digital signal processing system including at least one subsystem can determine that the signal to be processed is a zero-input signal by detecting that the number of sampling points in a second signal to be processed whose amplitude is less than a first amplitude threshold is greater than or equal to the first threshold. Furthermore, based on the determination that the second signal to be processed is a zero-input signal, limit cycle processing can be directly performed on the second output signal of the second subsystem. This improves the stability of the digital signal processing system and only requires a single limit cycle processing step, significantly increasing the efficiency of limit cycle processing.

[0044] In some embodiments of the present application, at least one subsystem also includes a first subsystem and a second subsystem; the signal processing method may also include: inputting the first signal to be processed into at least one subsystem in a preset order to obtain a first output signal output by the first subsystem; obtaining a total delay time based on the delay time of at least one subsystem; performing delay processing on the first signal to be processed based on the total delay time to obtain a second signal to be processed; performing zero input detection on the second signal to be processed; obtaining a second output signal output by the second subsystem based on the first output signal output by the first subsystem; judging the amplitude of multiple sampling points of the second signal to be processed based on the zero input detection result; if the amplitude of the multiple sampling points of the second signal to be processed is less than the first amplitude threshold, and the number of the multiple sampling points is greater than or equal to the first threshold, reducing the amplitude of the second output signal to obtain the final output signal.

[0045] In some embodiments of the present application, at least one subsystem may be an infinite impulse response subsystem; or at least one subsystem may include an infinite impulse response subsystem and a non-infinite impulse response subsystem.

[0046] It is understood that an IIR subsystem may refer to a discrete-time system whose output signal depends not only on the current input signal but also on past input signals and past output signals. For example, an IIR system may include an IIR filter.

[0047] It is understood that a non-IIR system can refer to a system that does not have IIR characteristics, that is, the system's output depends only on the current input signal and past input signals, but not on past output signals. For example, a non-IIR system can include a pure delay system. A pure delay system refers to a system with a time delay. That is, after the input signal acts on the system, the output signal does not change immediately, but only begins to respond after a specific period of time. In a pure delay system, there is a fixed delay time between the input signal and the output signal, and this delay time does not depend on the specific characteristics of the input signal.

[0048] According to some embodiments of the present application, Figure 1The flow chart of a signal processing method is shown. The signal processing method can be executed by an electronic device or a digital signal processing system in the electronic device. Figure 1 As shown, the process of the signal processing method may include:

[0049] S101: Input a first signal to be processed into at least one subsystem according to a preset order to obtain a first output signal, and calculate a total delay time based on a delay time of the at least one subsystem.

[0050] In some embodiments of the present application, a first signal to be processed is input into at least one subsystem in a preset order, and a total delay time is calculated based on the delay time of the at least one subsystem. The first signal to be processed may be an input signal of a digital signal processing system. For example, the first signal to be processed may be an input signal x[n] of the digital signal processing system. The first signal to be processed may be input into at least one subsystem of the digital signal processing system in a preset order.

[0051] It is understood that in digital signal processing, a digital signal processing system processes signals based on discrete sampling points. Therefore, when the first signal to be processed is an analog signal, the digital signal processing system can sample the first signal to be processed at a certain sampling rate to obtain multiple sampling points of the first signal to be processed. That is, the first signal to be processed can include multiple sampling points (i.e., discrete points), and the amplitude value corresponding to each sampling point can be different. Therefore, analysis and processing of the first signal to be processed can be achieved based on the multiple sampling points in the first signal to be processed.

[0052] Furthermore, the total delay time is calculated based on the delay time of at least one subsystem. In some embodiments of the present application, since delay is an inherent property of each subsystem, the delay of each subsystem can be directly obtained and added together to obtain the total delay time T of the entire system. Assuming that there are currently N subsystems, and the delay of each subsystem is Ti, 1<=i<=N, the total delay time can be calculated with reference to formula (1).

[0053]

[0054] In formula (1), T is the total delay time, Ti can be the delay time corresponding to each subsystem, and ∑ is the summation symbol, which means that the total delay time T is obtained by summing all Ti items with i from 1 to N.

[0055] In some embodiments of the present application, N may be 2, that is, two subsystems (eg, a first subsystem and a second subsystem). Then, N=2 may be substituted into formula (1) to calculate the total delay time T.

[0056] It can be understood that the above example of N=2 and the digital signal processing system including the first subsystem and the second subsystem is only an exemplary description. In other embodiments, the digital signal processing system can also include more subsystems, such as a third subsystem, etc., and N can also be other corresponding values, which are not specifically limited here.

[0057] In some embodiments of the present application, the first output signal may refer to a signal output by the first subsystem, wherein the first subsystem may process the first signal to be processed based on its first differential equation to obtain the first output signal.

[0058] Specifically, after the digital signal processing system obtains the first signal to be processed x[n], it can process the first signal to be processed x[n] based on the first subsystem to obtain the first output signal y1[n].

[0059] It can be understood that the first subsystem can derive a corresponding first difference equation based on its transfer function and use the first difference equation to calculate the first output signal. The transfer function is a mathematical tool that describes the input-output relationship of a system, providing a theoretical framework for system analysis and design. The difference equation is used to implement the system's specific operations and calculations.

[0060] Specifically, the process of obtaining the first output signal y1[n] based on the transfer function of the first subsystem and the first differential equation is described by taking the first subsystem as a second-order IIR filter as an example. The transfer function of the first subsystem can refer to formula (2).

[0061]

[0062] In formula (2), H(z) is the transfer function of the second-order IIR filter, and z is the complex variable in the Z transform, which is used to convert the time domain signal to the Z domain. In digital signal processing, z is often used to represent the displacement operator of discrete-time signals. y(z) is the z transform of the output signal y[n], and x[z] is the z change of the input signal x[n]. Both x[n] and y[n] are time domain (discrete time) signals. By performing a z transform on x[n] and y[n], x[n] and y[n] can be converted from time domain (discrete time) signals to the Z domain (complex frequency domain). In addition, b0, b1, and b2 are feedforward coefficients. Feedforward coefficients refer to coefficients related to the current input signal and the past input signal in the transfer function or difference equation of the digital signal processing system. a0, a1, and a2 are feedback coefficients. Feedback coefficients refer to coefficients related to the current output signal and the past output signal in the transfer function or difference equation of the digital signal processing system.

[0063] Furthermore, the first subsystem can derive a corresponding first differential equation based on formula (2), and the first differential equation can refer to formula (3).

[0064] y1[n]=b0x[n]+b1x[n-1]+b2x[n-2]+a1y1[n-1]+a2y1[n-2] (3)

[0065] In formula (3), n is a discrete time index used to represent the position of the input signal in the time series. In digital signal processing, n usually starts from 0 or 1 and can be regarded as a sampling point of the current sample in the input signal. y1[n] represents the first output signal, x[n] represents the value corresponding to sampling point n in the input signal, and b0 represents the feedforward coefficient associated with x[n]. x[n-1] represents the value corresponding to sampling point n-1 in the input signal, and b1 represents the feedforward coefficient associated with x[n-1]. x[n-2] represents the value corresponding to sampling point n-2 in the input signal, and b2 represents the feedforward coefficient associated with x[n-2]. y[n-1] represents the value of the output signal corresponding to sampling point n-1, and a1 represents the feedback coefficient associated with y1[n-1]. y[n-2] represents the value of the output signal corresponding to sampling point n-2, and a2 represents the feedback coefficient associated with y1[n-2].

[0066] In this way, the first output signal y1[n] can be obtained based on the input signal x[n] and formula (3).

[0067] It can be understood that in other embodiments of the present application, the first differential equation can also be expressed in other forms, which are not limited here.

[0068] S102: Performing delay processing on the first signal to be processed based on the total delay time to obtain a second signal to be processed, wherein the second signal to be processed includes a plurality of sampling points.

[0069] In some embodiments of the present application, after obtaining the total delay time T, the first signal to be processed, i.e., X[n], can be delayed based on the total delay time T to obtain a second signal to be processed after delay processing, so that zero input detection can be performed on the second signal to be processed (i.e., the input signal after delay processing) subsequently.

[0070] It can be understood that by delaying the first signal to be processed, i.e., the input signal X[n], to obtain the second signal to be processed, it can be ensured that when performing zero input detection, the various parts of the second signal to be processed at different times can be correctly aligned, thereby improving the accuracy of zero input detection.

[0071] For example, Figure 2 A schematic diagram of input signal delay processing is shown. Figure 2 In the figure, the upper signal is the first signal to be processed, i.e., the input signal X[n]. Assuming that the total delay time T of the entire digital signal processing system is calculated to be Xms, the lower signal is a signal delayed by Xms, which can refer to the second signal to be processed.

[0072] S103: Perform zero input detection on the second signal to be processed.

[0073] In some embodiments of the present application, after obtaining the second signal to be processed, a zero input detection can be performed on the second signal to be processed. The process of performing zero input detection on the second signal to be processed can include: first, detecting whether the amplitudes of multiple sampling points in the second signal to be processed are less than a first amplitude threshold. Second, based on the presence of multiple sampling points in the second signal to be processed whose amplitudes are less than the first amplitude threshold, detecting whether the number of sampling points in the second signal to be processed whose amplitudes are less than the first amplitude threshold is greater than or equal to the first threshold.

[0074] It can be understood that the first amplitude threshold can be preset and is used to measure the parameter of the signal strength of the second signal to be processed. If it is detected that the amplitude of multiple sampling points in the second signal to be processed is less than the first amplitude threshold, it can be said that the signal is too weak. In the embodiment of the present application, such a signal can be regarded as a zero input signal. In addition, the first threshold can be preset and is used to measure the number of sampling points detected with an amplitude less than the first amplitude threshold. If the number of sampling points detected with an amplitude less than the first amplitude threshold is greater than or equal to the first threshold, it can be said that the amplitude of the consecutive sampling points in the second signal to be processed is zero, and the input signal can be determined to be a zero input signal.

[0075] Therefore, if it is determined that the number of sampling points in the second signal to be processed whose amplitudes are less than the first amplitude threshold is greater than or equal to the first threshold, it can be determined that the second signal to be processed is a zero input signal.

[0076] S104: Based on the zero-input detection result, the amplitudes of the plurality of sampling points of the second signal to be processed are judged.

[0077] In some embodiments of the present application, a zero-input detection result may be obtained based on the above S103 .

[0078] If, based on the zero input detection result, it is determined that the amplitudes of multiple sampling points of the second signal to be processed are less than the first amplitude threshold, and the number of the multiple sampling points is greater than or equal to the first threshold, then the second signal to be processed can be determined to be a zero input signal.

[0079] If it is determined based on the zero-input detection result that the amplitudes of the plurality of sampling points of the second signal to be processed are greater than or equal to the first amplitude threshold, it can be determined that the second signal to be processed is not a zero-input signal.

[0080] S105: If the amplitudes of the plurality of sampling points of the second signal to be processed are smaller than the first amplitude threshold, and the number of the plurality of sampling points is greater than or equal to the first threshold, reducing the amplitude of the first output signal.

[0081] In some embodiments of the present application, if the amplitude of multiple sampling points of the second signal to be processed is determined to be less than a first amplitude threshold based on the zero-input detection result, and the number of the multiple sampling points is greater than or equal to the first threshold, the second signal to be processed can be determined to be a zero-input signal, that is, the first output signal can be determined to be in a limit cycle state, and the gain of the first output signal can be reduced to reduce the amplitude of the first output signal. It is understood that this scenario corresponds to at least one subsystem including only one subsystem.

[0082] S106: If the amplitudes of the plurality of sampling points of the second signal to be processed are greater than or equal to the first amplitude threshold, increase the amplitude of the first output signal.

[0083] In other embodiments of the present application, based on the zero-input detection result, determining the amplitude of multiple sampling points of the second signal to be processed includes: if the amplitude of the multiple sampling points of the second signal to be processed is greater than or equal to a first amplitude threshold, increasing the amplitude of the first output signal to obtain a final output signal. It is understood that this scenario corresponds to at least one subsystem including only one subsystem.

[0084] S107: Obtain the final output signal.

[0085] It can be understood that the final output signal can be obtained based on the above S105 or S106.

[0086] Based on the above method, a digital signal processing system including one subsystem can determine that the signal to be processed is a zero-input signal by detecting that the number of sampling points in a second signal to be processed whose amplitude is less than a first amplitude threshold is greater than or equal to the first threshold. Furthermore, based on the determination that the second signal to be processed is a zero-input signal, limit cycle processing can be directly performed on the first output signal of the second subsystem. This improves the stability of the digital signal processing system and only requires a single limit cycle processing step, significantly increasing the efficiency of limit cycle processing.

[0087] According to some embodiments of the present application, Figure 3 A flow chart of another signal processing method is shown. The signal processing method can be executed by an electronic device or a digital signal processing system in the electronic device. Figure 3 The description is based on that at least one subsystem includes a first subsystem and a second subsystem.

[0088] like Figure 3 As shown, the process of the signal processing method may include:

[0089] S201: Input a first signal to be processed into at least one subsystem according to a preset order to obtain a first output signal output by the first subsystem, and calculate a total delay time based on a delay time of the at least one subsystem.

[0090] It can be understood that S201 can refer to the above S101, wherein y1[n] can be used as the first output signal obtained by the first subsystem based on the first differential equation.

[0091] S202: Perform delay processing on the first signal to be processed based on the total delay time to obtain a second signal to be processed, wherein the second signal to be processed includes a plurality of sampling points.

[0092] It can be understood that S202 can refer to the above S102 and will not be repeated here.

[0093] S203: Perform zero input detection on the second signal to be processed.

[0094] It can be understood that S203 can refer to the above S103 and will not be repeated here.

[0095] S204: Obtain a second output signal output by the second subsystem based on the first output signal output by the first subsystem.

[0096] It can be understood that in some embodiments of the present application, S202 to S203 can also be executed after S204, or S202 to S203 can be executed synchronously with S204, which is not specifically limited in the present application.

[0097] In some embodiments of the present application, a first output signal y1[n] can be obtained based on the above S101, and the first subsystem can send the first output signal y1[n] to the second subsystem. In addition, the first output signal can be processed based on the second differential equation of the second subsystem to obtain a second output signal.

[0098] In some embodiments of the present application, the first output signal is processed based on the second differential equation of the second subsystem to obtain the second output signal, including: determining the delay time of the second subsystem, and obtaining the second output signal based on the number of sampling points corresponding to the delay time of the second subsystem, the first output signal and the second differential equation.

[0099] Specifically, when the second subsystem receives the first output signal y1[n] sent by the first subsystem, the first output signal y1[n] can be used as the input signal of the second subsystem. Furthermore, the second subsystem can process the first output signal y1[n] to obtain the second output signal y2[n].

[0100] In some embodiments of the present application, the process of determining the second output signal y2[n] is described using the second subsystem as a pure time-delay system as an example. Based on the second subsystem being a pure time-delay system, the second output signal y2[n] can be directly obtained using the second differential equation corresponding to the second subsystem. The second differential equation can refer to formula (4).

[0101]

[0102] In formula (4), y2[n] represents the second output signal output by the second subsystem. When the corresponding sampling point n is less than the number of sampling points q corresponding to the delay time, the second output signal y2[n] is 0, that is, the second output signal y2[n]=0, which indicates that the second subsystem did not receive the first output signal y1[n] as its input signal before the delay, and therefore did not generate any output.

[0103] It is understood that the number of sampling points q corresponding to the delay time can refer to the length of time the input signal is delayed in the digital signal processing system, measured in terms of the number of sampling points. In other words, the number of sampling points q corresponding to the delay time can be used to represent the length of time the input signal of the second subsystem, i.e., the first output signal y1[n], is delayed in the second subsystem.

[0104] In formula (4), the corresponding sampling point n is greater than or equal to the number of sampling points q corresponding to the delay time, and the second output signal y2[n] can be equal to the first output signal y1[nq] which is the input signal of the second subsystem q sampling points ago, then the second output signal y2[n]=y1[nq].

[0105] It can be understood that in other embodiments of the present application, the second differential equation can also be expressed in other forms, which are not limited here.

[0106] It can be understood that the process of calculating the output signal y[n] based on x[n] in a pure delay system can specifically include: assuming that the total delay time of the entire digital signal processing system is T = Xms, and the sampling rate of x[n] is S, then the number of delayed sampling points corresponding to the total delay time T is p = S*X. Then, corresponding to x[n], the output signal y[n] needs to be based on the need to move the sampling points in x[n] backward by p delayed sampling points to obtain the output signal y[n], and y[n] can be calculated based on formula (5).

[0107]

[0108] In formula (5), y[n] is the output signal, x[np] is the value corresponding to the sampling point np in the input signal, where n is the current sampling point index, and p is the number of delayed sampling points calculated based on the total delay time Xms and the sampling rate S.

[0109] It is understood that the number of delayed sampling points p can refer to the length of time x[n] is delayed in the digital signal processing system. For example, assuming the total delay time T of the digital signal processing system is X ms and the sampling rate of x[n] is S, the number of delayed sampling points p corresponding to the total delay time can be calculated based on the total delay time X ms and the sampling rate S as p = S * X. For example, if X = 5 ms and S = 1000 Hz, then p = 5.

[0110] In some embodiments of the present application, the length of time x[n] is delayed as it passes through the digital signal subsystem (which may include the first subsystem and the second subsystem) can be determined by the number of delayed sampling points p. For example, if y2[n] = x[n-5], this indicates that x[n] is delayed as it passes through the digital signal subsystem (which may include the first subsystem and the second subsystem) by 5 sampling points.

[0111] It can be understood that formula (4) is derived based on formula (5). That is, y2[n] in formula (4) can correspond to y[n] in formula (5). y1[nq] in formula (4) can correspond to x[np] in formula (5).

[0112] S205: Based on the zero-input detection result, the amplitudes of the plurality of sampling points of the second signal to be processed are judged.

[0113] It can be understood that S205 can refer to the above S104 and will not be repeated here.

[0114] S206: If the amplitudes of the plurality of sampling points of the second signal to be processed are smaller than the first amplitude threshold, and the number of the plurality of sampling points is greater than or equal to the first threshold, reducing the amplitude of the second output signal.

[0115] In some embodiments of the present application, if the amplitude of multiple sampling points of the second signal to be processed is determined to be less than a first amplitude threshold based on the zero-input detection result, and the number of the multiple sampling points is greater than or equal to the first threshold, the second signal to be processed can be determined to be a zero-input signal, that is, the first output signal can be determined to be in a limit cycle state, and the gain of the second output signal can be reduced to reduce the amplitude of the second output signal. It is understood that this scenario corresponds to at least one subsystem including the first subsystem and the second subsystem.

[0116] S207: If the amplitudes of the plurality of sampling points of the second signal to be processed are smaller than the first amplitude threshold, and the number of the plurality of sampling points is greater than or equal to the first threshold, increase the amplitude of the second output signal.

[0117] In other embodiments of the present application, based on the zero-input detection result, determining the amplitudes of multiple sampling points of the second signal to be processed includes: if the amplitudes of the multiple sampling points of the second signal to be processed are greater than or equal to a first amplitude threshold, increasing the amplitude of the second output signal to obtain a final output signal. It is understood that this scenario corresponds to at least one subsystem including the first subsystem and the second subsystem.

[0118] S208: Obtain the final output signal.

[0119] It can be understood that the final output signal can be obtained based on the above S206 or S207.

[0120] Based on the above method, a digital signal processing system comprising at least one subsystem (e.g., a first subsystem and a second subsystem) can determine that the signal to be processed is a zero-input signal by detecting that the number of sampling points in a second signal to be processed whose amplitude is less than a first amplitude threshold is greater than or equal to the first threshold. Furthermore, based on the determination that the second signal to be processed is a zero-input signal, limit cycle processing can be directly performed on the second output signal of the second subsystem. This improves the stability of the digital signal processing system and only requires a single limit cycle processing step, significantly increasing the efficiency of limit cycle processing.

[0121] In some embodiments of the present application, at least one subsystem also includes a third subsystem; the signal processing method also includes: obtaining a third output signal output by the third subsystem based on the second output signal output by the second subsystem; performing zero input detection on the second signal to be processed; based on the zero input detection result, judging the amplitude of multiple sampling points of the second signal to be processed; if the amplitude of the multiple sampling points of the second signal to be processed is less than the first amplitude threshold, and the number of the multiple sampling points is greater than or equal to the first threshold, reducing the amplitude of the third output signal to obtain the final output signal.

[0122] It can be understood that the third subsystem may be a finite impulse response (FIR) filter, such as a 64-order FIR filter, etc., which is not specifically limited here.

[0123] Specifically, the signal processing process is described below using the example of at least one subsystem including a first subsystem, a second subsystem, and a third subsystem: After the digital signal processing system obtains x[n], it can process it in the order of the first subsystem, the second subsystem, and the third subsystem to obtain a third output signal y3[n] output by the third subsystem. Specifically, after obtaining the second output signal y2[n] in S204 above, the second subsystem can send the second output signal y2[n] to the third subsystem, and the third subsystem processes the second output signal y2[n] to obtain a third output signal y3[n].

[0124] It can be understood that the third subsystem can use the corresponding transfer function to derive the corresponding third differential equation, and then use the third differential equation and the second output signal y2[n] to obtain the third output signal y3[n]. For example, assuming that the third subsystem is a 64-order FIR filter, its transfer function can refer to formula (6).

[0125]

[0126] In formula (6), H(z) is the transfer function of the 64th-order FIR filter, and z is the complex variable in the Z transform, which is used to convert the time domain signal to the Z domain. In digital signal processing, z is usually used to represent the displacement operator of discrete-time signals. h(n) is the coefficient of the FIR filter, corresponding to the impulse response of the FIR filter. In the FIR filter, h(n) represents the impulse response value at time n. This coefficient determines the characteristics of the FIR filter, such as frequency response and phase response. ∑ is the summation symbol, which means that all [h(n)*zn] items with n ranging from 0 to 63 are summed. N is the index variable of the summation, representing time. z -n This is the inverse of the shift operator z in the Z transform, which represents the time delay of the signal. In FIR filters, z -n Indicates that the signal is delayed by n samples. 64 represents the order of the FIR filter, that is, the impulse response length of the FIR filter, that is, the FIR filter has 64 coefficients from h(0) to h(63).

[0127] Then, the third subsystem can be based on formula (6) and the second output signal is y2[n], and the third differential equation corresponding to the third subsystem (such as a 64-order FIR filter, etc.) can be obtained. The third differential equation can refer to formula (7).

[0128]

[0129] In formula (7), y3[n] represents the third output signal, and y2[ni] represents the value of the third subsystem's input signal y2[n] delayed by i time units. hi is the coefficient of the FIR filter, with 64 coefficients from h0 to h63. These coefficients determine the filter's characteristics, such as frequency response and phase response. ∑ is the summation symbol, indicating the summation of all hi*y2[ni] terms for i from 0 to 63. It can be understood that the output signal of the FIR filter is a weighted sum of the current input signal and the past input signal.

[0130] Based on formula (7) and the input signal y2[n] of the third subsystem (ie, the second output signal), the third output signal y3[n] can be obtained.

[0131] In some embodiments of the present application, after obtaining the third output signal y3[n], if the number of sampling points corresponding to the detection of the second signal to be processed at which the amplitude is less than the first amplitude threshold is greater than or equal to the first threshold, and if it is determined that the second signal to be processed is a zero input signal, the amplitude of the third output signal y3[n] can be reduced. This can avoid the situation where the third output signal still oscillates at a certain amplitude even when the second signal to be processed is zero, effectively preventing the third output signal from being in a limit cycle state.

[0132] It can be understood that the above example of at least one subsystem including a first subsystem, a second subsystem, and a third subsystem is only an exemplary description. In other embodiments of the present application, at least one subsystem can also include more different types of subsystems, which is not specifically limited here.

[0133] It can be understood that the above example of the first subsystem being an IIR filter, the second subsystem being a pure delay system, and the third subsystem being an FIR filter is intended to be an exemplary description. In other embodiments, the first subsystem can also be a pure delay system or an FIR filter, etc., the second subsystem can also be an IIR filter or an FIR filter, etc., and the third subsystem can also be a pure delay system or an FIR filter, etc., and no specific limitation is made here.

[0134] The following is based on Figure 4 The flowchart of zero input detection and limit cycle processing shown in FIG. 1 illustrates the specific process of zero input detection and limit cycle processing. It can be understood that Figure 4 The process of zero input detection and limit cycle processing is described by taking at least one subsystem including a first subsystem and a second subsystem as an example.

[0135] I understand. Figure 4 Each process shown can be executed by an electronic device or a digital signal processing system in the electronic device. Figure 4 As shown, the specific process may include:

[0136] S301: Obtain a second signal to be processed.

[0137] In some embodiments of the present application, the second signal to be processed may refer to an input signal after delay processing.

[0138] S302: Determine whether the amplitude of the sampling point in the second signal to be processed is less than a first amplitude threshold.

[0139] If the judgment result is yes, go to S303 and increase the number of sampling points whose amplitude is less than the first amplitude threshold by 1;

[0140] If the judgment result is no, the process goes to S304 , where the number of sampling points with amplitudes smaller than the first amplitude threshold is set to 0, and the system state flag is set to the second state flag.

[0141] It can be understood that the second signal to be processed may include multiple sampling points, and the amplitudes corresponding to different sampling points in the second signal to be processed may be different or the same, which is not specifically limited here.

[0142] In some embodiments of the present application, after the second signal to be processed is acquired, it may be determined whether the amplitude of a sampling point in the second signal to be processed is less than a first amplitude threshold.

[0143] It is understood that the first amplitude threshold can be preset and used as a parameter to measure the signal strength of the input signal. If the amplitude of the input signal is detected to be less than the first amplitude threshold, it can be indicated that the second signal to be processed is too weak. In the embodiments of the present application, such input signals can be regarded as zero input signals, which is not limited here.

[0144] S303: Increase the number of sampling points whose amplitudes are smaller than the first amplitude threshold by 1.

[0145] In some embodiments of the present application, when it is detected that the amplitude of a sampling point in the second signal to be processed is less than the first amplitude threshold, the digital signal processing system may increase the number of sampling points with amplitudes less than the first amplitude threshold by 1.

[0146] It can be understood that the amplitude being less than the first amplitude threshold value can indicate that a sampling point in the second signal to be processed is detected to be zero, and it can be determined that the second signal to be processed is a zero input signal.

[0147] S304: The number of sampling points with amplitudes smaller than the first amplitude threshold is set to 0, and the system state flag is set to the second state flag.

[0148] In some embodiments of the present application, when it is detected that the amplitude of a sampling point in the second signal to be processed is not less than (i.e., greater than or equal to) a first amplitude threshold, it can indicate that the sampling point in the second signal to be processed is not zero, and it can also indicate that the second signal to be processed is not a zero input signal. The digital signal processing system can then set the number of sampling points with amplitudes less than the first amplitude threshold to 0. In addition, the system state flag (Flag) is set to the second state flag (False), indicating that the current output signal (e.g., the second output signal or the third output signal, etc.) is not in a limit cycle state.

[0149] It is understandable that in other embodiments of the present application, the second state flag can be set to True, indicating that the current output signal (such as the second output signal or the third output signal, etc.) is not in the limit cycle state, which is not limited here.

[0150] S305: Determine whether the number of sampling points whose amplitudes are smaller than the first amplitude threshold is smaller than the first threshold.

[0151] If the judgment result is yes, go to S306 and judge whether the system status flag is the first status flag;

[0152] If the judgment result is no, go to S307, set the number of sampling points whose amplitudes are smaller than the first amplitude threshold to 0, and mark the system state as the first state mark.

[0153] It will be appreciated that the first threshold can be preset and used to measure the number of detected sampling points having amplitudes less than the first amplitude threshold. If the number of detected sampling points having amplitudes less than the first amplitude threshold is greater than or equal to the first threshold, it can be indicated that the amplitudes of consecutive sampling points in the second signal to be processed are zero, and the second signal to be processed can be determined to be a zero input signal.

[0154] S306: Determine whether the system status identifier is the first status identifier.

[0155] If the judgment result is yes, go to S308 and compress the gain of the current output signal;

[0156] If the judgment result is no, go to S309 and release the gain of the current output signal.

[0157] In some embodiments of the present application, when it is determined that the number of sampling points with amplitudes smaller than the first amplitude threshold is smaller than the first threshold, it can be further determined whether the system state flag (Flag) is the first state flag (True).

[0158] It can be understood that in the embodiment of the present application, when the system state flag (Flag) is set to the first state flag (True), it can be set to indicate that the current output signal (such as the second output signal or the third output signal, etc.) is in a limit cycle state.

[0159] It can be understood that in other embodiments of the present application, it can also be set that when the first state is marked as (False), it means that the current output signal (such as the second output signal or the third output signal, etc.) is in a limit cycle state, which is not limited here.

[0160] It can be understood that in a digital signal processing system, compressing the gain of the current output signal means reducing the gain of the current output signal to avoid the current output signal (such as the second output signal or the third output signal, etc.) still maintaining a certain amplitude oscillation when the second signal to be processed is zero.

[0161] It can be understood that releasing the gain of the output signal means increasing the gain of the output signal so that when the second signal to be processed is not zero, the amplitude of the current output signal is effectively amplified to improve the visibility of the current output signal and the stability of the system.

[0162] S307: The number of sampling points with amplitudes smaller than the first amplitude threshold is set to 0, and the system state flag is set to the first state flag.

[0163] In some embodiments of the present application, when it is determined that the number of sampling points having amplitudes less than a first amplitude threshold is not less than (i.e., greater than or equal to) the first threshold, this may indicate that there are consecutive zero sampling points in the second signal to be processed, or may indicate that the second signal to be processed is a zero input signal. Based on this, the system state flag may be set to the first state flag, indicating that the digital signal processing system is currently in a limit cycle state without a valid input.

[0164] S308: Compress the gain of the current output signal.

[0165] In some embodiments of the present application, when the system state identifier is determined to be the first state identifier, it can be determined that the current output signal of the digital signal processing system (such as the second output signal or the third output signal) is in a limit cycle state in the absence of a valid input. To improve the limit cycle state, the gain of the output signal can be compressed to reduce the gain of the current output signal, thereby reducing the amplitude of the current output signal to improve the limit cycle state of the current output signal.

[0166] S309: Release the gain of the current output signal.

[0167] In some embodiments of the present application, when it is determined that the system state identifier is not the first state identifier, it can be determined that the current output signal of the digital signal processing system is not in a limit cycle state. The gain of the current output signal can then be released, i.e., the gain of the current output signal can be increased, so that when the input signal is non-zero, the amplitude of the current output signal is effectively amplified to improve the visibility of the current output signal and the stability of the system.

[0168] S310: Output the final output signal.

[0169] In some embodiments of the present application, based on the above processing, an output signal after compression gain or an output signal after release gain can be obtained as a final output signal and output.

[0170] Based on the above method, a zero-input detection can be performed on the second signal to be processed to determine whether the second signal to be processed is zero, thereby determining whether the current output signal is in a limit cycle state. Furthermore, gain compression is performed on the current output signal in a limit cycle state to improve the limit cycle state of the current output signal and enhance the stability of the digital signal processing system. Furthermore, the signal processing method provided in this application only requires a single zero-input limit cycle process to improve the output signal limit cycle problem caused by a zero-input signal, significantly improving the efficiency of limit cycle processing.

[0171] The present application also provides a chip, which is used to execute the signal processing method provided in the embodiments of the present application.

[0172] The present application also provides an electronic device, comprising: a memory for storing instructions; and a processor for executing instructions to implement the signal processing method provided in an embodiment of the present application.

[0173] The various embodiments of the mechanisms disclosed in this application can be implemented in hardware, software, firmware, or a combination of these implementation methods. The embodiments of the present application can be implemented as a computer program or program code executed on a programmable system that includes multiple processors, a storage system (including volatile and non-volatile memory and / or storage elements), multiple input devices, and multiple output devices.

[0174] Program code can be applied to input instructions to perform the functions described herein and generate output information. The output information can be applied to one or more output devices in a known manner. For purposes of this application, a processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0175] Program code can be implemented with a high-level programming language or an object-oriented programming language to communicate with the processing system. Where necessary, program code can also be implemented in assembly language or machine language. In fact, the mechanism described in this application is not limited to the scope of any particular programming language. In either case, the language can be a compiled language or an interpreted language.

[0176] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed over a network or through other computer-readable media. Therefore, a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including but not limited to floppy disks, optical disks, optical discs, read-only memories (CD-ROMs), magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memory, or a tangible machine-readable memory for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in electrical, optical, acoustic, or other forms of propagation signals. Therefore, a machine-readable medium includes any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0177] In the accompanying drawings, some structural or method features may be shown in a particular arrangement and / or order. However, it should be understood that such a particular arrangement and / or order may not be required. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. In addition, the inclusion of a structural or method feature in a particular figure does not imply that such feature is required in all embodiments, and in some embodiments, such features may not be included or may be combined with other features.

[0178] It should be noted that the units / modules mentioned in the various device embodiments of the present application are all logical units / modules. Physically, a logical unit / module can be a physical unit / module, or a part of a physical unit / module, or can be implemented as a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important. The combination of functions implemented by these logical units / modules is the key to solving the technical problems raised by this application. In addition, in order to highlight the innovative part of this application, the above-mentioned device embodiments of this application do not introduce units / modules that are not closely related to solving the technical problems raised by this application. This does not mean that other units / modules do not exist in the above-mentioned device embodiments.

[0179] It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprises" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprises a" do not exclude the presence of other identical elements in the process, method, article or device that includes the mentioned elements.

[0180] Although the present application has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the application.

Claims

1. A signal processing method, characterized in that: Applied to electronic equipment, the electronic equipment includes at least one subsystem; The method comprises: Inputting the first signal to be processed into the at least one subsystem in a preset order to obtain a first output signal; Obtaining a total delay time based on the delay time of the at least one subsystem; Performing delay processing on the first signal to be processed based on the total delay time to obtain a second signal to be processed, wherein the second signal to be processed includes a plurality of sampling points; performing zero-input detection on the second signal to be processed; Based on the zero-input detection result, determining the amplitudes of a plurality of sampling points of the second signal to be processed; If the amplitudes of the plurality of sampling points of the second signal to be processed are smaller than the first amplitude threshold, and the number of the plurality of sampling points is greater than or equal to the first threshold, the amplitude of the first output signal is reduced to obtain a final output signal.

2. The method according to claim 1, characterized in that The determining of the amplitudes of a plurality of sampling points of the second signal to be processed based on the zero-input detection result further includes: If the amplitudes of the plurality of sampling points of the second signal to be processed are greater than or equal to the first amplitude threshold, the amplitude of the first output signal is increased to obtain a final output signal.

3. The method according to claim 1, characterized in that The at least one subsystem further comprises a first subsystem and a second subsystem; The method further comprises: Inputting the first signal to be processed into the at least one subsystem in a preset order to obtain a first output signal output by the first subsystem; Obtaining a total delay time based on the delay time of the at least one subsystem; Performing delay processing on the first signal to be processed based on the total delay time to obtain a second signal to be processed; performing zero-input detection on the second signal to be processed; obtaining a second output signal output by the second subsystem based on a first output signal output by the first subsystem; Based on the zero-input detection result, determining the amplitudes of a plurality of sampling points of the second signal to be processed; If the amplitudes of the plurality of sampling points of the second signal to be processed are smaller than the first amplitude threshold, and the number of the plurality of sampling points is greater than or equal to the first threshold, the amplitude of the second output signal is reduced to obtain a final output signal.

4. The method according to claim 1, wherein The at least one subsystem is an infinite impulse response subsystem; Alternatively, the at least one subsystem includes an infinite impulse response subsystem and a non-infinite impulse response subsystem.

5. The method according to claim 3, characterized in that The obtaining, based on the first output signal output by the first subsystem, a second output signal output by the second subsystem, includes: Processing the first signal to be processed based on the first differential equation of the first subsystem to obtain the first output signal, and sending the first output signal to the second subsystem; The first output signal is processed based on a second differential equation of the second subsystem to obtain the second output signal.

6. The method according to claim 5, characterized in that The processing of the first output signal based on the second differential equation of the second subsystem to obtain the second output signal includes: The delay time of the second subsystem is determined, and the second output signal is obtained based on the number of sampling points corresponding to the delay time of the second subsystem, the first output signal, and the second differential equation.

7. The method according to claim 3, characterized in that If the amplitudes of the plurality of sampling points of the second signal to be processed are less than the first amplitude threshold, and the number of the plurality of sampling points is greater than or equal to the first threshold, reducing the amplitude of the second output signal to obtain a final output signal, includes: If the amplitudes of the plurality of sampling points of the second signal to be processed are less than the first amplitude threshold, and the number of the plurality of sampling points is greater than or equal to the first threshold, determining that the second output signal is in a limit cycle state; The gain of the second output signal is reduced to reduce the amplitude of the second output signal, thereby obtaining a final output signal.

8. The method according to claim 3, characterized in that The determining, based on the zero-input detection result, the amplitudes of a plurality of sampling points of the second signal to be processed includes: If the amplitudes of the plurality of sampling points of the second signal to be processed are greater than or equal to a first amplitude threshold, determining that the second output signal is not in a limit cycle state; The gain of the second output signal is increased to increase the amplitude of the second output signal to obtain a final output signal.

9. The method according to claim 3, characterized in that The at least one subsystem further includes a third subsystem; The method further comprises: obtaining a third output signal output by the third subsystem based on the second output signal output by the second subsystem; performing zero-input detection on the second signal to be processed; Based on the zero-input detection result, determining the amplitudes of a plurality of sampling points of the second signal to be processed; If the amplitudes of the plurality of sampling points of the second signal to be processed are smaller than the first amplitude threshold, and the number of the plurality of sampling points is greater than or equal to the first threshold, the amplitude of the third output signal is reduced to obtain a final output signal.

10. The method according to claim 9, characterized in that The first subsystem is an IIR filter, the second subsystem is a pure delay system, and the third subsystem is a FIR filter.

11. A chip, characterized in that: Used to execute the signal processing method according to any one of claims 1 to 10.

12. An electronic device, characterized in that: include: a memory for storing instructions; A processor, configured to execute the instructions to implement the signal processing method according to any one of claims 1 to 10.

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