Receiver circuit with peak filtering

Abstract

The invention discloses a receiver circuit with peak filtering, relates to the technical field of integrated circuits, and aims to solve the problems of limited power supply range and insufficient anti-interference capability of the circuit, and the receiver circuit comprises a preprocessing module which generates reference voltage adaptive to different power supply voltages and preprocesses an input signal; the comparison module is used for comparing the preprocessed input signal with a reference voltage to obtain a stable receiving signal; and the filtering module is used for carrying out peak filtering on the received signal to obtain an output signal. According to the receiver circuit with the peak filtering function, the component circuits are simple in structure, the receiver circuit can adapt to a wider power supply range, peak pulses and burst interference are effectively filtered out, the robustness and adaptability of an IO-Link communication system are improved, and the strict requirements of the industrial environment are met.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a receiver circuit with peak filtering. Background Art

[0002] IO-Link receivers are key components in IO-Link communication systems, responsible for receiving data from the bus and converting it into digital signals recognizable by the control system. With the rapid development of industrial automation and smart manufacturing, market demand for IO-Link receivers, a key component in enabling IO-Link communication, is growing. Industrial automation is the primary application area for IO-Link receivers. As manufacturing demands for production efficiency, product quality, and cost control continue to rise, and as automation levels increase, the demand for IO-Link receivers is also increasing.

[0003] Due to the complexity and harshness of industrial environments, IO-Link receivers need to have a wide power supply range and anti-interference capabilities, typically covering the industrial standard voltage range of 9 to 36V to ensure reliable and stable communication. At the same time, due to the various interference sources present in industrial environments, brief spike pulses can be generated during IO-Link communication, disrupting the normal operation of other circuits. Therefore, the receiver also needs to have effective spike filtering capabilities to eliminate the impact of electromagnetic pulses on communication. Existing receiver circuits have the following problems: First, the power supply range is limited and cannot adapt to a wide range of power supply voltages; second, the anti-interference capability is insufficient, lacking an effective spike filtering mechanism, making it susceptible to sudden interference; third, the circuit complexity is high, and some solutions require additional external components, increasing system cost and design complexity.

[0004] For example, there is a Chinese patent with publication number CN114024562A, which involves the present invention providing a low-voltage wide common-mode detection range receiver, providing a resistor network to divide the bus voltage and convert it into a small voltage signal, an adjustment network to perform potential shifting and offset voltage bias on the small voltage signal after voltage division, and an amplifier to gain amplify the signal after the adjustment network. One side of the ground network is connected to the resistor network, and the other side is connected to the amplifier, which is used to use the small voltage after voltage division to provide a reference ground potential for the amplifier; the comparator compares the amplified signal and outputs a logic signal of the power domain, which can operate under low power supply voltage and detect a wider bus common-mode voltage range. However, the Chinese patent with publication number CN114024562A lacks an effective spike filtering mechanism and is easily affected by sudden interference. Summary of the Invention

[0005] To address the problems of limited circuit power supply range and insufficient anti-interference capability, the present invention proposes a receiver circuit with spike filtering. The component circuit structure is simple and can adapt to a wider power supply range. It effectively filters out spike pulses and sudden interference, improves the robustness and adaptability of the IO-Link communication system, and meets the strict requirements of industrial environments.

[0006] To achieve the above object, the present invention adopts the following technical solution: a receiver circuit with spike filtering, comprising: a preprocessing module, generating a reference voltage adapted to different power supply voltages and preprocessing an input signal; The comparison module compares the pre-processed input signal with the reference voltage to obtain a stable received signal; The filtering module performs peak filtering on the received signal to obtain an output signal.

[0007] In this technical solution, the power supply V is firstly L+ Pre-processing is performed to make it meet the input range of the next level comparator, and then the comparator compares it with the reference voltage. L+ When the voltage is lower than 18V, a clamping circuit is formed to change the reference voltage according to the power supply signal, so as to adapt to different power supply voltages of 9 to 36V and improve the versatility of the circuit.

[0008] In this technical solution, a digital filter is used, relying on two level-triggered D-type latches. Regardless of whether the glitch appears at the low or high level of the clock, it will be filtered out by the first-stage latch or the second-stage latch, thereby effectively filtering out spike pulses and sudden interference and improving the reliability of communication.

[0009] Preferably, the pre-processing module comprises: a first voltage divider circuit, comprising a first resistor voltage divider network, for converting the power supply voltage signal into a first clamping signal; The clamping circuit includes a comparator and a feedback loop, and adjusts the reference voltage according to the comparison result between the first clamping signal and the reference voltage to adapt to different power supply voltage ranges; The second voltage-dividing circuit includes a second resistor voltage-dividing network, and converts the input signal into a first voltage-dividing signal and a second voltage-dividing signal.

[0010] Preferably, the comparison module includes: The hysteresis circuit controls the on / off of the first and second voltage-divided signals through output level feedback to obtain a second clamping signal, thereby preventing the circuit from frequently turning on and off at the threshold flip point, thereby ensuring stable operation of the chip. a comparator circuit, for comparing the second clamping signal with a reference voltage and outputting corresponding high and low level signals; The shaping circuit includes a Schmitt trigger and an inverter, which shapes the high and low level signals to ensure the stability and reliability of the output signal.

[0011] Preferably, the filtering module includes: A clock signal generating circuit generates a first clock pulse and a second clock pulse having opposite phases; The filter circuit includes a latch and an XOR gate. Through the delayed latching function of the latch and the feedback control of the XOR gate, it filters out spike pulses and sudden interference in the signal, ensuring the stability and reliability of the output signal. Moreover, the filter circuit can adapt to various changes in the input signal frequency, ensuring that the interference signal can be effectively filtered out at different frequencies.

[0012] Preferably, the first voltage divider circuit includes a resistor R1, a first end of the resistor R1 is connected to the power supply voltage signal, a second end of the resistor R1 is connected in series with the first end of the resistor R2, and the second end of the resistor R2 is grounded. The output end of the first voltage divider circuit is located between the resistor R1 and the resistor R2, and the output end outputs the first clamping signal.

[0013] Preferably, the clamping circuit includes a first comparator, wherein the non-inverting input terminal of the first comparator is connected to a reference voltage obtained by passing a reference voltage generated by a bandgap reference circuit through a buffer, the inverting input terminal is connected to the output terminal of the first voltage divider circuit, the output terminal is connected to the gate of the transistor MN1, the drain of the transistor MN1 is connected to the non-inverting input terminal of the first comparator via a resistor R3, and the source of the transistor MN1 is grounded.

[0014] Preferably, the second voltage divider circuit includes a resistor R4, a first end of the resistor R4 is connected to the input signal, a second end of the resistor R4 is connected in series with the first end of the resistor R6 through a resistor R5, and a second end of the resistor R6 is grounded. The first output end of the second voltage divider circuit is located between the resistor R4 and the resistor R5, and the second output end of the second voltage divider circuit is located between the resistor R5 and the resistor R6.

[0015] Preferably, the hysteresis circuit includes a transistor MN2 and a transistor MN3, the source of the transistor MN2 is connected to the first voltage-divided signal, the drain of the transistor MN3 is connected to the second voltage-divided signal, and the drain of the transistor MN2 and the source of the transistor MN3 serve as output ends of the hysteresis circuit to output the second clamping signal.

[0016] Preferably, the comparison circuit includes a second comparator, the shaping circuit includes a Schmitt trigger, the non-inverting input terminal of the second comparator is connected to the reference voltage, the inverting input terminal is connected to the second clamping signal, the output terminal is connected to the input terminal of the inverter through the Schmitt trigger, the output terminal of the inverter is connected to the filter circuit, and the gate of the transistor MN2 and the gate of the transistor MN3 are respectively connected to the input terminal and output terminal of the inverter.

[0017] Preferably, the clock input ends of the first latch and the second latch included in the filter circuit are respectively connected to the first clock pulse and the second clock pulse, the data input end of the first latch is connected to the receiving signal, the receiving signal and the data output end of the second latch are respectively connected to the two input ends of the XOR gate, the output end of the XOR gate is connected to the clock generation circuit, and the output of the inverting output end of the second latch passes through the NOT gate to obtain the output signal.

[0018] The beneficial effects of the present invention are: 1) Wide power supply range: Through resistor voltage pre-processing and reference signal clamping, it can adapt to different power supply voltages of 9 to 36V, improving the versatility of the circuit; 2) Strong anti-interference ability: It can effectively filter out spike pulses and sudden interference, allowing the circuit to work stably in an industrial environment and improve communication reliability; 3) High integration: The circuit is fully integrated inside the chip, without the need for additional external components, reducing system cost and design complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a block diagram of the overall circuit structure of the present invention.

[0020] Figure 2 4 is a circuit diagram of the preprocessing module of the present invention.

[0021] Figure 3 FIG. 4 is a circuit diagram of a comparison module of the present invention.

[0022] Figure 4 is a circuit diagram of the filter module of the present invention.

[0023] Reference numerals: first voltage divider circuit 1; clamp circuit 2; second voltage divider circuit 3; comparison module 4; clock signal generating circuit 5; filter circuit 6; power supply voltage signal V L+ ; Reference voltage VREF; First clamp signal V L+_PRE ; Reference voltage V REF_PRE ; Input signal V C / Q ; The second clamp signal V C / Q_PRE ; Clock signal CLK; Receive signal V FIL_IN ; The first control signal V ctr1; The second control signal V ctr2 Output signal V RX . DETAILED DESCRIPTION

[0024] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific implementation method described herein is only an optimal embodiment of the present invention, which is only used to explain the present invention and does not limit the scope of protection of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0025] Example 1 This embodiment provides a receiver circuit with peak filtering. The circuit structure is referenced Figure 1 , including preprocessing module, comparison module and filtering module.

[0026] The pre-processing module can generate a reference voltage that adapts to different power supply voltages and pre-process the input signal.

[0027] In this embodiment, the pre-processing module is mainly composed of a first voltage divider circuit, a clamping circuit and a second voltage divider circuit. Figure 2 As shown, the specific implementation of each circuit in the preprocessing module is described in detail below.

[0028] The first voltage divider circuit is composed of resistors R1 and R2. The first end of R1 is connected to the power supply voltage signal V L+ , the second end of R1 is connected to the first end of R2, and the second end of R2 is grounded.

[0029] The output end of the first voltage divider circuit is located between R1 and R2, and outputs the first clamping signal V L+_PRE .

[0030] The main function of the first voltage divider circuit is to convert the power supply voltage signal V L+ Perform voltage division processing to adapt it to the operating voltage range of subsequent circuits.

[0031] For example, when V L+ When the voltage is 24V, by properly selecting the resistance ratio of R1 and R2, V L+_PRE Reduce to the required voltage, thereby meeting the operating voltage requirements of subsequent comparator and other circuits.

[0032] The clamping circuit adjusts the magnitude of the reference voltage according to a comparison result between the first clamping signal and the reference voltage.

[0033] In this embodiment, the clamping circuit includes a first comparator and a transistor MN1 .

[0034] The non-inverting input of the first comparator is connected to the reference voltage V obtained by the reference voltage VREF through the buffer. REF_PRE , the inverting input terminal and the output terminal of the first voltage divider circuit V L+_PRE The reference voltage VREF can be provided by a bandgap reference circuit or an external bandgap reference voltage source.

[0035] The output terminal of the first comparator is connected to the gate of the transistor MN1 , the drain of MN1 is connected to the non-inverting input terminal of the first comparator via the resistor R3 , and the source is grounded.

[0036] The working principle of the clamp circuit is: when V L+ When it is greater than 18V, V L+_PRE Greater than V REF_PRE , the first comparator outputs a low level, MN1 is turned off, and the reference voltage V REF_PRE Keep VREF; when V L+ When it is less than 18V, V L+_PRE Less than V REF_PRE , the first comparator outputs a high level, MN1 is turned on, MN1 and R3 form a feedback loop, and the reference voltage V REF_PRE Equal to V L+_PRE .

[0037] In this way, the clamp circuit can be adjusted according to the power supply voltage V L+ The size of the reference voltage V REF_PRE , ensuring that the subsequent comparator can accurately compare signals under different power supply voltages.

[0038] In this embodiment, the second voltage divider circuit is composed of resistors R4, R5 and R6. The first end of R4 is connected to the input signal V C / Q The second end of R4 is connected to the first end of R6 through R5, and the second end of R6 is grounded. The first output end of the second voltage divider circuit is located between R4 and R5, and outputs the first voltage divider signal V C / Q_PRE1 The second output terminal is located between R5 and R6, and outputs the second voltage-divided signal V C / Q_PRE2 .

[0039] The function of the second voltage divider circuit is to C / Q The voltage division process is performed to obtain two voltage division signals with different amplitudes, which provide suitable input signals for the subsequent hysteresis circuit and comparator circuit.

[0040] For example, when V C / Q When the voltage is 24V, the resistance of R4, R5 and R6 can be reasonably selected to reduce the V C / Q_PRE1 and V C / Q_PRE2 They are reduced to appropriate voltage values to meet the working requirements of subsequent circuits.

[0041] The IO-Link standard specifies that devices operate with a sensor supply voltage between 18V and 30V, but industrial sensors often operate with supply voltages as low as 9V.

[0042] The receiver of the present invention is designed to be able to L+ Below 18V(V L+ <18V), enabling device operation at lower supply voltages.

[0043] The circuit includes a first voltage divider circuit and a clamp circuit, so that V L+ Different reference signals will be generated when the voltage is greater than 18V and when it is less than 18V.

[0044] The comparison module compares the preprocessed input signal with the reference voltage to obtain a stable received signal.

[0045] The comparison module consists of a hysteresis circuit, a comparator circuit and a shaping circuit. The specific implementation of each circuit in the comparison module is described in detail below.

[0046] The hysteresis circuit includes a transistor MN2 and a transistor MN3.

[0047] The source of MN2 is connected to the first voltage-divided signal V C / Q_PRE1 The drain and source of MN3 serve as the output of the hysteresis circuit, outputting the second clamping signal V C / Q_PRE MN3’s drain is connected to the second voltage-divided signal V C / Q_PRE2 .

[0048] The working principle of the hysteresis circuit is to control the on and off of MN2 and MN3 through output level feedback, thereby realizing the hysteresis function.

[0049] Specifically, when the output level is high, MN2 is turned on, MN3 is turned off, and V C / Q_PRE Equal to V C / Q_PRE1 ; When the output level is low, MN2 is turned off, MN3 is turned on, V C / Q_PRE Equal to V C / Q_PRE2 .

[0050] In this way, the hysteresis circuit can automatically adjust the on and off of the input signal according to the state of the output level, effectively preventing the circuit from frequently turning on and off at the threshold flip point, ensuring the stable operation of the chip and delaying chip aging.

[0051] The comparator circuit includes a second comparator, the non-inverting input terminal of the second comparator is connected to the reference voltage V REF_PRE , the reverse input terminal is connected to the second clamp signal V C / Q_PRE , the output end is connected to the input end of the inverter through a Schmitt trigger.

[0052] The working process of the comparator circuit is: when V C / Q_PRE2 Greater than V REF_PRE When V C / Q_PRE2 Less than V REF_PRE When , the second comparator outputs a high level.

[0053] The shaping circuit is composed of a Schmitt trigger and an inverter, which shapes the high and low level signals output by the comparator.

[0054] The Schmitt trigger has good anti-interference ability, can effectively suppress high-frequency noise in the input signal, and output a stable square wave signal.

[0055] The inverter inverts and amplifies the signal to ensure that the amplitude and polarity of the output signal meet the requirements of the subsequent circuit.

[0056] In this embodiment, the Schmitt trigger is used to shape the signal output by the comparator to eliminate glitches and interference in the signal, ensuring signal stability and reliability. The inverter further shapes and amplifies the signal to improve the signal driving capability.

[0057] The filtering module performs peak filtering on the received signal to obtain an output signal.

[0058] In this embodiment, the filtering module is composed of a clock signal generating circuit and a filter circuit. The specific implementation of each circuit in the filtering module is described in detail below.

[0059] The clock signal generating circuit generates a first clock pulse CP1 and a second clock pulse CP2 with opposite phases, provides an accurate clock signal for the filter circuit, and controls the working state of the latch.

[0060] The clock signal generating circuit can adopt a common oscillator circuit or a clock generator circuit. Through reasonable circuit design and parameter selection, it is ensured that the generated clock signal has a stable frequency and phase relationship.

[0061] The filter circuit includes a first latch LATCH1 , a second latch LATCH2 , and an exclusive OR gate XOR.

[0062] The clock inputs of LATCH1 and LATCH2 are connected to CP1 and CP2 respectively, and the data input of LATCH1 is connected to the receiving signal V FIL_IN , V FIL_IN The data output of LATCH2 is connected to the two inputs of XOR respectively. The output of XOR is connected to the clock generation circuit. The reverse output of LATCH2 passes through the NOT gate to obtain the output signal V RX .

[0063] The working principle of the filter circuit is explained in detail below.

[0064] When a glitch occurs when CP1 is at a low level, since CP lags behind the input transition, the D transmitted to LATCH2 is the receiver signal when CP1 is at a high level. LATCH1 directly filters out the glitch. When the glitch occurs, CP2 is at a high level, and LATCH2 directly outputs the receiver signal.

[0065] When a glitch appears when CP1 is high, it will be transmitted to LATCH2 along with the signal, but the glitch amplitude will drop to the power supply voltage. Since the CP2 and CP1 signals are necessarily opposite signals, CP2 is low at this time, LATCH2 outputs the latched receiver signal, and the glitch is filtered out after passing through the second-stage latch.

[0066] In this way, the filter circuit can effectively filter out spike pulses and sudden interference in the signal, thereby improving the reliability of communication.

[0067] Example 2 In this embodiment, the implementation of the pre-processing module is basically the same as that of embodiment 1, but is optimized in some details.

[0068] For example, the resistors R1 and R2 in the first voltage divider circuit are made of higher precision resistance materials to improve the accuracy of voltage division.

[0069] At the same time, the first comparator in the clamping circuit adopts a low-power design, which reduces the overall power consumption of the circuit.

[0070] In addition, the resistance ratio of the resistors R4 , R5 and R6 in the second voltage divider circuit can be fine-tuned to better adapt to a specific input signal range.

[0071] The pre-processing module can generate a reference voltage that adapts to different power supply voltages and pre-process the input signal.

[0072] In this embodiment, the pre-processing module is mainly composed of a first voltage divider circuit, a clamping circuit and a second voltage divider circuit. Figure 2 As shown, the specific implementation of each circuit in the preprocessing module is described in detail below.

[0073] The first voltage divider circuit is composed of resistors R1 and R2. The first end of R1 is connected to the power supply voltage signal V L+ , the second end of R1 is connected to the first end of R2, and the second end of R2 is grounded.

[0074] The output end of the first voltage divider circuit is located between R1 and R2, and outputs the first clamping signal V L+_PRE .

[0075] The main function of the first voltage divider circuit is to convert the power supply voltage signal V L+ Perform voltage division processing to adapt it to the operating voltage range of subsequent circuits.

[0076] For example, when V L+ When the voltage is 24V, by properly selecting the resistance ratio of R1 and R2, V L+_PRE Reduce to the required voltage, thereby meeting the operating voltage requirements of subsequent comparator and other circuits.

[0077] The clamping circuit adjusts the magnitude of the reference voltage according to a comparison result between the first clamping signal and the reference voltage.

[0078] In this embodiment, the clamping circuit includes a first comparator and a transistor MN1 .

[0079] The non-inverting input of the first comparator is connected to the reference voltage V obtained by the reference voltage VREF through the buffer. REF_PRE , the inverting input terminal and the output terminal of the first voltage divider circuit V L+_PRE The reference voltage VREF can be provided by a bandgap reference circuit or an external bandgap reference voltage source.

[0080] The output terminal of the first comparator is connected to the gate of the transistor MN1 , the drain of MN1 is connected to the non-inverting input terminal of the first comparator via the resistor R3 , and the source is grounded.

[0081] The clamp circuit can be based on the power supply voltage V L+ The size of the reference voltage V REF_PRE , ensuring that the subsequent comparator can accurately compare signals under different power supply voltages.

[0082] In this embodiment, the second voltage divider circuit is composed of resistors R4, R5 and R6. The first end of R4 is connected to the input signal V C / Q The second end of R4 is connected to the first end of R6 through R5, and the second end of R6 is grounded. The first output end of the second voltage divider circuit is located between R4 and R5, and outputs the first voltage divider signal V C / Q_PRE1 The second output terminal is located between R5 and R6, and outputs the second voltage-divided signal V C / Q_PRE2 .

[0083] The function of the second voltage divider circuit is to C / Q The voltage division process is performed to obtain two voltage division signals with different amplitudes, which provide suitable input signals for the subsequent hysteresis circuit and comparator circuit.

[0084] For example, when V C / Q When the voltage is 24V, the resistance of R4, R5 and R6 can be reasonably selected to reduce the V C / Q_PRE1 and V C / Q_PRE2They are reduced to appropriate voltage values to meet the working requirements of subsequent circuits.

[0085] The IO-Link standard specifies that devices operate with a sensor supply voltage between 18V and 30V, but industrial sensors often operate with supply voltages as low as 9V.

[0086] The receiver of the present invention is designed to be able to L+ Below 18V(V L+ <18V), enabling device operation at lower supply voltages.

[0087] The circuit includes a first voltage divider circuit and a clamp circuit, so that V L+ Different reference signals will be generated when the voltage is greater than 18V and when it is less than 18V.

[0088] The working principle of the preprocessing module is explained in detail below.

[0089] Design an appropriate resistor divider coefficient to REF_PRE Divided into two thresholds, when V L+ >18V, V L+_PRE >V REF_PRE , the comparator outputs a low level MN1 and turns off. At this time, the reference voltage V REF_PRE = VREF; when V L+ <18V, V L+_PRE Less than V REF_PRE , the comparator outputs a high level MN1 and turns on. At this time, MN1 and resistor R3 form a feedback loop of COM1. The reference voltage V REF_PRE =V L+_PRE .

[0090] Among them, the input signal VREF is the reference voltage generated by the bandgap reference circuit and is obtained after passing through the first level BUFFER. REF_PRE Reference voltage, power supply voltage signal V L+ After the resistor voltage division preprocessing, the first voltage division signal V L+_PRE .

[0091] The comparison module of this embodiment is further improved on the basis of embodiment 1.

[0092] The transistors MN2 and MN3 in the hysteresis circuit are manufactured using a more advanced process, which improves the switching speed and reliability of the transistors.

[0093] The second comparator in the comparator circuit adopts a high-gain design to improve the sensitivity and accuracy of signal comparison.

[0094] The Schmitt trigger and inverter in the shaping circuit are also optimized to reduce signal transmission delay and improve signal response speed.

[0095] like Figure 3 As shown, the input signal V C / Q After resistor voltage division preprocessing, the second clamping signal V C / Q_PRE , V REF_PRE It is the reference voltage under different power supply voltages obtained by the preprocessing module.

[0096] The comparator positive input terminal is connected to the reference voltage V REF_PRE The negative input terminal is connected to the second clamp signal V obtained after preprocessing the input signal. C / Q_PRE .

[0097] The comparator output is shaped by the Schmitt trigger to obtain the filter input signal V FIL_IN .

[0098] The working principle of the comparison module is described in detail below.

[0099] When the power supply V L+ >18V, V REF_PRE = VREF, if V C / Q Input high level V C / Q_PRE >V REF_PRE = VREF, the comparator outputs a low level, and then outputs a high level after being shaped by the Schmitt trigger and a first-level inverter. If the input is low, V C / Q_PRE <V REF_PRE = VREF, the comparator outputs a high level, and then after being shaped by the Schmitt trigger and a first-level inverter, it outputs a low level, completing the signal reception.

[0100] When the power supply V L+ When <18V, V REF_PRE =V L+_PRE , if V C / Q Input high level V C / Q_PRE >V REF_PRE =V L+_PRE , the comparator outputs a low level, and then outputs a high level after being shaped by the Schmitt trigger and a first-level inverter. If the input is a low level, V C / Q_PRE <V REF_PRE =V L+_PRE , the comparator outputs a high level, and then after being shaped by the Schmitt trigger and a first-level inverter, it outputs a low level, completing the signal reception.

[0101] The present invention features a hysteresis function that prevents the circuit from frequently turning on and off at the threshold flip point, ensuring stable chip operation and slowing chip aging. Hysteresis is achieved by feeding back the output level to control the gates of the comparator's negative input terminals, MN2 and MN3. The control signals for MN2 and MN3 are in antiphase, ensuring that one is turned on while the other is turned off. Different resistor divider branches can be selected for comparison.

[0102] The receiver low and high level judgment thresholds and hysteresis voltage calculation formulas are as follows: V HYS =V TH -V TL .

[0103] Since there are various electromagnetic interference sources in industrial sites, the receiver of the present invention is also designed with an effective peak filtering function to eliminate the impact of electromagnetic pulses on communication. In this embodiment, the filtering module is composed of a clock signal generating circuit and a filter circuit. The circuit structure of the filtering module is as follows: Figure 4 shown.

[0104] Among them, CLK is the clock signal, and the receiving signal V FIL_IN The first control signal V is the filter input signal obtained after the output of the previous comparator is shaped by the Schmitt trigger. ctr1 and the second control signal V ctr2 It is the control signal fed back to the clock signal generating circuit, and the output signal V RX It is the final output of the receiver after filtering and is also the input of the microcontroller.

[0105] The working principle of the filtering module is described in detail below.

[0106] The loop adds an XOR gate, whose inputs are the receiver signal input and the input after LATCH2. There is a delay between the two signals. The XOR gate controls the clock signal generation circuit so that CP1 lags behind V FIL_IN The signal edge moment will not jump again, preventing the D flip-flop latch moment from being inconsistent with V FIL_IN The signal edge moment conflicts. Latch LATCH1 and LATCH2 form a D flip-flop to latch the receiver signal. XOR gate XOR and CLK form the control signal V ctr1 , V ctr2 It is the same phase signal as CLK.

[0107] When V ctr1When it is low, MP6 is turned on, the bias current is mirrored to the MP2 branch through the current mirror, the mirror current charges C1, the MN9 gate is pulled high and turned on, the voltage at point A1 is pulled low, and after being shaped by the Schmitt trigger, B1 is high.

[0108] When V ctr1 When it is high, MN8 is turned on, C1 discharges to the ground through MN8, the gate of MN9 is pulled down and then cut off, the voltage at point A1 is pulled high by MP3, and after being shaped by the Schmitt trigger, B1 is low.

[0109] Similarly, when V ctr2 When it is at a low level, MP7 is turned on, and the bias current is mirrored to the MP4 branch through the current mirror. The mirror current charges C2, the MN11 gate is pulled high and turned on, the voltage at point A0 is pulled low, and after being shaped by the Schmitt trigger, B0 is at a high level.

[0110] When V ctr1 When it is high, MN10 is turned on, C2 discharges to the ground through MN10, the gate of MN11 is pulled down and then cut off, the voltage at point A0 is pulled up by MP5, and after being shaped by the Schmitt trigger, B0 is low.

[0111] B1 and B0 are the inputs of the RS trigger, and ultimately provide the CLK clock signal for the filter circuit.

[0112] The clock signal generating circuit of this embodiment has a simple structure, does not require an additional oscillator circuit, and forms a stable loop with the filter circuit.

[0113] The realization of the filtering function mainly relies on the two latches LATCH1 and LATCH2 in the figure. The first-level LATCH1 is the master latch, and the second-level LATCH2 is the slave latch. The two together form a D flip-flop, which is characterized by edge triggering. It will only trigger the LATCH1 input terminal, namely V FIL_IN The data state is copied to the LATCH2 output terminal. The LATCH2 output terminal signal has a hold function at all other times. Therefore, no matter when the input signal changes, the output can remain stable, thus filtering out glitches other than the falling edge of the clock.

[0114] Example 3 The circuit structure of the preprocessing module in this embodiment is different from that of the previous two embodiments.

[0115] The first voltage divider circuit adopts a multi-stage voltage divider network, which can more flexibly adapt to power supply voltages in different ranges.

[0116] An additional feedback control mechanism is added to the clamp circuit to further improve the accuracy of reference voltage adjustment.

[0117] The second voltage divider circuit uses a programmable resistor array, which can dynamically adjust the voltage divider ratio according to actual needs to meet the requirements of different input signals.

[0118] The comparison module in this embodiment adopts a completely new circuit architecture.

[0119] The hysteresis circuit adopts multi-level feedback control to achieve more complex hysteresis characteristics and improve the stability and anti-interference ability of the circuit.

[0120] The comparator circuit adopts a differential input structure, which can more effectively suppress common-mode interference signals.

[0121] Signal amplification and filtering functions are added to the shaping circuit to further improve the quality of the output signal.

[0122] The filtering module in this embodiment adopts advanced digital filtering technology.

[0123] The clock signal generation circuit is combined with the digital signal processing circuit to achieve more precise clock control and signal synchronization.

[0124] The filter circuit adopts a multi-stage latching and filtering algorithm, which can more effectively filter out interference signals of various frequencies and amplitudes.

[0125] At the same time, the filtering module also has an adaptive adjustment function, which can automatically optimize the filtering parameters according to the real-time situation of the signal and improve the filtering effect.

[0126] Through the detailed description of the above three embodiments, it can be seen that the receiver circuit with spike filtering provided by the present invention has wide applicability and good performance in different application scenarios. Each embodiment is optimized and improved on the basis of the previous embodiment to meet higher technical requirements and practical application needs.

Claims

1. A receiver circuit with spike filtering, characterized in that: include: A preprocessing module preprocesses the power supply voltage signal and the input signal respectively, and generates a reference voltage adapted to different power supply voltages; The comparison module compares the pre-processed input signal with the reference voltage to obtain a stable received signal; The filtering module performs peak filtering on the received signal to obtain an output signal.

2. A receiver circuit with peak filtering according to claim 1, characterized in that: The pre-processing module includes: a first voltage divider circuit, including a first resistor voltage divider network, which converts the power supply voltage signal into a first clamping signal; The clamping circuit adjusts the reference voltage according to a comparison result between the first clamping signal and the reference voltage; The second voltage-dividing circuit includes a second resistor voltage-dividing network, and converts the input signal into a first voltage-dividing signal and a second voltage-dividing signal.

3. The receiver circuit with peak filtering according to claim 1, characterized in that: The comparison module includes: The hysteresis circuit controls the on / off of the first voltage-divided signal and the second voltage-divided signal through output level feedback to obtain a second clamping signal; a comparator circuit, for comparing the second clamping signal with a reference voltage and outputting corresponding high and low level signals; The shaping circuit includes a Schmitt trigger and an inverter, and shapes the high and low level signals.

4. A receiver circuit with peak filtering according to claim 1 or 3, characterized in that: The filtering module includes: A clock signal generating circuit generates a first clock pulse and a second clock pulse having opposite phases; The filter circuit includes a latch and an XOR gate, and filters out spike pulses and sudden interference in the signal through the delayed latch function of the latch and the feedback control of the XOR gate.

5. The receiver circuit with peak filtering according to claim 2, characterized in that: The first voltage divider circuit includes a resistor R1, a first end of the resistor R1 is connected to a power supply voltage signal, a second end of the resistor R1 is connected in series with a first end of a resistor R2, and a second end of the resistor R2 is grounded. The output end of the first voltage divider circuit is located between the resistor R1 and the resistor R2, and the output end outputs a first clamping signal.

6. A receiver circuit with peak filtering according to claim 2 or 5, characterized in that: The clamping circuit includes a first comparator, wherein the non-inverting input terminal of the first comparator is connected to the reference voltage obtained by passing the reference voltage through the buffer, the inverting input terminal is connected to the output terminal of the first voltage divider circuit, the output terminal is connected to the gate of the transistor MN1, the drain of the transistor MN1 is connected to the non-inverting input terminal of the first comparator via the resistor R3, and the source of the transistor MN1 is grounded.

7. The receiver circuit with peak filtering according to claim 2, characterized in that: The second voltage divider circuit includes a resistor R4, a first end of the resistor R4 is connected to the input signal, a second end of the resistor R4 is connected in series with the first end of the resistor R6 through a resistor R5, and a second end of the resistor R6 is grounded. The first output end of the second voltage divider circuit is located between the resistor R4 and the resistor R5, and the second output end of the second voltage divider circuit is located between the resistor R5 and the resistor R6.

8. The receiver circuit with peak filtering according to claim 3, characterized in that: The hysteresis circuit includes a transistor MN2 and a transistor MN3. The source of the transistor MN2 is connected to the first voltage-divided signal, and the drain of the transistor MN3 is connected to the second voltage-divided signal. The drain of the transistor MN2 and the source of the transistor MN3 serve as the output ends of the hysteresis circuit to output a second clamping signal. The second clamping signal is obtained based on the first voltage-divided signal and the second voltage-divided signal.

9. The receiver circuit with peak filtering according to claim 8, characterized in that: The comparator circuit includes a second comparator, and the shaping circuit includes a Schmitt trigger. The non-inverting input terminal of the second comparator is connected to the reference voltage, the inverting input terminal is connected to the second clamping signal, and the output terminal is connected to the input terminal of the inverter through the Schmitt trigger. The output terminal of the inverter is connected to the filter circuit, and the gate of the transistor MN2 and the gate of the transistor MN3 are respectively connected to the input terminal and the output terminal of the inverter.

10. The receiver circuit with peak filtering according to claim 4, characterized in that: The filter circuit includes a first latch and a second latch, whose clock input ends are connected to a first clock pulse and a second clock pulse respectively, a data input end of the first latch is connected to a received signal, the received signal and the data output end of the second latch are respectively connected to two input ends of an exclusive OR gate, the output end of the exclusive OR gate is connected to a clock generation circuit, and the output of the inverting output end of the second latch passes through a NOT gate to obtain an output signal.

Images