Depletion type gallium nitride device direct drive circuit without insertion loss

Abstract

The invention discloses a depletion type gallium nitride device direct drive circuit without insertion loss, which not only can simplify the circuit design and reduce the system cost, but also can improve the reliability and the stability of the circuit, and provides a new solution for the high-efficiency and high-power-density development of a radio frequency power amplifier. In addition, the implementation of the direct drive circuit promotes the wide application of a depletion type gallium nitride device in the fields of 5G communication, radar, satellite communication, future 6G communication and the like, and lays a foundation for performance improvement and technical progress of a modern wireless communication system. By optimizing the circuit structure and the device characteristics, the direct drive circuit without insertion loss is expected to become one of key technologies in a high-power radio frequency system in the future, and a new solution is provided for the design of a radio frequency power amplifier with high efficiency and high power density.

Description

Technical Field

[0001] The present invention relates to a depletion-type gallium nitride device direct drive circuit with no insertion loss, belonging to the technical field of integrated circuit design. Background Art

[0002] With the rapid development of wireless communication technology, the demand for high-efficiency, high-power-density RF power amplifiers (PAs) is becoming increasingly urgent. Traditional silicon-based LDMOS devices are gradually showing performance bottlenecks in high-frequency, high-power applications. Gallium nitride (GaN), as a third-generation semiconductor material, has become an ideal choice for high-power RF devices due to its excellent properties such as wide bandgap, high electron saturation drift velocity, and high breakdown electric field. As a normally-on device, the depletion-mode (D-mode) GaN high electron mobility transistor (HEMT) has the advantages of low on-resistance, high current density, and fast switching speed. It is particularly suitable for RF power amplifiers and can significantly improve the system's power handling capability and efficiency.

[0003] A traditional surge suppression solution such as Figure 1 As shown, this surge suppression circuit is connected in series between the bridge rectifier and the energy storage capacitor. It uses a surge suppression limiting resistor RT in parallel with a relay, and the circuit is placed at positions A, B, or C. This circuit is simple, easy to drive, low-cost, and simple to control. However, the relay is large, and its resistance after conduction is over 50mΩ, resulting in high operating losses, making it unsuitable for the design of high-power, high-density, and high-efficiency power supplies. RT often uses a thermistor to suppress the inrush current generated at power-up. After the power supply is operating normally, the relay delays the current limiting current short-circuit to reduce power consumption. However, the relay's on-resistance of approximately 100mΩ is still large, and the surge suppression circuit is connected in series with the main power circuit, resulting in high conduction current. The losses generated by the relay are still significant. Furthermore, the relay's large size makes it unsuitable for the design requirements of high-power-density power supplies. The relay also requires an additional driver and a third-party power supply, making the circuit complex and costly.

[0004] Another traditional surge suppression solution is Figure 2 As shown, this solution places the surge suppression resistor RT below C5, with the other end grounded. At the moment of power-on, RT, connected in series with C5, suppresses current. When C5 is fully charged and the inrush current returns to normal, the depletion-mode gallium nitride (GaN) power device Qr is turned on by the control and drive circuitry, short-circuiting RT and redirecting the current through Qr. RT no longer consumes power, and Qr's low on-resistance also reduces its power consumption. Furthermore, since neither Qr nor RT are part of the main power circuit, the current flowing through it is only 3%-20% of the main power circuit, further reducing power consumption.

[0005] Traditional depletion-mode GaN device driver circuits typically require a negative voltage to turn off the device, which not only increases circuit complexity and cost but also introduces additional insertion loss, reducing system efficiency. Furthermore, the use of a negative voltage power supply and level-shifting circuit increases system size and power consumption, limiting the adoption of depletion-mode GaN devices in high-integration, high-efficiency applications.

[0006] like Figure 3 and 4 As shown in the figure, there are two connection methods for single-tube depletion-mode gallium nitride (GaN) power devices: direct drive and cascade.

[0007] In direct-drive circuits, the isolated driver must adopt a positive and negative voltage control strategy: positive voltage turns Q2 on, and negative voltage turns it off. This circuit has a fatal flaw because Q2 is a depletion-mode device. During startup and power-down, the driver has no output, but Q2 remains in a naturally on state. If this state persists for too long, excessive current in Q2 can burn out the device.

[0008] In the cascade circuit, GaN device Q2 forms a cascade connection with enhancement-mode Si-based MOSFET Q3. The isolated driver actually indirectly turns Q2 on and off by driving Q3. Because Q3 is an enhancement-mode device, it does not require positive or negative voltages; only single-voltage control is required. Furthermore, this circuit avoids the problem of excessive current burning components during startup and power-down, as in direct-drive circuits. However, the addition of Q3 in series increases the circuit's on-resistance, thereby increasing operating losses. Q3's large junction capacitance also limits the circuit's operating frequency.

[0009] like Figure 5 and Figure 6 As shown in the figure, dual-bridge depletion-mode gallium nitride (GaN) power devices can be connected in series or cascade. However, the dual-bridge structure has a fatal flaw. Because Q1 and Q2 are depletion-mode devices, both bridge transistors are naturally on during power-on and power-off. This can cause shoot-through failures and damage the device. To prevent shoot-through, especially during power-on and power-off, an enhancement-mode Si-based MOSFET is often required.

[0010] In a series circuit, GaN devices Q1 and Q2 are connected in series with an enhancement-mode Si-based MOSFET Q3. Each of these three devices uses three independent drivers. While Q2 and Q3 turn on and off simultaneously, Q1 turns on and off 180° out of phase with Q2 and Q3. This approach is uncommon because the timing control of these three independent drivers is complex.

[0011] In a cascade circuit, GaN device Q2 forms a cascade connection with enhancement-mode Si-based MOSFET Q3, effectively integrating Q2 and Q3. Q2 and Q3 naturally switch on and off simultaneously, while Q1 switches on and off 180° out of phase with Q2 and Q3. This approach is the most common and relatively simple to control.

[0012] Whether it is a series or cascade circuit, Q3 is connected in series, which will increase the on-resistance in the circuit and thus increase the working loss, and the large junction capacitance of Q3 will also limit the operating frequency of the circuit.

[0013] Currently, several patents and research have proposed different drive circuit schemes. For example, patent US20170230058A1 proposes a level-shifting circuit for converting a positive voltage control signal into a negative voltage signal to drive a depletion-mode GaN device. The disadvantage of this design is that it introduces additional insertion loss, reducing system efficiency. Patent US20210152045A1 proposes a direct-drive circuit for depletion-mode GaN devices without a negative voltage driver. This design achieves zero insertion loss by optimizing the drive logic and device structure. While this design simplifies the circuit structure and improves efficiency, its applicability and reliability still require further verification. Therefore, developing a direct-drive circuit for depletion-mode GaN devices without insertion loss has become a hot topic of research. This direct-drive circuit can shut down the device without relying on a negative voltage supply, eliminating the insertion loss in traditional drive circuits and further improving the overall efficiency of RF power amplifiers. Summary of the Invention

[0014] The purpose of the present invention is to provide a depletion-mode gallium nitride device direct drive circuit with no insertion loss, so as to solve the problem of direct conduction during startup and shutdown and improve device reliability.

[0015] The purpose of the present invention is achieved through the following technical solutions:

[0016] A depletion-mode gallium nitride device direct drive circuit with no insertion loss, comprising: resistors Ra, Rc, Rx, a diode group Da, a capacitor C1, power devices Q1, Q2, Q3, Q4, and Q5, and also comprising a high-end device drive unit, a low-end device drive unit, and a surge suppression time control unit. The source of the power device Q5 is connected to a negative voltage. The resistor Rc is a gate-source discharge resistor of the power device Q5, one end of which is connected to the source of the power device Q5, and the other end is simultaneously connected to the gate of the power device Q5. The gate of Q5 is connected to the negative electrode of a voltage regulator tube ZD1, the positive electrode of the voltage regulator tube ZD1 is connected to the gate of the power device Q4, the drain of the power device Q5 is connected to the gate of the power device Q3, the source of the power device Q3 is simultaneously connected to the source of the power device Q4 and the negative electrode of the diode group Da, the drain of the power device Q3 is connected to one end of the resistor Rx, and the high-end device drive unit is used to supply power to the power device. Q1 provides a driving signal, and the low-end device driving unit is used to provide a driving signal to Q2. The other end of the resistor Rx is connected between the output of the high-end device driving unit and the gate of Q1 to prevent the output of the high-end device driving unit from short-circuiting after Q3 is turned on. The source of the power device Q1 is connected to the drain of the power device Q2. The source of the power device Q2 is also connected to the positive electrode of the diode group Da, the negative electrode of the capacitor C1, and the drain of the power device Q4. The resistor Ra is connected in parallel with the diode group Da. The surge suppression timing control unit is used to provide driving signals to the power devices Q4 and Q5 to achieve 180° phase-shifted switching of Q3 and Q4, and provides a voltage input terminal for the direct drive circuit. The drain of the power device Q4 is connected to the reference zero potential, the negative input terminal of the input terminal is connected to the negative electrode of the diode group Da, and the positive input terminal is simultaneously connected to the drain of the power device Q1 and the positive electrode of the capacitor C1.

[0017] Preferably, the surge suppression time control unit includes a diode D1, resistors R1, R2, R3, R4, R5 and R6, a capacitor C2, transistors M1 and M2, the collector of transistor M2 is connected to the power supply voltage source Vcc of the direct drive circuit, the signal output by the emitter is the control signal of the power devices Q4 and Q5, the base is connected to one end of the resistor R5, the other end of the resistor R5 is connected to the emitter of the transistor M1, the collector of the transistor M1 is simultaneously connected to one end of the capacitor C2 and one end of the resistor R3, and the input end of the direct drive circuit is between one end of the resistor R3 and the positive electrode of the diode D1, the base is connected to one end of the resistor R6, the other end of the resistor R6 is simultaneously connected to the other end of the capacitor C2, the other end of the resistor R3 and one end of the resistor R2, the resistor R2 is connected in series with R1, the other end of the resistor R1 is connected to the negative electrode of the diode D1, one end of the resistor R4 is connected to the collector of the transistor M2, and the other end is connected to the base of the transistor M2, wherein the transistor M1 is a PNP transistor and the transistor M2 is an NPN transistor.

[0018] Preferably, the control logic of the surge suppression time control unit is: define the node where the resistors R2, R3, R6 and the capacitor C2 are connected as point C, and detect the voltage V at point C. c , when V c Lower than the voltage source input voltage V cc When , transistor M1 is turned on and pulls down the base of M2, causing M2 to turn off. The surge suppression time control unit outputs a low-level signal, the power device Q4 is turned off, the voltage regulator ZD1 is not turned on, the power device Q5 is turned off, and Q3 is naturally turned on. Otherwise, a high-level signal is output to drive Q4 to turn on, the voltage regulator ZD1 is turned on, Q5 is turned on, the gate of Q3 is pulled down to a negative voltage, and Q3 is turned off.

[0019] Preferably, the high-end device driving unit has the same structure as the low-end device driving unit, and controls the power devices Q1 and Q2 to work 180 degrees out of phase and turn on or off. In the high-end device driving unit, the input voltage is converted by a push-pull circuit, and then rectified and filtered by diodes Dp1, Dp2, capacitors Cp1, and Cp2 to output two sets of symmetrical positive and negative voltages. The positive voltage is filtered by capacitor Cp3 and linearly stepped down by LDO, and then provided to a single voltage isolation driver chip as a driving power supply voltage. The single voltage isolation driver chip has a set of PWM inputs and outputs VOA1 and VOA2. VOA1 and VOA2 work 180 degrees out of phase. VOA1 is connected to the gate of the power device Q1 through a resistor Rg1. The gate of the power device Q1 is connected to VOA2 through a diode Dg1 and is also connected to the emitter of the transistor M3 through a resistor Rg3. The base of the transistor M3 is connected to VOA2 through a resistor Rg2. The collector of the transistor M3 is connected to the negative voltage terminal of the symmetrical output.

[0020] Preferably, the driving logic of the high-end device driving unit is as follows: when the VOA1 of the single voltage isolation driver chip outputs a high level, the current flows through the resistor Rg1 to the gate-source of the power device Q1 and then returns to the single voltage isolation driver chip, driving Q1 to be turned on with a positive voltage. At this time, VOA2 is in a high resistance state, and at the same time, the diode Dg1 blocks the flow of the base current of the transistor M3, and M3 is in a cut-off state.

[0021] When VOA2 outputs a low level, the gate-source voltage of Q1 is first pulled down to 0V through diode Dg1. The gate voltage of Q1 reaches VOA2 through Rg3, M3, and Rg2, causing M3 to turn on. After M3 is turned on, the gate voltage of Q1 is pulled down to a negative voltage through Rg3 and M3, driving Q1 to turn off at a negative voltage.

[0022] Preferably, the power devices Q1, Q2, Q3, and Q5 are all p-type transistors or depletion-mode gallium nitride-based power devices, and the power device Q4 is an n-type transistor or an enhancement-mode gallium nitride-based power device.

[0023] Preferably, a power insertion circuit is further included, wherein the input end of the power insertion circuit is connected to the source of the power device Q4, the output end is connected to the drain of Q1, and is connected to the positive electrode of the capacitor C1.

[0024] Preferably, the power insertion circuit is a direct short circuit or a power factor correction circuit.

[0025] Preferably, the input current of the direct drive circuit is pure DC or pulsed DC formed by rectifying AC.

[0026] Preferably, the diode group Da is composed of several diodes connected in series.

[0027] Preferably, the negative voltage connected to the source of the power device Q5 comes from the negative voltage output by the low-end device driving unit.

[0028] This invention proposes a novel direct-drive circuit for depletion-mode gallium nitride devices with no insertion loss. This circuit not only simplifies circuit design and reduces system costs, but also improves circuit reliability and stability, providing a new solution for the development of high-efficiency and high-power density RF power amplifiers. Furthermore, the implementation of this direct-drive circuit will promote the widespread application of depletion-mode gallium nitride devices in fields such as 5G communications, radar, satellite communications, and future 6G communications, laying the foundation for performance improvements and technological advancements in modern wireless communication systems. By optimizing circuit structure and device characteristics, direct-drive circuits with no insertion loss are expected to become one of the key technologies in future high-power RF systems, providing a new solution for the design of high-efficiency, high-power-density RF power amplifiers.

[0029] The beneficial effects of the present invention are as follows:

[0030] 1. Combination of surge suppression circuit and power device driver: solve the problem of power-on direct current;

[0031] 2. Complete capacitor discharge before power failure: solve the problem of power-on during shutdown;

[0032] 3. Double isolation of power supply and drive (optional). BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 For traditional surge suppression solutions1.

[0034] Figure 2 For traditional surge suppression solutions2.

[0035] Figure 3 It is a direct drive connection method for single-tube depletion-mode gallium nitride (GaN) power devices.

[0036] Figure 4 It is a cascade connection method for single-tube depletion-mode gallium nitride (GaN) power devices.

[0037] Figure 5 It is a series connection method of bridge-type dual-tube depletion-mode gallium nitride (GaN) power devices.

[0038] Figure 6 It is a cascade connection method of bridge-type dual-tube depletion-mode gallium nitride (GaN) power devices.

[0039] Figure 7 This is a direct drive circuit diagram of a depletion-mode gallium nitride device according to the present invention.

[0040] Figure 8 This is a timing diagram of the circuit startup operation of the present invention.

[0041] Figure 9 This is a timing diagram of the circuit shutdown or input power-down operation of the present invention.

[0042] Figure 10 The present invention is an implementation plan for a surge suppression time control unit.

[0043] Figure 11 Implementation plan for Q1 and Q2 drive units. DETAILED DESCRIPTION

[0044] To make the objectives, technical solutions, and advantages of the present invention more apparent, the following describes the technical solutions in the embodiments of the present invention in more detail with reference to the accompanying drawings. Throughout the drawings, identical or similar reference numerals represent identical or similar elements or elements having identical or similar functions. The described embodiments are only some, not all, of the embodiments of the present invention.

[0045] All other embodiments obtained by persons of ordinary skill in the art based on the embodiments of the present invention without creative work shall fall within the scope of protection of the present invention.

[0046] Example 1

[0047] like Figure 7 As shown, the depletion-mode GaN device direct drive circuit with no insertion loss has a pure DC input current or a pulsed DC formed by rectified AC, and includes: resistors Ra, Rc, and Rx, a diode group Da, a capacitor C1, and power devices Q1, Q2, Q3, Q4, and Q5. The power devices Q1, Q2, Q3, and Q5 are all p-type transistors or depletion-mode GaN-based power devices, and the power device Q4 is an n-type transistor or an enhancement-mode GaN-based power device.

[0048] The device also includes a high-end device driving unit, a low-end device driving unit and a surge suppression time control unit. The source of the power device Q5 is connected to a negative voltage of -10V, which is the negative voltage of the symmetrical positive and negative voltages output by the low-end device driving unit. The resistor Rc is the gate-source bleeder resistor of the power device Q5, which is commonly but not limited to 2k-20kΩ. One end is connected to the source of the power device Q5, and the other end is also connected to the gate of the power device Q5. The gate of Q5 is connected to the negative electrode of the voltage regulator ZD1. The value of ZD1 is commonly but not limited to 2-10V. The positive electrode of the voltage regulator ZD1 is connected to the gate of the power device Q4. The drain of the power device Q5 is connected to the gate of the power device Q3. The source of the power device Q3 is simultaneously connected to the source of the power device Q4 and the negative electrode of the diode group Da. The drain of the power device Q3 is connected to one end of the resistor Rx. The high-end device driving unit is used to provide a driving signal to the power device Q1, and the low-end device driving unit is used to provide a driving signal to Q2. The other end of the resistor Rx is connected between the output of the high-end device driving unit and the gate of Q1. In order to prevent the output of the high-end device driving unit from being short-circuited after Q3 is turned on, the source of the power device Q1 is connected to the drain of the power device Q2, and the source of the power device Q2 is connected to the positive electrode of the diode group Da, the negative electrode of the capacitor C1, and the drain of the power device Q4. The resistor Ra is connected in parallel with the diode group Da, and Ra is connected in series with the input to suppress the input surge current. Its resistance is usually designed to be in the range of several ohms to tens of ohms. It can also suppress the through current of Q1 and Q2. The surge suppression time control unit is used to give Power devices Q4 and Q5 provide driving signals to realize the 180° phase-shifted switching on and off of Q3 and Q4, that is, Q3 is turned off when Q4 is turned on, and Q3 is turned on when Q4 is turned off, and provide a voltage input end for the direct drive circuit. At the same time, the surge suppression time control unit can also detect whether the input is power-off. Ra can be short-circuited through Q4, the drain of the power device Q4 is connected to the reference zero potential, the negative input end of the input end is connected to the cathode of the diode group Da, and the positive input end is connected to the drain of the power device Q1 and the positive electrode of the capacitor C1 at the same time.

[0049] like Figure 10As shown, the surge suppression time control unit includes a diode D1, resistors R1, R2, R3, R4, R5 and R6, a capacitor C2, transistors M1 and M2, the collector of transistor M2 is connected to an external power supply Vcc, VCC comes from an external independent power supply, which is common but not limited to 12-20V, the emitter outputs a control signal for power devices Q4 and Q5, the base is connected to one end of resistor R5, the other end of resistor R5 is connected to the emitter of transistor M1, the collector of transistor M1 is connected to one end of capacitor C2 and one end of resistor R3 at the same time, the The voltage input terminal of the direct drive circuit is connected between one end and the positive electrode of the diode D1. The base is connected to one end of the resistor R6. The other end of the resistor R6 is connected to the other end of the capacitor C2, the other end of the resistor R3 and one end of the resistor R2. The resistors R2 and R1 are connected in series. The other end of the resistor R1 is connected to the negative electrode of the diode D1. One end of the resistor R4 is connected to the collector of the transistor M2, and the other end is connected to the base of the transistor M2. The transistor M1 is a PNP transistor, and the transistor M2 is an NPN transistor. M1, M2, R4, R5, and R6 constitute a logic control unit.

[0050] The control logic of the surge suppression time control unit is as follows: the node where resistors R2, R3, R6 and capacitor C2 are connected is defined as point C, and the voltage V at point C is detected. c , when V c Lower than the voltage source input voltage V cc When , transistor M1 is turned on and pulls down the base of M2, causing M2 to turn off. The surge suppression time control unit outputs a low-level 0V signal, the power device Q4 is turned off, the voltage regulator ZD1 is not connected, the power device Q5 is turned off, and Q3 is naturally turned on; otherwise, a high-level signal is output to drive Q4 to turn on, the voltage regulator ZD1 is connected, Q5 is turned on, the gate of Q3 is pulled down to -10V, and Q3 is turned off.

[0051] like Figure 11As shown, the structure and driving logic of the high-end device driving unit are the same as those of the low-end device driving unit, and the power devices Q1 and Q2 are controlled to work on or off with a 180° phase shift. In the high-end device driving unit, the low-voltage DC input is generally lower than 100V. The input voltage is converted by the push-pull circuit and then rectified and filtered by diodes Dp1, Dp2, capacitors Cp1, and Cp2 to output two sets of symmetrical positive and negative voltages, which are common but not limited to +10V and -10V. The +10V voltage is then filtered by Cp3 and linearly stepped down by LDO to be provided to the single voltage isolation driver chip as the driving power supply voltage, which is common but not limited to The positive voltage is limited to +6V, and after being filtered by capacitor Cp3 and linearly stepped down by LDO, the single-voltage isolation driver chip has one set of PWM inputs and two sets of outputs. The two sets of outputs are VOA1 and VOA2. VOA1 and VOA2 operate 180 degrees out of phase. VOA1 is connected to the gate of power device Q1 through resistor Rg1. The gate of power device Q1 is connected to VOA2 through diode Dg1 and is also connected to the emitter of transistor M3 through resistor Rg3. The base of transistor M3 is connected to VOA2 through resistor Rg2. The collector of transistor M3 is connected to the negative voltage terminal of the symmetrical output.

[0052] The high-side device driver logic is as follows: When VOA1 outputs a high level, the current flows through Rg1 to the gate-source (GS) of Q1 and then back to the single-voltage isolated driver chip, driving Q1 to a positive voltage and turning it on. Rg1's resistance is typically, but not limited to, 0-100Ω. At this point, VOA2 is in a high-impedance state, and Dg1 blocks the base current of M3, turning M3 off.

[0053] When VOA2 outputs a low level, the gate-source voltage of Q1 is first pulled down to 0V through Dg1, and the gate voltage of Q1 reaches VOA2 through Rg3, M3, and Rg2, causing M3 to turn on. After M3 is turned on, the gate voltage of Q1 is pulled down to -10V through Rg3 and M3, driving Q1 to turn off with a negative voltage.

[0054] It can also include a power insertion circuit, the input end of which is connected to the source of the power device Q4, the output end is connected to the drain of Q1, and is connected to the positive electrode of the capacitor C1. The power insertion circuit can be directly short-circuited or inserted into a common power factor correction circuit.

[0055] The timing diagram of the startup operation is as follows Figure 8 As shown, at the moment of power on, the input voltage is loaded. Due to the presence of large capacitor C1, the input current i0 (i0 is i c1 (Right now Figure 7A surge spike occurs at the sum of i1) and i2 (the sum of the two components). The surge current flows through the parallel connection of Ra and Da, generating a high negative voltage (between -10V and -3V) at point b. At this time, since Q3 is in a naturally on state, the conduction of Q3 pulls the gate voltage of Q1 to the negative voltage at point b, forcing Q1 to turn off and preventing the direct conduction of Q1 and Q2. At this point, as long as the input remains, the loop from the input to C1 to point a and then to point b will continue to operate, and point b will always maintain a high negative voltage state (between -10V and -3V), thus ensuring that Q1 is always forced to turn off.

[0056] Q4 short-circuits Ra, reducing the negative voltage at point b (greater than -2V), thus affecting Q1's effective shutdown. Similarly, the conduction of Q3 also affects Q1's effective shutdown. Therefore, the operating timing of Q3 and Q4 must ensure Q1's effective shutdown and prevent shoot-through.

[0057] When the surge current duration ends, as long as Q3 remains on and Q4 remains off, point b will always maintain a high negative voltage state (between -10V and -3V), thus ensuring that Q1 is always forced to be turned off.

[0058] After the drive signals for Q1 and Q2 arrive and Q1 and Q2 enter their normal 180° phase-shifted on and off state, Q3 is turned off and Q4 is turned on. After Q3 is turned off, it will no longer hinder the normal on and off of Q1, and after Q4 is turned on, it will reduce the voltage drop across Ra, thereby reducing loop operating losses.

[0059] Shutdown or input power-down working sequence diagram is as follows Figure 9 As shown in the figure, the logic of the shutdown or input power-off moment is exactly the opposite of the startup moment.

[0060] After shutdown, due to the presence of large capacitor C1, the voltage on capacitor C1 begins to drop, accompanied by a delay in the input current i0 before slowly decreasing. To prevent a direct pass through in the loop from C1 to Q1 and Q2, Q1 must be forcibly turned off before the drivers of Q1 and Q2 are turned off. This is done by turning Q3 back on and Q4 back off at the same time when a drop in input voltage is detected, causing the voltage at point b to return to a higher negative voltage (between -10V and -3V), forcing Q1 to shut down.

[0061] In addition, it can also ensure that the power-off speed of the driving power supply of Q1 and Q2 is lower than the power-off speed of C1, so that Q1 and Q2 will terminate the normal 180° phase-shifted switching and closing working state only when the voltage of C1 drops to a lower value.

[0062] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be considered as equivalent replacement methods and are included in the scope of protection of the present invention.

Claims

1. A depletion-mode gallium nitride device direct drive circuit with no insertion loss, characterized in that: include: Resistors Ra, Rc, Rx, diode group Da, capacitor C1, power devices Q1, Q2, Q3, Q4, Q5, also include a high-end device driving unit, a low-end device driving unit and a surge suppression time control unit, the source of the power device Q5 is connected to a negative voltage, the resistor Rc is the gate-source discharge resistor of the power device Q5, one end is connected to the source of the power device Q5, and the other end is connected to the gate of the power device Q5, the gate of Q5 is connected to the negative electrode of the voltage regulator ZD1, the positive electrode of the voltage regulator ZD1 is connected to the gate of the power device Q4, the drain of the power device Q5 is connected to the gate of the power device Q3, the source of the power device Q3 is simultaneously connected to the source of the power device Q4 and the negative electrode of the diode group Da, the drain of the power device Q3 is connected to one end of the resistor Rx, the high-end device driving unit is used to provide a driving signal to the power device Q1, the low-end The device driving unit is used to provide a driving signal to Q2. The other end of the resistor Rx is connected between the output of the high-end device driving unit and the gate of Q1 to prevent the output of the high-end device driving unit from being short-circuited after Q3 is turned on. The source of the power device Q1 is connected to the drain of the power device Q2. The source of the power device Q2 is simultaneously connected to the positive electrode of the diode group Da, the negative electrode of the capacitor C1, and the drain of the power device Q4. The resistor Ra is connected in parallel with the diode group Da. The surge suppression timing control unit is used to provide a driving signal to the power devices Q4 and Q5 to achieve 180° phase-shifted switching of Q3 and Q4, and provide a voltage input terminal for the direct drive circuit. The drain of the power device Q4 is connected to the reference zero potential, the negative input terminal of the input terminal is connected to the negative electrode of the diode group Da, and the positive input terminal is simultaneously connected to the drain of the power device Q1 and the positive electrode of the capacitor C1.

2. The depletion-mode gallium nitride device direct drive circuit according to claim 1, characterized in that: The surge suppression time control unit includes a diode D1, resistors R1, R2, R3, R4, R5 and R6, a capacitor C2, transistors M1 and M2, the collector of transistor M2 is connected to the power supply voltage source Vcc of the direct drive circuit, the signal output by the emitter is the control signal of the power devices Q4 and Q5, the base is connected to one end of the resistor R5, the other end of the resistor R5 is connected to the emitter of the transistor M1, the collector of the transistor M1 is simultaneously connected to one end of the capacitor C2 and one end of the resistor R3, and the area between one end of the resistor R3 and the positive electrode of the diode D1 serves as the input end of the direct drive circuit, the base is connected to one end of the resistor R6, the other end of the resistor R6 is simultaneously connected to the other end of the capacitor C2, the other end of the resistor R3 and one end of the resistor R2, the resistor R2 is connected in series with R1, the other end of the resistor R1 is connected to the negative electrode of the diode D1, one end of the resistor R4 is connected to the collector of the transistor M2, and the other end is connected to the base of the transistor M2, wherein the transistor M1 is a PNP transistor and the transistor M2 is an NPN transistor.

3. The depletion-mode gallium nitride device direct drive circuit according to claim 2, wherein: The control logic of the surge suppression time control unit is as follows: define the node where resistors R2, R3, R6 and capacitor C2 are connected as point C, and detect the voltage V at point C. c , when V c Lower than the voltage source input voltage V cc When , transistor M1 is turned on and pulls down the base of M2, causing M2 to turn off. The surge suppression time control unit outputs a low-level signal, the power device Q4 is turned off, the voltage regulator ZD1 is blocked, and the power device Q5 is turned off; otherwise, a high-level signal is output to drive Q4 to turn on, the voltage regulator ZD1 is connected, and Q5 is turned on.

4. The depletion-mode gallium nitride device direct drive circuit according to claim 2, wherein: The high-end device drive unit has the same structure as the low-end device drive unit and controls the power devices Q1 and Q2 to operate 180 degrees out of phase and turn on and off. In the high-end device drive unit, the input voltage is converted by a push-pull circuit, and then rectified and filtered by diodes Dp1, Dp2, and capacitors Cp1 and Cp2 to output two sets of symmetrical positive and negative voltages. The positive voltage is filtered by capacitor Cp3 and linearly stepped down by an LDO before being provided to a single-voltage isolation driver chip as a drive power supply voltage. The single-voltage isolation driver chip has a set of PWM inputs and outputs VOA1 and VOA2. VOA1 and VOA2 operate 180 degrees out of phase. VOA1 is connected to the gate of the power device Q1 through a resistor Rg1. The gate of the power device Q1 is connected to VOA2 through a diode Dg1 and is also connected to the emitter of a transistor M3 through a resistor Rg3. The base of the transistor M3 is connected to VOA2 through a resistor Rg2. The collector of the transistor M3 is connected to the negative voltage terminal of the symmetrical output.

5. The depletion-mode gallium nitride device direct drive circuit according to claim 4, characterized in that: The driving logic of the high-end device driver unit is as follows: when the VOA1 of the single-voltage isolation driver chip outputs a high level, it passes through resistor Rg1 to the gate-source of the power device Q1 and then returns to the single-voltage isolation driver chip, driving Q1 to turn on with a positive voltage. At this time, VOA2 is in a high-resistance state, and diode Dg1 blocks the base current of transistor M3, causing M3 to be in the off state. When VOA2 outputs a low level, the gate-source voltage of Q1 is first pulled down to 0V through diode Dg1. The gate voltage of Q1 reaches VOA2 through Rg3, M3, and Rg2, causing M3 to turn on. After M3 is turned on, the gate voltage of Q1 is pulled down to a negative voltage through Rg3 and M3, driving Q1 to turn off at a negative voltage.

6. The depletion-mode gallium nitride device direct drive circuit according to any one of claims 1 to 5, characterized in that: The power devices Q1, Q2, Q3, and Q5 are all p-type tubes or depletion-mode gallium nitride-based power devices, and the power device Q4 is an n-type tube or enhancement-mode gallium nitride-based power device.

7. The depletion-mode gallium nitride device direct drive circuit according to claim 6, characterized in that: It also includes a power insertion circuit, the input end of which is connected to the source of the power device Q4, the output end of which is connected to the drain of Q1 and the positive electrode of the capacitor C1.

8. The depletion-mode gallium nitride device direct drive circuit according to claim 7, characterized in that: The power insertion circuit is a direct short circuit or a power factor correction circuit.

9. The depletion-mode gallium nitride device direct drive circuit according to claim 6, characterized in that: The diode group Da is composed of several diodes connected in series.

10. The depletion-mode gallium nitride device direct drive circuit according to claim 6, characterized in that: The negative voltage connected to the source of the power device Q5 comes from the negative voltage output by the low-end device driving unit.

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