Switching circuit, power supply circuit, chip and electronic equipment

Abstract

The embodiment of the invention provides a switching circuit, a power supply circuit, a chip and electronic equipment, the switching circuit comprises a switching transistor, the first end of the switching transistor is connected with a power supply end, and the second end of the switching transistor is used for outputting a target voltage; the communication module is used for responding to the first switch enable signal to control the on-off of an access between the control end of the switch transistor and the second end of the switch transistor; and the switch control module is used for responding to the first switch enable signal and controlling the control end voltage of the switch transistor according to the voltage of the power supply end. When the first switch enable signal is invalid, the access between the control end of the switch transistor and the second end of the switch transistor is controlled to be connected through the connection module, and the access between the control end of the switch transistor and the power supply end is disconnected through the switch control module, so that the problem of current backflow in the switch circuit can be comprehensively solved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a switching circuit, a power supply circuit, a chip, and an electronic device. Background Art

[0002] Currently, integrated circuit design typically requires a switching circuit to supply voltage to downstream circuits to ensure proper operation. However, if the power supply voltage drops, there is a risk of excessive voltage in the downstream circuits, leading to current backflow and potentially damaging the circuits. Summary of the Invention

[0003] In view of the above problems, embodiments of the present application provide a switching circuit, a power supply circuit, a chip, and an electronic device to solve the above technical problems.

[0004] In a first aspect, an embodiment of the present application provides a switching circuit, comprising:

[0005] a switching transistor, wherein a first terminal of the switching transistor is connected to the power supply terminal, and a second terminal of the switching transistor is used to output a target voltage;

[0006] a communication module, the communication module being configured to control the on / off of a path between the control terminal of the switching transistor and the second terminal of the switching transistor in response to a first switch enable signal;

[0007] a switch control module, the switch control module being configured to control a control terminal voltage of the switch transistor according to a voltage at the power terminal in response to a first switch enable signal;

[0008] When the first switch enable signal is invalid, the connection module controls the path between the control end of the switch transistor and the second end of the switch transistor to be connected, and the switch control module disconnects the path between the control end of the switch transistor and the power supply end.

[0009] In a second aspect, the present application provides a power supply circuit, characterized in that it includes the switching circuit as described in the first aspect.

[0010] In a third aspect, an embodiment of the present application further provides a chip comprising the switching circuit as described in the first aspect.

[0011] In a fourth aspect, an embodiment of the present application further provides an electronic device comprising the above-mentioned chip or switching circuit.

[0012] In the present application, when the first switch enable signal is invalid, the communication module controls the path between the control terminal of the switching transistor and the second terminal of the switching transistor to be connected, thereby ensuring that the switching transistor is in the off state. At the same time, because the switch control module disconnects the path between the control terminal of the switching transistor and the power supply terminal, after the path between the control terminal of the switching transistor and the second terminal of the switching transistor is connected, the phenomenon of backflow current flowing into the power supply terminal through the control terminal of the switching transistor and the switch control module can also be avoided.

[0013] It can be seen that when the first switch enable signal of the present application is invalid, the switching transistor itself remains in the cut-off state and no backflow current will pass through it, and the backflow current will not flow to the power supply end through the control end of the switching transistor and the switch control module. Therefore, the present application can comprehensively solve the current backflow problem in the switching circuit.

[0014] These and other aspects of the present application will become more readily apparent from the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A schematic diagram of a switch circuit in the related art is shown.

[0017] Figure 2 A schematic diagram of a switch circuit in an embodiment of the present application is shown.

[0018] Figure 3 Another schematic diagram of the switch circuit in an embodiment of the present application is shown.

[0019] Figure 4 Another schematic diagram of the switch circuit in an embodiment of the present application is shown.

[0020] Figure 5 Another schematic diagram of the switch circuit in an embodiment of the present application is shown.

[0021] Figure 6 Another schematic diagram of the switch circuit in an embodiment of the present application is shown.

[0022] Figure 7 Another schematic diagram of the switch circuit in an embodiment of the present application is shown.

[0023] Figure 8 Another schematic diagram of the switch circuit in an embodiment of the present application is shown.

[0024] Figure 9 Another schematic diagram of the switch circuit in an embodiment of the present application is shown.

[0025] Figure 10 Another schematic diagram of the switch circuit in an embodiment of the present application is shown.

[0026] Figure 11 Another schematic diagram of the switch circuit in an embodiment of the present application is shown.

[0027] Figure 12 Another schematic diagram of the switch circuit in an embodiment of the present application is shown.

[0028] Figure 13 Another schematic diagram of the switch circuit in an embodiment of the present application is shown.

[0029] Figure 14 Another schematic diagram of the switch circuit in an embodiment of the present application is shown.

[0030] Figure 15 Another schematic diagram of the switch circuit in an embodiment of the present application is shown.

[0031] Among them, 100 is a switch circuit, 200 is a low voltage difference linear regulator, and 300 is a maximum voltage selection circuit;

[0032] 10 connection module, 20 switch control module, 21 first connection unit, 22 resistance voltage dividing unit, 23 second connection unit, 24 bias voltage generating unit;

[0033] Switching transistor M0, power supply terminal VDD1, ground terminal GND, target voltage VDD2, first switch enable signal SW, second switch enable signal SWN, first enable signal S1, second enable signal S2, third voltage VDD3, fourth voltage VDD4, maximum voltage VMAX, first node m1, second node m2, preset bias voltage VBN, bias current Ibais;

[0034] A first resistor R1, a second resistor R2, a third resistor R3, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. DETAILED DESCRIPTION

[0035] The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0036] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0037] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, etc., are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0038] Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0039] In the description of the embodiments of this application, words such as "example" or "for example" are used to indicate an example, illustration, or description. Any embodiment or design described as "for example" or "for example" in the embodiments of this application is not to be construed as being preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to clearly present relative concepts.

[0040] In addition, in the embodiments of the present application, "plurality" refers to two or more. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two, or more. For example, "including at least one" means including one, two, or more, and does not limit which ones are included. For example, "including at least one of A, B, and C" means including A, B, C, A and B, A and C, B and C, or A, B, and C.

[0041] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0042] The control terminal of each transistor used in the embodiments of the present application is a gate, the first electrode / first end of each transistor is one of the source and the drain, and the second electrode / second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable, that is, the first electrode / first end and the second electrode / second end of the transistor in the embodiments of the present application can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode / first end of the transistor is the source, and the second electrode / second end is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode / first end of the transistor is the source, and the second electrode / second end is the drain.

[0043] In the circuit structure provided in the embodiments of the present application, the first node, the second node and other nodes do not represent actual components, but represent the junction points of related couplings in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0044] Currently, in order to avoid the current backflow phenomenon, the related technology usually adopts the method of switching the output tube substrate connection to solve the current backflow problem. For example, see Figure 1 , Figure 1 A schematic diagram of a switch circuit in the related art is shown, wherein the switch circuit includes a PMOS transistor MP1, an NMOS transistor MN1, an output PMOS transistor MP0, a switch s1 and a switch s2.

[0045] When the switching circuit operates normally, the PMOS transistor MP1 is turned off, the NMOS transistor MN1 is turned on, the switch s1 is closed, and the switch s2 is opened. At this time, the substrate of the output PMOS transistor MP0 is connected to its first terminal. Since the gate voltage of the output PMOS transistor MP0 is lower than the source voltage, the output PMOS transistor MP0 is normally turned on, and the switching circuit can normally provide the output voltage VOUT according to the voltage of the power supply terminal VDD.

[0046] When the switching circuit stops working, the PMOS transistor MP1 is turned on, the NMOS transistor MN1 is turned off, the switch s1 is opened, and the switch s2 is closed. At this time, the substrate of the output PMOS transistor MP0 is connected to its second end. Since the gate voltage of the output PMOS transistor MP0 is higher than the source voltage, the output PMOS transistor MP0 is turned off, and the switching circuit stops providing the output voltage VOUT.

[0047] It can be seen that when the switching circuit stops working, since the substrate of the output PMOS transistor MP0 is connected to its second terminal, the body diode of the output PMOS transistor MP0 will prevent the current from flowing from the second terminal of the output PMOS transistor MP0 to the first terminal thereof, thereby avoiding the current backflow phenomenon when the switching circuit stops working.

[0048] However, if the power supply terminal VDD loses power, the voltage of the power supply terminal VDD may be lower than the output voltage VOUT. This will cause the gate voltage of the output PMOS transistor MP0 to be lower than its source voltage, causing the PMOS transistor to still be turned on, ultimately resulting in current backflow when the switching circuit stops working.

[0049] To this end, the present application provides a switching circuit, a power supply circuit, a chip and an electronic device, which are described in detail below.

[0050] First, see Figure 2 , Figure 2 A schematic diagram of a switch circuit 100 in an embodiment of the present application is shown, wherein the switch circuit 100 includes a switch transistor M0 , a connection module 10 and a switch control module 20 .

[0051] Specifically, a first terminal of the switching transistor M0 is connected to the power supply terminal VDD1, and a second terminal of the switching transistor M0 can be connected to a subsequent circuit to output a target voltage VDD2 to the subsequent circuit and enable the subsequent circuit to operate. Generally, the switching transistor M0 can be a P-type transistor, for example, but not limited to, a PMOS transistor, a P-type IGBT transistor, etc.

[0052] It should be noted that the control terminal of the switch transistor M0 is controlled by the switch control module 20, which will be described in detail later. As for the substrate of the switch transistor M0, the substrate of the switch transistor M0 can be made of Figure 1 The anti-backflow design is to set a switch between the substrate and the first end of the switching transistor M0, and set another switch between the substrate and the second end of the switching transistor M0, so as to control the substrate voltage of the switching transistor M0 through the two switches; alternatively, in some possible embodiments, the substrate of the switching transistor M0 can also be directly connected to the second end of the switching transistor M0, thereby solving the risk of current backflow caused by the body diode of the switching transistor M0.

[0053] For ease of understanding, in the subsequent description of this embodiment, this document will specifically illustrate the switching circuit 100 provided in this embodiment by taking the substrate of the switching transistor M0 connected to the second end of the switching transistor M0 as an example. It should be understood that this content does not constitute a limitation of the embodiment of the present application.

[0054] The communication module 10 is connected to the control end of the switching transistor M0, and the communication module 10 is connected to the second end of the switching transistor M0. The communication module 10 can control the on / off of the path between the control end of the switching transistor M0 and the second end of the switching transistor M0 in response to the first switch enable signal SW.

[0055] For example, when the first switch enable signal SW is valid (for example, the first switch enable signal SW is at a high level), the connection module 10 can disconnect the path between the control end of the switch transistor M0 and the second end of the switch transistor M0 to ensure that the switch control module 20 normally controls the control end voltage of the switch transistor M0; and when the first switch enable signal SW is invalid (for example, the first switch enable signal SW is at a low level), the connection module 10 can connect the path between the control end of the switch transistor M0 and the second end of the switch transistor M0. Combined with the fact that the substrate of the switch transistor M0 is connected to the second end of the switch transistor M0, it can be seen that the source voltage and the gate voltage of the switch transistor M0 are equal, so it can be ensured that the switch transistor M0 itself is in the cut-off state.

[0056] The switch control module 20 is connected between the power supply terminal VDD1 and the ground terminal GND, and is connected to the control terminal of the switching transistor M0. The switch control module 20 can control the control terminal voltage of the switching transistor M0 according to the voltage of the power supply terminal VDD1 in response to the first switch enable signal SW, so as to control the switching transistor M0 to be turned on or off.

[0057] For example, the switch control module 20 may include a plurality of resistors connected in series and a switch element. When the first switch enable signal SW is valid (e.g., the first switch enable signal SW is at a high level), the switch element closes to energize the plurality of resistors connected in series. The plurality of resistors in series generate a voltage signal of appropriate magnitude through resistor voltage division, which is input to the control terminal of the switching transistor M0, thereby controlling the switching transistor M0 to conduct. When the first switch enable signal SW is invalid (e.g., the first switch enable signal SW is at a high level), the switch element opens to stop supplying power to the plurality of resistors in series, thereby stopping controlling the voltage at the control terminal of the switching transistor M0.

[0058] In an embodiment of the present application, when the first switch enable signal SW is valid (for example, the first switch enable signal SW is at a high level), the connection module 10 controls the path between the control end of the switch transistor M0 and the second end of the switch transistor M0 to be disconnected, and the switch control module 20 can output a control voltage to the control end of the switch transistor M0 according to the voltage of the power supply end VDD1, thereby turning on the switch transistor M0 and outputting the target voltage VDD2.

[0059] When the first switch enable signal SW is invalid (for example, the first switch enable signal SW is at a low level), the connection module 10 controls the path between the control terminal of the switch transistor M0 and the second terminal of the switch transistor M0 to be connected. Combined with the connection of the substrate of the switch transistor M0 to the second terminal of the switch transistor M0, it can be seen that the voltages of the control terminal and the substrate of the switch transistor M0 are equal (that is, the source voltage and the gate voltage of the switch transistor M0 are equal), thereby ensuring that the switch transistor M0 is in the off state. At the same time, because the switch control module 20 disconnects the path between the control terminal of the switch transistor M0 and the power supply terminal VDD1, after the path between the control terminal of the switch transistor M0 and the second terminal of the switch transistor M0 is connected, the phenomenon of backflow current flowing into the power supply terminal VDD1 through the control terminal of the switch transistor M0 and the switch control module 20 can also be avoided.

[0060] It can be seen that when the first switch enable signal SW is invalid, the body diode of the switching transistor M0 cannot pass the backflow current, the switching transistor M0 itself remains in the off state and will not pass the backflow current, and the backflow current will not flow through the control end of the switching transistor M0 and the switch control module 20 to the power supply end VDD1. Therefore, the present application can more comprehensively solve the current backflow problem in the switching circuit 100.

[0061] In some embodiments of this application, see Figure 3 , Figure 3 Another schematic diagram of the switching circuit 100 in an embodiment of the present application is shown, wherein the connection module 10 includes a first transistor M1 and a second transistor M2; the first end of the first transistor M1 is connected to the control end of the switching transistor M0, the second end of the first transistor M1 is connected to the second end of the second transistor M2, and the first end of the second transistor M2 is connected to the second end of the switching transistor M0; the control end of the first transistor M1 is used to access the first switch enable signal SW, and the control end of the second transistor M2 is used to access the first switch enable signal SW.

[0062] For example, taking the case where the first switch enable signal SW is valid when it is at a high level and invalid when it is at a low level, and the first transistor M1 and the second transistor M2 are PMOS transistors, when the first switch enable signal SW is at a high level, the first transistor M1 and the second transistor M2 are in a cut-off state. Since the second end of the first transistor M1 is connected to the second end of the second transistor M2, the body diodes of the first transistor M1 and the second transistor M2 conduct in opposite directions, and the body diodes of the first transistor M1 and the second transistor M2 will not conduct. Therefore, the path between the control end of the switch transistor M0 and the second end of the switch transistor M0 is disconnected, thereby ensuring that the switch control module 20 can normally control the control end voltage of the switch transistor M0.

[0063] When the first switch enable signal SW is at a low level, the first transistor M1 and the second transistor M2 are in the on state. At this time, the path between the control end of the switch transistor M0 and the second end of the switch transistor M0 is connected, so that the switch transistor M0 remains in the off state when the first switch enable signal SW is invalid.

[0064] It is understandable that the first transistor M1 and the second transistor M2 may also be NMOS transistors, IGBT transistors, etc., and those skilled in the art may adjust them according to actual needs.

[0065] In some embodiments of the present application, when the first switch enable signal SW is valid, the switch control module 20 controls the control terminal voltage of the switch transistor M0 to be less than the voltage of the power supply terminal VDD1 and greater than the voltage of the ground terminal GND, and the switch transistor M0 operates in the linear region.

[0066] It should be noted that, see Figure 1 In the related art, when the switching circuit provides the output voltage VOUT, the NMOS transistor MN1 is fully turned on, the gate voltage of the switch PMOS transistor M0 is the voltage of the ground terminal GND, and the current output by the switch PMOS transistor M0 is unconstrained. If the voltage-stabilizing capacitor C0 of the subsequent circuit breaks down, causing the second terminal of the switch PMOS transistor M0 to be directly grounded, the switch PMOS transistor M0 may burn out due to insufficient overcurrent capability.

[0067] In the above embodiment, the switch control module 20 can clamp the control terminal voltage of the switching transistor M0, so that the switch control module 20 controls the control terminal voltage of the switching transistor M0 to be less than the voltage of the power supply terminal VDD1 and greater than the voltage of the ground terminal GND. At this time, the switching transistor M0 is not fully turned on and operates in the linear region, thereby avoiding the phenomenon of the transistor being burned out due to insufficient overcurrent capacity when the second terminal of the switching transistor M0 is grounded.

[0068] In some embodiments of this application, see Figure 4 , Figure 4Another schematic diagram of the switching circuit 100 in an embodiment of the present application is shown, wherein the switch control module 20 includes a first communication unit 21, a resistor divider unit 22 and a second communication unit 23. The first communication unit 21, the resistor divider unit 22 and the second communication unit 23 are connected in series between the power supply terminal VDD1 and the ground terminal GND, and the control end of the switching transistor M0 is connected to the resistor divider unit 22; the first communication unit 21 is used to control the on-off of the path between the first end of the resistor divider unit 22 and the power supply terminal VDD1 in response to the first switch enable signal SW; the second communication unit 23 is used to control the on-off of the path between the second end of the resistor divider unit 22 and the ground terminal GND in response to the first switch enable signal SW.

[0069] It should be noted that the resistance voltage divider unit 22 may include multiple resistors connected in series, or the resistance voltage divider unit 22 may also include multiple electronic components connected in series as resistors, so as to control the control terminal voltage of the switching transistor M0 through the resistance voltage divider principle, so that the control terminal voltage of the switching transistor M0 is less than the voltage of the power supply terminal VDD1 and greater than the voltage of the ground terminal GND.

[0070] Specifically, when the first switch enable signal SW is valid, the first connecting unit 21 turns on the path between the first end of the resistance divider unit 22 and the power supply terminal VDD1, and the second connecting unit 23 turns on the path between the second end of the resistance divider unit 22 and the ground terminal GND. At this time, the resistance divider unit 22 is equivalent to being directly connected between the power supply terminal VDD1 and the ground terminal GND. Therefore, the resistance divider unit 22 can clamp the control terminal voltage of the switching transistor M0 through the resistance divider principle, thereby avoiding the phenomenon that the switching transistor M0 is burned out due to insufficient overcurrent capacity.

[0071] When the first switch enable signal SW is invalid, the first connecting unit 21 disconnects the path between the first end of the resistor divider unit 22 and the power supply terminal VDD1, and the second connecting unit 23 disconnects the path between the second end of the resistor divider unit 22 and the ground terminal GND. At this time, the resistor divider unit 22 is disconnected from the power supply terminal VDD1 and the ground terminal GND. Combined with the connection module 10 controlling the path between the control end of the switching transistor M0 and the second end of the switching transistor M0, it can be seen that the backflow current will not flow into the power supply terminal VDD1 through the control end of the switching transistor M0 and the switch control module 20.

[0072] In some embodiments of this application, see Figure 5 , Figure 5Another schematic diagram of the switch circuit 100 in an embodiment of the present application is shown, wherein the first connection unit 21 includes a third transistor M3 and a fourth transistor M4; a first end of the third transistor M3 is connected to the power supply terminal VDD1, a second end of the third transistor M3 is connected to the second end of the fourth transistor M4, and a first end of the fourth transistor M4 is connected to the first end of the resistor divider unit 22; a control end of the third transistor M3 is used to access the first enable signal S1, and a control end of the fourth transistor M4 is used to access the first enable signal S1.

[0073] It should be noted that the levels of the first enable signal S1 and the second enable signal S2 are opposite to the level of the first switch enable signal SW. For example, taking the first switch enable signal SW as valid when it is at a high level and invalid when it is at a low level, and the third transistor M3 and the fourth transistor M4 are PMOS transistors as an example, when the first switch enable signal SW is at a high level, the first enable signal S1 and the second enable signal S2 are at a low level, so the third transistor M3 and the fourth transistor M4 are turned on. At this time, the path between the first end of the resistor divider unit 22 and the power supply terminal VDD1 is connected, so that the resistor divider unit 22 can normally output the voltage and control the voltage of the control terminal of the switch transistor M0.

[0074] When the first switch enable signal SW is at a low level, the first enable signal S1 and the second enable signal S2 are at a high level, and the third transistor M3 and the fourth transistor M4 are in a cut-off state. Since the second end of the third transistor M3 is connected to the second end of the fourth transistor M4, the body diodes of the third transistor M3 and the fourth transistor M4 conduct in opposite directions, and the body diodes of the third transistor M3 and the fourth transistor M4 do not conduct. At this time, the path between the first end of the resistor divider unit 22 and the power supply terminal VDD1 is disconnected, so as to prevent backflow current from flowing to the power supply terminal VDD1 through the control end of the switch transistor M0, the resistor divider unit 22, and the first connecting unit 21.

[0075] In some embodiments of the present application, the first enable signal S1 is a level signal of a first voltage domain, and the second enable signal S2 is a level signal of a second voltage domain; the first voltage domain is the voltage domain corresponding to the first end of the switching transistor M0, and the second voltage domain is the voltage domain corresponding to the second end of the switching transistor M0.

[0076] It should be noted that the voltage domain corresponding to the first terminal of the switching transistor M0 refers to the voltage domain between the voltage of the power supply terminal VDD1 and the ground terminal GND, that is, the first voltage domain is the voltage domain between the voltage of the power supply terminal VDD1 and the ground terminal GND. For example, Figure 5In the embodiment, the first switch enable signal SW can output the first enable signal S1 through an inverter connecting the power supply terminal VDD1 and the ground terminal GND. Therefore, when the first enable signal S1 is at a high level, its voltage is the voltage of the power supply terminal VDD1, which can make the source voltage and the gate voltage of the third transistor M3 equal, thereby ensuring that the third transistor M3 remains in the off state when the first enable signal S1 is at a high level.

[0077] The voltage domain corresponding to the second terminal of the switch transistor M0 is the voltage domain between the target voltage VDD2 and the ground terminal GND, that is, the second voltage domain is the voltage domain between the target voltage VDD2 and the ground terminal GND. For example, Figure 5 In the embodiment, the first switch enable signal SW can output the second enable signal S2 through an inverter connected to the target voltage VDD2 and the voltage of the ground terminal GND. Therefore, when the second enable signal S2 is at a high level, its voltage is the target voltage VDD2. After the control terminal of the switching transistor M0 and the second terminal of the switching transistor M0 are turned on, the source voltage and the gate voltage of the fourth transistor M4 are both the target voltage VDD2. Therefore, it can also be ensured that the fourth transistor M4 remains in the off state when the second enable signal S2 is at a high level.

[0078] It can be seen that when the first enable signal S1 is a level signal of the first voltage domain and the second enable signal S2 is a level signal of the second voltage domain, stable control of the third transistor M3 and the fourth transistor M4 can be guaranteed, avoiding the phenomenon that the backflow current cannot be limited due to the different voltage domains connected to the third transistor M3 and the fourth transistor M4.

[0079] It is understandable that the first enable signal S1 and the second enable signal S2 may also be level signals corresponding to a higher voltage domain.

[0080] In some embodiments of this application, see Figure 6 , Figure 6 Another schematic diagram of the switching circuit 100 in an embodiment of the present application is shown, wherein the second connection unit 23 includes a fifth transistor M5; the second end of the fifth transistor M5 is connected to the second end of the resistance divider unit 22, the first end of the fifth transistor M5 is connected to the ground end GND, and the control end of the fifth transistor M5 is used to access the first switch enable signal SW.

[0081] For example, taking the example of the fifth transistor M5 being an NMOS transistor, which is enabled when the first switch enable signal SW is at a high level and disabled when the first switch enable signal SW is at a low level, when the first switch enable signal SW is at a high level, the fifth transistor M5 is turned on, thereby connecting the second end of the resistor divider unit 22 to the ground terminal GND, so that the resistor divider unit 22 can normally output a voltage and control the voltage at the control terminal of the switch transistor M0. When the first switch enable signal SW is at a low level, the fifth transistor M5 is turned off, thereby disconnecting the path between the second end of the resistor divider unit 22 and the ground terminal GND, thereby preventing the control terminal of the switch transistor M0 from being grounded and remaining in the on state.

[0082] In some embodiments of this application, see Figure 7 , Figure 7 Another schematic diagram of the switch circuit 100 in the embodiment of the present application is shown, wherein the resistor voltage divider unit 22 includes a sixth transistor M6 and a first resistor R1; the second end of the sixth transistor M6 is connected to the first connecting unit 21 (at Figure 7 In the corresponding embodiment, the second end of the sixth transistor M6 can be connected to the second end of the fourth transistor M4), the first end of the sixth transistor M6 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the second connecting unit 23 (in Figure 7 In the corresponding embodiment, the second end of the first resistor R1 can be connected to the second end of the fifth transistor M5); wherein, the control end of the switch transistor M0 is connected to the first node m1 between the sixth transistor M6 and the first resistor R1, and the control end of the sixth transistor M6 is used to access the preset bias voltage VBN when the first switch enable signal SW is valid.

[0083] It should be noted that when the first switch enable signal SW is valid, the control terminal of the sixth transistor M6 is connected to the preset bias voltage VBN and operates in the saturation region. At this time, the sixth transistor M6 can be considered as an equivalent resistor. The sixth transistor M6 and the first resistor R1 divide the voltage, so that a voltage of appropriate magnitude can be generated at the first node m1 and the control terminal voltage of the switching transistor M0 can be controlled, so that the switching transistor M0 operates in the linear region, so as to avoid the phenomenon that the switching transistor M0 is burned out due to insufficient overcurrent capability.

[0084] It is understood that the implementation of the resistor voltage divider unit 22 is not limited thereto. For example, see Figure 8 , Figure 8 Another schematic diagram of the switch circuit 100 in an embodiment of the present application is shown, wherein the resistor divider unit 22 may also include a first resistor R1 and a second resistor R2 connected in series, and the control terminal voltage of the switch transistor M0 is controlled by the first resistor R1 and the second resistor R2.

[0085] In some embodiments of this application, see Figure 9 , Figure 9 Another schematic diagram of the switch circuit 100 in an embodiment of the present application is shown, wherein the switch control module 20 further includes a bias voltage generating unit 24, which is connected to the control terminal of the sixth transistor M6. When the first switch enable signal SW is valid, the bias voltage generating unit 24 can input a preset bias voltage VBN to the control terminal of the sixth transistor M6, thereby causing the sixth transistor M6 to operate in a saturation region and limit the current flowing through the first resistor R1, so as to control the voltage of the first node m1 (i.e., the control terminal voltage of the switch MOS transistor).

[0086] As an example, see Figure 10 , Figure 10 Another schematic diagram of the switch circuit 100 in an embodiment of the present application is shown, wherein the bias voltage generating unit 24 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a plurality of tenth transistors M10; a first end of the seventh transistor M7 is connected to the power supply terminal VDD1, a second end of the seventh transistor M7 is connected to the bias current Ibais, and a control end of the seventh transistor M7 is connected to the second end of the seventh transistor M7; a first end of the eighth transistor M8 is connected to the power supply terminal VDD1, and a control end of the eighth transistor M8 is connected to the control end of the seventh transistor M7; a first end of the ninth transistor M9 is connected to the power supply terminal VDD1, a second end of the ninth transistor M9 is connected to the control end of the seventh transistor M7, and the control end of the ninth transistor M9 is used to receive the first switch enable signal SW; a plurality of tenth transistors M10 are connected in series between the second end of the eighth transistor M8 and the ground terminal GND, and the control end of each tenth transistor M10 is connected to its second end; wherein the control end of the sixth transistor M6 is connected to the second end of the eighth transistor M8.

[0087] It should be noted that when the first switch enable signal SW is valid (e.g., the first switch enable signal SW is at a high level), the ninth transistor M9 is in an off state, and the seventh transistor M7 and the eighth transistor M8 form a current mirror circuit. Therefore, the eighth transistor M8 can mirror the bias current Ibais flowing through the seventh transistor M7 according to a set ratio. At the same time, because the control terminal of each tenth transistor M10 is connected to its second terminal to form a diode, the mirrored output current of the eighth transistor M8 can generate a preset bias voltage VBN through the multiple tenth transistors M10 connected in series, thereby achieving the purpose of inputting the preset bias voltage VBN to the control terminal of the sixth transistor M6 when the first switch enable signal SW is valid.

[0088] When the first switch enable signal SW is invalid (for example, the first switch enable signal SW is at a low level), the ninth transistor M9 is in an on-state, and the gate voltage and the source voltage of the eighth transistor M8 are both at the voltage of the power supply terminal VDD1. Therefore, the eighth transistor M8 is in an off-state and stops outputting the mirror current. At this time, the bias voltage generating unit 24 stops inputting the preset bias voltage VBN to the control terminal of the sixth transistor M6.

[0089] It is understandable that when the first switch enable signal SW is invalid, a switch can be set to directly connect the control terminal of the sixth transistor M6 to the ground. For example, see Figure 11 , Figure 11 Another schematic diagram of the switch circuit 100 in an embodiment of the present application is shown, wherein the bias voltage generating unit 24 further includes an eleventh transistor M11, and the control terminal of the eleventh transistor M11 is connected to the second switch enable signal SWN which is the inversion of the first switch enable signal SW, so that the control terminal of the sixth transistor M6 is controlled to be grounded through the eleventh transistor M11 when the first switch enable signal SW is invalid (that is, the second switch enable signal SWN is valid).

[0090] In some embodiments of the present application, for example, in an embodiment in which the substrate of the switch transistor M0 is connected to the second end of the switch transistor M0, see Figure 12 , Figure 12 Another schematic diagram of the switching circuit 100 in an embodiment of the present application is shown, wherein the connection module 10 may further include a third resistor R3, a first end of the third resistor R3 is connected to the second end of the second transistor M2, and a second end of the third resistor R3 is connected to the second end of the switching transistor M0. The substrate of the switching transistor M0 can be connected to the third resistor R3 and the second node m2 of the second transistor M2, so as to limit the current flowing into the substrate and the control end of the switching transistor M0 through the third resistor R3.

[0091] It is worth noting that the above contents about the switch circuit 100 are intended to clearly illustrate the implementation verification process of the present application. Those skilled in the art can make equivalent modified designs under the guidance of the present application, for example, referring to Figure 13 , Figure 13Another schematic diagram of the switch circuit 100 in an embodiment of the present application is shown, wherein the bias voltage generating unit 24 may further include a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and a fifteenth transistor M15. The twelfth transistor M12 and the thirteenth transistor M13 form a current mirror circuit to mirror the bias current Ibais, thereby indirectly controlling the current in the branch where the seventh transistor M7 is located; the fourteenth transistor M14 can control whether the control end of the twelfth transistor M12 and its second end are connected, and the fifteenth transistor M15 can control whether the control ends of the twelfth transistor M12 and the thirteenth transistor M13 are grounded, thereby controlling whether the current mirror circuit formed by the twelfth transistor M12 and the thirteenth transistor M13 operates normally.

[0092] To better implement the switch circuit 100 in the embodiments of the present application, the present application further provides a power supply circuit based on the switch circuit 100, which includes the switch circuit 100 described in any of the above embodiments. Since the power supply circuit of the present application includes the switch circuit 100 described in the above embodiments, it has all the beneficial effects of the switch circuit 100 in the above embodiments, which will not be repeated here.

[0093] As an exemplary embodiment of a power supply circuit, see Figure 14 , Figure 14 A schematic diagram of a power supply circuit in an embodiment of the present application is shown, wherein a switching circuit 100 outputs a target voltage VDD2 according to a voltage at a power supply terminal VDD1. The power supply circuit further includes a low-voltage difference linear regulator 200, which is configured to output a fourth voltage VDD4 according to a third voltage VDD3; and a maximum voltage selection circuit 300, which is configured to output a maximum voltage VMAX according to a voltage at the power supply terminal VDD1 and a fourth voltage VDD4.

[0094] It should be noted that the LDO 200 is a charge pump type LDO 200, and the fourth voltage VDD4 is the output voltage of the charge pump in the LDO 200. The fourth voltage VDD4 can indicate whether the LDO 200 is powered. Furthermore, the output terminals of the LDO 200 and the switch circuit 100 are connected. When the power supply voltage drops, the maximum voltage VMAX output by the maximum voltage selection circuit 300 can shut down the switch circuit 100. If the LDO 200 is operating normally, the voltage output by the power supply circuit will be the output voltage of the LDO 200. Conversely, when the third voltage VDD3 drops, the maximum voltage VMAX output by the maximum voltage selection circuit 300 can shut down the LDO 200. If the switch circuit 100 is operating normally, the voltage output by the power supply circuit will be the target voltage VDD2 output by the switch circuit 100.

[0095] It can be seen that when one of the switch circuit 100 and the low-voltage dropout linear regulator 200 is working and the other one is stopped, the power supply circuit can ensure normal power supply to the subsequent circuit.

[0096] It is worth noting that the above content about the power supply circuit is intended to clearly illustrate the implementation verification process of this application. Those skilled in the art can make modifications with equivalent output under the guidance of this application. For example, see Figure 15 , Figure 15 Another schematic diagram of the power supply circuit in an embodiment of the present application is shown, wherein the maximum voltage selection circuit 300 can also directly output the maximum voltage VMAX based on the output voltage of the switching circuit 100 and the low-voltage difference linear regulator 200, and use the maximum voltage VMAX as the power supply voltage of the subsequent stage voltage.

[0097] The present application also provides a chip including the aforementioned switching circuit 100. An integrated circuit (IC) is also referred to as a chip, and the chip may be, but is not limited to, a system-on-chip (SOC) chip or a system-in-package (SIP) chip. Because the chip of the present application includes the switching circuit 100 described in the aforementioned embodiment, it possesses all the beneficial effects of the switching circuit 100 described in the aforementioned embodiment, and therefore will not be further elaborated here.

[0098] The embodiment of the present application also provides an electronic device, which includes a device body and a chip as described above provided in the device body. The electronic device can be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control panel, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablet computers, and POS (point of sales terminal). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0099] The above is only a preferred embodiment of the present application and does not constitute any form of limitation to the present application. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in this field can make some changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A switching circuit, characterized in that: include: a switching transistor, wherein a first terminal of the switching transistor is connected to the power supply terminal, and a second terminal of the switching transistor is used to output a target voltage; a communication module, configured to control the on / off of a path between the control terminal of the switch transistor and the second terminal of the switch transistor in response to a first switch enable signal; a switch control module, configured to control a control terminal voltage of the switch transistor according to a voltage of the power terminal in response to the first switch enable signal; When the first switch enable signal is invalid, the connection module controls the path between the control end of the switch transistor and the second end of the switch transistor to be connected, and the switch control module disconnects the path between the control end of the switch transistor and the power supply end.

2. The switching circuit according to claim 1, wherein: When the first switch enable signal is valid, the switch control module controls the control terminal voltage of the switch transistor to be less than the voltage of the power terminal and greater than the voltage of the ground terminal, and the switch transistor operates in the linear region.

3. The switching circuit according to claim 2, wherein: The switch control module includes a first connection unit, a resistance voltage dividing unit and a second connection unit, and the control end of the switch transistor is connected to the resistance voltage dividing unit; The first connection unit is used to control the connection and disconnection of the path between the first end of the resistor voltage dividing unit and the power supply end in response to the first switch enable signal; The second connection unit is used to control the connection and disconnection of the path between the second end of the resistance voltage dividing unit and the ground end in response to the first switch enable signal.

4. The switching circuit according to claim 3, wherein: The first connection unit includes a third transistor and a fourth transistor; The first end of the third transistor is connected to the power supply end, the second end of the third transistor is connected to the second end of the fourth transistor, and the first end of the fourth transistor is connected to the first end of the resistance voltage dividing unit; The control terminal of the third transistor is used to receive a first enable signal, and the control terminal of the fourth transistor is used to receive a second enable signal. Levels of the first enable signal and the second enable signal are opposite to that of the first switch enable signal.

5. The switching circuit according to claim 4, wherein: The first enable signal is a level signal of a first voltage domain, and the second enable signal is a level signal of a second voltage domain; The first voltage domain is a voltage domain corresponding to the first end of the switch transistor, and the second voltage domain is a voltage domain corresponding to the second end of the switch transistor.

6. The switching circuit according to claim 3, wherein: The second connection unit includes a fifth transistor; The second end of the fifth transistor is connected to the second end of the resistor voltage divider unit, the first end of the fifth transistor is connected to the ground end, and the control end of the fifth transistor is used to access the first switch enable signal.

7. The switching circuit according to claim 3, wherein: The resistance voltage dividing unit includes a sixth transistor and a first resistor; The second end of the sixth transistor is connected to the first connection unit, the first end of the sixth transistor is connected to the first end of the first resistor, and the second end of the first resistor is connected to the second connection unit; The control terminal of the switch transistor is connected to a first node between the sixth transistor and the first resistor, and the control terminal of the sixth transistor is used to access a preset bias voltage when the first switch enable signal is valid.

8. The switching circuit according to claim 7, wherein: The switch control module further includes a bias voltage generating unit, wherein the bias voltage generating unit is connected to the control terminal of the sixth transistor; When the first switch enable signal is valid, the bias voltage generating unit inputs the preset bias voltage to the control terminal of the sixth transistor.

9. The switching circuit according to claim 8, wherein: The bias voltage generating unit includes a seventh transistor, an eighth transistor, a ninth transistor and a plurality of tenth transistors; The first end of the seventh transistor is connected to the power supply end, the second end of the seventh transistor is connected to the bias current, and the control end of the seventh transistor is connected to the second end of the seventh transistor; The first terminal of the eighth transistor is connected to the power supply terminal, and the control terminal of the eighth transistor is connected to the control terminal of the seventh transistor; A first end of the ninth transistor is connected to the power supply end, a second end of the ninth transistor is connected to the control end of the seventh transistor, and the control end of the ninth transistor is used to receive the first switch enable signal; A plurality of the tenth transistors are connected in series between the second end of the eighth transistor and the ground end, and the control end of each of the tenth transistors is connected to the second end thereof; Wherein, the control end of the sixth transistor is connected to the second end of the eighth transistor.

10. The switching circuit according to any one of claims 1 to 9, characterized in that: The communication module includes a first transistor and a second transistor; The first end of the first transistor is connected to the control end of the switch transistor, the second end of the first transistor is connected to the second end of the second transistor, and the first end of the second transistor is connected to the second end of the switch transistor; The control terminal of the first transistor is used to access the first switch enable signal, and the control terminal of the second transistor is used to access the first switch enable signal.

11. The switching circuit according to any one of claims 1 to 9, wherein: The substrate of the switch transistor is connected to the second end of the switch transistor.

12. A power supply circuit, characterized in that: The switch circuit comprises the switch circuit according to any one of claims 1 to 10.

13. The power supply circuit according to claim 12, wherein: The switch circuit is used to output a target voltage according to the voltage of the power supply terminal, and the power supply circuit further includes: a low-dropout linear regulator, configured to output a fourth voltage based on the third voltage; a maximum voltage selection circuit, configured to output a maximum voltage according to the power supply terminal voltage and the fourth voltage; When the power supply voltage is powered off, the maximum voltage is configured to turn off the switch circuit; when the third voltage is powered off, the maximum voltage is configured to turn off the low voltage difference linear regulator.

14. A chip, characterized in that: The device comprises a switching circuit according to any one of claims 1 to 11.

15. An electronic device, characterized in that: Comprising the chip as claimed in claim 14.

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