A high-performance low-power LDPC decoder

Abstract

This application discloses a high-performance, low-power LDPC decoder, including a parity check matrix selection module, a variable node management module, a parity node management module, a front node switching network, a parity node and variable node update module, a back node switching network, and a cyclic redundancy check (CRC) module. The parity node and variable node update module employs an optimized read / write order for the upper and lower rows of the parity check matrix, allowing the decoding of the next large row to begin before the decoding of each large row is fully completed, without sacrificing decoding accuracy. Both the front and back node switching networks are implemented using two selectors, employing shifting and concatenation to achieve a simple and efficient hardware implementation of front and back node switching. The presence or absence of read / write conflicts determines whether each SRAM is single-port or dual-port, adjusting the aspect ratio of each SRAM to reduce its area footprint.

Description

Technical Field

[0001] This application relates to the field of digital communication technology, and in particular to an LDPC decoder. Background Technology

[0002] Channel coding and decoding is a crucial component of modern digital communication systems, and LDPC (low-density parity-check code) is one of the significant achievements in this field. LDPC codes can provide coding performance close to the Shannon limit while maintaining low complexity, and have been widely used in 5G high-speed data transmission scenarios.

[0003] In 5G communication, numerous high-speed mobile and complex channel communication scenarios exist, making error correction particularly important. LDPC codes use iterative decoding algorithms to correct errors in received data, and their iterative nature is beneficial for improving error correction capabilities. For ease of hardware implementation, most LDPC decoders currently employ the min-sum algorithm and its derivatives. While the min-sum algorithm sacrifices some error correction performance, it completes the core decoding work solely through sorting the minimum and second-minimum values, making the algorithm less sensitive to channel parameter estimation.

[0004] Two key considerations for LDPC decoders are as follows: First, the impact of the input signal bit width and the intermediate result bit width on error correction capability; generally, a larger bit width results in stronger error correction capability. Second, the impact of decoding parallelism on decoding iteration speed; generally, a higher parallelism results in faster decoding iteration speed. However, in hardware implementation, larger bit widths and parallelisms lead to a dramatic increase in chip area. How to select appropriate bit widths and parallelisms to satisfy both error correction capability requirements and chip area and speed requirements is a pressing technical problem that needs to be solved. Summary of the Invention

[0005] The technical problem to be solved by this application is: how to speed up the decoding speed, reduce the power consumption, and improve the utilization of hardware resources in an LDPC decoder.

[0006] To address the aforementioned technical problems, this application proposes a high-performance, low-power LDPC decoder, including a parity check node and a variable node update module. The LDPC decoder decodes based on a parity check matrix; the parity check matrix is ​​obtained by amplifying the base matrix using an expansion factor zc, followed by cyclic shifting using an initial offset shift; each row of the base matrix is ​​amplified to zc rows in the parity check matrix, these zc rows being called a large row of the parity check matrix; columns with elements "1" in each row of the parity check matrix are valid columns; each row of the parity check matrix is ​​a parity check node, and each column in each row is a variable node. The parity check node and variable node update module has p independent expansion factor processing units; the LDPC decoder simultaneously processes a large row or a portion of the parity check matrix; when p ≥ zc, the LDPC decoder processes a large row of the parity check matrix in only one round, and the number of rows processed simultaneously is zc; when k × p < zc ≤ (k + 1) × p, k is a positive integer, the LDPC decoder processes a large row of the parity check matrix in k + 1 rounds; the number of rows processed simultaneously in the first k rounds is p, and the number of rows processed simultaneously in the k + 1 round is zc - k × p. The check node and variable node update module is used to control the updating of VN-PART1 variable nodes and check nodes in multiple rows of the parity check matrix that are processed simultaneously. When the valid columns of two adjacent rows in the parity check matrix are repeated or partially repeated, the check node and variable node update module first writes the VN-PART1 variable nodes of the repeated or partially repeated valid columns for the upper row, and then writes the VN-PART1 variable nodes of the non-repeating valid columns for the lower row. The check node and variable node update module first reads the VN-PART1 variable nodes of the non-repeating valid columns for the lower row, and then reads the VN-PART1 variable nodes of the repeated or partially repeated valid columns.

[0007] Furthermore, for VN-PART1 variable nodes in adjacent rows of the parity check matrix where valid columns are repeated or partially repeated, the check node and variable node update module begins reading the VN-PART1 variable nodes in the same valid column of the lower row after writing the VN-PART1 variable node of a certain valid column in the upper row, regardless of whether all variable nodes in the upper row have been written.

[0008] Furthermore, the verification node and variable node update module also includes a sixth SRAM for caching intermediate results of the VN-PART1 variable node; the sixth SRAM is two single-port SRAMs using a ping-pong storage architecture; each single-port SRAM has a depth of 19 and a bit width of p×n bits; where n = the capacity of the SRAM storing the source data of the VN-PART1 variable node for this LDPC decoding ÷ 384.

[0009] Furthermore, p can be a positive integer that is divisible by 384.

[0010] Furthermore, the LDPC decoder also includes a front-node switching network; the front-node switching network uses a 51-to-1 selector and a 384-to-1 selector to handle the exchange of source data for the VN-PART1 variable nodes through shifting and concatenation. The workflow of the front-node switching network is as follows: The input to the front-node switching network is a 384×n bit data, represented by 384 indices from 0 to 383, with n bits as a unit; the input from index 0 to zc-1 is useful data, and the input from index zc to 383 is useless data. The input data from index 0 to zc-1 is shifted left to the highest position, i.e., shifted left by (384-zc)×n bits, with low-order bits padded with 0, resulting in a new 384×n bit data; this left shift operation is implemented using a 51-to-1 selector. The left-shifted data is placed in the lower 384×n bits, and the original input data is placed in the upper 384×n bits, resulting in a concatenated 2×384×n bit data. The concatenated data is shifted right by (384 - zc + shift) × n bits, and then the least significant p × n bits are extracted. The p × n bits correspond to the data between the index shift and shift + p - 1 in the concatenated data. This right shift operation is implemented using a 384-to-1 selector.

[0011] Furthermore, the LDPC decoder also includes a post-node switching network; the post-node switching network uses a p-to-1 selector and a 384-to-1 selector to handle the exchange of new data for the VN-PART1 variable nodes through shifting and concatenation. The workflow of the post-node switching network is as follows: The input p×n-bit new data of the VN-PART1 variable nodes is divided into p groups according to n-bit units. A 1-bit valid indicator signal is added to each group to obtain p×(n+1)-bit extended data. The extended data is left-shifted by zc_ini, where zc_ini is the starting position of the exchanged new data of the VN-PART1 variable nodes written back to the SRAM; zc_ini takes a value between 0 and 383, and this left shift operation is implemented by a 384-to-1 selector; after left shifting, zeros are padded to obtain 384×(n+1)-bit left-shifted data; the left-shifted data is represented by indices from 0 to 383 according to n+1-bit units; the unit with a valid indicator signal of 1 is called valid data. When there is no valid data between the indices zc-1 and 383 of the left-shifted data, the remaining portion of the left-shifted data after removing the valid indicator signals in each cell is used as the write data to be written back to SRAM. When there is valid data between the indices zc-1 and 383 of the left-shifted data, the extended data is right-shifted by (zc - zc_ini) × (n + 1) bits; the right-shift value is between 0 and p-1, and this right-shift operation is implemented by a p-to-1 selector; after right-shifting, zeros are padded to obtain 384 × (n + 1) bits of right-shifted data; if the valid indicator signal of a cell in the right-shifted data is 1, the corresponding cell is used as the write data to be written back to SRAM after removing the valid indicator signal; if the valid indicator signal of a cell in the left-shifted data is 1, the corresponding cell is used as the write data to be written back to SRAM after removing the valid indicator signal; otherwise, the corresponding cell for the write data to be written back to SRAM is filled with 0; thus, the complete write data to be written back to SRAM is obtained.

[0012] Furthermore, the LDPC decoder also includes a variable node management module; the variable node management module includes: a single-port first static random access memory (SRAM) for storing the VN-PART1 variable node source data for the next LDPC decoding, a dual-port second SRAM for storing the VN-PART1 variable node source data for the current LDPC decoding, and two single-port third SRAMs for storing the VN-PART2 variable node source data to be decoded in a ping-pong storage manner.

[0013] Further, the operation of the variable node management module is as follows: the source data of the VN-PART1 variable node from the first LDPC decoding is input into the first SRAM for storage, and the source data of the VN-PART2 variable node from the first LDPC decoding is input into one of the third SRAMs for storage; if the LDPC decoder is idle at this time, the first SRAM forwards the source data of the VN-PART1 variable node from the first LDPC decoding to the second SRAM, and the first LDPC decoding is started; during the first LDPC decoding process, the LDPC decoder interacts with one of the second and third SRAMs; when the first SRAM completes forwarding, the source data of the VN-PART1 variable node from the second LDPC decoding is input into the first SRAM for storage, and the source data of the VN-PART2 variable node from the second LDPC decoding is input into the second of the third SRAMs for storage; after the first LDPC decoding is completed, the first SRAM forwards the source data of the VN-PART1 variable node from the second LDPC decoding to the second SRAM, and the second LDPC decoding is started, and the LDPC decoder interacts with the second and third SRAMs.

[0014] Furthermore, the LDPC decoder also includes a parity node management module; the parity node management module includes: a fourth SRAM for caching the minimum, second smallest, and minimum value column indices of all rows of the parity check matrix, i.e., all parity check nodes; and a fifth SRAM for caching the sign variables of the expansion factors of each valid column of each row of the parity check matrix. The fourth SRAM is a single-port SRAM with a depth of 46 × 384 ÷ p and a bit width of m × p bits; or, the fourth SRAM is 384 ÷ p single-port SRAMs with a depth of 46 and a bit width of m × p bits; where m represents the total number of bits for the minimum, second smallest, and minimum value column indices of each row of the parity check matrix, i.e., each parity check node. The fifth SRAM is a dual-port SRAM with a depth of 274 and a bit width of 384 bits; or, the fifth SRAM is 384 ÷ p dual-port SRAMs with a depth of 274 and a bit width of p bits.

[0015] Furthermore, the LDPC decoder also includes a Cyclic Redundancy Check (CRC) module; the CRC module is used to perform two CRC checks on the LDPC decoding result; only when two consecutive CRC checks are correct is the LDPC decoding determined to be correct.

[0016] The technical advantages achieved by this application are as follows: The parity check node and variable node update modules employ an optimized read / write order for adjacent upper rows and lower rows of valid columns in the parity check matrix that have duplicates or partial duplicates. This allows for the early commencement of decoding the next row before the decoding of the upper row of the parity check matrix is ​​fully completed, without sacrificing LDPC decoding accuracy. Both the front-node and back-node switching networks are implemented using two selectors, employing shifting and concatenation methods to achieve a simple and efficient hardware implementation of front-node and back-node switching. The aspect ratio of each SRAM is adjusted based on the presence of read / write conflicts to reduce its area footprint. The CRC check module uses a two-step check decision strategy, further reducing the false positive rate in complex scenarios such as 5G RedCap. In summary, this application offers advantages such as fast decoding speed, small overall area, low power consumption, and high hardware resource utilization. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall structure of the high-performance, low-power LDPC decoder proposed in this application.

[0018] Figure 2 yes Figure 1 A structural diagram of the variable node management module in the document.

[0019] Figure 3 yes Figure 1 A schematic diagram of the structure of the verification node management module.

[0020] Figure 4 yes Figure 1 A schematic diagram of the workflow of the front-node switching network.

[0021] Figure 5 yes Figure 1 The diagram shows the structure of the verification node and variable node update module.

[0022] Figure 6 yes Figure 1 The diagram illustrates three possible scenarios for the data after the last node in the network shifts left.

[0023] The attached diagrams are labeled as follows: 1. Parity check matrix selection module; 2. Variable node management module; 3. Check node management module; 4. Front node exchange network; 5. Check node and variable node update module; 6. Back node exchange network; 7. CRC check module. Detailed Implementation

[0024] Please see Figure 1The high-performance, low-power LDPC decoder proposed in this application includes a parity check matrix (PCM) selection module 1, a variable node management module 2, a check node management module 3, a front node exchange network 4, a check node and variable node update module 5, a back node exchange network 6, and a CRC (cyclic redundancy check) verification module 7.

[0025] The LDPC decoder decodes based on a parity check matrix H. In the parity check matrix H, only a very small number of elements are "1", and the vast majority are zero. The number of "1"s in each row is called the row weight, and the column number corresponding to each "1" is the valid column number of that row. The parity check matrix H is not composed of random 0s and 1s, but rather of circulant permutation matrices (CPMs) or zero matrices. The CPMs are obtained by cyclically shifting a zc×zc identity matrix to the right, where zc is the expansion factor of the LDPC decoder, and this shift value is the initial offset shift. Essentially, the parity check matrix H is obtained by enlarging the base graph using the expansion factor zc, and then cyclically shifting it using the initial offset shift. Each row in the base matrix is ​​enlarged to zc rows in the parity check matrix; these zc rows are called a large row of the parity check matrix. The maximum value of the expansion factor zc is 384.

[0026] A parity check matrix H can be represented by a Tanner graph. Each row of the parity check matrix H corresponds to a check node (CN) in the Tanner graph. Each column in each row of the parity check matrix H corresponds to a variable node (VN) in the Tanner graph. Assuming the parity check matrix H has x rows and y columns, then the corresponding Tanner graph has y variable nodes on one side and x check nodes on the other side. The column and row containing the element "1" in the parity check matrix H are represented in the Tanner graph as a line connecting the corresponding variable node and check node. The number of elements with a value of "1" in the parity check matrix H is equal to the number of lines in the corresponding Tanner graph.

[0027] The parity check matrix selection module 1 is used to look up the row weight, valid column number, and initial offset shift of the parity check matrix H according to whether the base matrix of the parity check matrix H is BG1 or BG2. The BG1 base matrix is ​​46 rows × 68 columns. The BG2 base matrix is ​​42 rows × 52 columns. The parity check matrix selection module 1 passes the valid column number to the variable node management module 2 and the initial offset shift to the previous node exchange network 4 and the next node exchange network 6.

[0028] The variable node management module 2 uses a single-port first SRAM (Static Random Access Memory) to store the VN-PART1 variable node source data for the next LDPC decoding, a dual-port second SRAM to store the VN-PART1 variable node source data for the current LDPC decoding, and two single-port third SRAMs in a ping-pong storage manner to store the VN-PART2 variable node source data to be decoded. The variable node management module 2 receives the valid column number from the parity check matrix selection module 1, uses the valid column number as the read address to read the VN-PART1 variable node source data from the second SRAM, and then transmits the read VN-PART1 variable node source data to the front node switching network 4. The variable node management module 2 receives the new VN-PART1 variable node data output from the rear node switching network 6 after switching, stores it back in the second SRAM, and completes the update of the VN-PART1 variable node data.

[0029] During LDPC decoding, variable nodes are categorized into two types, VN-PART1 and VN-PART2, based on their column index. If the column index is less than 26, it is a VN-PART1 variable node; otherwise, it is a VN-PART2 variable node. VN-PART1 variable nodes require data updates, meaning both read and write operations are performed on their data. VN-PART2 variable nodes do not require data updates; they are only used as initial values ​​for check nodes, meaning only read operations are performed on their data.

[0030] The parity check node management module 3 is used to cache the minimum, second minimum, and minimum column indices of all rows (i.e., all parity check nodes) of the parity check matrix H. A row of the base matrix is ​​expanded by the expansion factor zc to obtain zc rows in the parity check matrix H, corresponding to zc parity check nodes. Each parity check node has minimum, second minimum, and minimum column indices. The parity check node management module 3 is also used to cache the sign variable (his_sign) of the expansion factor for each valid column of each row of the parity check matrix H. In each row of the base matrix, the column corresponding to "1" is a valid column of that row. Assuming a row of the base matrix has v valid columns, after being expanded by the expansion factor zc, it becomes zc rows in the parity check matrix H. Each of these zc rows has v valid columns, with a total of v × zc elements "1", corresponding to v × zc expansion factor sign variables with "1" elements. A parity check matrix H uses the same expansion factor, but the sign variables of the expansion factor at different element positions may be different. During each iteration update of the verification node, the verification node and variable node update module 5 reads the sign variables of the minimum and second smallest values ​​of the corresponding verification node and the expansion factors of the valid columns in that row, stored in the verification node management module 3, as part of the input information for the verification node update. After each iteration update of the verification node is completed, the verification node and variable node update module 5 writes the sign variables of the updated minimum and second smallest values ​​of the verification node and the expansion factors of the valid columns in that row into the verification node management module 3.

[0031] The preceding node exchange network 4 is used to exchange the source data of the VN-PART1 variable node by using a 51-to-1 selector and a 384-to-1 selector through shifting and splicing before each iteration update of the VN-PART1 variable node, based on the expansion factor zc and the initial offset shift. The exchanged VN-PART1 variable node source data is then passed to the verification node and the variable node update module 5.

[0032] The check node and variable node update module 5 is used to control the updating of the VN-PART1 variable nodes and check nodes in LDPC decoding. The update process is roughly described as follows: The variable node management module 2 reads the VN-PART1 variable node source data of this LDPC decoding and passes it to the front node switching network 4. The front node switching network 4 exchanges the VN-PART1 variable node source data, and the exchanged VN-PART1 variable node source data is passed to the check node and variable node update module 5. The check node and variable node update module 5 reads from the check node management module 3 the minimum value, the second smallest value, the minimum value column index, and the sign variables of the expansion factors of the effective columns in these rows of the parity check matrix H that are processed simultaneously (corresponding to multiple check nodes). The parity check node and variable node update module 5 updates the parity check nodes and variable nodes of the simultaneously processed rows of the parity check matrix H, using the minimum sum algorithm as the smallest granularity. Based on the minimum, second minimum, minimum value column index, and sign variables of the expansion factors of the valid columns in these rows, along with the exchanged VN-PART1 variable node source data, it updates these data. The resulting updated minimum, second minimum, minimum value column index, and sign variables of the expansion factors of the valid columns in these rows are then passed to the parity check node management module 3. The resulting updated VN-PART1 variable node data is then passed to the subsequent node exchange network 6. The subsequent node exchange network 6 exchanges the new VN-PART1 variable node data, and the exchanged new VN-PART1 variable node data is then passed to the variable node management module 2.

[0033] The check node and variable node update module 5 has p independent expansion factor processing units (CNPs). To meet the performance requirements of the LDPC decoding algorithm, the number of parallel expansion factor processing units, p, should be a number divisible by 384, such as 384, 192, 96, 48, etc. The LDPC decoder simultaneously processes multiple rows of the parity check matrix H obtained by amplifying a row of the base matrix through an expansion factor zc. The number of rows processed simultaneously depends on the values ​​of p and zc. When p ≥ zc, the LDPC decoder processes only one large row (zc rows) of the parity check matrix H in one round, processing zc rows simultaneously. When p < zc, the LDPC decoder processes the large row of the parity check matrix in multiple rounds. For example, when p < zc ≤ 2p, the LDPC decoder processes rows 1 to p of the large row of the parity check matrix H simultaneously in the first round, and rows p+1 to zc of the large row of the parity check matrix H simultaneously in the second round. For example, when 2p < zc ≤ 3p, the LDPC decoder processes rows 1 to p of a large row of the parity check matrix H in the first round, rows p+1 to 2p of a large row of the parity check matrix H in the second round, and rows 2p+1 to zc of a large row of the parity check matrix H in the third round.

[0034] The post-node switching network 6 is used to exchange the new data of the VN-PART1 variable nodes after each iteration update, based on the spread factor zc and the initial offset shift. It employs a p-to-1 selector and a 384-to-1 selector, using shifting and concatenation to achieve this. The exchanged new data is then passed to the variable node management module 2 as input for the next iteration's decoding. The post-node switching network 6 also maps the exchanged new data—may it be mapped to 1 if the new data is ≤0, and to 0 if it is >0—to obtain the LDPC decoding result, which is then passed to the CRC verification module 7.

[0035] The CRC check module 7 performs two CRC checks on the LDPC decoding result. Only when two consecutive CRC checks are correct is the LDPC decoding considered correct. In complex network environments, erroneous data in the channel has a very small probability of being judged as correct by a single CRC check. The double CRC check mechanism reduces the false positive rate in complex 5G RedCap scenarios.

[0036] The variable node management module 2 in this application will be described in detail below.

[0037] Traditional LDPC decoders use a ping-pong storage architecture for all variable nodes, employing two identical sets of SRAM to store the "ping" variable node data and the "pong" variable node data respectively, without distinguishing between VN-PART1 variable nodes and VN-PART2 variable nodes.

[0038] Please see Figure 2 The variable node management module 2 of this application manages variable nodes according to VN-PART1 and VN-PART2 types respectively. The first SRAM is used to receive and store the source data of the VN-PART1 variable nodes for the next LDPC decoding in advance; the second SRAM is used to store the source data of the VN-PART1 variable nodes for the current LDPC decoding; and the third SRAM is used to store the source data of the VN-PART2 variable nodes to be decoded in a ping-pong storage manner. The first SRAM does not directly participate in the computation and reading during the LDPC decoding process, so there is no read-write conflict problem; it is implemented using a single-port SRAM. The second SRAM involves read and write operations during the LDPC decoding process, so it is implemented using a dual-port SRAM. The third SRAM is only read during the LDPC decoding process, so there is no read-write conflict problem; it uses two single-port SRAMs to form a ping-pong storage architecture, referred to as Third SRAM One and Third SRAM Two, respectively. Due to the extensive use of single-port SRAM, the variable node management module 2 of this application can reduce the total area by approximately 40% without sacrificing LDPC decoding performance.

[0039] The operation of the variable node management module 2 in this application is described as follows: The source data of the VN-PART1 variable node from the first LDPC decoding is input into the first SRAM for storage, and the source data of the VN-PART2 variable node from the first LDPC decoding is input into one of the third SRAMs for storage. If the LDPC decoder is idle at this time, the first SRAM forwards the VN-PART1 variable node source data from the first LDPC decoding to the second SRAM, and the first LDPC decoding begins. During the first LDPC decoding process, the LDPC decoder interacts with one of the second and third SRAMs. When the first SRAM completes forwarding, the source data of the VN-PART1 variable node from the second LDPC decoding is input into the first SRAM for storage, and the source data of the VN-PART2 variable node from the second LDPC decoding is input into the second of the third SRAMs for storage. After the first LDPC decoding is completed, the first SRAM forwards the VN-PART1 variable node source data from the second LDPC decoding to the second SRAM, and the second LDPC decoding begins, with the LDPC decoder interacting with the second and second of the third SRAMs.

[0040] The following is a detailed description of the verification node management module 3 in this application.

[0041] Please see Figure 3 The parity check node management module 3 includes: a fourth SRAM for caching the minimum, second minimum, and minimum column index of all rows (i.e., all check nodes) of the parity check matrix H; and a fifth SRAM for caching the symbolic variables of the expansion factors of each valid column of each row of the parity check matrix H.

[0042] In LDPC decoding, the minimum, second minimum, and minimum column indices of each row (i.e., each parity check node) of the parity check matrix H total m bits. According to the LDPC decoding algorithm, the maximum value of the expansion factor zc is 384, and the maximum number of rows in the base matrix is ​​46. Therefore, the total amount of data that the fourth SRAM needs to store is 384 × 46 × m = 17664 × m bits. When the parity check node and variable node update module 5 use p independent expansion factor processing units (CNPs), the fourth SRAM needs to support p-way concurrency, meaning it needs to support at least p × m bits of data read / write per cycle. The fourth SRAM has a long read / write interval, so there will be no read / write conflict issues, and a single-port SRAM can be used. From a hardware implementation perspective, for storing the same amount of data, the closer the aspect ratio of the SRAM is to 1:1, the smaller its physical area. The length of the SRAM refers to its depth, and the width refers to the data bit width. In traditional LDPC decoders, the fourth SRAM is implemented using a single-port SRAM with a depth of 46 and a bit width of 384×m bits. The value of m is typically between 15 and 20, resulting in a significant difference in the length and width of the fourth SRAM. In this application, the fourth SRAM is implemented using a single-port SRAM with a depth of 46×384÷p and a bit width of m×p bits. Alternatively, the fourth SRAM can be implemented using 384÷p single-port SRAMs with a depth of 46 and a bit width of m×p bits. It can be observed that the aspect ratio of the fourth SRAM is closer to that of existing technologies, which can reduce the area of ​​the fourth SRAM by approximately 10%. The specific selection of the two fourth SRAMs provided in this application depends on the circuit synthesis results. Circuit synthesis refers to the process of automatically converting high-level RTL (Register Transfer Level) code of circuit behavior into a gate-level netlist composed of basic logic units.

[0043] In LDPC decoding, the sign variable of the expansion factor at each element position of the parity check matrix H is 1 bit. According to the LDPC decoding algorithm, the maximum value of the expansion factor zc is 384, and the maximum total number of effective columns in all rows of the base matrix is ​​316. Therefore, the total amount of data that the fifth SRAM needs to store is 384 × 316 = 121344 bits. When the parity check node and variable node update module 5 use p independent expansion factor processing units, the fifth SRAM needs to support p-way concurrent operation, meaning that the fifth SRAM needs to support at least p bits of data read / write per cycle. Since the fifth SRAM needs to be read and written simultaneously in continuous time, only a dual-port SRAM can be used. From a hardware implementation perspective, for storing the same amount of data, the closer the aspect ratio of the SRAM is to 1:1, the smaller its physical area. The length of the SRAM refers to its depth, and the width refers to the data bit width. In traditional LDPC decoders, the fifth SRAM is implemented using a dual-port SRAM with a depth of 316 and a bit width of 384 bits. When selecting a fifth SRAM, it's necessary to analyze the actual number of columns that need to be stored, which is likely less than the number of valid columns specified by the LDPC algorithm. In this application, the number of valid columns to be read is 316 - 42 = 274, where 42 are the parity bits corresponding to column numbers 26 to 67 of BG1, which do not need to be updated, and the fifth SRAM does not need to store these valid columns. Therefore, the fifth SRAM is implemented using a dual-port SRAM with a depth of 274 and a bit width of 384 bits. Alternatively, the fifth SRAM can be implemented using 384 ÷ p dual-port SRAMs with a depth of 274 and a bit width of p bits. By removing the valid columns that do not need to be stored, the area of ​​the fifth SRAM can be reduced by about 15% compared to the prior art. The specific selection of the two fifth SRAMs provided in this application depends on the circuit synthesis results.

[0044] The front node switching network 4 in this application will be described in detail below.

[0045] Before LDPC decoding begins, the source data of the VN-PART1 variable nodes to be decoded needs to be swapped. The swapped VN-PART1 variable node source data will have its data header offset to the initial offset `shift` position. The initial offset `shift` is an integer, ranging from 0 to 383. The expansion factor `zc` supports 51 configuration values, also integers, ranging from 0 to 383. The entire parity check matrix H uses the same expansion factor `zc`. The same row in the parity check matrix H uses the same initial offset `shift`. Furthermore, the `shift` value of each row in the parity check matrix H is always less than the `zc` value.

[0046] The swapped source data for the VN-PART1 variable nodes is ordered as {data from index shift to zc-1, data from index 0 to shift-1, data from index zc to 383}, where each index corresponds to n bits of data. Data from index zc to 383 is invalid. The data from index shift to zc-1 needs to be placed before the data from index 0 to shift-1, skipping over the data from index zc to 383; this is called "flipping". Shift and zc are two variables for the hardware, and under different configurations, they are only constrained by their numerical relationship. Hardware struggles to handle variables without a fixed mathematical formula. In traditional LDPC decoders, the front-node switching network needs to determine the flipping position, corresponding to the data at index zc-1. After determining the flipping position, it also needs to determine the length of the truncated data after the flip, corresponding to the data from index 0 to shift-1. The numerous configuration combinations of zc and shift necessitate the use of a massive selector in front-node switching network implementations, resulting in high hardware overhead and significant adverse effects on timing and area considerations during hardware implementation.

[0047] Based on the characteristics of zc and shift in the LDPC decoding algorithm, this application implements the front node switching network 4 using a 51-to-1 selector and a 384-to-1 selector. The front node switching network 4 receives the VN-PART1 variable node source data read from the second SRAM in the variable node management module 2 and the initial offset shift transmitted from the parity check matrix selection module 1. The shift logic is implemented using a 51-to-1 selector and a 384-to-1 selector, and combined with fixed-length concatenation and truncation operations, the hardware handling of the loop-flipping problem at zc-1 is avoided. The data left and right shifts and fixed-length data concatenation and truncation implemented by the selectors in this application have minimal hardware overhead, greatly simplifying the complexity of the algorithm's hardware implementation.

[0048] Please see Figure 4 The workflow of the front-node switching network 4 is described below. For example, if the bit width of the second SRAM is 384×n bits, then the input of the front-node switching network 4 is a 384×n bit data.

[0049] Figure 4 The first line represents the input data of the front-node switching network 4, with a length of 384 × n bits. Assuming n bits form a unit, this input data can be represented by 384 indices from 0 to 383, with the left side representing the high-order bit and the right side representing the low-order bit. The input from index 0 to zc-1 is the useful data, while the input from index zc to 383 is the useless data. zc represents the expansion factor of the LDPC decoding algorithm.

[0050] Figure 4 The second line indicates that the input data from index 0 to zc-1 is shifted left to the highest position, that is, shifted left by (384 - zc) × n bits, with the low bits padded with 0, resulting in a new 384 × n bit data. Since the LDPC decoding algorithm limits the extension factor zc to a maximum of 51 configuration values, the above left shift function can be achieved by using a 51-to-1 selector.

[0051] Figure 4 The third line in the code indicates that the two data segments above are concatenated, the data shifted to the left (as shown in the second line) is placed in the lower 384×n bits, and the original input (as shown in the first line) is placed in the upper 384×n bits, resulting in a 2×384×n bit data.

[0052] Figure 4 Line 4 in the diagram represents the result after processing by the front-node switching network 4. The specific process is as follows: the concatenated 2×384×n bit data is right-shifted by (384 - zc + shift)×n bits, and then the least significant p×n bits are extracted. Here, the p×n bits correspond to the data between index shift and shift+p-1 in line 4. Since 384 - zc + shift can only take values ​​between 0 and 383, the right shift can be implemented using a 384-to-1 selector.

[0053] By performing the four steps described above, the desired exchange of source data between the VN-PART1 variable nodes can be achieved, while avoiding the problem of looping at zc-1 in the previous node exchange network 4.

[0054] The following is a detailed description of the verification node and variable node update module 5 in this application.

[0055] Please see Figure 5 The parity check node and variable node update module 5 includes: p independent expansion factor processing units (CNPs) and a sixth SRAM for caching intermediate results of VN-PART1 variable nodes. The p independent expansion factor processing units process a large row or a portion of the parity check matrix H in parallel, with the number of rows processed simultaneously depending on the values ​​of p and zc. When zc ≤ p, the update process is performed in one round. When zc > p, the update process is performed in multiple rounds. The sixth SRAM consists of two single-port SRAMs using a ping-pong storage architecture. This ping-pong storage method avoids the additional time loss caused by reading and writing intermediate results of VN-PART1 variable nodes to different rows of the parity check matrix H. Each single-port SRAM has a depth of 19 and a bit width of p × n bits. The depth is defined as 19 based on the maximum row weight of 19 in the base matrix.

[0056] Assume the base matrix of the parity check matrix H is BG2. The effective column numbers to be processed in rows 0 to zc-1 (called the first major row) of the parity check matrix H obtained by amplifying the first row of the base matrix using an expansion factor zc are {0,3,4,5,6,7,8,9,11,12}. Similarly, the effective column numbers to be processed in rows zc to 2×zc-1 (called the second major row) of the parity check matrix H obtained by amplifying the second row of the base matrix using an expansion factor zc are {1,2,4,5,6,7,8,9,10,13}. Each column in each row of the parity check matrix H represents a variable node. If the parity check matrix H has x rows × y columns, then each row has y variable nodes. Each major row of the parity check matrix H refers to row zc of the parity check matrix H obtained by amplifying a row of the base matrix using an expansion factor zc, and has a total of zc×y variable nodes.

[0057] In traditional LDPC decoders, when updating parity check nodes and variable nodes based on the min-sum algorithm, rows 0 to zc-1 and rows zc to 2×zc-1 of the parity check matrix H are read and written sequentially according to the valid column numbers of each row. That is, the read / write order of variable nodes in rows 0 to zc-1 is {0,3,4,5,6,7,8,9,11,12}, and the read / write order of variable nodes in rows zc to 2×zc-1 is {1,2,4,5,6,7,8,9,10,13}. In the hardware implementation of LDPC decoding, updating variable nodes requires a certain amount of time, i.e., the delay between data reading and data writing. The input of the lower row decoder depends on the output of the upper row decoder, and multiple variable nodes to be read in the lower row decoder may be duplicates of those in the upper row. For example, the variable nodes in rows 0 to zc-1 and rows zc to 2×zc-1 with valid columns 4, 5, 6, 7, 8, and 9 are duplicates. Therefore, it is necessary to wait for the variable nodes with valid columns 4, 5, 6, 7, 8, and 9 in rows 0 to zc-1 to be read and written before the reading and writing of the variable nodes with valid columns 4, 5, 6, 7, 8, and 9 in rows zc to 2×zc-1 can begin. The disadvantage is that the data reading time for the lower rows of the parity check matrix H is delayed. If this time is wasted for every two adjacent rows in the parity check matrix H, it will significantly increase the LDPC decoding time.

[0058] In this application, when implementing the check node and variable node update module 5, the write order of variable nodes in rows 0 to zc-1 is {4,5,6,7,8,9,0,3,11,12}, and the read order of variable nodes in rows zc to 2×zc-1 is {1,2,10,13,4,5,6,7,8,9}. That is, if there is a duplicate or partial duplicate of valid columns in adjacent lower and upper rows of the parity check matrix H, the upper row first writes the variable nodes of the duplicate or partially duplicated valid columns, and then writes the variable nodes of the non-duplicate valid columns; the lower row first reads the variable nodes of the non-duplicate valid columns, and then reads the variable nodes of the duplicate or partially duplicated valid columns. The variable node read and write order in this application ensures, as far as possible, that when decoding each row of the parity check matrix H begins, the variable node data read is the latest, meaning that when reading the variable nodes of the duplicate valid columns in the lower row begins, the upper row has already completed writing the corresponding duplicate valid column variable nodes. In this way, the lower row can begin reading the variable nodes of the duplicate valid columns without waiting for the variable nodes of the upper row to be fully updated. It only needs to ensure that the variable node data of the corresponding duplicate valid columns read from the upper row is up-to-date. Even if the upper row is still updating its variable nodes, the lower row can begin updating its variable nodes. This allows the expansion factor processing unit to start updating the variable nodes and check nodes of the next row of the parity check matrix H ahead of time, during the current row's update process, without sacrificing decoding accuracy. This better guarantees LDPC decoding accuracy. From a horizontal timeline perspective, this application can start variable node reading fastest without increasing hardware overhead; it only rationally plans and adjusts the read / write order of variable nodes. Deploying the read order of each row in this way, and then adding multiple rounds of decoding iterations, can save a significant amount of LDPC decoding time without sacrificing decoding accuracy.

[0059] The following is a detailed description of the post-node switching network 6 in this application.

[0060] In traditional LDPC decoders, the post-node switching network needs to determine the flip position. Because there are many configuration combinations of zc and shift, the implementation of the post-node switching network requires a huge selector, resulting in high hardware overhead and significant adverse effects on timing and area in hardware implementation.

[0061] The post-node switching network 6 of this application is implemented by a p-to-1 selector and a 384-to-1 selector. The post-node switching network 6 receives new data of the VN-PART1 variable node from the check node and variable node update module 5. The shift logic of the new data of the VN-PART1 variable node is implemented through the two selectors. Combined with fixed-length data expansion and splicing, the hardware handling of the loop-flipping problem at zc-1 in traditional LDPC decoders is avoided, which greatly simplifies the complexity of the algorithm hardware implementation.

[0062] The processing of the downstream node switching network 6 can be viewed as the reverse process of the upstream node switching network 4. The specific workflow of the downstream node switching network 6 is described below.

[0063] First, the post-node switching network 6 expands the new VN-PART1 variable node data transmitted from the check node and variable node update module 5 from p×n bits to p×(n+1) bits. The expanded data is denoted as llr_new. The expansion method is as follows: the original data is divided into p groups of n bits each, and then 1 bit is added before the most significant bit of each group of n bits as a valid indication signal. A valid indication signal of 1 indicates that the n bits of data in that group are valid, and a valid indication signal of 0 indicates that the n bits of data in that group are invalid. As an example, zc is 112 and p is 96, requiring two rounds of processing. In the first round of processing, a total of 96 expansion factors are processed, and 96 groups are written back, each group being n bits, with a valid indication signal of 1 for all groups. In the second round of processing, the remaining 16 expansion factors are processed, but 96 data are still output in parallel. Only the 16 groups with the least significant bit have a valid indication signal of 1, while the valid indication signals for the remaining groups are all 0.

[0064] Subsequently, the back node switching network 6 shifts the extended data llr_new left by a shift amount of zc_ini. zc_ini represents the starting position of the second SRAM in the variable node management module 2 after the swapped VN-PART1 variable node data is written back. Since zc_ini can only take values ​​between 0 and 383, the left shift can be implemented using a 384-to-1 selector. After the left shift, zeros are first padded to the lower bits by zc_ini × (n + 1) bits. If the length of the padded data is 384 × (n + 1) bits, it is used as the left-shifted data llr_new_lsft. If the length of the padded data is less than 384 × (n + 1) bits, zeros are padded to the higher bits to make the data length 384 × (n + 1) bits, which is then used as the left-shifted data llr_new_lsft.

[0065] Please see Figure 6The left-shifted data llr_new_lsft has three possible cases. Using n+1 bits as a unit, the left-shifted data llr_new_lsft can be represented by 384 indices from 0 to 383, with the left side representing the high-order bit and the right side representing the low-order bit. The gray area represents multiple units of data where the valid indicator signal is 1; each unit consists of n+1 bits and is called valid data.

[0066] The first possible scenario is as follows: Figure 6 As shown in line 1, valid data did not fall into the portion from index zc-1 to 383. This indicates that there was no looping issue at zc-1 when writing data back to the second SRAM in the variable node management module 2. At this time, the remaining part of the left-shifted data llr_new_lsft after removing the valid indicator signal in each cell (length is 384×n bits) is used as the write data llr_out of the second SRAM (total 384×n bits). The subsequent node switching network 6 only writes the data of the cell in the write data llr_out where the final valid indicator signal is 1 to the second SRAM, completing the update of the variable node row.

[0067] The second possible scenario is as follows: Figure 6 As shown in the second line, a portion of the valid data falls into the section from index zc-1 to 383, and the section from index zc-1 to 383 also contains all-zero data.

[0068] The third possible scenario is as follows: Figure 6 As shown in line 3, a portion of the valid data falls into the section from index zc-1 to 383, and the section from index zc-1 to 383 is entirely valid data with no data consisting entirely of zeros.

[0069] Both of the latter cases indicate that there is a looping problem at position zc-1 in the second SRAM of the variable node management module 2 during the data write-back. In this case, the extended data llr_new is shifted right by (zc - zc_ini) × (n + 1) bits. Since the right shift range can only be between 0 and p-1, the right shift can be implemented using a p-to-1 selector. If the length of the right-shifted data is 384 × (n + 1) bits, it is used as the right-shifted data llr_new_rsft. If the length of the right-shifted data is less than 384 × (n + 1) bits, zeros are padded to the high bits of the right-shifted data to make the data length 384 × (n + 1) bits, resulting in the right-shifted data llr_new_rsft. At this time, the length of the left-shifted data llr_new_lsft is 384 × (n + 1) bits, divided into 384 units, each unit having a length of n + 1 bits, and each unit containing 1 bit of valid indicator signal. At this point, the right-shifted data `llr_new_rsft` has a length of 384 × (n + 1) bits, divided into 384 units, each unit having a length of n + 1 bits and containing 1 bit of valid indicator signal. The write data `llr_out` for the second SRAM is generated based on the left-shifted and right-shifted data `llr_new_lsft`. First, the write data `llr_out` for the second SRAM has a length of 384 × n bits, divided into 384 units, each unit having a length of n bits. Therefore, each unit of the left-shifted data `llr_new_lsft` after removing the valid indicator signal, and each unit of the right-shifted data `llr_new_rsft` after removing the valid indicator signal, have a one-to-one correspondence with each unit of the write data `llr_out` for the second SRAM. Second, the 384 valid indicator signals in the left-shifted data `llr_new_lsft` are logically ORed with the 384 valid indicator signals in the right-shifted data `llr_new_rsft` to obtain 384 final valid indicator signals. Next, for those cells where the final valid indicator signal is 1, and the corresponding cell in the right-shifted data `llr_new_rsft` also has a valid indicator signal of 1, remove the valid indicator signal from the corresponding cell in the right-shifted data `llr_new_rsft` and fill it into the corresponding cell of the write data `llr_out` in the second SRAM. For those cells where the final valid indicator signal is 1, and the corresponding cell in the left-shifted data `llr_new_lsft` also has a valid indicator signal of 1, remove the valid indicator signal from the corresponding cell in the left-shifted data `llr_new_lsft` and fill it into the corresponding cell of the write data `llr_out` in the second SRAM. For those cells where the final valid indicator signal is 0, fill the corresponding cell of `llr_out` with 0. This yields the complete write data `llr_out` of the second SRAM.The subsequent node switching network 6 writes only the data of the cell in the write data llr_out that has the final valid indicator signal of 1 to the second SRAM, thus completing the update of the variable node row.

[0070] Compared with the prior art, the LDPC decoder proposed in this application has the following beneficial effects.

[0071] First, the parity check node and variable node update module 5 changes the reading and writing order of variable nodes in different rows of the parity check matrix H. Compared with the existing technology, it reduces the extra waiting time when the parity check matrix H switches between rows, and can complete the row iteration of the parity check matrix H faster, which has the characteristics of fast decoding speed.

[0072] Second, both the front node switching network 4 and the back node switching network 6 are implemented by two selectors, which simplifies the logic of the front and back node switching networks of variable nodes, avoids the hardware handling of the loop-flipping problem at zc-1 in traditional LDPC decoders, greatly simplifies the complexity of the hardware implementation of the LDPC decoding algorithm, and reduces the area and power consumption of the computing unit.

[0073] Third, this application reduces the area of ​​storage cells with the same data volume by integrating each SRAM storage cell and adjusting the aspect ratio, thereby reducing power consumption.

[0074] Fourth, using TSMC's 22nm process, the area of ​​the LDPC decoder in this application is only 0.6 square millimeters, which shows that this application makes efficient use of hardware resources and achieves good power consumption.

[0075] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A high-performance, low-power LDPC decoder, characterized in that, Includes verification node and variable node update modules; The LDPC decoder performs decoding based on a parity check matrix. The parity check matrix is ​​obtained by expanding the base matrix by an expansion factor zc and then cyclically shifting it by an initial offset shift. Each row in the base matrix is ​​expanded to zc rows in the parity check matrix, and these zc rows are called a large row of the parity check matrix. The columns with "1" in each row of the parity check matrix are valid columns. Each row of the parity check matrix is ​​a check node, and each column in each row is a variable node. The parity check node and variable node update module has p independent expansion factor processing units; the LDPC decoder simultaneously processes a large row or a portion of the parity check matrix; when p ≥ zc, the LDPC decoder processes a large row of the parity check matrix in only one round, and the number of rows processed simultaneously is zc; when k × p < zc ≤ (k + 1) × p, k is a positive integer, the LDPC decoder processes a large row of the parity check matrix in k + 1 rounds; the number of rows processed simultaneously in the first k rounds is p, and the number of rows processed simultaneously in the k + 1 round is zc - k × p; The check node and variable node update module is used to control the updating of VN-PART1 variable nodes and check nodes in multiple rows of the parity check matrix that are processed simultaneously. When the valid columns of two adjacent rows in the parity check matrix are repeated or partially repeated, the check node and variable node update module first writes the VN-PART1 variable nodes of the repeated or partially repeated valid columns for the upper row, and then writes the VN-PART1 variable nodes of the non-repeating valid columns for the lower row. The check node and variable node update module first reads the VN-PART1 variable nodes of the non-repeating valid columns for the lower row, and then reads the VN-PART1 variable nodes of the repeated or partially repeated valid columns. The VN-PART1 variable node refers to a variable node with a column index less than 26; the VN-PART1 variable node needs to have its variable node data updated, that is, there are read and write operations.

2. The high-performance, low-power LDPC decoder according to claim 1, characterized in that, For VN-PART1 variable nodes in adjacent rows of the parity check matrix where valid columns are repeated or partially repeated, the check node and variable node update module starts reading the VN-PART1 variable nodes in the same valid column of the lower row after writing the VN-PART1 variable node of a certain valid column in the upper row, regardless of whether all variable nodes in the upper row have been written.

3. The high-performance, low-power LDPC decoder according to claim 1, characterized in that, The verification node and variable node update module also includes a sixth SRAM for caching intermediate results of the VN-PART1 variable node; the sixth SRAM is two single-port SRAMs using a ping-pong storage architecture; each single-port SRAM has a depth of 19 and a bit width of p×n bits; where n = the capacity of the SRAM storing the source data of the VN-PART1 variable node for this LDPC decoding ÷ 384.

4. The high-performance, low-power LDPC decoder according to claim 1, characterized in that, p is a positive integer that is divisible by 384.

5. The high-performance, low-power LDPC decoder according to claim 1, characterized in that, It also includes a front node switching network; the front node switching network uses a 51-to-1 selector and a 384-to-1 selector to be responsible for exchanging the source data of the VN-PART1 variable nodes by shifting and splicing. The workflow of the front-node switching network is as follows; The input data of the front-node switching network is a 384×n bit data, with n bits as a unit. This input data is represented by 384 indices from 0 to 383. The input from index 0 to zc-1 is the useful data, and the input from index zc to 383 is the useless data. The input data from index 0 to zc-1 is shifted left to the highest position, that is, shifted left by (384-zc)×n bits, and the low bits are filled with 0, resulting in a new 384×n bit data; this left shift operation is implemented by a 51-to-1 selector; The left-shifted data is placed in the lower 384×n bits, and the original input data is placed in the upper 384×n bits, resulting in a 2×384×n bit concatenated data. Shift the concatenated data to the right by (384 - zc + shift) × n bits, and then extract the least significant p × n bits; here, the p × n bits correspond to the data between index shift and shift + p - 1 in the concatenated data. This right shift operation is implemented using a 384-to-1 selector.

6. The high-performance, low-power LDPC decoder according to claim 5, characterized in that, It also includes a post-node switching network; the post-node switching network uses a p-to-1 selector and a 384-to-1 selector to handle the exchange of new data for the VN-PART1 variable nodes by shifting and splicing. The workflow of the post-node switching network is as follows: The new data of the input p×n bit VN-PART1 variable node is divided into p groups according to n bits as units, and a 1 bit effective indication signal is added to each group to obtain p×(n+1) bit extended data. The extended data is shifted left by zc_ini, where zc_ini is the starting position of the new data of the swapped VN-PART1 variable node written back to SRAM; zc_ini takes a value between 0 and 383, and this left shift operation is implemented using a 384-to-1 selector; after the left shift, zeros are padded to obtain 384×(n+1) bits of left-shifted data; the left-shifted data is represented by indices from 0 to 383, using n+1 bits as units; the unit with a valid indicator signal of 1 is called valid data; When there is no valid data between index zc-1 and 383 of the left-shifted data, the remaining part of the left-shifted data after removing the valid indicator signals in each cell is used as the write data to be written back to SRAM. When there is valid data between the index zc-1 and 383 of the data after left shift, the extended data is shifted right by (zc - zc_ini) × (n + 1) bits; the value of the right shift is between 0 and p-1, and this right shift operation is implemented by a p-to-1 selector; after right shift, zeros are padded to obtain 384 × (n + 1) bits of right-shifted data; if the valid indicator signal of a certain cell of the right-shifted data is 1, the corresponding cell is used as the corresponding cell for writing data back to SRAM after removing the valid indicator signal; if the valid indicator signal of a certain cell of the left-shifted data is 1, the corresponding cell is used as the corresponding cell for writing data back to SRAM after removing the valid indicator signal; otherwise, the corresponding cell for writing data back to SRAM is filled with 0; thus, the complete write data back to SRAM is obtained.

7. The high-performance, low-power LDPC decoder according to claim 1, characterized in that, It also includes a variable node management module; The variable node management module includes: a first static random access memory (SRAM) with a single port for storing the source data of the VN-PART1 variable node for the next LDPC decoding; a second SRAM with a dual port for storing the source data of the VN-PART1 variable node for the current LDPC decoding; and a third SRAM with two single ports for storing the source data of the VN-PART2 variable node to be decoded in a ping-pong storage manner. The VN-PART2 variable node refers to a variable node with a column index greater than or equal to 26; the VN-PART2 variable node does not require updating of variable node data, that is, only read operations exist.

8. The high-performance, low-power LDPC decoder according to claim 7, characterized in that, The variable node management module operates as follows: the source data of the VN-PART1 variable node from the first LDPC decoding is input into the first SRAM for storage, and the source data of the VN-PART2 variable node from the first LDPC decoding is input into one of the third SRAMs for storage; if the LDPC decoder is idle at this time, the first SRAM forwards the source data of the VN-PART1 variable node from the first LDPC decoding to the second SRAM, and the first LDPC decoding is started; during the first LDPC decoding process, the LDPC decoder interacts with one of the second and third SRAMs; when the first SRAM completes forwarding, the source data of the VN-PART1 variable node from the second LDPC decoding is input into the first SRAM for storage, and the source data of the VN-PART2 variable node from the second LDPC decoding is input into the second of the third SRAMs for storage; after the first LDPC decoding is completed, the first SRAM forwards the source data of the VN-PART1 variable node from the second LDPC decoding to the second SRAM, and the second LDPC decoding is started, and the LDPC decoder interacts with the second and third SRAMs.

9. The high-performance, low-power LDPC decoder according to claim 1, characterized in that, It also includes a verification node management module; The parity check node management module includes: a fourth SRAM for caching the minimum, second minimum, and minimum value column indices of all rows of the parity check matrix, i.e., all parity check nodes; and a fifth SRAM for caching the symbolic variables of the expansion factors of each valid column of each row of the parity check matrix. The fourth SRAM uses a single-port SRAM with a depth of 46×384÷p and a bit width of m×p bits; or, the fourth SRAM uses 384÷p single-port SRAMs with a depth of 46 and a bit width of m×p bits; where m represents the total number of bits of the minimum, second minimum, and minimum value column indices of each row of the parity check matrix, i.e., each check node. The fifth SRAM uses a dual-port SRAM with a depth of 274 and a bit width of 384 bits; or, the fifth SRAM uses 384 ÷ p dual-port SRAMs with a depth of 274 and a bit width of p bits.

10. The high-performance, low-power LDPC decoder according to claim 1, characterized in that, It also includes a Cyclic Redundancy Check (CRC) module; the CRC module is used to perform two CRC checks on the LDPC decoding result; only when two consecutive CRC checks are correct is the LDPC decoding determined to be correct.

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