High throughput matrix interleaving method and device
By using two interleaved memories to write and read data in a jump-by-skirt method in the matrix interleaving method, the throughput and delay problems in the prior art are solved, and more efficient data processing is achieved.
Patent Information
- Application Number
- CN202510339981.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-21
- Publication Date
- 2025-08-12
AI Technical Summary
The throughput and processing delay of existing matrix interleaving methods are low, especially when ASIC or FPGA implementations, data throughput is severely limited and processing delay is large.
Two interleaved memories are used, and two data are written in parallel each time, and two columns are written in parallel. Pingpong switches memory usage, reads data in rows in a jump-by-step manner, and adjusts the data order through remapping circuits.
It improves the throughput of matrix interleaving, reduces processing delay, achieves higher processing efficiency and lower waiting delay, and is easy to implement with hardware.
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Figure CN120474565A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to a channel coding technology, and in particular to a matrix interleaving method. Background Art
[0002] In wireless mobile communication systems, due to the noise and fading characteristics of the wireless transmission channel, transmitted bits often experience continuous errors. Various channel coding technologies have a certain degree of error correction capability, but their ability to handle consecutive erroneous bit sequences is often limited. Therefore, interleaving is often used to address this issue. Interleaving can be briefly described as follows. At the transmitter, the order of the previously encoded data stream is shuffled before it is fed into the subsequent modulation module. At the receiver, the shuffled received information is deinterleaved, converting the potentially consecutive erroneous bit sequences into a single (or very short) erroneous bit sequence. The error correction capability of the channel decoding is then used to recover the correct original bits.
[0003] One interleaving technique is matrix interleaving, also known as packet interleaving or block interleaving. Figure 1This is a typical matrix interleaving structure, specifically an M-row × N-column interleaving matrix implemented in memory. The transmitter writes the pre-encoded data streams d0, d1, d2, ..., into the interleaving matrix row by row, writing the data after each row, as indicated by the solid arrows. The size of the interleaving matrix is L = M × N. After the interleaving matrix is fully written with the data of an interleaved frame of length L, the interleaved data is read out in columns, and after each column is read, the next column is read, as indicated by the dashed arrows, and sent to the subsequent modulation module. Therefore, the transmitter uses a "row write, column read" operation for the interleaving matrix. In practical applications, if the number of columns N is much larger than the number of rows M, when implemented on an ASIC (application-specific integrated circuit) or FPGA (field-programmable gate array), the data bit width stored at a single memory address is limited. In this case, the matrix is often transposed and stored, that is, the interleaved data is cached by storing the same column data at the same address, which is equivalent to a "column write, row read" operation. Deinterleaving at the receiving end is the inverse of interleaving. If the transmitting end writes data using the "write columns, read rows" operation, the receiving end writes the demodulated data into the interleaving matrix row by row, then reads it out column by column to complete the deinterleaving and feed it into the subsequent decoding module. This means that the receiving end uses the "write rows, read columns" operation on the interleaving matrix. For ease of explanation, this application will explain the "write columns, read rows" interleaving matrix operation at the transmitting end.
[0004] Assume that the number of interleaved data frames is L = 64, the data bit width of the pre-encoded data stream is 1 bit, the depth of the memory constituting the interleaving matrix is 16, and the data bit width of each address in the memory is 4 bits. In this case, the interleaving matrix is 16 rows × 4 columns, and each matrix cell stores 1 bit of data.
[0005] See also Figure 2 The existing matrix interleaving method uses a column-by-column writing scheme as follows: using the DMASK (data bit selection) function of the memory, starting from the 0th bit of each address, the data stream d0, d1, d2, ... after the previous stage encoding is written into the memory in a column-by-column writing manner, one bit at a time. Specifically, the lowest bit bit [0] of each address in the memory is first written into the column - in the order of memory addresses from small to large, that is, addr is 0, addr is 1, addr is 2, ..., and then the second lowest bit bit [1] of each address in the memory is written into the column - in the order of memory addresses from small to large, after one column is written into the next column, and so on, as shown by the dotted arrows.
[0006] See also Figure 3The existing matrix interleaving method uses a row-based reading scheme to read the memory 4 bits at a time. Specifically, the 4 bits at the lowest address (addr = 0) of the memory are read first, in the order of bits from small to large in the same memory address, i.e., bit[0], bit[1], bit[2], etc. Then, the 4 bits at the next lowest address (addr = 1) of the memory are read, in the order of bits from small to large in the same memory address. After reading one row, the next row is read, and so on, as shown by the dotted arrows. If the data bit width of each address of the memory is N bits, N bits of data can be read out in parallel at a time.
[0007] In existing matrix interleaving implementations, only one bit can be written at a time, and data cannot be read until the entire interleaving matrix is filled. Therefore, data throughput is severely limited and processing delay is large. Summary of the Invention
[0008] The technical problem to be solved by this application is: how to improve the throughput of matrix interleaving and reduce the processing delay of matrix interleaving.
[0009] To solve the above technical problems, the present application proposes a high-throughput matrix interleaving method, which includes the following steps. Step S1: Assume that the interleaving matrix is M rows × N columns, and the bit width of each data in the data stream encoded by the pre-interleaver is d bits, where M, N, and d are all positive integers greater than 1; implement two interleaving memories, each of which has a depth of M, and the data bit width of each address in each interleaving memory is N × d bits. Step S2: Write the data stream encoded by the pre-interleaver into one of the interleaving memories in a parallel writing mode of two data and two columns at a time; specifically, first write the two data into the lowest 2 columns of the lowest address of the interleaving memory at the same time, then write the two data into the lowest 2 columns of the second lowest address of the interleaving memory at the same time, and so on; after writing the lowest 2 columns of all addresses, write the next lowest 2 columns of each address in sequence, and so on. Step S3: When one interleaving memory is full, write to the other interleaving memory, and keep switching in ping-pong mode. Step S4: After any interleaving memory is full, data is read from the interleaving memory in a row-by-row manner, N data at a time. Specifically, the lowest address of the interleaving memory is read simultaneously first, followed by half of the address of the memory, followed by the next lowest address of the interleaving memory, followed by half of the address plus one of the address of the interleaving memory, and so on. Steps S3 and S4 may be performed either before or simultaneously. Step S5: The data read from the interleaving memory is converted into the correct interleaved order by the remapping circuit.
[0010] Preferably, in step S1, the physical entity of the interleaving memory is a random access memory (RAM) with a single port.
[0011] Furthermore, in step S1, the single-port RAM has a write data bit selection DMASK function, that is, each time writing, only part of the bits of a certain address can be written, and it is not required to write all the bits of the address.
[0012] Furthermore, in step S2, the data stream after the pre-stage encoding of the interleaver is d0, d1, d2, ...; d0 and d1 are first written simultaneously into the lowest 2d bits bit[d-1:0] and bit[2d-1:d] in the lowest address of the interleaving memory, and then d2 and d3 are written simultaneously into the lowest 2d bits bit[d-1:0] and bit[2d-1:d] in the second lowest address of the interleaving memory. After the two columns of the lowest 2d bits bit[d-1:0] and bit[2d:d] are written, the two columns of the second lowest 2d bits bit[4d-1:3d] and bit[3d-1:2d] are written, and so on.
[0013] Furthermore, in step S4, N×d bits of the interleaving memory with an address of 0 are first read simultaneously, then N×d bits of the memory with an address of M / 2 are read simultaneously, then N×d bits of the interleaving memory with an address of 1 are read simultaneously, then N×d bits of the interleaving memory with an address of M / 2 plus 1 are read simultaneously, and one row is read in the aforementioned jumping order before the next row is read, and so on.
[0014] Furthermore, in step S5, the remapping circuit is primarily composed of three sets of selectors and three sets of registers. The remapping circuit divides data read from an interleaved memory into two sets of data, wherein data read at odd times constitutes a first set of data, and data read at even times constitutes a second set of data. The first set of data is sequentially cached in two levels by a first selector, a first register, and a second register, resulting in x2. The first selector is controlled by a first selection signal, which is high for odd-numbered reads and low for even-numbered reads. Data read from the interleaved memory at a particular time in the first set of data and the output x1 of the first register serve as two inputs of the first selector. The output z1 of the first selector is connected to the first register. The output x1 of the first register is connected to one input of the first selector and the second register, and the second register outputs x2. The second set of data passes through the second selector and the third register for L1 caching, resulting in x3. The second selector is controlled by a second select signal, which is high for even-numbered reads and low for odd-numbered reads. Data from the interleaved memory read once in the second set of data and x3 serve as the two inputs of the second selector. The output z2 of the second selector is connected to the third register. The output x3 of the third register is connected to an input of the second selector and is also output externally. The third selector is controlled by a third select signal, which is high for odd-numbered reads and low for even-numbered reads. x2 and x3 serve as the two inputs of the third selector, and the third selector outputs the final N interleaved parallel data, each with a bit width of d.
[0015] Furthermore, in a certain clock cycle when the first selection signal is at a high level, the output z1 of the first selector is the data read from the interleaved memory at one time in the first group of data; in the next clock cycle when the first selection signal is at a low level, the output z1 of the first selector remains unchanged; in this clock cycle and the next clock cycle, the output x1 of the first register is connected to the second register, and x1 is the data read from the interleaved memory at one time in the first group of data; in the next and the next clock cycles, the output x2 of the second register is the data read from the interleaved memory at one time in the first group of data, which is recorded as x2 = {x2[N-1],...,x2[2],x2[1],x2[0]}.
[0016] Furthermore, in a certain clock cycle when the second selection signal is at a high level, the output z2 of the second selector is the data read from the interleaved memory at one time in the second group of data; in the next clock cycle when the second selection signal is at a low level, the output z2 of the second selector remains unchanged; in this clock cycle and the next clock cycle, the output x3 of the third register is the data read from the interleaved memory at one time in the second group of data, which is recorded as x3 = {x3[N-1],..., x3[2], x3[1], x3[0]}.
[0017] Furthermore, when the third selection signal is at a high level, the output of the third selector is {x3[N-2],x2[N-2],…,x3[2],x2[2],x3[0],x2[0]}; when the third selection signal is at a low level, the output of the third selector is {x3[N-1],x2[N-1],…,x3[3],x2[3],x3[1],x2[1]}.
[0018] The present application also proposes a high-throughput matrix interleaving device, comprising a memory implementation unit, a two-column writing unit, a ping-pong switching unit, a jump-type row-by-row reading unit, and a remapping unit. The memory implementation unit uses two interleaving memories; each interleaving memory has a depth of M, and the data bit width of each address in each interleaving memory is N×d bits, corresponding to the data bit width of each data stream encoded by the pre-interleaver being d bits, and the interleaving matrix is M rows × N columns. The two-column writing unit writes the data stream encoded by the pre-interleaver into one of the interleaving memories in a parallel writing manner of two data and two columns at a time; specifically, the two data are first written simultaneously into the lowest two columns of the lowest address of the interleaving memory, and then the two data are written simultaneously into the lowest two columns of the next lowest address of the interleaving memory, and so on; after the lowest two columns of all addresses are written, the next lowest two columns of each address are written in sequence, and so on. The ping-pong switching unit is used to write to the other interleaving memory when one interleaving memory is full, continuously ping-pong switching. The skip-row reading unit reads data from any interleaving memory after it is full, in a row-by-row reading mode of N data at a time; specifically, it first reads the lowest address of the interleaving memory, then reads half of the address of the memory, then reads the next lowest address of the interleaving memory, then reads half of the address plus one of the address of the interleaving memory, and so on. The remapping unit is used to convert the data read from the interleaving memory into the correct interleaved order through a remapping circuit.
[0019] The technical effect achieved by this application is: by optimizing the writing and reading methods of interleaved data in two ping-pong interleaved memories, higher processing efficiency and lower waiting delay are achieved, and it has the characteristics of simple implementation and easy promotion and application. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 This is a schematic diagram of a typical matrix interleaving structure.
[0021] Figure 2 It is a schematic diagram of a column-by-column writing scheme of an existing matrix interleaving method.
[0022] Figure 3 It is a schematic diagram of a row-by-row reading scheme of an existing matrix interleaving method.
[0023] Figure 4 This is a flowchart of the high-throughput matrix interleaving method proposed in this application.
[0024] Figure 5 This is a schematic diagram of a two-column writing scheme of the high-throughput matrix interleaving method proposed in this application.
[0025] Figure 6 This is a schematic diagram of a skip-row reading scheme of the high-throughput matrix interleaving method proposed in this application.
[0026] Figure 7 This is a schematic diagram of data read from the interleaved memory.
[0027] Figure 8 It is a schematic diagram of data converted into the correct interleaved order by the remapping circuit.
[0028] Figure 9 is a schematic diagram of an example of a remapping circuit proposed in this application.
[0029] Figure 10 yes Figure 9 Schematic diagram of the timing of each signal in .
[0030] Figure 11 This is a schematic diagram of the structure of the high-throughput matrix interleaving device proposed in this application.
[0031] Explanation of the reference numerals in the figure: memory implementation unit 1, two-column writing unit 2, ping-pong switching unit 3, skipping row reading unit 4, and remapping unit 5. DETAILED DESCRIPTION
[0032] See also Figure 4 The high-throughput matrix interleaving method proposed in this application includes the following steps.
[0033] Step S1: Assume that the interleaving matrix has M rows × N columns, and the size of the interleaving matrix is L = M × N. For ease of implementation, M is an even number. The data bit width of the data stream after pre-interleaver encoding is d bits, that is, the size of each data element is d bits. M, N, and d are all positive integers greater than 1. This implements two interleaving memories. Each interleaving memory has a depth of M (equivalent to the number of rows in the interleaving matrix), and the data bit width of each address in each interleaving memory is N × d bits. Each address in each interleaving memory (equivalent to each row in the interleaving matrix) can be used to store N d bits of data. The physical entity of the interleaving memory is preferably a single-port RAM (random-access memory). Single-port RAM uses the same set of ports for reading and writing. Any address in the RAM can be accessed in a clock cycle, but only one of the read and write functions can be active at the same time. Compared to dual-port RAM, single-port RAM sacrifices the ability to read and write simultaneously, but has advantages in terms of area and power consumption. The single-port RAM has a DMASK function, which means that only a portion of the bits of a certain address can be written during each write, rather than requiring the entire bit of the address to be written.
[0034] Step S2: Write the data streams d0, d1, d2, ... after the pre-stage encoding of the interleaver into one of the interleaving memories in a parallel writing mode of two data and two columns at a time. Each data d0, d1, d2, ... is d bits in size. Specifically, d0 and d1 are first written into the lowest 2d bits bit[d-1:0] and bit[2d-1:d] in the lowest address of the interleaving memory at the same time, and then d2 and d3 are written into the lowest 2d bits bit[d-1:0] and bit[2d-1:d] in the second lowest address of the interleaving memory at the same time. After writing the two columns of the lowest 2d bits bit[d-1:0] and bit[2d:d], the two columns of the second lowest 2d bits bit[4d-1:3d] and bit[3d-1:2d] are written, and so on. Figure 5 Indicated by the dotted arrow. Figure 5 Only an example with N=4 is given.
[0035] Step S3: When one interleaving memory is full, write to the other interleaving memory, switching continuously in a ping-pong manner. Since the RAM reads faster than the write speed, writing can always operate at maximum throughput, and two data bits of width d can be written in each clock cycle.
[0036] Step S4: After any interleaving memory is full, data is read from the interleaving memory in a row-by-row manner, with N data at a time. Specifically, the N×d bits (i.e., N data with a bit width of d) of the lowest address (addr is 0) of the interleaving memory are read simultaneously first, followed by the N×d bits of the half address (addr is M / 2) of the memory, followed by the N×d bits of the second lowest address (addr is 1) of the interleaving memory, followed by the N×d bits of the half plus one address (addr is M / 2 plus 1) of the interleaving memory, and so on. After reading one row in the aforementioned skipping order, the next row is read, and so on. Figure 6 Indicated by the dotted arrow. Figure 6 Only an example of M = 16 and N = 4 is given. Since the read speed of RAM is faster than the write speed, the data of one interleaved memory is stopped after it is read, and data is read from the other interleaved memory again after the other interleaved memory is full.
[0037] There is no strict restriction on the order of step S3 and step S4, and they can be performed either before or simultaneously.
[0038] Step S5: The data read from the interleaving memory is not in the correct interleaved order yet and is converted to the correct interleaved order through a remapping circuit. Conventionally, after reading interleaved data from the interleaving matrix, no remapping circuit is required. This application utilizes a skip-style row read order in step S4, which needs to be combined with the remapping circuit in step S5 to achieve the correct interleaved order obtained by conventional interleaving matrix reading methods.
[0039] continue Figure 6 In the example of N=4, the order of data read out from an interleaving memory is as follows Figure 7 As shown. The first time the 0th row (lowest address) is read, the N bit-width d data obtained are d33, d32, d1, d0. The second time the 8th row (half the address) is read, the N bit-width d data obtained are d49, d48, d17, d16. The third time the 1st row (second lowest address) is read, the N bit-width d data obtained are d35, d34, d3, d2. The fourth time the 9th row (half plus one) is read, the N bit-width d data obtained are d51, d50, d19, d18. And so on. Each time the data is read, the N bit-width d data of a row are read in parallel. However, this is not the required interleaved order. Remapping is required to obtain the correct interleaved result. The correct interleaved order is as follows: Figure 8 shown. Figure 8 After the interleaving is completed, the interleaved frame data shown is the same as Figure 3 The row-by-row reading order of the conventional matrix interleaving method shown is consistent.
[0040] See also Figure 9 , which is an example of the remapping circuit proposed in this application. Figure 10 yes Figure 9 The remapping circuit mainly consists of three sets of selectors M1, M2, M3 and three sets of registers K1, K2, K3. The remapping circuit splits the data read from an interleaved memory into two groups of data, where the data read 1, 3, 5, ... (odd number) is the first group of data, and the data read 2, 4, 6, ... (even number) is the second group of data. The parity depends on Figure 10 The read count signal in .
[0041] The first set of data (data read from row 0, row 1, row 2, etc.) is sequentially cached in two levels by the first selector M1, the first register K1, and the second register K2, resulting in x2. The first selector M1 is controlled by the first selection signal sel1, which is high during odd-numbered reads and low during even-numbered reads. The data read from the interleaved memory at a particular time in the first set of data (N data with a bit width of d) and x1 serve as the two inputs of the first selector M1. The output z1 of the first selector M1 is connected to the first register K1. The output x1 of the first register K1 is connected to one input of the first selector M1 and the second register K2, which outputs x2. During a certain clock cycle (for example, the second) when the first selection signal sel1 is high, the output z1 of the first selector M1 is the data read from the interleaved memory at a particular time in the first set of data. During the next clock cycle (for example, the third) when the first selection signal sel1 is low, the output z1 of the first selector M1 remains unchanged. In this (for example, the 3rd) clock cycle and the next (for example, the 4th) clock cycle, the output x1 of the first register K1 is connected to the second register K2, and x1 is the data read from the interleaving memory at one time in the first set of data. In the next (for example, the 4th) and the next (for example, the 5th) clock cycle, the output x2 of the second register k2 is the data read from the interleaving memory at one time in the first set of data, which is recorded as x2 = {x2[N-1], ..., x2[2], x2[1], x2[0]}. If continued Figure 6 In the example where N=4, x2 is, for example, {d33, d32, d1, d0}.
[0042] The second set of data (data read from row M / 2, row M / 2+1, row M / 2+2, etc.) is sequentially cached through the second selector M2 and the third register K3 for L1 caching, resulting in x3. The second selector M2 is controlled by the second selection signal sel2, which is high during even-numbered reads and low during odd-numbered reads. Data from the second set of data read from the interleaved memory at a particular time (N data with a bit width of d) and x3 serve as the two inputs of the second selector M2. The output z2 of the second selector M2 is connected to the third register K3. The output x3 of the third register K3 is connected to an input of the second selector M2 and also outputs x3. During a certain clock cycle (e.g., the third) when the second selection signal sel2 is high, the output z2 of the second selector M2 is the data read from the interleaved memory at a particular time in the second set of data. During the next clock cycle (e.g., the third) when the second selection signal sel2 is low, the output z2 of the second selector M2 remains unchanged. In this (e.g., 4th) clock cycle and the next (e.g., 5th) clock cycle, the output x3 of the third register K3 is the data read from the interleaving memory at one time in the second group of data (N data with a bit width of d), which is recorded as x3 = {x3[N-1], ..., x3[2], x3[1], x3[0]}. Figure 6 In the example where N=4, x3 is, for example, {d49, d48, d17, d16}.
[0043] The third selector M3 is controlled by the third selection signal sel3, which is high when read an odd number of times and low when read an even number of times. When the third selection signal sel3 is high, the output of the third selector M3 is {x3[N-2], x2[N-2], …, x3[2], x2[2], x3[0], x2[0]}. When the third selection signal sel3 is low, the output of the third selector M3 is {x3[N-1], x2[N-1], …, x3[3], x2[3], x3[1], x2[1]}. If continued Figure 6For example, when the third selection signal sel3 is high, the output of the third selector M3 is {x3[2], x2[2], x3[0], x2[0]}; when the third selection signal sel3 is low, the output of the third selector M3 is {x3[3], x2[3], x3[1], x2[1]}. x2 and x3 are the two inputs of the third selector M3, and the output of the third selector M3 is the final interleaved N parallel data, each with a bit width of d. The first interleaved data is {d48, d32, d16, d0}, the second interleaved data is {d49, d33, d17, d1}, the third interleaved data is {d50, d34, d18, d2}, and so on.
[0044] See also Figure 11 The high-throughput matrix interleaving device proposed in this application includes a memory implementation unit 1, a two-column writing unit 2, a ping-pong switching unit 3, a skip-row reading unit 4, and a remapping unit 5. Figure 11 The device shown corresponds to Figure 4 The method shown.
[0045] The memory implementation unit 1 uses two interleaving memories. The depth of each interleaving memory is M, and the data bit width of each address in each interleaving memory is N×d bits. The data bit width of each data stream after the pre-interleaver encoding is d bits, and the interleaving matrix is M rows×N columns.
[0046] The two-column writing unit 2 writes the data stream encoded by the interleaver pre-stage into one of the interleaving memories in a parallel writing mode of two data at a time, two columns at a time. Specifically, the two data are first written simultaneously into the lowest two columns of the lowest address of the interleaving memory, then the two data are written simultaneously into the lowest two columns of the next lowest address of the interleaving memory, and so on. After the lowest two columns of all addresses are written, the next two columns of each address are written sequentially in ascending address order, and so on.
[0047] The ping-pong switching unit 3 is used to write to another interleaving memory when one interleaving memory is full, and continuously ping-pong switch.
[0048] The skip-row reading unit 4 reads data from any interleaved memory after it is full, reading N data at a time, row by row. Specifically, it first reads the lowest address of the interleaved memory, then reads half of the address of the memory, then reads the next lowest address of the interleaved memory, then reads half of the address of the interleaved memory plus one, and so on.
[0049] The remapping unit 5 is used to convert the data read out from the interleaving memory into a correct interleaved sequence through a remapping circuit.
[0050] Under the existing "column write and row read" operation mode, since only one data can be written at a time, the data processing throughput of the interleaving module is restricted. The theoretical maximum data processing throughput is equal to the clock frequency, and each time it is necessary to wait for the entire memory to be written before reading. Each time it is completely read before writing again, the interleaving module is less efficient. The matrix interleaving solution provided by the present application can write in parallel to two columns when writing, so compared with the traditional single-column writing solution, the writing efficiency is doubled, while the reading efficiency is the same as the traditional solution, and a maximum of one row can be read in parallel, so the theoretical maximum data throughput is twice the clock frequency. In addition, the present application realizes alternating reading and writing through two memories. When writing to one memory, the other memory can be read without waiting for each other. Because the reading rate is greater than the writing rate, it is easy to construct a read-write balance control circuit. The present application can realize pipeline reading and writing through this ping-pong structure, reducing the read and write waiting delay in the traditional solution.
[0051] Existing technology This application Write clock cycles 64 32 Read out the number of clock cycles 16 16 Two frames write wait clock cycles 16 / 0 0 Two frames read waiting clock cycles 64 / 48 16
[0052] Table 1: Comparison of processing time between prior art and this application
[0053] Table 1 compares the processing time of the present application and the prior art when the interleaving circuit pipeline is fully loaded, for an embodiment of the present application with M=16 and N=4. It can be seen that the processing bottleneck of the prior art interleaving technology lies in writing. When reading a frame of interleaved data, the present application achieves the same speed as the prior art, both reading all interleaved data in 16 clock cycles. On the write side, the present application doubles the processing speed, requiring only 32 clock cycles to write all data. Furthermore, the prior art has a write latency of 16 clock cycles (without a ping-pong structure) and 0 clock cycles (with a ping-pong structure), respectively, while the present application has a write latency of 0 clock cycles for two interleaved frames. The prior art has a read latency of 64 clock cycles (without a ping-pong structure) and 48 clock cycles (with a ping-pong structure), respectively, while the present application has a read latency of 16 clock cycles for two interleaved frames. In summary, the present application can significantly reduce the processing latency of the interleaving module, thereby improving the efficiency of the entire communication system. In addition, the interleaving circuit implementation provided in this application is not complicated, and is comparable in difficulty to the existing technology, and is easily applicable to the hardware implementation of various communication systems.
[0054] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.
Claims
1. A high-throughput matrix interleaving method, characterized in that: The method includes the following steps: Step S1: Assume that the interleaving matrix is M rows × N columns, the bit width of each data in the data stream after the pre-interleaver encoding is d bits, and M, N, and d are all positive integers greater than 1; Implement two interleaving memories, each of which has a depth of M and a data bit width of each address of each interleaving memory of N×d bits; Step S2: writing the data stream encoded by the interleaver pre-stage into one of the interleaving memories in a parallel writing mode of two data and two columns at a time; specifically, first writing the two data into the lowest two columns of the lowest address of the interleaving memory, then writing the two data into the lowest two columns of the second lowest address of the interleaving memory, and so on; after writing the lowest two columns of all addresses, writing them into the second lowest two columns of each address in sequence, and so on; Step S3: When one interleaving memory is full, write to another interleaving memory, and keep ping-pong switching; Step S4: After any interleaving memory is full, data is read from the interleaving memory in a row-by-row manner, with N data at a time. Specifically, the lowest address of the interleaving memory is read simultaneously first, then half of the address of the memory is read simultaneously, then the second lowest address of the interleaving memory is read simultaneously, then half of the address plus one of the interleaving memory is read simultaneously, and the next row is read after one row is read in the aforementioned skipping order, and so on; Step S3 and step S4 may be performed either before or simultaneously; Step S5: The data read out from the interleaving memory is converted into the correct interleaved order through the remapping circuit.
2. The high-throughput matrix interleaving method according to claim 1, wherein: In the step S1, the physical entity of the interleaving memory is a random access memory (RAM) with a single port.
3. The high-throughput matrix interleaving method according to claim 2, wherein: In step S1, the single-port RAM has a write data bit selection DMASK function, that is, each time writing, only part of the bits of a certain address can be written, and it is not required to write all the bits of the address.
4. The high-throughput matrix interleaving method according to claim 1, wherein: In step S2, the data stream after the pre-stage encoding of the interleaver is d0, d1, d2, ...; d0 and d1 are first written simultaneously into the lowest 2D bits bit[d-1:0] and bit[2d-1:d] in the lowest address of the interleaving memory, and then d2 and d3 are written simultaneously into the lowest 2D bits bit[d-1:0] and bit[2d-1:d] in the second lowest address of the interleaving memory. After the two columns of the lowest 2D bits bit[d-1:0] and bit[2d:d] are written, the two columns of the second lowest 2D bits bit[4d-1:3d] and bit[3d-1:2d] are written, and so on.
5. The high-throughput matrix interleaving method according to claim 1, wherein: In step S4, N×d bits of the interleaving memory with an address of 0 are first read simultaneously, then N×d bits of the memory with an address of M / 2 are read simultaneously, then N×d bits of the interleaving memory with an address of 1 are read simultaneously, then N×d bits of the interleaving memory with an address of M / 2 plus 1 are read simultaneously, and one row is read in the aforementioned skipping order before the next row is read, and so on.
6. The high-throughput matrix interleaving method according to claim 1, wherein: In step S5, the remapping circuit is mainly composed of three groups of selectors and three groups of registers; the remapping circuit splits the data read from an interleaving memory into two groups of data, where the data read at odd times is the first group of data, and the data read at even times is the second group of data; The first set of data is sequentially cached in two levels through the first selector, the first register, and the second register to obtain x2; the first selector is controlled by a first selection signal, which is high when read an odd number of times and low when read an even number of times; data read from the interleaving memory at a certain time in the first set of data and the output x1 of the first register serve as the two inputs of the first selector; the output z1 of the first selector is connected to the first register; the output x1 of the first register is connected to one input of the first selector and the second register, and the second register outputs x2; The second set of data is sequentially passed through the second selector and the third register for L1 caching, obtaining x3. The second selector is controlled by a second selection signal, which is high when read an even number of times and low when read an odd number of times. The data read from the interleaved memory at a certain time in the second set of data and x3 serve as two inputs of the second selector. The output z2 of the second selector is connected to the third register. The output x3 of the third register is connected to one input of the second selector and is also output externally. The third selector is controlled by the third selection signal, which is high when read an odd number of times and low when read an even number of times; x2 and x3 are the two inputs of the third selector, and the output of the third selector is the final N parallel data after interleaving, and the bit width of each data is d.
7. The high-throughput matrix interleaving method according to claim 6, wherein: When the first selection signal is at a high level in a certain clock cycle, the output z1 of the first selector is data read from the interleaving memory at a certain time in the first group of data; when the first selection signal is at a low level in the next clock cycle, the output z1 of the first selector remains unchanged; In this clock cycle and the next clock cycle, the output x1 of the first register is connected to the second register, where x1 is the data read from the interleaved memory at one time in the first set of data; in the next and the next clock cycles, the output x2 of the second register is the data read from the interleaved memory at one time in the first set of data, which is recorded as x2 = {x2[N-1],..., x2[2], x2[1], x2[0]}.
8. The high-throughput matrix interleaving method according to claim 6, wherein: When the second selection signal is at a high level in a certain clock cycle, the output z2 of the second selector is data read from the interleaving memory at a certain time in the second group of data; when the second selection signal is at a low level in the next clock cycle, the output z2 of the second selector remains unchanged; In this clock cycle and the next clock cycle, the output x3 of the third register is the data read from the interleaving memory at one time in the second group of data, which is recorded as x3 = {x3[N-1],..., x3[2], x3[1], x3[0]}.
9. The high-throughput matrix interleaving method according to claim 6, wherein: When the third selection signal is at a high level, the output of the third selector is {x3[N-2],x2[N-2],…,x3[2],x2[2],x3[0],x2[0]}; when the third selection signal is at a low level, the output of the third selector is {x3[N-1],x2[N-1],…,x3[3],x2[3],x3[1],x2[1]}.
10. A throughput matrix interleaving device, characterized in that: It includes a memory implementation unit, a two-column writing unit, a ping-pong switching unit, a skip-type row reading unit, and a remapping unit; The memory implementation unit uses two interleaving memories; the depth of each interleaving memory is M, the data bit width of each address of each interleaving memory is N×d bits, the data bit width of each data stream after the interleaver pre-stage encoding is d bits, and the interleaving matrix is M rows×N columns; The two-column writing unit writes the data stream encoded by the interleaver pre-stage into one of the interleaving memories in a parallel writing mode of two data at a time and two columns at a time; specifically, the two data are first written simultaneously into the lowest two columns of the lowest address of the interleaving memory, and then the two data are written simultaneously into the lowest two columns of the second lowest address of the interleaving memory, and so on; after the lowest two columns of all addresses are written, the next two columns of each address are written in sequence, and so on; The ping-pong switching unit is used to write to another interleaving memory when one interleaving memory is full, and continuously ping-pong switch; The skip-type row-by-row reading unit reads data from any interleaved memory in a row-by-row reading mode of N data at a time after any interleaved memory is full. Specifically, the lowest address of the interleaved memory is first read simultaneously, then half of the address of the memory is read simultaneously, then the second lowest address of the interleaved memory is read simultaneously, then half of the address plus one of the interleaved memory is read simultaneously, and so on; The remapping unit is used to convert the data read out from the interleaving memory into a correct interleaved sequence through a remapping circuit.