POE switch test circuit and test method

Abstract

The invention relates to a POE switch test circuit and method, and the circuit comprises a power unit which is used for converting a power voltage into a 3.3 V power supply voltage and a 5V power supply voltage; the test interface unit is used for forwarding a to-be-tested POE signal from the to-be-tested POE switch; the network isolation transformation unit is used for performing differential signal isolation on the detected POE signal; the rectifying unit is used for generating rectified voltage from the isolated tested POE signal; the PD unit is used for switching the duty ratio of the MPS according to the rectified voltage and generating corresponding characteristic current; the load unit is connected with the PD unit and the power supply unit and is used for communicating the rectified voltage; the driving control unit is used for driving the Autoclass mode and the MPS duty ratio configuration of the PD unit; the grading unit is used for generating a gear signal according to the characteristic current; and the microcontroller is used for controlling the PD unit, the load unit and the driving control unit, and confirming the power classification of the POE switch according to the gear signal of the grading unit.

Description

Technical Field

[0001] The present invention relates to the technical field of POE detection, and in particular to a POE switch test circuit and a test method. Background Art

[0002] POE (Power over Ethernet) refers to a technology that, without modifying the existing Ethernet Cat.5 cabling infrastructure, allows IP-based terminals (such as IP phones, wireless LAN access points (APs), and network cameras) to transmit data signals while also providing DC power to these devices. As a key component of Ethernet communication networks, POE switches deliver high-quality information transmission while also providing remote power. This dual function of communication data exchange and remote device power supply eliminates the need for additional sockets and wiring, directly supplying power to Ethernet network devices through the network cable, reducing the complexity and cost of communication equipment wiring. Therefore, mass-produced POE switches must be tested during production to verify that their data transmission and power supply performance meet POE standard requirements.

[0003] Under current technology, the POE switch test device for testing POE switches cannot test and verify the power consumption of each PD level of the POE switch. Summary of the Invention

[0004] In view of the shortcomings of the existing technology, the present invention provides a POE switch test circuit and test method, which aims to solve the problem that the POE switch test device for testing POE switches under current technology cannot test and verify the power consumption of each PD level of the POE switch.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] In the first aspect, a POE switch test circuit includes: a power supply unit connected to an external power supply and used to convert the power supply voltage into a supply voltage of 3.3V and 5V; a test interface unit connected to the POE switch under test and used to forward the tested POE signal from the tested POE switch; a network isolation transformer unit connected to the test interface unit and used to perform differential signal isolation on the tested POE signal; a rectifier unit connected to the network isolation transformer unit and used to rectify the isolated tested POE signal to generate a rectified voltage; a PD unit connected to the rectifier unit and used to generate a rectified voltage according to the rectified voltage. Switching the duty cycle of the MPS and generating the corresponding characteristic current; the load unit is connected to the PD unit and the power supply unit, and is used to connect the rectifier voltage; the drive control unit is connected to the PD unit and the power supply unit, and is used to drive the Autoclass mode and MPS duty cycle configuration of the PD unit; the grading unit is connected to the PD unit, and is used to generate a gear signal according to the characteristic current; the microcontroller is connected to the PD unit, the load unit, the drive control unit, and the grading unit, and is used to control the PD unit, the load unit, and the drive control unit, and confirm the power classification of the POE switch according to the gear signal of the grading unit.

[0007] In a second aspect, a POE switch testing method comprises the following steps:

[0008] Step 1: The power module converts the power voltage of the external power supply into 3.3V and 5V supply voltages;

[0009] Step 2: After the microcontroller starts up, it controls the driver control unit, providing a test circuit for the detection resistor during the subsequent POE detection phase. It also drives the PD unit's Autoclass mode and MPS duty cycle configuration, and sets the PD's classification configuration resistors RclsA and RclsB to the preset impedance.

[0010] Step 3: Connect the network cable of the POE switch to be tested to the test interface unit, so that the two sets of POE signals to be tested are rectified by the network isolation transformer unit and the rectifier unit and then sent to the PD unit to start POE detection;

[0011] Step 4: The PD unit generates two corresponding characteristic currents based on the two sets of rectified voltages. When the two characteristic currents meet the current requirements of the POE switch under test for the detection phase, the POE classification phase begins.

[0012] Step 5: The microcontroller controls the rectifier unit to raise the rectifier voltage to within a preset threshold range, causing the PD unit to generate a characteristic current to indicate to the POE switch under test that the PD unit supports the Autoclass mode. A preset voltage is also applied to the RclsA pin and RclsB pin of the PD unit, causing the PD unit to generate two corresponding characteristic currents.

[0013] Step 6: The classification generates a gear signal according to the characteristic current. The microcontroller adjusts the load unit according to the gear signal and verifies the power consumption of the POE switch PD level according to the total power consumption of the load unit.

[0014] The present invention provides a POE switch test circuit and test method, which have the following beneficial effects:

[0015] The network isolation transformer unit performs differential signal isolation on the tested POE signal, and the rectifier unit rectifies the isolated tested POE signal to generate a rectified voltage. The network isolation transformer unit and the rectifier unit are designed to be compatible with different PSE types (Type 1 to 4). The load unit is connected to the rectified voltage. The load unit is designed with a programmable constant current source to accurately simulate the actual power consumption scenario. The microcontroller controls the drive control unit to drive the Autoclass mode and MPS duty cycle configuration of the PD unit, supporting multiple POE standards. The PD unit switches the MPS duty cycle according to the rectified voltage and generates the corresponding characteristic current. The grading unit generates a gear signal according to the characteristic current. The microcontroller tests and verifies the power consumption of multiple PD levels of the POE switch according to the gear signal of the grading unit, covering the detection, classification, and power supply stages of the POE switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is an overall block diagram of a POE switch test circuit according to an embodiment of the present invention;

[0017] Figure 2 1 is a schematic diagram of the circuit structure of a power supply unit according to an embodiment of the present invention;

[0018] Figure 3 1 is a schematic diagram of the circuit structure of a microcontroller according to an embodiment of the present invention;

[0019] Figure 4 1 is a schematic diagram of the circuit structure of the test interface unit and the network isolation transformer unit according to an embodiment of the present invention;

[0020] Figure 5 1 is a schematic diagram of the circuit structure of a rectifier unit according to an embodiment of the present invention;

[0021] Figure 6 Schematic diagram of the circuit structure of the PD unit according to an embodiment of the present invention;

[0022] Figure 7 1 is a schematic diagram of the circuit structure of a load unit according to an embodiment of the present invention;

[0023] Figure 8 1 is a schematic diagram of the circuit structure of a drive control unit according to an embodiment of the present invention;

[0024] Figure 91 is a schematic diagram of the circuit structure of a grading unit according to an embodiment of the present invention;

[0025] Figure 10 is a circuit simulation example diagram of a load unit according to an embodiment of the present invention;

[0026] Figure 11 1 is a schematic diagram of the circuit structure of a communication interface unit according to an embodiment of the present invention;

[0027] Figure 12 1 is a schematic diagram of the circuit structure of a debug interface unit according to an embodiment of the present invention;

[0028] Figure 13 is a schematic diagram of the circuit structure of an information storage unit according to an embodiment of the present invention;

[0029] Figure 14 Schematic diagram of the circuit structure of the heat dissipation unit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0031] like Figure 1 As shown, the present invention provides a POE switch test circuit, comprising: a power supply unit connected to an external power supply, for converting the power supply voltage into a supply voltage of 3.3V and 5V; a test interface unit connected to a POE switch under test, for forwarding a POE signal under test from the POE switch under test; a network isolation transformer unit connected to the test interface unit, for performing differential signal isolation on the POE signal under test; a rectifier unit connected to the network isolation transformer unit, for rectifying the isolated POE signal under test to generate a rectified voltage; a PD unit connected to the rectifier unit, for The voltage switches the duty cycle of the MPS and generates the corresponding characteristic current; the load unit is connected to the PD unit and the power supply unit, and is used to connect the rectified voltage; the drive control unit is connected to the PD unit and the power supply unit, and is used to drive the Autoclass mode and MPS duty cycle configuration of the PD unit; the grading unit is connected to the PD unit, and is used to generate a gear signal according to the characteristic current; the microcontroller is connected to the PD unit, the load unit, the drive control unit, and the grading unit, and is used to control the PD unit, the load unit, and the drive control unit, and confirm the power classification of the POE switch according to the gear signal of the grading unit.

[0032] The network isolation transformer unit performs differential signal isolation on the tested POE signal, and the rectifier unit rectifies the isolated tested POE signal to generate a rectified voltage. The network isolation transformer unit and the rectifier unit are designed to be compatible with different PSE types (Type 1 to 4). The load unit is connected to the rectified voltage. The load unit is designed with a programmable constant current source to accurately simulate the actual power consumption scenario. The microcontroller controls the drive control unit to drive the Autoclass mode and MPS duty cycle configuration of the PD unit, supporting multiple POE standards. The PD unit switches the MPS duty cycle according to the rectified voltage and generates the corresponding characteristic current. The grading unit generates a gear signal according to the characteristic current. The microcontroller tests and verifies the power consumption of multiple PD levels of the POE switch according to the gear signal of the grading unit, covering the detection, classification, and power supply stages of the POE switch.

[0033] Furthermore, if Figure 2As shown, the power supply unit includes: a connector J1, a diode D1, a resistor R46, a resistor R47, a 3.3V conversion module and a 5V conversion module; the first pin, the second pin and the third pin of the connector J1 are grounded and connected to the positive end of the diode D1, the fourth pin, the fifth pin and the sixth pin of the connector J1 are all connected to the external power supply and connected to the negative end of the diode D1, the first ends of the resistors R46 and R47 are connected to the common connection end, and the second ends of the resistors R46 and R47 are grounded; the 3.3V conversion module includes: a power supply chip U5, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a capacitor C22, a capacitor C23, a capacitor C24, a capacitor C25, a capacitor C 26, capacitor C27, inductor L2; the first pin of the power chip U5 is grounded, the second pin of the power chip U5 is connected to the first end of the inductor L2, the second end of the inductor L2 is connected to the first end of the resistor R15, capacitor C24, capacitor C25, and capacitor C26 and outputs a 3.3V power supply voltage, the second ends of the capacitors C25 and C26 are grounded, the second end of the resistor R15 is connected to the fourth pin of the power chip U5, the second end of the capacitor C24 is connected to the first end of the resistor R17, the second end of the resistor R17 is grounded, the third pin of the power chip U5 is connected to the first end of the resistor R14, capacitor C22, and capacitor C23 and is connected to the negative terminal of the diode D1, capacitors C22 and capacitors The second end of C23 is grounded, the second end of resistor R14 is connected to the fifth pin of power chip U5, the first end of resistor R16, and the first end of capacitor C27, and the second end of resistor R16 is connected to the second end of capacitor C27; the 5V conversion module includes: power chip U10, resistor R134, resistor R135, resistor R136, resistor R137, capacitor C53, capacitor C54, capacitor C55, capacitor C56, capacitor C73, capacitor C74, and inductor L5; the first pin of power chip U10 is grounded, the second pin of power chip U10 is connected to the first end of inductor L5, the second end of inductor L5 is connected to the resistor R135, capacitor C55, capacitor C56, and capacitor C73 The first end is connected and outputs a 5V power supply voltage, the second ends of the capacitor C56 and the capacitor C73 are grounded, the second end of the resistor R135 is connected to the fourth pin of the power chip U10, the second end of the capacitor C55 is connected to the first end of the resistor R137, the second end of the resistor R137 is grounded, the third pin of the power chip U10 is connected to the resistor R134, the capacitor C53, the first end of the capacitor C54 and the negative terminal of the diode D1, the second ends of the capacitor C53 and the capacitor C54 are grounded, the second end of the resistor R134 is connected to the fifth pin of the power chip U10, the first end of the resistor R136, and the first end of the capacitor C74, the second end of the resistor R136 and the second end of the capacitor C74 are grounded.Two-stage DC-DC conversion ensures 3.3V and 5V voltage accuracy (±1%) to meet the needs of MCU and analog circuits. Multi-stage filter capacitors (such as C22 to C27 and C53 to C56) suppress power supply noise and improve system stability.

[0034] Furthermore, if Figure 3 As shown, the microcontroller includes: a control chip U4, capacitors C11 to C20, resistors R10 to R13, an inductor L1, and a crystal oscillator Y1. Pins 1, 24, 36, and 48 of the control chip U4 are connected to the first ends of the capacitors C13 to C17 and are connected to a 3.3V power supply voltage. The second ends of the capacitors C13 to C17 are grounded. The fifth pin of the control chip U4 is connected to the first end of the capacitor C11 and the fourth pin of the crystal oscillator Y1. The sixth pin of the control chip U4 is connected to the first end of the capacitor C12 and the second pin of the crystal oscillator Y1. The first pin of the crystal oscillator Y1 is connected to the first end of the capacitor C11. The third pin of the crystal oscillator Y1 is grounded. The second end of the capacitor C12 is connected to the first end of the capacitor C11. Ground, pins 8, 23, 35, and 47 of the control chip U4 are grounded, pin 7 of the control chip U4 is connected to the first ends of capacitor C20, resistors R10, R12, and R13, the second ends of resistors R10 and R13 are connected to the 3.3V power supply voltage, capacitor C20 and the second end of resistor R12 are grounded, pin 44 of the control chip U4 is connected to the first end of resistor R11, the second end of resistor R11 is grounded, pin 9 of the control chip U4 is connected to the first ends of inductor L1, capacitor C18, and capacitor C19, the second end of inductor L1 is connected to the 3.3V power supply voltage, and the second ends of capacitors C18 and C19 are grounded. Signal interaction between modules is achieved through multiple pins (such as GPIO, ADC, and DAC), simplifying system complexity. The 3.3V power supply is combined with low-power modes (such as sleep mode) to reduce the power consumption of the test circuit itself.

[0035] Furthermore, if Figure 4 and Figure 5As shown, the test interface unit includes: an Ethernet connector J3 and a surge protection chip U3, the B3 pin of the Ethernet connector J3 is connected to the first pin of the surge protection chip U3, the B6 pin of the Ethernet connector J3 is connected to the second pin of the surge protection chip U3, the third pin of the surge protection chip U3 is grounded, and the NC1, NC2, S1, S2, S3, and S4 pins of the Ethernet connector J3 are grounded; the network isolation transformer unit includes: an isolation chip T1, capacitors C33 to C41, and resistors R27 to R30, the 1st, 4th, 7th, and 10th pins of the isolation chip T1 are respectively connected to the first ends of the capacitors C33 to C36, the second ends of the capacitors C33 to C36 are grounded, and the 48th, 45th, and 46th pins of the isolation chip T1 are grounded. Pins 42 and 39 are connected to the first ends of resistors R27 to R30 respectively, the second ends of resistors R27 to R30 are connected to the first end of capacitor C41, the second end of capacitor C41 is grounded, and pins 47, 46, 44, 43, 41, 40, 38, and 37 of isolation chip T1 are connected to pins A2, A1, A4, A3, A6, A5, A8, and A7 of Ethernet connector J3 respectively. The rectifier unit includes: a first rectifier module, a second rectifier module, a third rectifier module, and a fourth rectifier module; the first rectifier module includes: diodes D3 to D6, the positive terminal of diode D3 and the negative terminal of diode D4 are connected to pin 3 of isolation chip T1, the positive terminal of diode D5 and the negative terminal of diode D6 are connected to the isolation The second pin of the chip T1, the cathode end of the diode D3 and the diode D5 output the rectified voltage VDD1, and the positive end of the diode D4 and the diode D6 is connected to the negative end of the external power supply; the second rectifier module includes: diodes D12 to D15, the positive end of the diode D12 and the negative end of the diode D13 are connected to the 6th pin of the isolation chip T1, the positive end of the diode D14 and the negative end of the diode D15 are connected to the 5th pin of the isolation chip T1, the negative end of the diode D12 and the diode D14 output the rectified voltage VDD1, and the positive end of the diode D13 and the diode D15 are connected to the common connection end; the third rectifier module includes: diodes D16 to D19, the positive end of the diode D16 and the negative end of the diode D17 The positive terminal of the diode D16 and the negative terminal of the diode D18 are connected to the 9th pin of the isolation chip T1, the positive terminal of the diode D18 and the negative terminal of the diode D19 are connected to the 8th pin of the isolation chip T1, the negative terminal of the diode D16 and the diode D18 output the rectified voltage VDD1, and the positive terminal of the diode D17 and the diode D19 are connected to the common connection terminal; the fourth rectifier module includes: diodes D7 to D10, the positive terminal of the diode D7 and the negative terminal of the diode D8 are connected to the 12th pin of the isolation chip T1, the positive terminal of the diode D9 and the negative terminal of the diode D10 are connected to the 11th pin of the isolation chip T1, the negative terminal of the diode D7 and the diode D9 output the rectified voltage VDD1, and the positive terminal of the diode D8 and the diode D10 are connected to the common connection terminal.Surge protection chip and isolation transformer prevent high voltage shock to ensure test safety. Isolation transformer suppresses common mode noise to ensure POE signal transmission quality.

[0036] Furthermore, if Figure 8 and Figure 10 As shown, the drive control unit includes: a first drive module, a second drive module and a third drive module; the first drive module includes: a relay J4, an NMOS tube Q6, a resistor R42, a resistor R44, and a resistor R45, the first pin of the relay J4 is connected to the 5V power supply voltage, the second pin of the relay J4 is connected to the rectifier voltage VDD1, the fourth pin of the relay J4 is connected to the PD unit, the third pin of the relay J4 is connected to the first end of the resistor R42 and the third pin of the NMOS tube Q6, the second end of the resistor R42 is connected to the 5V power supply voltage, the second pin of the NMOS tube Q6 is connected to the common connection end, the first pin of the NMOS tube Q6 is connected to the first end of the resistor R44 and the resistor R45, the second end of the resistor R44 is connected to the common connection end, and the second end of the resistor R45 is connected to the 40th pin of the control chip U4; the second drive module includes: an NMOS tube Q7, a resistor R53, a resistor R58 and a resistor R59, the third pin of the NMOS tube Q7 is connected to the first end of the resistor R53, the second end of the resistor R53 is connected to the PD unit, and the second pin of the NMOS tube Q7 is connected to the common connection end , the first pin of the NMOS tube Q7 is connected to the first end of the resistor R59 and the resistor R58, the second end of the resistor R58 is connected to the 42nd pin of the control chip U4, and the second end of the resistor R59 is connected to the common connection end; the third driving module includes: an NMOS tube Q8, an NMOS tube Q21, a resistor R54, a resistor R55, a resistor R56, a resistor R57, a resistor R60, and a resistor R61, the third pins of the NMOS tube Q8 and the NMOS tube Q21 are connected to the first end of the resistor R57 and the resistor R54, respectively, and the resistor R57 is connected to the resistor R51. The second end of pin 4 is connected to the PD unit. The second pins of NMOS transistor Q8 and NMOS transistor Q21 are connected to a common connection terminal. The first pin of NMOS transistor Q8 is connected to the first ends of resistors R60 and R61. The second end of resistor R60 is connected to pin 45 of control chip U4. The second end of resistor R61 is connected to the common connection terminal. The first pin of NMOS transistor Q21 is connected to the first ends of resistors R55 and R56. The second end of resistor R55 is connected to pin 43 of control chip U4. The second end of resistor R56 is connected to the common connection terminal. The relay and MOS transistor combination supports dynamic switching of graded resistance (such as 63.4Ω / 90.9Ω) and MPS mode. The low Rds(on) of NMOS transistors (such as AO3400) reduces power consumption in the drive circuit.

[0037] Furthermore, if Figure 6As shown, the PD unit includes: an Ethernet power supply control chip U7, a diode D11, a resistor R31, a resistor R133, a resistor R52, a resistor R122, a resistor R123, a resistor R124, a resistor R125, a resistor R128, a resistor R130, and a capacitor C50. The first pin of the Ethernet power supply control chip U7 is connected to the cathode terminal of the diode D11 and the first end of the capacitor C50 and is connected to the rectified voltage VDD1. The positive terminal of the diode D11 and the second end of the capacitor C50 are connected to the common connection terminal. The second pin of the Ethernet power supply control chip U7 is connected to the first end of the resistor R31. The second end of the resistor R31 is connected to the fourth pin of the relay J4. The third pin of the Ethernet power supply control chip U7 is connected to the classification unit. The sixth pin of the Ethernet power supply control chip U7 is connected to the classification unit. The tenth pin of the Ethernet power supply control chip U7 is connected to the second end of the resistor R53. The eighth pin of the Ethernet power supply control chip U7 is connected to the first end of the resistor R133. The second end of the resistor R133 is connected to the common connection terminal. Pin 7 of the Ethernet power supply control chip U7 is connected to the first end of the resistor R52, and the second end of the resistor R52 is connected to the common connection end. Pin 9 of the Ethernet power supply control chip U7 is connected to the second ends of the resistor R57 and the resistor R54. Pins 4, 5, and 21 of the Ethernet power supply control chip U7 are connected to the common connection end. Pins 11 and 12 of the Ethernet power supply control chip U7 are connected to the RTN end. Pins 19, 18, and 17 of the Ethernet power supply control chip U7 are respectively connected to the first ends of the resistors R122 to R124 and are also respectively connected to pins 46, 21, and 22 of the control chip U4. The second ends of the resistors R122 to R124 are connected to the 3.3V power supply voltage. Pin 13 of the Ethernet power supply control chip U7 is connected to the first end of the resistor R125, and the second end of the resistor R125 is connected to the rectified voltage VDD1. The first ends of the resistors R128 and R130 are connected to pin 11 of the control chip U4, the second end of the resistor R128 is connected to the rectified voltage VDD1, and the second end of the resistor R130 is connected to the common connection end.

[0038] Furthermore, if Figure 7As shown, the load unit includes: a first load module, a second load module, a third load module and a fourth load module; the first load module includes: an amplifier U6A, a MOS tube Q3, a resistor R50, a resistor R32, a resistor R33, a resistor R36, a resistor R34, a resistor R35, and capacitors C42 to C46. The first pin of the amplifier U6A is connected to the first end of the resistor R33 and the capacitor C45, the second end of the resistor R33 is connected to the first pin of the MOS tube Q3, the second end of the capacitor C45 is connected to the second pin of the amplifier U6A, and the second pin of the amplifier U6A is connected to the resistor R36 The first end of the MOS transistor Q3 is connected to the first end of the MOS transistor Q4, the second end of the resistor R36 is connected to the second pin of the MOS transistor Q3, the third pin of the amplifier U6A is connected to the first end of the resistor R32, the second end of the resistor R32 is connected to the first end of the capacitor C43 and the resistor R50 and is connected to the 14th pin of the control chip U4, the second end of the capacitor C43 and the resistor R50 is connected to the common connection terminal, the third pin of the MOS transistor Q3 is connected to the first end of the capacitor C42 and is connected to the rectified voltage VDD1, the second end of the capacitor C42 is connected to the RTN terminal, the second pin of the MOS transistor Q3 is connected to the first end of the resistor R34, the resistor R35, and the capacitor C46 One end is connected, the second ends of the resistor R34, the resistor R35, and the capacitor C46 are connected to the RTN end; the second load module includes: an amplifier U6B, a MOS tube Q4, a resistor R49, a resistor R37, a resistor R38, a resistor R41, a resistor R39, a resistor R40, and capacitors C47-C49, the seventh pin of the amplifier U6B is connected to the first end of the resistor R38 and the capacitor C48, the second end of the resistor R38 is connected to the first pin of the MOS tube Q4, the second end of the capacitor C48 is connected to the sixth pin of the amplifier U6B, and the sixth pin of the amplifier U6B is connected to the first end of the resistor R41 The second end of the resistor R41 is connected to the second pin of the MOS transistor Q4, the fifth pin of the amplifier U6B is connected to the first end of the resistor R37, the second end of the resistor R37 is connected to the first end of the capacitor C47 and the resistor R49 and is connected to the 14th pin of the control chip U4, the second end of the capacitor C47 and the resistor R49 is connected to the common connection terminal, the third pin of the MOS transistor Q4 is connected to the rectified voltage VDD1, the second pin of the MOS transistor Q4 is connected to the first end of the resistor R39, the resistor R40, and the capacitor C49, and the second ends of the resistor R39, the resistor R40, and the capacitor C49 are connected to the RTN terminal;The third load module includes: an amplifier U8A, a MOS tube Q9, a resistor R48, a resistor R62, a resistor R63, a resistor R66, a resistor R64, a resistor R65, and capacitors C57 to C61. The first pin of the amplifier U8A is connected to the first end of the resistor R63 and the capacitor C60, the second end of the resistor R63 is connected to the first pin of the MOS tube Q9, the second end of the capacitor C60 is connected to the second pin of the amplifier U6A, the second pin of the amplifier U8A is connected to the first end of the resistor R66, and the second end of the resistor R66 is connected to the second pin of the MOS tube Q9. The third pin of the amplifier U8A is connected to the first end of the resistor R62, the second end of the resistor R62 is connected to the first end of the capacitor C58 and the resistor R48 and is connected to the 15th pin of the control chip U4, the second end of the capacitor C58 and the resistor R48 is connected to the common connection terminal, the third pin of the MOS tube Q9 is connected to the first end of the capacitor C57 and is connected to the rectified voltage VDD1, the second end of the capacitor C57 is connected to the RTN terminal, the second pin of the MOS tube Q9 is connected to the first end of the resistor R64, the resistor R65, and the capacitor C61, the resistor R64, the resistor R65, and the capacitor C6 1 is connected to the RTN terminal; the fourth load module includes: an amplifier U8B, a MOS tube Q10, a resistor R51, a resistor R67, a resistor R68, a resistor R71, a resistor R69, a resistor R70, and capacitors C62-C64. The seventh pin of the amplifier U8B is connected to the resistor R68 and the first end of the capacitor C63, the second end of the resistor R68 is connected to the first pin of the MOS tube Q10, the second end of the capacitor C63 is connected to the sixth pin of the amplifier U8B, the sixth pin of the amplifier U8B is connected to the first end of the resistor R71, and the second end of the resistor R71 is connected. Connected to the second pin of MOS transistor Q10, the fifth pin of amplifier U8B is connected to the first end of resistor R67, the second end of resistor R67 is connected to the first end of capacitor C62 and resistor R51, and to pin 15 of control chip U4. Capacitor C62 and the second end of resistor R51 are connected to a common connection terminal. The third pin of MOS transistor Q10 is connected to rectified voltage VDD1, and the second pin of MOS transistor Q10 is connected to the first end of resistor R69, resistor R70, and capacitor C64. The second ends of resistors R69, resistor R70, and capacitor C64 are connected to RTN. The constant current source has an error of <1% and accurately simulates PD power consumption (e.g., 54V × 0.329A = 17.76W / channel). Four independent loads support multi-port parallel testing. Table 1 shows the power consumption of different PD levels corresponding to load regulation.

[0039] Table 1

[0040] VDD1 PD_MAX V_DC_IN1 V_DC_IN2 54V 3.84W 35.6mV 0V 54V 6.49W 60mV 0V 54V 12.95W 120mV 0V 54V 25.3W 236mV 0V 54V 40W 185mV 185mV 54V 51W 236mV 236mV 54V 62W 287mV 287mV 54V 71W 329mV 329mV

[0041] Furthermore, if Figure 9 As shown, the grading unit includes: a first grading module and a second grading module;

[0042] The first classification module includes: NMOS tubes Q11-Q15, resistors R95, R87, R76, R73, R78, R81, R83, R86, R89, R93, R98, R77, R82, R88, and R96; a first pin of the NMOS tube Q15 is connected to the first ends of the resistors R95 and R98, a second end of the resistor R95 is connected to the 12th pin of the control chip U4, a second end of the resistor R98 is connected to the common connection end, a second pin of the NMOS tube Q15 is connected to the common connection end, a third pin of the NMOS tube Q15 is connected to the first end of the resistor R87, and a second end of the resistor R87 is connected to the common connection end. Connected to the 3rd pin of the Ethernet power supply control chip U7; the first pin of the NMOS tube Q11 is connected to the first ends of the resistors R76 and R77, the second end of the resistor R76 is connected to the 13th pin of the control chip U4, the second end of the resistor R77 is connected to the common connection terminal, the second pin of the NMOS tube Q11 is connected to the common connection terminal, the third pin of the NMOS tube Q11 is connected to the first end of the resistor R73, and the second end of the resistor R73 is connected to the 3rd pin of the Ethernet power supply control chip U7; the first pin of the NMOS tube Q12 is connected to the first ends of the resistors R81 and R82, the second end of the resistor R81 is connected to the 16th pin of the control chip U4, and the second end of the resistor R82 is connected to the common connection terminal. The second pin of the NMOS transistor Q12 is connected to the common connection terminal, the third pin of the NMOS transistor Q12 is connected to the first end of the resistor R78, and the second end of the resistor R78 is connected to the third pin of the Ethernet power supply control chip U7; the first pin of the NMOS transistor Q13 is connected to the first ends of the resistor R86 and the resistor R88, the second end of the resistor R86 is connected to the 17th pin of the control chip U4, the second end of the resistor R88 is connected to the common connection terminal, the second pin of the NMOS transistor Q13 is connected to the common connection terminal, the third pin of the NMOS transistor Q13 is connected to the first end of the resistor R83, and the second end of the resistor R83 is connected to the third pin of the Ethernet power supply control chip U7; the first pin of the NMOS transistor Q14 is connected to the resistor R93 , a first end of a resistor R96 is connected, a second end of a resistor R93 is connected to pin 32 of the control chip U4, a second end of a resistor R96 is connected to a common connection terminal, a second pin of an NMOS transistor Q14 is connected to the common connection terminal, a third pin of the NMOS transistor Q14 is connected to a first end of a resistor R89, and a second end of the resistor R89 is connected to pin 3 of the Ethernet power control chip U7; a second hierarchical module includes: NMOS transistors Q16 to Q20, resistors R72, R74, R43, R79, R80, R75, R85, R90, R84, R92, R94, R91, R99, R100, and R97;A first pin of the NMOS transistor Q16 is connected to the first ends of the resistors R72 and R74, the second end of the resistor R72 is connected to the 33rd pin of the control chip U4, the second end of the resistor R74 is connected to the common connection terminal, the second pin of the NMOS transistor Q16 is connected to the common connection terminal, the third pin of the NMOS transistor Q16 is connected to the first end of the resistor R43, and the second end of the resistor R43 is connected to the 6th pin of the Ethernet power supply control chip U7; a first pin of the NMOS transistor Q17 is connected to the first ends of the resistors R79 and R80, the second end of the resistor R79 is connected to the 38th pin of the control chip U4, the second end of the resistor R80 is connected to the common connection terminal, the second pin of the NMOS transistor Q17 is connected to the common connection terminal, the third pin of the NMOS transistor Q17 is connected to the first end of the resistor R75, and the second end of the resistor R75 is connected to the 6th pin of the Ethernet power supply control chip U7; a first pin of the NMOS transistor Q18 is connected to the first ends of the resistors R85 and R90, the second end of the resistor R85 is connected to the 18th pin of the control chip U4, and the second end of the resistor R90 is connected to the common connection terminal. The second pin of the MOS transistor Q18 is connected to the common connection terminal. The third pin of the NMOS transistor Q18 is connected to the first end of the resistor R84. The second end of the resistor R84 is connected to the 6th pin of the Ethernet power control chip U7. The first pin of the NMOS transistor Q19 is connected to the first ends of the resistors R92 and R94. The second end of the resistor R92 is connected to the 19th pin of the control chip U4. The second end of the resistor R94 is connected to the common connection terminal. The second pin of the NMOS transistor Q19 is connected to the common connection terminal. The third pin of the NMOS transistor Q19 is connected to the first end of the resistor R91. The second end of the resistor R91 is connected to the 6th pin of the Ethernet power control chip U7. The first pin of the NMOS transistor Q20 is connected to the first ends of the resistors R99 and R100. The second end of the resistor R99 is connected to the 39th pin of the control chip U4. The second end of the resistor R100 is connected to the common connection terminal. The second pin of the NMOS transistor Q20 is connected to the common connection terminal. The third pin of the NMOS transistor Q20 is connected to the first end of the resistor R97. The second end of the resistor R97 is connected to the 6th pin of the Ethernet power control chip U7. Flexible configurations for Classes 0 to 8 are supported, covering all PoE standards. Independent resistor networks (such as R73 to R100) prevent signal crosstalk. Table 2 shows the CLSA configuration resistors for PD chips at different entry levels and signal levels.

[0043] Table 2

[0044]

[0045]

[0046] Table 3 shows the CLSA configuration resistance of the PD chip at different levels of entry and signal levels.

[0047] Table 3

[0048] SIGNAL NAME SIGNAL LEVEL CLSB CLSB_RES1 HIGH 1.21K CLSB_RES2 HIGH 249R CLSB_RES3 HIGH 140R CLSB_RES4 HIGH 90.9R CLSB_RES5 HIGH 63.4R

[0049] Table 4 shows the PD CLASS (power level) and corresponding PD POWER (power) range under different CLSA and CLSB combinations.

[0050] Table 4

[0051] CLSA CLSB PD CLASS (power class) PD POWER (power) range 1.21K 1.21K 0 0.44W-12.95W 249R 249R 1 0.44W-3.84W 140R 140R 2 3.84W-6.49W 90.9R 90.9R 3 6.49W-12.95W 63.4R 1.21K 5 25.5W-40W 63.4R 249R 6 40W-51W 63.4R 140R 7 51W-62W 63.4R 90.9R 8 62W-71W

[0052] Furthermore, if Figures 11 to 14It also includes: a communication interface unit, which is connected to an external communication device, a power supply unit and a microcontroller, and is used for the microcontroller to exchange signals with the external communication device; the communication interface unit includes: a transceiver U2, capacitors C3 to C10, and resistors R4 to R9. The first pin of the transceiver U2 is connected to the third pin of the transceiver U2 through the capacitor C3, the fourth pin of the transceiver U2 is connected to the fifth pin of the transceiver U2 through the capacitor C6, the eleventh pin of the transceiver U2 is connected to the 30th pin of the control chip U4 through the resistor R4, the tenth pin of the transceiver U2 is grounded through the resistor R6, and the 12th pin of the transceiver U2 is connected to the control chip U4 through the resistor R7. The 31st pin of U4 and the 16th pin of transceiver U2 are connected to the first end of capacitor C4 and capacitor C5 and are connected to the 3.3V power supply voltage. The 15th pin of transceiver U2 is connected to the second end of capacitor C4 and capacitor C5 and is grounded. The 2nd pin of transceiver U2 is connected to the 3.3V power supply voltage through capacitor C7. The 6th pin of transceiver U2 is grounded through capacitor C8. The 14th pin of transceiver U2 is grounded through resistor R5 and capacitor C9 in sequence. The 13th pin of transceiver U2 is grounded through resistor R8 and capacitor C10 in sequence. The 8th pin of transceiver U2 is grounded through resistor R9 in sequence. The debugging interface unit is connected to the external debugging equipment, The power supply unit is connected to the microcontroller and is used to debug the microcontroller; the debugging interface unit includes: a connector J2, the 1st and 2nd pins of the connector J2 are connected to the 3.3V power supply voltage, the 5th and 6th pins of the connector J2 are grounded, and the 3rd and 4th pins of the connector J2 are respectively connected to the 34th and 37th pins of the control chip U4; an information storage unit is connected to the power supply unit and the microcontroller and is used to store information parameters for the microcontroller to call and read; the information storage unit includes: a memory chip U1, a resistor R1, a resistor R2, a resistor R3, a capacitor C1 and a capacitor C2, the 1st pin of the memory chip U1 is connected to the first end of the resistor R1 and is connected to the 2nd pin of the control chip U4 Pin 5 of the memory chip U1 is connected to the 3.3V power supply voltage. The second end of the resistor R1 is connected to the 3.3V power supply voltage. The second pin of the memory chip U1 is connected to the 27th pin of the control chip U4. The 6th pin of the memory chip U1 is connected to the 26th pin of the control chip U4. The 5th pin of the memory chip U1 is connected to the 28th pin of the control chip U4. The 3rd pin of the memory chip U1 is connected to the first end of the resistor R2. The second end of the resistor R2 is connected to the 3.3V power supply voltage. The 7th pin of the memory chip U1 is connected to the first end of the resistor R3. The second end of the resistor R3 is connected to the 3.3V power supply voltage. The 8th pin of the memory chip U1 is connected to the first ends of the capacitors C1 and C2 and is connected to the 3.3V power supply voltage.A 3V power supply voltage is provided, and the fourth pin of the memory chip U1 is connected to the second ends of the capacitors C1 and C2 and is grounded. A heat dissipation unit is connected to a fan, an external power supply, and a microcontroller for heat dissipation. The heat dissipation unit includes: a MOS transistor Q1, a MOS transistor Q2, resistors R18 to 24, capacitors C29 to C32, a diode D2, a plug FAN1, and an inductor L3. A first pin of the MOS transistor Q1 is connected to a first end of the resistor R22, a second end of the resistor R22 is connected to a first end of the resistor R25 and a pin 29 of the control chip U4, a second end of the resistor R25 is grounded, a second pin of the MOS transistor Q1 is grounded, a third pin of the MOS transistor Q1 is connected to a first end of the resistor R23 and a first end of the resistor R18, a second end of the resistor R18 is connected to an external power supply, and a second end of the resistor R23 is connected to a first end of the capacitor C28 and a first pin of the MOS transistor Q2. The second end of capacitor C28 is grounded, the second pin of MOS transistor Q2 is grounded, and the third pin of MOS transistor Q2 is connected to the first ends of resistor R19 and resistor R24. The second end of resistor R19 is connected to an external power supply. The second end of resistor R24 is connected to the first ends of resistor R26 and resistor R20. The second end of resistor R26 is grounded. The second end of resistor R20 is connected to pin 4 of connector FAN1. Pin 3 of connector FAN1 is connected to pin 10 of control chip U4 through resistor R21. Pin 2 of connector FAN1 is connected to the cathode of the diode and the first ends of capacitors C32, C31, and inductor L3. The positive end of the diode and the second ends of capacitors C32 and C31 are grounded. The second end of inductor L3 is connected to the first ends of capacitors C30 and C29 and to the power supply. The second ends of capacitors C30 and C29 are grounded. A communication interface enables test data upload and remote control. A storage chip records historical test results to facilitate fault analysis. The PWM fan dynamically adjusts speed based on temperature, extending equipment life.

[0053] The present invention also provides a POE switch testing method, comprising the following steps:

[0054] Step 1: The power module converts the power voltage of the external power supply into 3.3V and 5V supply voltages;

[0055] Step 2: After the microcontroller starts up, it controls the driver control unit, providing a test circuit for the detection resistor during the subsequent POE detection phase. It also drives the PD unit's Autoclass mode and MPS duty cycle configuration, and sets the PD's classification configuration resistors RclsA and RclsB to the preset impedance.

[0056] Step 3: Connect the network cable of the POE switch to be tested to the test interface unit, so that the two sets of POE signals to be tested are rectified by the network isolation transformer unit and the rectifier unit and then sent to the PD unit to start POE detection;

[0057] Step 4: The PD unit generates two corresponding characteristic currents based on the two sets of rectified voltages. When the two characteristic currents meet the current requirements of the POE switch under test for the detection phase, the POE classification phase begins.

[0058] Step 5: The microcontroller controls the rectifier unit to raise the rectifier voltage to within a preset threshold range, causing the PD unit to generate a characteristic current to indicate to the POE switch under test that the PD unit supports the Autoclass mode. A preset voltage is also applied to the RclsA pin and RclsB pin of the PD unit, causing the PD unit to generate two corresponding characteristic currents.

[0059] Step 6: The classification generates a gear signal according to the characteristic current. The microcontroller adjusts the load unit according to the gear signal and verifies the power consumption of the POE switch PD level according to the total power consumption of the load unit.

[0060] The following describes the POE switch testing method using a Type 4 PSE and a Class 8 PD as examples. A complete POE system consists of two components: a power sourcing equipment (PSE) and a powered device (PD). The PSE provides power to Ethernet client devices and manages the entire POE power supply process. The PD is the load receiving power from the PSE, representing the client device of the POE system. In this application, the POE switch is the PSE, and the POE switch test circuit is the PD.

[0061] First, 12V power is supplied to the system through connector J1. Power chip U10 then outputs 5V to the back-end op amp and relays. Power chip U5 then outputs 3V3 to power microcontroller U4. Once microcontroller U4 is operational, it pulls Pin 40 high (network name: DEN_RES). This turns on the DS pin of NMOS transistor Q6, closing relay J4 and connecting Pins 3 and 4. This then connects R31 (a 24.9K detection resistor) from VDD1 to Pin 2 of Power over Ethernet controller U7, providing a test circuit for the detection resistor during the subsequent PoE detection phase. To support Autoclass mode, microcontroller U4's Pin 42 (Network Name: AUTO_RES) is pulled high. This turns on the DS pin of NMOS transistor Q7, which pulls Pin 10 of PoE controller U7 low to ground. This indicates to PoE controller U7 that Autoclass mode is required. Automatic MPS can be controlled via microcontroller U4's Pins 43 and 45. Pulling Pin 43 (Network Name: MPS_DUTY_RES1) or Pin 45 (Network Name: MPS_DUTY_RES2) high or low switches the MPS duty cycle (supported only in Type 3 or 4 PSEs). When the system-condition Cbulk capacitance of the Power over Ethernet (PoE) controller chip U7 is less than 60µF and the external network cable is less than 100m, the MPS will be configured to an 8.1% duty cycle. This means pulling up Pin 45 of the microcontroller U4, and then pulling up Pin 32 (network name: CLSA_RES5) and Pin 19 (network name: CLSB_RES4) of the microcontroller U4. This means setting the Power over Ethernet (PoE) controller chip U7's tiered configuration resistors RclsA and RclsB to 63.4R and 90.9R, respectively, to meet the 71W power consumption requirement of PD Class 8. After these configurations are complete, the PoE switch's network cable is plugged into port A of Ethernet connector J3 (RJ45). The voltage is then rectified by isolation chip T1 and a diode bridge, and then fed into the system's VDD1 network. During the initial POE detection phase, the POE switch sends two voltages of 1.4 to 10.9V to the VDD1 network via the Ethernet cable. This voltage is then fed through relays J4 and R31 to the Pin 2 detection pin of the Power over Ethernet (PoE) control chip U7. This generates two detection currents within the PoE control chip U7. When VDD1 = 1.4V, the detection current is 56.5uA; when VDD1 = 10.9V, the detection current is 410uA. Both detection currents meet the POE switch's detection phase current requirements, allowing the system to proceed to the next POE classification phase.During the classification phase, the VDD1 voltage is raised to between 13V and 21V. After the classification start time (Tacs) (81.5ms), the VDD, AUTCLS, and VSS links of the Power over Ethernet controller U7 generate a 1-4mA current (the characteristic current of PD Class 0) to indicate to the PSE that the PD supports Autoclass mode. A 2.5V voltage is applied to the CLSA and CLSB pins. This voltage passes through the previously configured RclsA (63.4R) and RclsB (90.9R) to VSS, generating the corresponding characteristic current on the link. A Type 4 PSE and PD Class 8 require five classification cycles. During each cycle, the POE switch detects the characteristic current and returns the VDD1 voltage to the detection phase voltage. This is called the Mark period. At this time, because the voltage of VDD1 is no longer in the range of 13 to 21V, the 2.5V voltage applied by the Ethernet power supply control chip U7 to the external CLSA and CLSB will be disconnected. At this time, the current on the link is 0, that is, the characteristic current during the Mark period is 0, and this cycle repeats. In the first two classification cycles, the Ethernet power supply control chip U7 will switch the 2.5V to the CLSA pin through the switch inside, that is, the link will generate a classification characteristic current of about 2.5V / 63.4R=39mA. In the last three classification cycles, the Ethernet power supply control chip U7 will cut the internal 2.5V to the CLSB pin, that is, the link will generate a classification characteristic current of about 2.5V / 90.9R=27mA. After reading the classification characteristic current over five cycles, the Type 4 PSE knows the PD's class and begins to slowly boost the VDD1 voltage. When it reaches at least 38V (i.e., reaching the maximum turn-on threshold of the chip's undervoltage lockout), the hot-swap MOSFET inside the Ethernet power control chip U7 enters the inrush current limiting phase, limiting the current to approximately 200mA, and simultaneously begins charging the external Cbuck capacitor. Figure 7During a normal startup, the voltage on RTN gradually decreases from VDD1 to VSS1, and once the current on RTN drops to approximately 10% of the inrush current, the current limit on the PoE controller U7 switches to its normal current limit of approximately 1.85A. A subsequent overload condition causes the voltage between RTN and VSS1 to increase. If this rises to 14.5V and persists for at least 1.65ms, current limiting protection is triggered, restoring the current limit on the PoE controller U7 to the inrush current limit (200mA), and the above steps are repeated. During a normal startup, the TPH, TPL, and BT outputs on the PoE controller U7 typically become enabled 24ms after PG transitions from low to disconnected. The currently configured PSE type and PD class can be determined by reading the voltage levels on the MCU's Pin 46 (Network Name: PD_BT), Pin 21 (Network Name: PD_TPH), and Pin 22 (Network Name: PD_TPL). This time, we use Type 4 PSE and Class 8 PD, so the level status that will be read is: Pin46, Pin21 and Pin22 of the MCU are all low levels. We can obtain these parameter information through the external serial port connected to the B port of J3. When the voltage of VDD1 sampled by Pin11 of the MCU (network name: VDD1_ADC) is around 54V, Pin14 (network name: DAC_IN1) and Pin15 (network name: DAC_IN2) of the microcontroller U4 will output 329mV. At the same time, Pin29 (network name: FAN_PWM) of the microcontroller U4 is set to a duty cycle of 1, that is, the fan runs at full speed. Taking the first load module as an example, the constant current source circuit of U6A, Q3, R34 will generate a current of 329mA on VDD1, Q3, R34, and RTN. The power consumption of the first load module is VDD1*0.329A=54V*0.329A=about 17.76W (see Figure 10 The power consumption of the adjustable load circuit simulation example in the figure above, plus the power consumption of the other three load modules, is about 71W in total. This power consumption is the maximum power consumption required, which indicates the maximum power consumption required by the PD to the PSE end.

[0062] The above are merely preferred embodiments of the present invention and do not limit the technical scope of the present invention. Therefore, any minor modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A POE switch test circuit, characterized in that: include: A power supply unit, connected to an external power supply, for converting the power supply voltage into 3.3V and 5V supply voltages; A test interface unit, connected to the POE switch under test, for forwarding the POE signal under test from the POE switch under test; A network isolation transformer unit, connected to the test interface unit, for performing differential signal isolation on the tested POE signal; A rectifier unit, connected to the network isolation transformer unit, for rectifying the isolated POE signal to generate a rectified voltage; A PD unit, connected to the rectifier unit, configured to switch the duty cycle of the MPS according to the rectifier voltage and generate a corresponding characteristic current; a load unit, connected to the PD unit and the power supply unit, and configured to connect the rectified voltage; A driving control unit, connected to the PD unit and the power supply unit, for driving the Autoclass mode and MPS duty cycle configuration of the PD unit; a grading unit, connected to the PD unit, and configured to generate a gear signal according to a characteristic current; The microcontroller is connected to the PD unit, the load unit, the drive control unit, and the grading unit, and is used to control the PD unit, the load unit, and the drive control unit, and confirm the power classification of the POE switch according to the gear signal of the grading unit.

2. The POE switch test circuit according to claim 1, characterized in that: The power supply unit includes: a connector J1, a diode D1, a resistor R46, a resistor R47, a 3.3V conversion module and a 5V conversion module; the first pin, the second pin and the third pin of the connector J1 are grounded and connected to the positive end of the diode D1, the fourth pin, the fifth pin and the sixth pin of the connector J1 are all connected to the external power supply and connected to the negative end of the diode D1, the first ends of the resistors R46 and R47 are connected to the common connection end, and the second ends of the resistors R46 and R47 are grounded The 3.3V conversion module includes: a power chip U5, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a capacitor C22, a capacitor C23, a capacitor C24, a capacitor C25, a capacitor C26, a capacitor C27, and an inductor L2; a first pin of the power chip U5 is grounded, a second pin of the power chip U5 is connected to a first end of the inductor L2, and a second end of the inductor L2 is connected to the first ends of the resistor R15, the capacitor C24, the capacitor C25, and the capacitor C26 to output 3.3V power supply voltage, the second ends of the capacitors C25 and C26 are grounded, the second end of the resistor R15 is connected to the fourth pin of the power chip U5, the second end of the capacitor C24 is connected to the first end of the resistor R17, the second end of the resistor R17 is grounded, the third pin of the power chip U5 is connected to the first ends of the resistor R14, the capacitor C22, and the capacitor C23 and is connected to the negative terminal of the diode D1, the second ends of the capacitors C22 and C23 are connected The second end of the resistor R14 is connected to the fifth pin of the power chip U5, the first end of the resistor R16, and the first end of the capacitor C27, and the second end of the resistor R16 and the second end of the capacitor C27 are grounded; the 5V conversion module includes: a power chip U10, a resistor R134, a resistor R135, a resistor R136, a resistor R137, a capacitor C53, a capacitor C54, a capacitor C55, a capacitor C56, a capacitor C73, a capacitor C74, and an inductor L5; the power chip U10 The first pin of the power chip U10 is grounded. The second pin of the power chip U10 is connected to the first end of the inductor L5. The second end of the inductor L5 is connected to the first end of the resistor R135, the capacitor C55, the capacitor C56, and the capacitor C73, and outputs a 5V supply voltage. The second ends of the capacitors C56 and C73 are grounded. The second end of the resistor R135 is connected to the fourth pin of the power chip U10. The second end of the capacitor C55 is connected to the first end of the resistor R137. The second end of the resistor R137 is grounded. The third pin of the power chip U10 is connected to the first end of the resistor R134, the capacitor C53, and the capacitor C54, and is connected to the negative terminal of the diode D1. The second ends of the capacitors C53 and C54 are grounded. The second end of the resistor R134 is connected to the fifth pin of the power chip U10, the first end of the resistor R136, and the first end of the capacitor C74. The second end of the resistor R136 and the second end of the capacitor C74 are grounded.

3. The POE switch test circuit according to claim 2, characterized in that: The microcontroller includes: a control chip U4, capacitors C11 to C20, resistors R10 to R13, an inductor L1, and a crystal oscillator Y1. The 1st, 24th, 36th, and 48th pins of the control chip U4 are connected to the first ends of the capacitors C13 to C17 and to a 3.3V power supply voltage. The second ends of the capacitors C13 to C17 are grounded. The 5th pin of the control chip U4 is connected to the first end of the capacitor C11 and the fourth pin of the crystal oscillator Y1. The 6th pin of the control chip U4 is connected to the first end of the capacitor C12 and the second pin of the crystal oscillator Y1. The first pin of the crystal oscillator Y1 is connected to the first end of the capacitor C11, the third pin of the crystal oscillator Y1 is grounded, and the second end of the capacitor C12 is grounded. Pins 8, 23, 35, and 47 of the chip U4 are grounded, pin 7 of the control chip U4 is connected to the first ends of the capacitor C20, the resistor R10, the resistor R12, and the resistor R13, the second ends of the resistor R10 and the resistor R13 are connected to the 3.3V power supply voltage, the capacitor C20 and the second end of the resistor R12 are grounded, pin 44 of the control chip U4 is connected to the first end of the resistor R11, the second end of the resistor R11 is grounded, pin 9 of the control chip U4 is connected to the first ends of the inductor L1, the capacitor C18, and the capacitor C19, the second end of the inductor L1 is connected to the 3.3V power supply voltage, and the second ends of the capacitor C18 and the capacitor C19 are grounded.

4. The POE switch test circuit according to claim 3, characterized in that: The test interface unit includes: an Ethernet connector J3 and a surge protection chip U3, wherein the B3 pin of the Ethernet connector J3 is connected to the first pin of the surge protection chip U3, the B6 pin of the Ethernet connector J3 is connected to the second pin of the surge protection chip U3, the third pin of the surge protection chip U3 is grounded, and the NC1, NC2, S1, S2, S3, and S4 pins of the Ethernet connector J3 are grounded; the network isolation transformer unit includes: an isolation chip T1, capacitors C33 to C41, and resistors R27 to R30, wherein the 1st, 4th, 7th, and 10th pins of the isolation chip T1 are respectively connected to the first ends of the capacitors C33 to C36, and the capacitors The second ends of C33 to C36 are grounded, and the 48th, 45th, 42nd and 39th pins of the isolation chip T1 are respectively connected to the first ends of the resistors R27 to R30, and the second ends of the resistors R27 to R30 are connected to the first end of the capacitor C41, and the second end of the capacitor C41 is grounded. The 47th, 46th, 44th, 43rd, 41st, 40th, 38th and 37th pins of the isolation chip T1 are respectively connected to the A2th, A1th, A4th, A3th, A6th, A5th, A8th and A7 pins of the Ethernet connector J3. The rectifier unit includes: a first rectifier module, a second rectifier module, a third rectifier module and a fourth rectifier module; the first rectifier module includes: diodes D3 to D6, the The positive terminal of the diode D3 and the negative terminal of the diode D4 are connected to the 3rd pin of the isolation chip T1, the positive terminal of the diode D5 and the negative terminal of the diode D6 are connected to the 2nd pin of the isolation chip T1, the diode D3 and the negative terminal of the diode D5 output the rectified voltage VDD1, the positive terminal of the diode D4 and the diode D6 are connected to the negative terminal of the external power supply; the second rectifier module includes: diodes D12 to D15, the positive terminal of the diode D12 and the negative terminal of the diode D13 are connected to the 6th pin of the isolation chip T1, the positive terminal of the diode D14 and the negative terminal of the diode D15 are connected to the 6th pin of the isolation chip The 5th pin of the isolation chip T1, the cathode terminals of the diode D12 and the diode D14 output the rectified voltage VDD1, and the positive terminals of the diode D13 and the diode D15 are connected to the common connection terminal; the third rectifier module includes: diodes D16 to D19, the positive terminal of the diode D16 and the negative terminal of the diode D17 are connected to the 9th pin of the isolation chip T1, the positive terminal of the diode D18 and the negative terminal of the diode D19 are connected to the 8th pin of the isolation chip T1, the negative terminals of the diode D16 and the diode D18 output the rectified voltage VDD1, and the positive terminals of the diode D17 and the diode D19 are connected to the common connection terminal;The fourth rectifier module includes diodes D7 to D10. The anode terminal of diode D7 and the cathode terminal of diode D8 are connected to pin 12 of the isolation chip T1. The anode terminal of diode D9 and the cathode terminal of diode D10 are connected to pin 11 of the isolation chip T1. The cathode terminals of diode D7 and diode D9 output the rectified voltage VDD1. The anode terminals of diode D8 and diode D10 are connected to a common connection terminal.

5. The POE switch test circuit according to claim 4, characterized in that: The driving control unit includes: a first driving module, a second driving module and a third driving module; the first driving module includes: a relay J4, an NMOS tube Q6, a resistor R42, a resistor R44, and a resistor R45, the first pin of the relay J4 is connected to the 5V power supply voltage, the second pin of the relay J4 is connected to the rectified voltage VDD1, the fourth pin of the relay J4 is connected to the PD unit, the third pin of the relay J4 is connected to the first end of the resistor R42 and the third pin of the NMOS tube Q6, the second end of the resistor R42 is connected to the 5V power supply voltage, the NMOS tube Q The second pin of the NMOS tube Q6 is connected to the common connection end, the first pin of the NMOS tube Q6 is connected to the first end of the resistor R44 and the first end of the resistor R45, the second end of the resistor R44 is connected to the common connection end, and the second end of the resistor R45 is connected to the 40th pin of the control chip U4; the second driving module includes: an NMOS tube Q7, a resistor R53, a resistor R58 and a resistor R59, the third pin of the NMOS tube Q7 is connected to the first end of the resistor R53, the second end of the resistor R53 is connected to the PD unit, the second pin of the NMOS tube Q7 is connected to the common connection end, and the NMOS The first pin of the S transistor Q7 is connected to the first end of the resistor R59 and the first end of the resistor R58, the second end of the resistor R58 is connected to the 42nd pin of the control chip U4, and the second end of the resistor R59 is connected to the common connection end; the third driving module includes: an NMOS transistor Q8, an NMOS transistor Q21, a resistor R54, a resistor R55, a resistor R56, a resistor R57, a resistor R60, and a resistor R61, the third pins of the NMOS transistor Q8 and the NMOS transistor Q21 are connected to the first end of the resistor R57 and the first end of the resistor R54, respectively, and the second end of the resistor R57 and the second end of the resistor R54 are connected. connected to the PD unit, the NMOS tube Q8 and the second pin of the NMOS tube Q21 are connected to a common connection end, the first pin of the NMOS tube Q8 is connected to the first end of the resistor R60 and the resistor R61, the second end of the resistor R60 is connected to the 45th pin of the control chip U4, the second end of the resistor R61 is connected to the common connection end, the first pin of the NMOS tube Q21 is connected to the first end of the resistor R55 and the resistor R56, the second end of the resistor R55 is connected to the 43rd pin of the control chip U4, and the second end of the resistor R56 is connected to the common connection end.

6. The POE switch test circuit according to claim 5, characterized in that: The PD unit includes: an Ethernet power supply control chip U7, a diode D11, a resistor R31, a resistor R133, a resistor R52, a resistor R122, a resistor R123, a resistor R124, a resistor R125, a resistor R128, a resistor R130, and a capacitor C50. The first pin of the Ethernet power supply control chip U7 is connected to the cathode end of the diode D11 and the first end of the capacitor C50 and is connected to the rectified voltage VDD1. The positive end of the diode D11 and the second end of the capacitor C50 are connected to the common connection end. The Ethernet power supply control chip The second pin of U7 is connected to the first end of the resistor R31, the second end of the resistor R31 is connected to the fourth pin of the relay J4, the third pin of the Ethernet power supply control chip U7 is connected to the classification unit, the sixth pin of the Ethernet power supply control chip U7 is connected to the classification unit, the tenth pin of the Ethernet power supply control chip U7 is connected to the second end of the resistor R53, the eighth pin of the Ethernet power supply control chip U7 is connected to the first end of the resistor R133, the second end of the resistor R133 is connected to the common connection end, and the Ethernet power supply control chip U7 is connected to the first end of the resistor R133. The 7th pin of the Ethernet power supply control chip U7 is connected to the first end of the resistor R52, the second end of the resistor R52 is connected to the common connection end, the 9th pin of the Ethernet power supply control chip U7 is connected to the second end of the resistor R57 and the resistor R54, the 4th, 5th and 21st pins of the Ethernet power supply control chip U7 are connected to the common connection end, the 11th and 12th pins of the Ethernet power supply control chip U7 are connected to the RTN end, and the 19th, 18th and 17th pins of the Ethernet power supply control chip U7 are respectively connected to the first ends of the resistors R122 to R124 They are also respectively connected to the 46th, 21st, and 22nd pins of the control chip U4, the second ends of the resistors R122 to R124 are connected to the 3.3V power supply voltage, the 13th pin of the Ethernet power supply control chip U7 is connected to the first end of the resistor R125, the second end of the resistor R125 is connected to the rectified voltage VDD1, the first ends of the resistor R128 and the resistor R130 are connected to the 11th pin of the control chip U4, the second end of the resistor R128 is connected to the rectified voltage VDD1, and the second end of the resistor R130 is connected to the common connection end.

7. The POE switch test circuit according to claim 6, characterized in that: The load unit includes: a first load module, a second load module, a third load module and a fourth load module; the first load module includes: an amplifier U6A, a MOS tube Q3, a resistor R50, a resistor R32, a resistor R33, a resistor R36, a resistor R34, a resistor R35, and capacitors C42 to C46, the first pin of the amplifier U6A is connected to the first end of the resistor R33 and the capacitor C45, the second end of the resistor R33 is connected to the first pin of the MOS tube Q3, the second end of the capacitor C45 is connected to the second pin of the amplifier U6A, the second pin of the amplifier U6A is connected to the first end of the resistor R36, and the capacitors C42 to C46 are connected. The second end of the resistor R36 is connected to the second pin of the MOS tube Q3, the third pin of the amplifier U6A is connected to the first end of the resistor R32, the second end of the resistor R32 is connected to the first end of the capacitor C43 and the resistor R50 and is connected to the 14th pin of the control chip U4, the second end of the capacitor C43 and the resistor R50 is connected to the common connection terminal, the third pin of the MOS tube Q3 is connected to the first end of the capacitor C42 and is connected to the rectifier voltage VDD1, the second end of the capacitor C42 is connected to the RTN terminal, and the second pin of the MOS tube Q3 is connected to the first end of the resistor R34, the resistor R35, and the capacitor C46 , the second ends of the resistor R34, the resistor R35, and the capacitor C46 are connected to the RTN terminal; the second load module includes: an amplifier U6B, a MOS tube Q4, a resistor R49, a resistor R37, a resistor R38, a resistor R41, a resistor R39, a resistor R40, and capacitors C47 to C49. The seventh pin of the amplifier U6B is connected to the first end of the resistor R38 and the capacitor C48, the second end of the resistor R38 is connected to the first pin of the MOS tube Q4, the second end of the capacitor C48 is connected to the sixth pin of the amplifier U6B, the sixth pin of the amplifier U6B is connected to the first end of the resistor R41, and the resistor R The second end of the MOSFET 41 is connected to the second pin of the MOS transistor Q4, the fifth pin of the amplifier U6B is connected to the first end of the resistor R37, the second end of the resistor R37 is connected to the first end of the capacitor C47 and the resistor R49 and is connected to the 14th pin of the control chip U4, the second end of the capacitor C47 and the resistor R49 are connected to the common connection terminal, the third pin of the MOS transistor Q4 is connected to the rectified voltage VDD1, the second pin of the MOS transistor Q4 is connected to the first end of the resistor R39, the resistor R40, and the capacitor C49, and the second ends of the resistor R39, the resistor R40, and the capacitor C49 are connected to the RTN terminal;The third load module includes: an amplifier U8A, a MOS tube Q9, a resistor R48, a resistor R62, a resistor R63, a resistor R66, a resistor R64, a resistor R65, and capacitors C57 to C61. The first pin of the amplifier U8A is connected to the resistor R63 and the first end of the capacitor C60, the second end of the resistor R63 is connected to the first pin of the MOS tube Q9, the second end of the capacitor C60 is connected to the second pin of the amplifier U6A, the second pin of the amplifier U8A is connected to the first end of the resistor R66, the second end of the resistor R66 is connected to the second pin of the MOS tube Q9, and the third load module includes: an amplifier U8A, a resistor R48, a resistor R62, a resistor R63, a resistor R66, a resistor R64, a resistor R65, and capacitors C57 to C61. The first pin of the amplifier U8A is connected to the first end of the resistor R63 and the first end of the capacitor C60, the second end of the resistor R63 is connected to the first pin of the MOS tube Q9, and the second end of the capacitor C60 is connected to the second pin of the amplifier U6A. The third pin of the device U8A is connected to the first end of the resistor R62, the second end of the resistor R62 is connected to the first end of the capacitor C58 and the resistor R48 and is connected to the 15th pin of the control chip U4, the capacitor C58 and the second end of the resistor R48 are connected to the common connection terminal, the third pin of the MOS tube Q9 is connected to the first end of the capacitor C57 and is connected to the rectified voltage VDD1, the second end of the capacitor C57 is connected to the RTN terminal, the second pin of the MOS tube Q9 is connected to the first end of the resistor R64, the resistor R65, and the capacitor C61, the resistor R64, the resistor R65, the capacitor The second end of C61 is connected to the RTN end; the fourth load module includes: an amplifier U8B, a MOS tube Q10, a resistor R51, a resistor R67, a resistor R68, a resistor R71, a resistor R69, a resistor R70, and capacitors C62 to C64. The seventh pin of the amplifier U8B is connected to the resistor R68 and the first end of the capacitor C63, the second end of the resistor R68 is connected to the first pin of the MOS tube Q10, the second end of the capacitor C63 is connected to the sixth pin of the amplifier U8B, the sixth pin of the amplifier U8B is connected to the first end of the resistor R71, and the second end of the resistor R71 is connected to the MO The second pin of the MOS transistor Q10 is connected to the first end of the resistor R67. The second end of the resistor R67 is connected to the first end of the capacitor C62 and the resistor R51, and is connected to the 15th pin of the control chip U4. The second ends of the capacitor C62 and the resistor R51 are connected to a common connection terminal. The third pin of the MOS transistor Q10 is connected to the rectified voltage VDD1. The second pin of the MOS transistor Q10 is connected to the first end of the resistor R69, the resistor R70, and the capacitor C64. The second ends of the resistor R69, the resistor R70, and the capacitor C64 are connected to the RTN terminal.

8. The POE switch test circuit according to claim 6, characterized in that: The grading unit includes: a first grading module and a second grading module; the first grading module includes: NMOS tubes Q11 to Q15, resistors R95, R87, R76, R73, R78, R81, R83, R86, R89, R93, R98, R77, R82, R88, and R96; the first pin of the NMOS tube Q15 is connected to the first ends of the resistors R95 and R98, the second end of the resistor R95 is connected to the 12th pin of the control chip U4, the second end of the resistor R98 is connected to the common connection end, and the second pin of the NMOS tube Q15 is connected to the common connection end. The third pin of the NMOS transistor Q15 is connected to the first end of the resistor R87, and the second end of the resistor R87 is connected to the third pin of the Ethernet power supply control chip U7; the first pin of the NMOS transistor Q11 is connected to the first end of the resistor R76 and the first end of the resistor R77, the second end of the resistor R76 is connected to the 13th pin of the control chip U4, the second end of the resistor R77 is connected to the common connection terminal, the second pin of the NMOS transistor Q11 is connected to the common connection terminal, the third pin of the NMOS transistor Q11 is connected to the first end of the resistor R73, and the second end of the resistor R73 is connected to the third pin of the Ethernet power supply control chip U7; the first pin of the NMOS transistor Q12 is connected to the first end of the resistor R73, and the second end of the resistor R73 is connected to the third pin of the Ethernet power supply control chip U7. The first ends of the resistors R81 and R82 are connected, the second end of the resistor R81 is connected to the 16th pin of the control chip U4, the second end of the resistor R82 is connected to the common connection end, the second pin of the NMOS transistor Q12 is connected to the common connection end, the third pin of the NMOS transistor Q12 is connected to the first end of the resistor R78, and the second end of the resistor R78 is connected to the 3rd pin of the Ethernet power control chip U7; the first pin of the NMOS transistor Q13 is connected to the first ends of the resistors R86 and R88, the second end of the resistor R86 is connected to the 17th pin of the control chip U4, the second end of the resistor R88 is connected to the common connection end, and the NMOS transistor The second pin of Q13 is connected to the common connection terminal, the third pin of the NMOS transistor Q13 is connected to the first end of the resistor R83, and the second end of the resistor R83 is connected to the third pin of the Ethernet power control chip U7; the first pin of the NMOS transistor Q14 is connected to the first end of the resistor R93 and the first end of the resistor R96, the second end of the resistor R93 is connected to the 32nd pin of the control chip U4, the second end of the resistor R96 is connected to the common connection terminal, the second pin of the NMOS transistor Q14 is connected to the common connection terminal, the third pin of the NMOS transistor Q14 is connected to the first end of the resistor R89, and the second end of the resistor R89 is connected to the third pin of the Ethernet power control chip U7;The second classification module includes: NMOS tubes Q16 to Q20, resistors R72, R74, R43, R79, R80, R75, R85, R90, R84, R92, R94, R91, R99, R100, and R97; the first pin of the NMOS tube Q16 is connected to the first ends of the resistors R72 and R74, the second end of the resistor R72 is connected to the 33rd pin of the control chip U4, the second end of the resistor R74 is connected to the common connection end, the second pin of the NMOS tube Q16 is connected to the common connection end, and the third pin of the NMOS tube Q16 is connected to The first end of the resistor R43 and the second end of the resistor R43 are connected to the 6th pin of the Ethernet power supply control chip U7; the first pin of the NMOS tube Q17 is connected to the first end of the resistor R79 and the first end of the resistor R80, the second end of the resistor R79 is connected to the 38th pin of the control chip U4, the second end of the resistor R80 is connected to the common connection terminal, the second pin of the NMOS tube Q17 is connected to the common connection terminal, the third pin of the NMOS tube Q17 is connected to the first end of the resistor R75, and the second end of the resistor R75 is connected to the 6th pin of the Ethernet power supply control chip U7; the first pin of the NMOS tube Q18 is connected to the resistor R85 and the first end of the resistor R80 The first end of R90 is connected, the second end of the resistor R85 is connected to the 18th pin of the control chip U4, the second end of the resistor R90 is connected to the common connection terminal, the second pin of the NMOS transistor Q18 is connected to the common connection terminal, the third pin of the NMOS transistor Q18 is connected to the first end of the resistor R84, and the second end of the resistor R84 is connected to the 6th pin of the Ethernet power control chip U7; the first pin of the NMOS transistor Q19 is connected to the first end of the resistor R92 and the resistor R94, the second end of the resistor R92 is connected to the 19th pin of the control chip U4, the second end of the resistor R94 is connected to the common connection terminal, and the second pin of the NMOS transistor Q19 is connected to the first end of the resistor R92 and the first end of the resistor R94. The first pin of the NMOS transistor Q20 is connected to the first end of the resistor R99 and the first end of the resistor R100, the second end of the resistor R99 is connected to the 39th pin of the control chip U4, the second end of the resistor R100 is connected to the common connection terminal, the second pin of the NMOS transistor Q20 is connected to the common connection terminal, the third pin of the NMOS transistor Q20 is connected to the first end of the resistor R97, and the second end of the resistor R97 is connected to the 6th pin of the Power over Ethernet control chip U7.

9. The POE switch test circuit according to claim 3, characterized in that: Also includes: a communication interface unit connected to an external communication device, the power supply unit, and the microcontroller, and used for signal exchange between the microcontroller and the external communication device; The communication interface unit includes: a transceiver U2, capacitors C3 to C10, and resistors R4 to R9. The first pin of the transceiver U2 is connected to the third pin of the transceiver U2 through the capacitor C3, the fourth pin of the transceiver U2 is connected to the fifth pin of the transceiver U2 through the capacitor C6, the eleventh pin of the transceiver U2 is connected to the 30th pin of the control chip U4 through the resistor R4, the tenth pin of the transceiver U2 is grounded through the resistor R6, the twelfth pin of the transceiver U2 is connected to the 31st pin of the control chip U4 through the resistor R7, and the 16th pin of the transceiver U2 is connected to the 10th pin of the control chip U4 through the resistor R6. The first pin of the transceiver U2 is connected to the first end of the capacitor C4 and the first end of the capacitor C5 and is connected to the 3.3V power supply voltage. The 15th pin of the transceiver U2 is connected to the second end of the capacitor C4 and the second end of the capacitor C5 and is grounded. The 2nd pin of the transceiver U2 is connected to the 3.3V power supply voltage through the capacitor C7. The 6th pin of the transceiver U2 is grounded through the capacitor C8. The 14th pin of the transceiver U2 is grounded through the resistor R5 and the capacitor C9 in turn. The 13th pin of the transceiver U2 is grounded through the resistor R8 and the capacitor C10 in turn. The 8th pin of the transceiver U2 is grounded through the resistor R9 in turn. A debugging interface unit is connected to an external debugging device, the power supply unit, and the microcontroller for debugging the microcontroller; the adjustment interface unit includes: a connector J2, wherein pins 1 and 2 of the connector J2 are connected to a 3.3V power supply voltage, pins 5 and 6 of the connector J2 are grounded, and pins 3 and 4 of the connector J2 are connected to pins 34 and 37 of the control chip U4, respectively; An information storage unit is connected to the power supply unit and the microcontroller, and is used to store information parameters for the microcontroller to call and read; the information storage unit includes: a memory chip U1, a resistor R1, a resistor R2, a resistor R3, a capacitor C1 and a capacitor C2, the first pin of the memory chip U1 is connected to the first end of the resistor R1 and to the 25th pin of the control chip U4, the second end of the resistor R1 is connected to the 3.3V power supply voltage, the second pin of the memory chip U1 is connected to the 27th pin of the control chip U4, and the 6th pin of the memory chip U1 is connected to the 26th pin of the control chip U4. Pin, the 5th pin of the storage chip U1 is connected to the 28th pin of the control chip U4, the 3rd pin of the storage chip U1 is connected to the first end of the resistor R2, the second end of the resistor R2 is connected to the 3.3V power supply voltage, the 7th pin of the storage chip U1 is connected to the first end of the resistor R3, the second end of the resistor R3 is connected to the 3.3V power supply voltage, the 8th pin of the storage chip U1 is connected to the first end of the capacitor C1 and the capacitor C2 and is connected to the 3.3V power supply voltage, the 4th pin of the storage chip U1 is connected to the second end of the capacitor C1 and the capacitor C2 and is grounded; A heat dissipation unit is connected to the fan, the external power supply, and the microcontroller for heat dissipation; the heat dissipation unit includes: a MOS transistor Q1, a MOS transistor Q2, resistors R18-24, capacitors C29-C32, a diode D2, a plug FAN1, and an inductor L3. The first pin of the MOS transistor Q1 is connected to the first end of the resistor R22, the second end of the resistor R22 is connected to the first end of the resistor R25 and the 29th pin of the control chip U4, the second end of the resistor R25 is grounded, the second pin of the MOS transistor Q1 is grounded, the third pin of the MOS transistor Q1 is connected to the resistor R23 and the first end of the resistor R18, the second end of the resistor R18 is connected to the external power supply, the second end of the resistor R23 is connected to the first end of the capacitor C28 and the first pin of the MOS transistor Q2, the second end of the capacitor C28 is grounded, and the second pin of the MOS transistor Q2 is grounded. The third pin of the MOS transistor Q2 is connected to the first ends of the resistor R19 and the resistor R24. The second end of the resistor R19 is connected to the external power supply. The second end of the resistor R24 is connected to the first ends of the resistor R26 and the resistor R20. The second end of the resistor R26 is grounded. The second end of the resistor R20 is connected to the fourth pin of the plug FAN1. The third pin of the plug FAN1 is connected to the tenth pin of the control chip U4 via the resistor R21. The second pin of the plug FAN1 is connected to the cathode terminal of the diode and the first ends of the capacitor C32, the capacitor C31, and the inductor L3. The positive terminal of the diode and the second ends of the capacitors C32 and C31 are grounded. The second end of the inductor L3 is connected to the first ends of the capacitors C30 and C29 and to the power supply. The second ends of the capacitors C30 and C29 are grounded.

10. A POE switch testing method, characterized in that: The following steps are involved: Step 1: The power module converts the power voltage of the external power supply into 3.3V and 5V supply voltages; Step 2: After the microcontroller starts up, it controls the driver control unit, providing a test circuit for the detection resistor during the subsequent POE detection phase. It also drives the PD unit's Autoclass mode and MPS duty cycle configuration, and sets the PD's classification configuration resistors RclsA and RclsB to the preset impedance. Step 3: Connect the network cable of the POE switch to be tested to the test interface unit, so that the two sets of POE signals to be tested are rectified by the network isolation transformer unit and the rectifier unit and then sent to the PD unit to start POE detection; Step 4: The PD unit generates two corresponding characteristic currents based on the two sets of rectified voltages. When the two characteristic currents meet the current requirements of the POE switch under test for the detection phase, the POE classification phase begins. Step 5: The microcontroller controls the rectifier unit to raise the rectifier voltage to within a preset threshold range, causing the PD unit to generate a characteristic current to indicate to the POE switch under test that the PD unit supports the Autoclass mode. A preset voltage is also applied to the RclsA pin and RclsB pin of the PD unit, causing the PD unit to generate two corresponding characteristic currents. Step 6: The classification generates a gear signal according to the characteristic current. The microcontroller adjusts the load unit according to the gear signal and verifies the power consumption of the POE switch PD level according to the total power consumption of the load unit.

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