Silicon carbide device and manufacturing method thereof

Abstract

The invention discloses a silicon carbide device and a manufacturing method thereof, and belongs to the technical field of integrated circuits, the manufacturing method of the silicon carbide device comprises the steps that a substrate and an epitaxial layer on the top of the substrate are provided, a body region, a contact region and at least two source and drain regions are arranged in the epitaxial layer, and a gate oxide layer, a gate and a dielectric layer are sequentially arranged on the top of the epitaxial layer; an opening is formed in the top of the contact area; in the top of the contact region and the exposed region of the source and drain region, a sacrificial oxide layer is formed through a thermal oxidation process, and the top surface of the contact region is lower than the bottom surface of the source and drain region; and etching to remove the sacrificial oxide layer and a part of the side wall material layer so as to form a side wall on the side wall of the dielectric layer, and forming a gap between the bottom of the side wall and the top of the source-drain region. A subsequent Schottky diode is conveniently formed by etching the hole to the bottom of the source / drain region, and meanwhile, a section structure of a relatively ideal contact hole is formed by utilizing a gap below the side wall, so that the performance of the device is improved, the process cost is saved, and the production period is shortened.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a silicon carbide device and a method for manufacturing the same. Background Art

[0002] Third-generation semiconductors, represented by SiC, are widely used in the lighting industry, photovoltaic power supplies, power electronics, microwave radio frequency, and other fields. In addition, because SiC materials have a larger bandgap, critical breakdown electric field, and higher thermal conductivity, they are more suitable for the manufacture of high-voltage and high-power semiconductor devices. However, in the process of manufacturing silicon carbide devices, how to optimize the process and reduce manufacturing costs has received widespread attention in the industry. With the continuous iteration and evolution of the process, the design size of silicon carbide devices has gradually decreased, and the manufacturing cost has continued to rise, ultimately leading to high product prices. The traditional silicon carbide device manufacturing process has encountered bottlenecks in the hole etching process and the reduction of contact resistance. Either the hole size is increased to reduce the contact resistance, but this increases the input capacitance and affects the switching speed, or the method of increasing the injection concentration is used, but this method has also reached its limit.

[0003] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0004] The object of the present invention is to provide a silicon carbide device and a manufacturing method thereof to solve the problem of contact resistance.

[0005] In order to solve the above technical problems, the present invention provides a method for manufacturing a silicon carbide device, comprising the following steps: A substrate and an epitaxial layer on top of the substrate are provided, wherein the epitaxial layer is provided with a body region, a contact region, and at least two source and drain regions, wherein the body region is provided on opposite sides and bottoms of two adjacent source and drain regions, and the contact region is provided between the two adjacent source and drain regions, with both sides of the contact region being in contact with the body region. A gate oxide layer, a gate, and a dielectric layer are sequentially provided on top of the epitaxial layer, and an opening is provided on the top of the contact region, wherein the opening penetrates the dielectric layer and exposes at least a portion of the sidewalls and at least a portion of the top surface of the source and drain regions on a side close to the contact region. forming a sacrificial oxide layer on the top of the contact region and the exposed area of the source and drain regions by a thermal oxidation process, wherein the top surface of the contact region is lower than the bottom surface of the source and drain regions and higher than the bottom surface of the body region; forming a spacer material layer on the sacrificial oxide layer and the dielectric layer, and etching away the sacrificial oxide layer and a portion of the spacer material layer to form a spacer on the sidewall of the dielectric layer, with a gap between the bottom of the spacer and the top of the source and drain region; A concave contact metal layer is provided on the top of the contact area and in the gap.

[0006] Preferably, setting the body region and source / drain region on the epitaxial layer includes: forming a first oxide layer, a first hard mask layer and a first photoresist layer in sequence on the epitaxial layer, etching the first hard mask layer through the first photoresist layer to expose a portion of the first oxide layer for ion implantation to form the body region; forming a sidewall mask layer on the sidewall of the first hard mask layer, implanting ions into the exposed area to form the source / drain region, and performing annealing to activate the source / drain region and the body region.

[0007] Preferably, after forming the body region and the source / drain region, the first hard mask layer is removed, a second hard mask layer is formed on the first oxide layer, the second hard mask layer, the first oxide layer and the epitaxial layer are etched, and an opening is formed between two adjacent source / drain regions, the bottom surface of the opening is higher than the lower surface of the body region, an oxide is formed in the opening, the oxide and the remaining first oxide layer are connected to form a second oxide layer, and ions are implanted into the bottom of the opening to form a contact region.

[0008] Preferably, after forming the second oxide layer and the contact area, the second hard mask layer is removed, a polysilicon layer is formed on the second oxide layer, the polysilicon layer is etched to form a gate, and the second oxide layer on the top of the opening and a portion of the source and drain region is exposed, a dielectric material layer is deposited on the gate and the second oxide layer, and the dielectric material layer and the second oxide layer are wet-etched until at least a portion of the sidewalls and at least a portion of the top surface of the source and drain region are exposed to form a step structure, and the remaining second oxide layer serves as the gate oxide layer.

[0009] Preferably, the sidewalls are made of silicon nitride.

[0010] Preferably, etching away the sacrificial oxide layer and part of the sidewall material layer comprises: first etching the sidewall material layer to expose the sacrificial oxide layer, and wet etching the sacrificial oxide layer to expose the gap between the bottom of the sidewall and the top of the source and drain region.

[0011] Preferably, setting a concave contact metal layer on the top of the contact area and in the gap includes: depositing a contact metal material layer, the contact metal material layer covering the top of the dielectric layer, the side wall, the top of the contact area and the gap, and etching away excess contact metal material layer on the top of the dielectric layer and the side wall to form a concave contact metal layer.

[0012] Preferably, the conductivity type of the source and drain regions is N-type; and the conductivity type of the contact region is P-type.

[0013] A silicon carbide device is manufactured using the above-mentioned method for manufacturing a silicon carbide device.

[0014] A silicon carbide device, comprising: A substrate, wherein an epitaxial layer is provided on top of the substrate, wherein the epitaxial layer is provided with a body region, a contact region, and at least two source and drain regions, wherein the body region is provided on opposite sides and bottoms of two adjacent source and drain regions, wherein the contact region is provided between the two adjacent source and drain regions, and both sides of the contact region are in contact with the body region, wherein a gate oxide layer, a gate, and a dielectric layer are provided in sequence on top of the epitaxial layer, wherein an opening is provided on the top of the contact region, wherein the opening penetrates the dielectric layer and exposes the sidewalls of the source and drain regions on a side close to the contact region and at least a portion of the top surface, thereby forming a stepped structure; wherein the top surface of the contact region is lower than the bottom surface of the source and drain regions and higher than the bottom surface of the body region; A sidewall spacer is provided on the sidewall of the dielectric layer, and a gap is provided between the bottom of the sidewall spacer and the source / drain region; A concave contact metal layer is arranged on the top of the contact region and extends into the gap along the exposed sidewalls and top of the source and drain regions.

[0015] In the manufacturing method of the silicon carbide device provided by the present invention, a relatively ideal cross-sectional structure is obtained by using the back-end thin film deposition process as a mask and then performing hole lithography, hole etching, and wet etching. The characteristics of the process and design are utilized to allow the contact hole to be etched into the body region to facilitate the formation of a subsequent Schottky diode. At the same time, the structure utilizes the sidewall process and the "inward extension structure" under the sidewall to form a relatively ideal cross-sectional structure of the contact hole. The contact metal layer and the injected contact area can not only form a relatively ideal ohmic contact, but also effectively increase the contact area of the hole, thereby improving the performance of the device. At the same time, the composite sidewall structure is adopted to effectively reduce the capacitance and obtain a relatively ideal device figure of merit.

[0016] The silicon carbide device provided by the present invention and the method for manufacturing the silicon carbide device provided by the present invention belong to the same inventive concept. Therefore, the silicon carbide device provided by the present invention has at least all the advantages of the method for manufacturing the silicon carbide device provided by the present invention, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention. Figure 1 is a schematic diagram of a substrate structure according to an embodiment of the present invention; Figure 2 is a schematic diagram of a hard mask layer structure according to an embodiment of the present invention; Figure 3 is a schematic diagram of the body region structure according to an embodiment of the present invention; Figure 4 1 is a schematic diagram of the source and drain region structure according to an embodiment of the present invention; Figure 5 is a schematic structural diagram of a second photoresist layer according to an embodiment of the present invention; Figure 6 This is a schematic structural diagram of etching along the second photoresist layer according to an embodiment of the present invention; Figure 7 is a schematic diagram of the structure of the second oxide layer according to an embodiment of the present invention; Figure 8 1 is a schematic diagram of annealing according to an embodiment of the present invention; Figure 9 is a schematic diagram of the polysilicon layer structure according to an embodiment of the present invention; Figure 10 is a schematic diagram of a gate structure according to an embodiment of the present invention; Figure 11 is a schematic diagram of the dielectric material layer structure according to an embodiment of the present invention; Figure 12 is a schematic diagram of the dielectric layer structure according to an embodiment of the present invention; Figure 13 1 is a schematic diagram of the structure of a sidewall material layer according to an embodiment of the present invention; Figure 14 1 is a schematic diagram of the side wall structure of an embodiment of the present invention; Figure 15 is a schematic diagram of the structure of a contact metal material layer according to an embodiment of the present invention; Figure 16 1 is a schematic diagram of a cross-sectional structure of a silicon carbide device according to an embodiment of the present invention; Figure 17 It is an execution flow chart of an embodiment of the present invention.

[0018] In the attached figure: 100. Substrate; 101. Epitaxial layer; 102. First oxide layer; 102a. First oxide layer pattern; 103. Body region; 104. Source and drain region; 105. Opening; 106. Second oxide layer; 107. Contact region; 108. Gate oxide layer; 109. Sacrificial oxide layer; 110. Polysilicon layer; 111. Gate; 120. Dielectric material layer; 121. Dielectric layer; 130. Spacer material layer; 131. Spacer; 140. Contact metal material layer; 141. Contact metal layer; 200. First hard mask layer; 201. Spacer mask layer; 202. Second hard mask layer; 300. First photoresist layer; 301. Second photoresist layer; 302. Third photoresist layer; 400. Covering layer; 500. Conductive layer. DETAILED DESCRIPTION

[0019] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0020] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in a sense including "and / or", the term "several" is generally used in a sense including "at least one", and the term "at least two" is generally used in a sense including "two or more". In addition, the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features. Therefore, features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of such features. The term "proximal end" generally refers to the end closest to the operator, and the term "distal end" generally refers to the end closest to the patient. "One end" and "the other end" as well as "proximal end" and "distal end" generally refer to two corresponding parts, which include not only endpoints. The terms "mounted", "connected", and "connected" should be understood in a broad sense. For example, they can be fixedly connected, detachably connected, or integrated; they can be mechanically connected or electrically connected; they can be directly connected or indirectly connected through an intermediate medium; they can be internal communication between two elements or an interactive relationship between two elements. In addition, as used in the present invention, "one element is arranged on another element" generally only means that there is a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element, and it should not be understood to indicate or imply a spatial positional relationship between the two elements, that is, one element can be in any position such as inside, outside, above, below, or to the side of another element, unless the content clearly indicates otherwise. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0021] Research has found that third-generation semiconductors represented by SiC have a wide range of applications in the lighting industry, photovoltaic power supplies, power electronics, microwave radio frequency, and other fields. In addition, because SiC materials have a larger bandgap width, critical breakdown electric field, and higher thermal conductivity, they are more suitable for the manufacture of high-voltage and high-power semiconductor devices. However, in the process of manufacturing silicon carbide devices, how to optimize and reduce the hole contact resistance has received widespread attention in the industry and has become a hot topic of research in the industry. With the continuous iteration and evolution of the process, the design size of silicon carbide devices has gradually shrunk, and the size of the hole has also continued to decrease, which ultimately leads to an increase in the contact resistance of the hole. The increase in contact resistance has a very adverse effect on the performance of the device, such as an increase in threshold voltage, an increase in specific on-resistance, and easy heat generation.

[0022] Based on this, the core idea of the present invention is to propose a high-performance, low-cost SiC MOSFET device preparation process, borrow the back-end thin film deposition process as a mask and then perform photolithography, etching and implantation to obtain a more ideal implant profile structure. Utilizing the characteristics of the process and design, the hole is etched to the bottom of the source and drain region to facilitate the formation of the subsequent Schottky diode. At the same time, the structure utilizes the sidewall process and the "inward extension structure" under the sidewall to form a more ideal contact hole profile structure, thereby improving device performance and saving process costs and production cycle.

[0023] For details, please refer to Figures 1-17 , which is a schematic diagram of an embodiment of the present invention. Figure 17 As shown, a method for manufacturing a silicon carbide device includes the following steps.

[0024] A substrate 100 and an epitaxial layer 101 on top thereof are provided. The epitaxial layer 101 is provided with a body region 103, a contact region 107, and at least two source / drain regions 104. The body region 103 is provided on opposite sides and bottoms of two adjacent source / drain regions 104. The contact region 107 is provided between the two adjacent source / drain regions 104, and both sides of the contact region 107 are in contact with the body region 103. A gate oxide layer 108, a gate 111, and a dielectric layer 121 are provided in sequence on top of the epitaxial layer 101. An opening 105 is provided on top of the contact region 107. The opening 105 penetrates the dielectric layer 121 and exposes at least a portion of the sidewalls and at least a portion of the top surface of the source / drain region 104 on a side near the contact region 107. A sacrificial oxide layer 109 is formed on the top of the contact region 107 and the exposed area of the source and drain regions 104 by a thermal oxidation process, wherein the top surface of the contact region 107 is lower than the bottom surface of the source and drain regions 104 and higher than the bottom surface of the body region 103; forming a spacer material layer 130 on the sacrificial oxide layer 109 and the dielectric layer 121, and etching away the sacrificial oxide layer 109 and a portion of the spacer material layer 130 to form a spacer 131 on the sidewall of the dielectric layer 121, with a gap between the bottom of the spacer 131 and the top of the source and drain region 104; A concave contact metal layer 141 is disposed on the top of the contact region 107 , the exposed area of the body region 103 , and the exposed sidewalls and top of the source / drain region 104 .

[0025] like Figure 12 The structure of substrate 100 and epitaxial layer 101 is shown. A body region 103, a contact region 107, and at least two source and drain regions 104 are provided on epitaxial layer 101. A gate oxide layer 108, a gate electrode 111, and a dielectric layer 121 are sequentially formed on top of epitaxial layer 101. The top of contact region 107 and portions of the top and sidewalls of source and drain regions 104 are exposed through opening 105. A relatively thin sacrificial oxide layer 109 is grown as a buffer etch layer to form spacers 131. The spacer process and the "inward extension structure" of contact metal layer 141 formed in the gap below the spacer create a relatively ideal contact hole cross-section.

[0026] Furthermore, the formation of the sacrificial oxide layer 109 will consume a portion of the source and drain regions 104 and the contact region 107, and can trim the cross-sectional structure of the contact hole so that the bottom of the opening 105 is etched into the body region 103. The bottom of the opening 105 is also the top surface of the contact region 107. The top surface of the contact region 107 is lower than the bottom surface of the source and drain regions 104 and higher than the bottom surface of the body region 103, which facilitates the formation of a subsequent Schottky diode.

[0027] The following will be combined with the attached Figures 1 to 16 The method for manufacturing the silicon carbide device provided in this embodiment is described in more detail.

[0028] First, a body region 103 and a source / drain region 104 are formed on the epitaxial layer 101 by ion implantation. Arranging the body region 103 and the source / drain region 104 on the epitaxial layer 101 includes: sequentially forming a first oxide layer 102, a first hard mask layer 200, and a first photoresist layer 300 on the epitaxial layer 101; etching the first hard mask layer 200 through the first photoresist layer 300 to expose a portion of the first oxide layer 102 for ion implantation to form the body region 103; forming a sidewall mask layer 201 on the sidewall of the first hard mask layer 200, implanting ions into the exposed area to form the source / drain region 104, and performing annealing to activate the source / drain region 104 and the body region 103.

[0029] like Figure 1As shown, the wafer in this case adopts a multi-layer epitaxial substrate 100, and illustratively, the material of the epitaxial layer 101 is SiC. The whole wafer containing the silicon carbide epitaxial layer 101 is cleaned by the RCA process. A first hard mask layer 200 is deposited on the whole wafer, and the deposition method includes but is not limited to PECVD (plasma enhanced chemical vapor deposition), ALD (atomic layer deposition), LPCVD (low pressure chemical vapor deposition) and other methods. Then, the first hard mask layer 200 is coated with glue, photolithography, etching and ion implantation processes are performed to form the body region 103, the first photoresist layer 300 is photolithographically formed to form the desired photoresist pattern, the exposed first hard mask layer 200 is etched, and the exposed area of the first hard mask layer 200 is ion implanted to form the body region 103, as shown in FIG. Figure 2 As shown, then Figure 3 As shown, a spacer mask layer 201 is deposited on the top and sidewalls of the first hard mask layer 200 to define the source / drain regions 104 within the body region 103. Ion implantation is then performed to form the source / drain regions 104. Annealing is then performed directly to activate the body region 103 and the source / drain regions 104. Conventional processes would then utilize a hard mask for depositing the contact regions 107. However, due to optimization, this process is omitted in the present invention. Therefore, annealing is performed directly to activate the body region 103 and the source / drain regions 104.

[0030] Secondly, after forming the body region 103 and the source and drain regions 104, the first hard mask layer 200 is removed, and a second hard mask layer 202 is formed on the first oxide layer 102. The second hard mask layer 202, the first oxide layer 102 and the epitaxial layer 101 are etched to form an opening between two adjacent source and drain regions 104. The bottom surface of the opening 105 is higher than the lower surface of the body region 103, and an oxide is formed in the opening 105. The oxide and the remaining first oxide layer 102 are connected to form a second oxide layer 106. Ions are implanted into the bottom of the opening 105 to form a contact region 107.

[0031] like Figure 5 As shown, after removing the first hard mask layer 200, a second hard mask layer 202 and a second photoresist layer 301 are formed on the entire wafer. The second photoresist layer 301 is photoetched to define the area between two adjacent source and drain regions 104. The second hard mask layer 202 is etched and a portion of the first oxide layer 102 and the epitaxial layer 101 are etched to form an opening 105 between the source and drain regions 104. Figure 6 As shown, the first oxide layer 102 is separated by the opening 105 to form a first oxide layer pattern 102a. Figure 7 As shown, an oxide is formed in the opening 105, and the oxide is connected to the remaining first oxide layer 102 to form a second oxide layer 106. For example, a thermal oxidation process is used to form the oxide in the opening 105. Ion implantation is performed on the bottom of the opening 105 to form a contact region 107.

[0032] In one embodiment, a photoresist layer is deposited, and the opening 105 between the source and drain regions 104 is defined by photolithography, and ion implantation is performed to form the contact region 107, and then the photoresist layer is removed by stripping. Figure 8 As shown, a capping layer 400 is formed and annealed to activate the contact region 107 .

[0033] Next, after forming the second oxide layer 106 and the contact region 107, the second hard mask layer 202 is removed, and a polysilicon layer 110 is formed on the second oxide layer 106. The polysilicon layer 110 is etched to form a gate 111, and the second oxide layer 106 on the top of the opening 105 and a portion of the source and drain regions 104 is exposed. A dielectric material layer 120 is deposited on the gate 111 and the second oxide layer 106, and the dielectric material layer 120 and the second oxide layer 106 are wet-etched until at least a portion of the sidewalls and at least a portion of the top surface of the source and drain regions 104 are exposed, forming a step structure. The remaining second oxide layer 106 serves as the gate oxide layer 108. The first oxide layer 102, the second oxide layer 106, the gate oxide layer 108, and the sacrificial oxide layer 109 are all made of silicon oxide, and the dielectric material layer 120 is also made of silicon oxide. like Figure 9 As shown, after removing the second hard mask layer 202, the polysilicon layer 110 is formed, and the polysilicon layer 110 is etched to form a gate 111, as shown in FIG. Figure 10 As shown, the dielectric material layer 120 and the third photoresist layer 302 are deposited, and then the contact hole photolithography process is performed. After the etching process is completed, wet etching is performed to increase the area of the hole. It should be noted that the amount of wet etching needs to be controlled to ensure the formation of the step structure, forming Figure 12 The structure shown.

[0034] Next, a sacrificial oxide layer 109 is formed on the top of the contact region 107 and in the exposed area of the source and drain region 104 by a thermal oxidation process, wherein the top surface of the contact region 107 is lower than the bottom surface of the source and drain region 104 and higher than the bottom surface of the body region 103.

[0035] In this embodiment, a thinner sacrificial oxide layer 109 is grown as a buffer etching layer. The generated sacrificial oxide layer 109 makes the top surface of the contact region 107 lower than the bottom surface of the source and drain region 104 and higher than the bottom surface of the body region 103. After removing the sacrificial oxide layer 109, the opening 105 will completely expose one side wall of the source and drain region 104 and a portion of the body region 103.

[0036] A spacer material layer 130 is then formed on the sacrificial oxide layer 109 and the dielectric layer 121. The sacrificial oxide layer 109 and a portion of the spacer material layer 130 are removed by etching to form spacers 131 on the sidewalls of the dielectric layer 121. A gap is formed between the bottom of the spacer 131 and the top of the source / drain region 104. Exemplarily, the spacer 131 is made of silicon nitride.

[0037] Specifically, etching and removing the sacrificial oxide layer 109 and part of the sidewall material layer 130 includes: first etching the sidewall material layer 130 to expose the sacrificial oxide layer 109, and wet etching the sacrificial oxide layer 109 to expose the gap between the bottom of the sidewall 131 and the top of the source and drain region 104.

[0038] like Figure 13 As shown, a certain thickness of silicon nitride sidewall material layer 130 is deposited on the entire wafer and etched to clean the bottom silicon nitride sidewall material layer 130 so that the sacrificial oxide layer 109 is fully exposed. Subsequently, wet etching is performed to expose the required contact hole area, as shown in FIG. Figure 14 As shown, the contact hole region includes the opening 105 and the gap between the bottom of the spacer 131 and the top of the source and drain region 104 .

[0039] A concave contact metal layer 141 is further provided on the top of the contact region 107 and in the gap. That is, the concave contact metal layer 141 is provided on the top of the contact region 107, the exposed area of the body region 103, and the exposed sidewalls and top of the source and drain regions 104.

[0040] An ohmic contact metal deposition and ohmic contact annealing process are performed, and unreacted metal is removed by wet etching. Specifically, providing a concave contact metal layer 141 on the top of the contact area 107 and in the gap includes: depositing a contact metal material layer 140, wherein the contact metal material layer 140 covers the top of the dielectric layer 121, the sidewalls 131, the top of the contact area 107, and the gap; and etching away excess contact metal material layer 140 on the top of the dielectric layer 121 and the sidewalls of the sidewalls 131 to form the concave contact metal layer 141.

[0041] like Figure 14 As shown, after removing the sacrificial oxide layer 109, a slightly wider and deeper new opening 105 is obtained. The bottom surface of the opening 105 is also the top surface of the contact region 107. The sidewalls of the source and drain regions 104, part of the body region 103 and the top surface of the contact region 107 are exposed through the opening 105. Figure 15As shown, a contact metal material layer 140 is deposited on the entire wafer, and the contact metal material layer 140 is filled in the gap between the side wall 131 and the source and drain region 104. The excess contact metal material layer 140 on the side wall 131 is removed, and the concave contact metal layer 141 covers the top surface of the contact region 107, the side wall and part of the top surface of the source and drain region 104, and a part of the body region 103.

[0042] In one embodiment, the conductivity type of the source and drain regions 104 is N-type; the conductivity type of the contact region 107 is P-type.

[0043] like Figure 16 As shown, a conductive layer 500 is deposited to fill the opening 105 with the conductive layer 500 . The conductive layer 500 fills the opening 105 and covers the top surface of the dielectric layer 121 . The conductive layer 500 may be made of aluminum.

[0044] Based on the same technical concept, the present invention also provides a silicon carbide device, which is manufactured using the above-mentioned method for manufacturing a silicon carbide device.

[0045] Based on the same technical concept, the present invention also provides a silicon carbide device, comprising: A substrate 100 is provided with an epitaxial layer 101 on top of the substrate 100. The epitaxial layer 101 is provided with a body region 103, a contact region 107, and at least two source and drain regions 104. The body region 103 is provided on opposite sides and bottoms of two adjacent source and drain regions 104. The contact region 107 is provided between the two adjacent source and drain regions 104, and both sides of the contact region 107 are in contact with the body region 103. A gate oxide layer 108, a gate 111, and a dielectric layer 121 are provided in sequence on top of the epitaxial layer 101. An opening 105 is provided on the top of the contact region 107. The opening 105 penetrates the dielectric layer 121 and exposes the sidewalls and at least a portion of the top surface of the source and drain regions 104 on a side near the contact region 107, forming a stepped structure. The top surface of the contact region 107 is lower than the bottom surface of the source and drain regions 104 and higher than the bottom surface of the body region 103. A sidewall spacer 131 is provided on a sidewall of the dielectric layer 121 , and a gap is provided between the bottom of the sidewall spacer 131 and the source / drain region 104 ; The concave contact metal layer 141 is disposed on the top of the contact region 107 and extends along the exposed sidewalls and top of the source / drain region 104 into the gap.

[0046] The top surface of the contact region 107 is lower than the bottom surface of the source and drain region 104 and higher than the bottom surface of the body region 103. A portion of the body region 103 is exposed through the opening 105. The exposed body region 103 facilitates the formation of a Schottky diode. The contact metal layer 141 is filled in the gap below the side wall 131 to form an "inward extension structure", forming a more ideal ohmic contact, effectively increasing the contact area of the hole, and improving the performance of the device. At the same time, the composite side wall structure is adopted to effectively reduce the capacitance and obtain a more ideal device figure of merit.

[0047] At least two source and drain regions 104 are provided in the epitaxial layer 101. Body regions 103 are provided outside the source and drain regions 104. An opening 105 is provided between two adjacent source and drain regions 104. The bottom of the opening 105 is a contact region 107. A gate oxide layer 108, a gate 111, and a dielectric layer 121 are also provided on the epitaxial layer 101. The gate oxide layer 108 exposes a portion of the top surface of the source and drain regions 104. The gate oxide layer 108 and the dielectric layer 121 together cover the gate 111, forming a step structure between the opening 105 and the top surface of the source and drain regions 104. A contact metal layer 141 covers the bottom surface of the opening 105 and extends along the sidewalls of the exposed body region 103 and source and drain regions 104 to form the step structure, and fills the gap between the bottom of the sidewall spacer 131 and the top surface of the source and drain regions 104.

[0048] Exemplarily, the gate oxide layer 108 and the dielectric layer 121 are both made of silicon oxide, the gate 111 is made of polysilicon, and the sidewall spacer 131 is made of silicon nitride.

[0049] like Figure 16 As shown, the contact metal layer 141 and the sidewall spacer 131 are further filled with a conductive layer 500. The conductivity type of the source and drain regions 104 is N-type; the conductivity type of the contact region 107 is P-type.

[0050] The present invention provides a process for preparing a high-performance, low-capacitance SiC MOSFET device. The process utilizes a back-end thin film deposition process as a mask and then performs hole photolithography, hole etching, and wet etching to obtain a relatively ideal cross-sectional structure. Utilizing the characteristics of the process and design, the contact hole is etched into the body region 103 to facilitate the formation of a subsequent Schottky diode. At the same time, the structure utilizes a sidewall process and an "inward extension structure" under the sidewall to form a relatively ideal contact hole cross-sectional structure. The contact metal layer 141 and the implanted N-type SiC contact not only form a relatively ideal ohmic contact, but also effectively increase the contact area of the hole, thereby improving the performance of the device. At the same time, the composite sidewall structure is adopted to effectively reduce the capacitance and obtain a relatively ideal device figure of merit.

[0051] The above description is only a description of the preferred embodiment of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing a silicon carbide device, characterized in that: The following steps are involved: A substrate and an epitaxial layer on top of the substrate are provided, wherein the epitaxial layer is provided with a body region, a contact region, and at least two source and drain regions, wherein the body region is provided on opposite sides and bottoms of two adjacent source and drain regions, and the contact region is provided between the two adjacent source and drain regions, with both sides of the contact region being in contact with the body region. A gate oxide layer, a gate, and a dielectric layer are sequentially provided on top of the epitaxial layer, and an opening is provided on the top of the contact region, wherein the opening penetrates the dielectric layer and exposes at least a portion of the sidewalls and at least a portion of the top surface of the source and drain regions on a side close to the contact region. forming a sacrificial oxide layer on the top of the contact region and the exposed area of the source and drain regions by a thermal oxidation process, wherein the top surface of the contact region is lower than the bottom surface of the source and drain regions and higher than the bottom surface of the body region; forming a spacer material layer on the sacrificial oxide layer and the dielectric layer, and etching away the sacrificial oxide layer and a portion of the spacer material layer to form a spacer on the sidewall of the dielectric layer, with a gap between the bottom of the spacer and the top of the source and drain region; A concave contact metal layer is provided on the top of the contact area and in the gap.

2. The method for manufacturing a silicon carbide device according to claim 1, wherein: Providing the body region and the source / drain region on the epitaxial layer includes: sequentially forming a first oxide layer, a first hard mask layer, and a first photoresist layer on the epitaxial layer, etching the first hard mask layer through the first photoresist layer to expose a portion of the first oxide layer for ion implantation to form the body region; forming a sidewall mask layer on the sidewall of the first hard mask layer, implanting ions into the exposed area to form the source / drain region, and performing annealing to activate the source / drain region and the body region.

3. The method for manufacturing a silicon carbide device according to claim 2, wherein: After forming the body region and the source / drain region, the first hard mask layer is removed, a second hard mask layer is formed on the first oxide layer, the second hard mask layer, the first oxide layer and the epitaxial layer are etched, and an opening is formed between two adjacent source / drain regions, wherein the bottom surface of the opening is higher than the lower surface of the body region, an oxide is formed in the opening, and the oxide and the remaining first oxide layer are connected to form a second oxide layer, and ions are implanted into the bottom of the opening to form a contact region.

4. The method for manufacturing a silicon carbide device according to claim 3, wherein: After forming the second oxide layer and the contact region, the second hard mask layer is removed, a polysilicon layer is formed on the second oxide layer, the polysilicon layer is etched to form a gate, and the second oxide layer on top of the opening and a portion of the source and drain regions is exposed, a dielectric material layer is deposited on the gate and the second oxide layer, and the dielectric material layer and the second oxide layer are wet-etched until at least a portion of the sidewalls and at least a portion of the top surface of the source and drain regions are exposed to form a step structure, and the remaining second oxide layer serves as the gate oxide layer.

5. The method for manufacturing a silicon carbide device according to claim 1, wherein: The sidewalls are made of silicon nitride.

6. The method for manufacturing a silicon carbide device according to claim 1, wherein: Etching and removing the sacrificial oxide layer and part of the spacer material layer includes: first etching the spacer material layer to expose the sacrificial oxide layer, and wet etching the sacrificial oxide layer to expose the gap between the bottom of the spacer and the top of the source and drain region.

7. The method for manufacturing a silicon carbide device according to claim 1, wherein: Providing a concave contact metal layer on the top of the contact area and in the gap includes: depositing a contact metal material layer, the contact metal material layer covering the top of the dielectric layer, the sidewalls, the top of the contact area and the gap, and etching away excess contact metal material layer on the top of the dielectric layer and the sidewalls of the sidewalls to form a concave contact metal layer.

8. The method for manufacturing a silicon carbide device according to claim 1, wherein: The conductivity type of the source and drain regions is N-type; the conductivity type of the contact region is P-type.

9. A silicon carbide device, characterized in that: The silicon carbide device is manufactured using the method for manufacturing the silicon carbide device according to any one of claims 1 to 8.

10. A silicon carbide device, characterized in that: include: A substrate, wherein an epitaxial layer is provided on top of the substrate, wherein the epitaxial layer is provided with a body region, a contact region, and at least two source and drain regions, wherein the body region is provided on opposite sides and bottoms of two adjacent source and drain regions, wherein the contact region is provided between the two adjacent source and drain regions, and both sides of the contact region are in contact with the body region, wherein a gate oxide layer, a gate, and a dielectric layer are provided in sequence on top of the epitaxial layer, wherein an opening is provided on the top of the contact region, wherein the opening penetrates the dielectric layer and exposes the sidewalls of the source and drain regions on a side close to the contact region and at least a portion of the top surface, thereby forming a stepped structure; wherein the top surface of the contact region is lower than the bottom surface of the source and drain regions and higher than the bottom surface of the body region; A sidewall spacer is provided on the sidewall of the dielectric layer, and a gap is provided between the bottom of the sidewall spacer and the source / drain region; A concave contact metal layer is arranged on the top of the contact region and extends into the gap along the exposed sidewalls and top of the source and drain regions.

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