An integrated super junction power mos device with corrugated gate oxide and a method of manufacturing the same

Abstract

The application discloses an integrated super-junction power MOS device with corrugated gate oxide and a preparation method thereof, and belongs to the technical field of semiconductors. The device comprises a substrate, a buffer layer and an epitaxial layer which are sequentially stacked from bottom to top; wherein the epitaxial layer is provided with a plurality of vertically spaced super-junction columns, and the top of each super-junction column is provided with a body region; the surface layer of the body region is provided with a contact hole doped region and a source doped region which are in contact with each other; the upper surface of the epitaxial layer is further provided with a gate oxide layer; the gate oxide layer is in a corrugated structure, and the lower surface of the gate oxide layer is adapted to and contacts with a corrugated groove located on the upper surface of the epitaxial layer, the body region and part of the source doped region; the upper surface of the gate oxide layer and part of the source doped region is covered with a polysilicon layer, and the gate oxide layer and the polysilicon layer form a corrugated gate structure. The integrated super-junction power MOS device with corrugated gate oxide has good single-particle burnout resistance and single-particle gate penetration resistance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a superjunction power MOS device with integrated corrugated gate oxide and its fabrication method. Background Technology

[0002] Because outer space contains a large number of X-rays, gamma rays, neutrons, heavy particles, etc., spacecraft operating in space will be exposed to radiation from these rays and particles, causing disturbances to the spacecraft's electronic systems, and even leading to the failure of the electronic systems, seriously affecting the safe operation of the spacecraft in orbit.

[0003] As a crucial component of spacecraft, power MOS (Metal Oxide Semiconductor) devices experience total ionizing radiation dose effects when exposed to X-rays and gamma rays, causing parameter drift. Neutron radiation increases the power consumption of power MOS devices, but these issues can be mitigated through redundancy design. However, heavy particle radiation causes single-event gate breakdown (SEGR) and single-event burnout (SEB) effects in power MOS devices, leading to device failure and rendering the electronic system inoperable. This is particularly true for power MOS devices manufactured using micro / submicron processes and planar structures. SEG hardening of power MOS devices has become a bottleneck and weakness restricting the development of satellite power technology, information security control, and the self-sufficiency of core components.

[0004] Currently, superjunction power MOS devices have significant advantages over traditional power VDMOS (Vertical Double Diffused Metal Oxide Semiconductor) devices in terms of system efficiency, packaging cost, SEB resistance, and SEGR resistance. These advantages make them one of the core components of satellite secondary DC / DC (Direct Current-Direct Current) power supplies, playing a role in power conversion or power transformation in the power system and providing the necessary energy for the normal operation of satellite electronic systems.

[0005] Currently, single-event hardening of superjunction power MOS devices is mainly achieved by appropriately setting the doping concentration of the buffer zone, body, and source region. These methods can improve the radiation resistance of superjunction power MOS devices to some extent. However, for high-voltage and ultra-high-voltage superjunction power MOS devices, such as those above 600V, the existing hardening measures are still insufficient to meet the requirements for single-event gate breakdown resistance due to the limitations of the gate oxide layer. Furthermore, existing hardening measures can affect the performance indicators of the superjunction power MOS devices themselves, such as on-resistance and conduction losses, thus requiring further optimization. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a superjunction power MOS device with integrated corrugated gate oxide and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention proposes a superjunction power MOS device with integrated corrugated gate oxide, comprising a substrate, a buffer layer, and an epitaxial layer stacked sequentially from bottom to top; wherein... The epitaxial layer has multiple superstructures arranged vertically at intervals, and a body region is provided above each superstructure; the body region is located on the surface of the epitaxial layer, and the upper surfaces of both are flush. The surface of the body region is provided with contact hole doped regions and source doped regions that are connected to each other; the upper surfaces of the body region, contact hole doped regions and source doped regions are flush, and the depth of the contact hole doped regions and source doped regions is less than the depth of the body region. A gate oxide layer is also provided on the upper surface of the epitaxial layer; the gate oxide layer has a corrugated structure, and the lower surface of the gate oxide layer is adapted to and in contact with the corrugated trench located on the upper surface of the epitaxial layer, the body region and part of the source doped region; The gate oxide layer and the upper surface of part of the source doped region are covered with a polysilicon layer, and the gate oxide layer and the polysilicon layer form a corrugated gate structure.

[0007] Secondly, this invention proposes a method for fabricating a superjunction power MOS device with integrated corrugated gate oxide, comprising: S1: Select a substrate and grow a buffer layer on the upper surface of the substrate; S2: An epitaxial layer is formed on the buffer layer through multiple epitaxial deposition and ion implantation processes, and multiple superjunction pillars arranged vertically at intervals are formed in the epitaxial layer. S3: Prepare the body region above each superstructure column; S4: Etch part of the body region and the upper surface of the wafer between the two body regions to form a corrugated trench, and perform gate oxide oxidation to form a corrugated gate oxide layer. S5: Deposit a polysilicon layer on the gate oxide layer; S6: Ion implantation is performed on the body region to form contact hole doped region and source doped region.

[0008] The beneficial effects of this invention are: This invention provides a superjunction power MOS device with integrated corrugated gate oxide, comprising a substrate, a buffer layer, and an epitaxial layer stacked sequentially from bottom to top; wherein, the epitaxial layer has a plurality of vertically spaced superjunction pillars, and a body region is disposed above each superjunction pillar; the surface of the body region has contact hole doped regions and source doped regions that are connected to each other; a gate oxide layer is also disposed on the upper surface of the epitaxial layer; the gate oxide layer has a corrugated structure, and the lower surface of the gate oxide layer is adapted to and in contact with the corrugated trenches located on the upper surface of the epitaxial layer, the body region, and part of the source doped region; the upper surface of the gate oxide layer and the part of the source doped region is covered with a polysilicon layer, and the gate oxide layer and the polysilicon layer form a corrugated gate structure. The device employs a repeating corrugated gate oxide structure, which, when exposed to heavy ion radiation, extends the hole flow path generated after particle incidence, reducing the probability of parasitic transistor conduction to some extent and improving resistance to single-event burn-out. On the other hand, it reduces the number and density of holes accumulating under the gate oxide, lowers the electric field strength borne by the gate oxide layer, and improves the device's resistance to single-event gate penetration.

[0009] 2. The method for fabricating a superjunction power MOS device with integrated corrugated gate oxide provided by the present invention only requires adjustment of etching and partial implantation processes, without significantly increasing costs, and is relatively simple to implement.

[0010] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0011] Figure 1 A schematic diagram of the cell structure of a superjunction power MOS device with integrated corrugated gate oxide provided in an embodiment of the present invention; Figure 2 A schematic flowchart illustrating a method for fabricating a superjunction power MOS device with integrated corrugated gate oxide, provided in an embodiment of the present invention; Figures 3a-3i A schematic diagram illustrating the fabrication process of a superjunction power MOS device with integrated corrugated gate oxide, provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a single particle incident from above the source of a conventional device in a simulation experiment. Figure 5 This simulates the change of drain-source current over time when a single particle is incident from above the source of a conventional device in a simulation experiment. Figure 6 This is a comparison of the gate oxide intensity at different times after conventional devices are incident in a simulation experiment. Figure 7 This is a schematic diagram showing the positions where the electric field of a conventional device and the integrated corrugated gate oxide device of this invention were captured in the simulation experiment. Figure 8 The electric field intensity at different positions of a conventional gate oxide device after particle incident in a simulation experiment; Figure 9 The electric field intensity at different positions of the integrated corrugated gate oxide device of the present invention after particle incident is shown in the simulation experiment.

[0012] Explanation of reference numerals in the attached figures: 1-Substrate, 2-Buffer layer, 3-Epipolar layer, 4-Superjunction pillar, 5-Body region, 6-Contact hole doped region, 7-Source doped region, 8-Gate oxide layer, 9-Polysilicon layer, 10-Interlayer dielectric layer. Detailed Implementation

[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0014] A first aspect of the present invention provides a superjunction power MOS device with integrated corrugated gate oxide. See also... Figure 1 , Figure 1 This is a schematic diagram of the cell structure of a superjunction power MOS device with integrated corrugated gate oxide provided in an embodiment of the present invention. The device includes a substrate 1, a buffer layer 2, and an epitaxial layer 3 stacked sequentially from bottom to top; wherein, The epitaxial layer 3 has multiple superstructure pillars 4 arranged vertically at intervals, and a body region 5 is provided above each superstructure pillar 4; the body region 5 is located on the surface of the epitaxial layer 3, and the upper surfaces of the two are flush. The surface of the body region 5 is provided with contact hole doped regions 6 and source doped regions 7 that are connected to each other; the upper surfaces of the body region 5, contact hole doped regions 6 and source doped regions 7 are flush, and the depth of the contact hole doped regions 6 and source doped regions 7 is less than the depth of the body region 5. A gate oxide layer 8 is also disposed on the upper surface of the epitaxial layer 3; the gate oxide layer 8 has a corrugated structure, and the lower surface of the gate oxide layer 8 is adapted to and in contact with the corrugated trench located on the upper surface of the epitaxial layer 3, the body region 5 and part of the source doped region 7. The upper surface of the gate oxide layer 8 and part of the source doped region 7 is covered with a polysilicon layer 9, and the gate oxide layer 8 and the polysilicon layer 9 form a corrugated gate structure.

[0015] Optionally, in this embodiment, substrate 1 is a silicon substrate with a thickness of 715~735μm and a resistivity of 0.002~0.006Ω·cm.

[0016] It is understood that the superjunction power MOS device with integrated corrugated gate oxide provided in this embodiment can be an N-channel device or a P-channel device. When the superjunction power MOS device is an N-channel device, the substrate 1 is a heavily doped N-type Si substrate; when the superjunction power MOS device is a P-channel device, the substrate 1 is a heavily doped P-type Si substrate.

[0017] Optionally, in this embodiment, the buffer layer 2 can be a multilayer structure with different doping concentrations and thicknesses. For example, the resistivity of the buffer layer 2 is 0.01~0.5Ω·cm, the thickness of the buffer layer is 20~50μm, and the number of buffer layers is 2~5.

[0018] Furthermore, regarding the epitaxial layer 3, superjunction pillars 4, and body region 5, when the superjunction power MOS device is an N-channel device, an intrinsic epitaxial layer can be deposited on the surface of the buffer layer 2, and N-type ions can be implanted onto the intrinsic epitaxial layer to form an N-type epitaxial layer. Then, P-type ions are implanted into the N-type epitaxial layer, and this process is repeated multiple times to form multiple P-type superjunction pillars 4, also known as P-pillars. Finally, boron ions are implanted into the epitaxial layer 3 above the P-pillars to form a P-type body region 5. Correspondingly, when the superjunction power MOS device is a P-channel device, an intrinsic epitaxial layer can be deposited on the surface of the buffer layer 2, and P-type ions are implanted onto the intrinsic epitaxial layer to form a P-type epitaxial layer. Then, N-type ions are implanted into the P-type epitaxial layer, and this process is repeated multiple times to form multiple N-type superjunction pillars 4, also known as N-pillars. Finally, phosphorus ions are implanted into the epitaxial layer 3 above the N-pillars to form an N-type body region 5.

[0019] It is understandable that a JFET (Junction Field-Effect Transistor) region (not shown in the figure) is also formed in the central region within the epitaxial layer 3.

[0020] Furthermore, for the contact hole doped region 6 and the source doped region 7, appropriate ions can be doped at the corresponding locations according to the device type. For example, arsenic ions can be implanted into the source doped region 7 to form an N+ type source doped region, and BF2 ions can be implanted into the contact hole doped region 7 to form a P+ type contact hole doped region.

[0021] Specifically, in this embodiment, the gate oxide layer 8 (also referred to herein as gate oxide) is a corrugated gate oxide with a certain aspect ratio (the poly oxide will also exhibit a corrugated shape). Its corrugated structure is not repeated only in the X direction, i.e., the width direction of the device, but also in the Y direction. In other words, the gate oxide layer 8 has a corrugated structure along both the width and length directions of the device, such as... Figure 1 As shown.

[0022] It should be noted that the number and aspect ratio of the corrugated structure of the gate oxide layer 8 can be freely designed according to the actual electrical performance requirements of the device. For example, the aspect ratio of the corrugated structure of the gate oxide layer 8 can be set to 5:1 to 20:1, which can improve the radiation resistance by optimizing the carrier path extension and the uniformity of the electric field distribution.

[0023] It should be noted that, in this embodiment, the aspect ratio of the corrugated structure of the gate oxide layer 8 refers to the ratio of the corrugation period length λ to the amplitude A along the channel direction, which is λ / A. When λ / A < 5, the corrugation curvature radius is too small (R < 250 nm), resulting in local electric field concentration in the gate oxide and weakening the SEGR resistance. When λ / A > 20, the corrugated structure tends to be planar, and the hole path extension effect is insufficient (elongation < 15%), resulting in limited improvement in SEB resistance. Therefore, in this embodiment, λ / A is preferably 8:1-15:1, which achieves an electric field strength reduction of >30% under process controllability.

[0024] Furthermore, when the gate oxide layer 8 adopts a corrugated structure, the polysilicon layer 9 located on the gate oxide layer 8 also has a corrugated structure, and the two are combined to form a corrugated gate structure.

[0025] Optionally, the thickness of the gate oxide layer 8 is 50-120 nm; the thickness of the polysilicon layer 9 is 500-1000 nm.

[0026] Furthermore, it is understood that the superjunction power MOS device with integrated corrugated gate oxide provided in this embodiment also includes an interlayer dielectric layer 11, a source metal layer, and a drain metal layer; wherein, Interlayer dielectric layer 10 covers the upper surface of polysilicon layer 9; The source metal layer is disposed on the interlayer dielectric layer 10 and is isolated from the polysilicon layer 9 through the interlayer dielectric layer 10; multiple contact holes are formed on the interlayer dielectric layer 10 so that the source metal layer can contact the hole doped region 6 and the source doped region 7. The drain metal layer is disposed on the lower surface of substrate 1.

[0027] like Figure 1 As shown, to clearly illustrate the structure, the interlayer dielectric layer 10 is in Figure 1The dashed lines used to indicate that common source and drain metal layers and their conventional passivation layers are not included. Figure 1 As shown in the image.

[0028] The superjunction power MOS device with integrated corrugated gate oxide provided by this invention, based on the traditional hardened superjunction power MOS device, adopts a repeating corrugated gate oxide layer structure. This can extend the hole flow path generated after particle incident when the device is exposed to heavy ion radiation, reduce the probability of parasitic transistor conduction, and improve the resistance to single-event burn-out. On the other hand, it can reduce the number and density of holes accumulated under the gate oxide, reduce the electric field strength borne by the gate oxide layer, optimize the uniformity of electric field distribution, and improve the device's resistance to single-event gate penetration.

[0029] Based on the same inventive concept, a second aspect of the present invention also provides a method for fabricating a superjunction power MOS device with integrated corrugated gate oxide. (See also: [link to related information]) Figure 2 and Figures 3a-3i , Figure 2 A schematic flowchart illustrating a method for fabricating a superjunction power MOS device with integrated corrugated gate oxide, provided in an embodiment of the present invention; Figures 3a-3i This is a schematic diagram illustrating the fabrication process of a superjunction power MOS device with integrated corrugated gate oxide, provided by an embodiment of the present invention. The fabrication method of the superjunction power MOS device with integrated corrugated gate oxide provided by the present invention mainly includes the following steps: S1: Select substrate 1 and grow buffer layer 2 on the upper surface of substrate 1, such as... Figure 3a As shown.

[0030] First, the substrate in this embodiment is a Si substrate with a thickness of 715~735μm and a resistivity of 0.002~0.006Ω·cm. When fabricating an N-channel device, a heavily doped N-type Si substrate is selected as substrate 1, and when fabricating a P-channel device, a heavily doped P-type Si substrate is selected as substrate 1.

[0031] Then, several buffer layers with different doping concentrations and thicknesses can be grown on the upper surface of substrate 1. For example, the resistivity of the buffer layer is 0.01~0.5Ω·cm, the thickness of the buffer layer is 20~50μm, and the number of buffer layers is 2~5.

[0032] S2: Through multiple epitaxial deposition and ion implantation processes, an epitaxial layer 3 is formed on the buffer layer 2, and multiple vertically spaced superjunction pillars 4 are formed in the epitaxial layer 3.

[0033] This step involves multiple epitaxial depositions and ion implantations to form an epitaxial layer 3 on the upper surface of the buffer layer 2, comprising multiple vertically spaced superjunction pillars 4, as shown below. Figure 3b As shown.

[0034] Specifically, when fabricating an N-channel device, an intrinsic epitaxial layer with a thickness of 1-10 μm can be deposited on the sample surface obtained in step S1. N-type ions are then implanted onto this intrinsic epitaxial layer from the front, with an implantation energy of 100-300 keV and an implantation dose of 1×10⁻⁶. 12 ~9×10 13 An N-type epitaxial layer is formed; then, photoresist is spin-coated, and exposure and development are performed using a mask to obtain a superstructure pillar pattern window. P-type ion implantation is then performed within the superstructure pillar pattern window at an energy of 100–300 keV and an implantation dose of 1 × 10⁻⁶. 12 ~9×10 13 The epitaxial layer deposition and ion implantation process is repeated 5 to 15 times or more to form an epitaxial layer 3 containing multiple vertically spaced superstructure pillars 4 on the upper surface of the buffer layer 2.

[0035] When fabricating P-channel devices, an intrinsic epitaxial layer with a thickness of 1-10 μm can be deposited on the surface of the sample obtained in step S1. P-type ions are then implanted onto this intrinsic epitaxial layer from the front at an implantation energy of 100-300 keV and an implantation dose of 1×10⁻⁶. 12 ~9×10 13 A P-type epitaxial layer is formed; then, photoresist is spin-coated, and exposure and development are performed using a mask to obtain a superstructure pillar pattern window. N-type ion implantation is then performed within the superstructure pillar pattern window at an energy of 100–300 keV and an implantation dose of 1 × 10⁻⁶. 12 ~9×10 13 The epitaxial layer deposition and ion implantation process is repeated 5 to 15 times or more to form an epitaxial layer 3 containing multiple vertically spaced superstructure pillars 4 on the upper surface of the buffer layer 2.

[0036] S3: Prepare a body region 5 above each superstructure column 4, such as... Figure 3c As shown.

[0037] Specifically, when fabricating N-channel devices, photoresist is spin-coated onto the surface of the sample. Then, exposure and development are performed using a mask to obtain a body pattern window. Boron ions are implanted into the body pattern window at an energy of 100–300 keV and an implantation dose of 1 × 10⁻⁶. 12 ~9×10 13 This forms the body region 5. When fabricating P-channel devices, photoresist can be spin-coated onto the sample surface. Afterwards, exposure and development are performed using a mask to obtain the body pattern window. Phosphorus ions are implanted into the body pattern window at an energy of 100-300 keV and an implantation dose of 1×10⁻⁶. 12 ~9×10 13 .

[0038] It should be noted that before fabricating the body region 5, it may also include: forming a JFET region (not shown in the figure) in the central region within the epitaxial layer 3.

[0039] Specifically, when fabricating an N-channel device, photoresist is spin-coated onto the sample surface after the superjunction pillar is fabricated. Then, exposure and development are performed using a mask to obtain a JFET implantation pattern window. Phosphorus ions are then implanted into the JFET implantation pattern window. When fabricating a P-channel device, photoresist is spin-coated onto the sample surface after the superjunction pillar is fabricated. Then, exposure and development are performed using a mask to obtain a JFET implantation pattern window. Boron ions are then implanted into the JFET implantation pattern window. For example, the implantation energy is 200~400 keV, and the implantation dose is 2×10⁻⁶. 12 ~2×10 13 .

[0040] S4: Etch part of the body region 5 and the upper surface of the wafer between the two body regions 5 to form a corrugated trench, and perform gate oxide oxidation to form a corrugated gate oxide layer 8.

[0041] Optionally, when implementing this step, a corrugated trench is first formed by two-step etching, and then a corrugated gate oxide layer 8 is further formed by gate oxide operation, specifically including the following sub-steps S41-S43.

[0042] S41: Anisotropic etching is performed on part of body region 5 and the wafer surface between two body regions 5 using a dry etching process to form several inverted trapezoidal trenches.

[0043] Specifically, photoresist is spin-coated onto the wafer surface obtained in step S3, and exposure and development are performed using a mask to obtain a pattern window. Dry etching is then performed based on the pattern window. By controlling the selectivity, a trapezoidal trench structure with a smaller opening is first created, such as... Figure 3d As shown.

[0044] Optionally, the number of inverted trapezoidal grooves in this step is not fixed and depends on the actual gate oxide length and parameters. The length ratio of the upper opening to the bottom opening of the inverted trapezoidal groove is 8:1-15:1, mainly to facilitate the formation of the subsequent corrugated gate oxide structure.

[0045] S42: The inverted trapezoidal trench is subjected to sacrificial oxidation treatment, and after the sacrificial oxide layer is removed, the inverted trapezoidal trench is isotropically etched using a wet etching process to form a smooth, curved, wavy trench.

[0046] Specifically, the sample obtained in step S41 is first subjected to sacrificial oxidation treatment, wherein the thickness of the sacrificial oxide layer is 50-70 nm, and the specific process method can be referred to existing technology. Through sacrificial oxidation treatment, the inverted trapezoidal trenches formed by dry etching in step S41 are smoothed to facilitate further etching.

[0047] Next, the sacrificial oxide layer is removed, and photoresist is spin-coated onto the resulting wafer surface. Exposure and development are then performed using a mask to obtain patterned windows. The openings at this stage need to be slightly larger than the trench openings. Wet etching is then performed to obtain the final corrugated trenches, such as... Figure 3e As shown.

[0048] It should be noted that in step S42, the corrugated trench has a corrugated structure along both the width and length directions of the device, so that the subsequently grown corrugated gate oxide layer 8 has a corrugated structure along both the width and length directions of the device.

[0049] S43: Perform gate oxide oxidation on the corrugated trenches to obtain a corrugated gate oxide layer 8, such as... Figure 3f As shown, the thickness of the gate oxide layer 8 is 50~120 nm.

[0050] S5: Deposit a polysilicon layer 9 on the gate oxide layer 8.

[0051] Specifically, a polysilicon layer 9 with a thickness of 500-1000 nm is deposited on the corrugated gate oxide layer 8. Then, photoresist is spin-coated onto the resulting wafer surface. Exposure and development are performed using a mask to obtain a patterned window. Dry etching is then performed based on the patterned window to form the final corrugated gate structure, such as... Figure 3g As shown.

[0052] S6: Ion implantation is performed on body region 5 to form contact hole doped region 6 and source doped region 7.

[0053] For example, firstly, photoresist is spin-coated onto the sample surface obtained in step S5, and then exposed and developed using a mask to obtain source doped region pattern windows located on each body region. Then, arsenic ions are implanted into each source doped region pattern window to form source doped region 7. The implantation energy is 100~200 keV, and the implantation dose is 9×10⁻⁶. 14 ~5×10 15 .

[0054] Then, photoresist is spin-coated onto the obtained sample surface, and exposure and development are performed using a mask to obtain contact hole doped region pattern windows located on each body region. Subsequently, BF2 ions are implanted into each contact hole doped region pattern window to form contact hole doped region 6, as shown below. Figure 3hAs shown. The injection energy was 100~200 keV, and the injection dose was 9×10⁻⁶. 14 ~5×10 15 .

[0055] Following S6, it also includes: S7: An interlayer dielectric 10 is deposited on the surface of the polysilicon layer 8, and the deposited interlayer dielectric is etched to form contact holes to expose the contact hole doped region and part of the source doped region, thus forming an interlayer dielectric layer.

[0056] Specifically, photolithography and etching are performed on the sample obtained in step S6 to form the interlayer dielectric layer 10 and contact holes; wherein, the interlayer dielectric layer 10 covers the upper surface of the polysilicon layer 9 and contacts part of the upper surface of the source doped region 7, such as... Figure 3i As shown.

[0057] S8: A source metal layer is formed on the upper surface of the sample obtained in S7, and the lower surface of the source metal layer is in contact with the contact hole doped region and part of the source doped region.

[0058] Specifically, source metal is deposited on the upper surface of the sample obtained in step S7. For example, the metal is Al with a thickness of 4~6μm. After the source metal deposition is completed, photoresist is spin-coated on the surface of the obtained sample, and then exposed and developed using a mask to obtain a metal interconnect pattern window. The separation of the source metal layer and the gate electrode is completed according to the metal interconnect pattern window.

[0059] S9: Drain metal is formed on the lower surface of the substrate.

[0060] Specifically, a drain metal layer is formed by depositing drain metal on the lower surface of the substrate. For example, the deposited metals are Ti / Ni / Ag in sequence, with a thickness of 5~10μm.

[0061] Thus, the fabrication of a superjunction power MOS device with integrated corrugated gate oxide was completed.

[0062] This embodiment provides a method for fabricating a superjunction power MOS device with integrated corrugated gate oxide, as described in the first aspect above. Therefore, the fabricated device exhibits good resistance to single-event burn-out and single-event gate penetration. Furthermore, this method only requires adjustments to the etching and partial implantation processes, without significantly increasing costs, and is relatively simple to implement.

[0063] The following simulation demonstrates the performance of the superjunction power MOS device with integrated corrugated gate oxide proposed in this invention, and compares it with traditional power MOS devices to further illustrate the superiority of this invention.

[0064] Simulation 1: Determining the time when the electric field of the device is strongest during single-particle incident. Specifically, this embodiment uses conventional devices to simulate the time when the electric field is strongest, so that subsequent electric field comparisons are all based on the electric field at its strongest moment after incident. Please refer to... Figure 4 , Figure 4 This is a schematic diagram illustrating a single particle incident from above the source of a conventional device, provided as an embodiment of the present invention. Let the single particle be... Figure 4 As shown, when incident from above the source of a conventional device, the changes in drain-source current over time (in seconds) are compared. The results are as follows. Figure 5 As shown.

[0065] For further details, please see Figure 6 , Figure 6 This image shows a comparison of the gate oxide electric field strength when a single particle is incident from above the source of a conventional device in a simulation experiment. By comparing the electric field strength at different time points, it was determined that the gate oxide bears the strongest electric field strength at 1.0e-8s, reaching 4 x 10⁻⁸ s. 6 V / cm, such as Figure 6 As shown.

[0066] Simulation 2: Comparing the electric field strength at different locations of the strongest electric field in a conventional gate oxide device and the integrated corrugated gate oxide device of the present invention under the same conditions and locations. Please see Figure 7-9 , Figure 7 This is a schematic diagram showing the positions where the electric field of a conventional device and the integrated corrugated gate oxide device of this invention were captured in the simulation experiment. Figure 8 The electric field intensity at different positions of a conventional gate oxide device after particle incident in a simulation experiment; Figure 9 The electric field intensity at different positions of the integrated corrugated gate oxide device of the present invention after particle incident is shown in the simulation experiment.

[0067] from Figure 8 It can be seen that, by comparing the electric field strength at different locations after incident on a conventional gate oxide device, the highest field strength is 4 x 10⁻⁶. 6 V / cm. From Figure 9 It can be seen from the comparison of electric field strength at different positions after the integrated corrugated gate oxide device of the present invention is incident, that its highest field strength is 2.7 x 10⁻⁶. 6 V / cm.

[0068] Calculations show that, under the same bias conditions and incident position, at the moment when the electric field is strongest after incident, the integrated corrugated gate oxide device of this invention reduces the electric field strength of the gate oxide by 32.5%, which greatly reduces the gate oxide electric field strength and improves the device's resistance to single-particle gate penetration.

[0069] This verifies that the superjunction power MOS device with integrated corrugated gate oxide proposed in this invention has good resistance to single-event gate breakdown.

[0070] In the description of this specification, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the present invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0071] Furthermore, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Moreover, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0072] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0073] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A superjunction power MOS device with integrated corrugated gate oxide, characterized in that, It includes a substrate (1), a buffer layer (2), and an epitaxial layer (3) stacked sequentially from bottom to top; wherein, The epitaxial layer (3) is provided with a plurality of vertically spaced superstructure pillars (4), and a body region (5) is provided above each superstructure pillar (4); the body region (5) is located on the surface of the epitaxial layer (3), and the upper surfaces of the two are flush. The surface of the body region (5) is provided with contact hole doped regions (6) and source doped regions (7) that are connected to each other; the upper surfaces of the body region (5), the contact hole doped regions (6) and the source doped regions (7) are flush, and the depth of the contact hole doped regions (6) and the source doped regions (7) is less than the depth of the body region (5); The upper surface of the epitaxial layer (3) is further provided with a gate oxide layer (8); the gate oxide layer (8) has a corrugated structure, and the lower surface of the gate oxide layer (8) is adapted to and in contact with the corrugated trench located on the upper surface of the epitaxial layer (3), the body region (5) and part of the source doped region (7); The gate oxide layer (8) and the upper surface of part of the source doped region (7) are covered with a polysilicon layer (9), and the gate oxide layer (8) and the polysilicon layer (9) form a corrugated gate structure.

2. The superjunction power MOS device with integrated corrugated gate oxide according to claim 1, characterized in that, The gate oxide layer (8) has a corrugated structure along both the width and length of the device.

3. The superjunction power MOS device with integrated corrugated gate oxide according to claim 1, characterized in that, The ratio of the ripple period length λ to the amplitude A of the corrugated structure of the gate oxide layer (8) along the channel direction is 5:1 to 20:

1.

4. A superjunction power MOS device with integrated corrugated gate oxide according to claim 1, characterized in that, The thickness of the gate oxide layer (8) is 50-120 nm; the thickness of the polysilicon layer (9) is 500-1000 nm.

5. A superjunction power MOS device with integrated corrugated gate oxide according to claim 1, characterized in that, It also includes an interlayer dielectric layer (11), a source metal layer, and a drain metal layer; wherein, The interlayer dielectric layer (10) covers the upper surface of the polysilicon layer (9); The source metal layer is disposed on the interlayer dielectric layer (10) and is isolated from the polysilicon layer (9) through the interlayer dielectric layer (10); a plurality of contact holes are formed on the interlayer dielectric layer (10) so that the source metal layer can contact the contact hole doped region (6) and the source doped region (7); The drain metal layer is disposed on the lower surface of the substrate (1).

6. A method for fabricating a superjunction power MOS device with integrated corrugated gate oxide, characterized in that, include: S1: Select a substrate and grow a buffer layer on the upper surface of the substrate; S2: An epitaxial layer is formed on the buffer layer through multiple epitaxial deposition and ion implantation processes, and multiple superjunction pillars arranged vertically at intervals are formed in the epitaxial layer. S3: Prepare the body region above each superstructure column; S4: Etch a portion of the body region and the upper surface of the wafer between the two body regions to form a corrugated trench, and perform gate oxide oxidation to form a corrugated gate oxide layer. S5: Deposit a polysilicon layer on the gate oxide layer; S6: Ion implantation is performed on the body region to form contact hole doped region and source doped region.

7. The method for fabricating a superjunction power MOS device with integrated corrugated gate oxide according to claim 6, characterized in that, S4 include: S41: Anisotropic etching is performed on a portion of the body region and the upper surface of the wafer between the two body regions using a dry etching process to form several inverted trapezoidal trenches. S42: The inverted trapezoidal trench is subjected to sacrificial oxidation treatment, and after the sacrificial oxide layer is removed, the inverted trapezoidal trench is isotropically etched using a wet etching process to form a smooth, curved, wavy trench. S43: Perform gate oxide oxidation on the corrugated trench to obtain a corrugated gate oxide layer.

8. The method for fabricating a superjunction power MOS device with integrated corrugated gate oxide according to claim 7, characterized in that, In S41, the length ratio of the upper opening to the bottom opening of the inverted trapezoidal trench is 2:1-5:1; in S42, the thickness of the sacrificial oxide layer is 50-70 nm.

9. The method for fabricating a superjunction power MOS device with integrated corrugated gate oxide according to claim 6, characterized in that, In S42, the corrugated trench has a corrugated structure along both the width and length directions of the device, so that the subsequently grown corrugated gate oxide layer has a corrugated structure along both the width and length directions of the device.

10. The method for fabricating a superjunction power MOS device with integrated corrugated gate oxide according to claim 6, characterized in that, Following S6, it also includes: S7: An interlayer dielectric is deposited on the surface of the polysilicon layer, and the deposited interlayer dielectric is etched to form contact holes to expose the contact hole doped region and part of the source doped region, thereby forming an interlayer dielectric layer. S8: A source metal layer is formed on the upper surface of the sample obtained in S7, and the lower surface of the source metal layer is in contact with the contact hole doped region and part of the source doped region; S9: Drain metal is formed on the lower surface of the substrate.

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