Semiconductor device, method for manufacturing semiconductor device, and integrated circuit

Abstract

Embodiments of the present disclosure provide a semiconductor device, a method for manufacturing a semiconductor device, and an integrated circuit. The semiconductor device includes a substrate, a first region, a second region, and a gate. The substrate includes a groove. The first region is located at the bottom of the groove. The first region forms a first electrode of the semiconductor device. The second region is located at the inner sidewall of the groove. The second region includes a first segment extending toward the upper surface of the substrate and a second segment extending toward the first region. The first segment forms a second electrode. The second segment forms a channel region. The gate is arranged within the groove and adjacent to the second segment. The gate is separated from the first region and the second region by an isolation layer. With this arrangement, the semiconductor device meets the current discharge requirement by establishing a vertical conductive path in the second region, without the need to establish a lateral current discharge path in the substrate adjacent to the upper surface, thereby reducing the lateral size of the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of semiconductor devices, and more particularly, to a semiconductor device, a method for manufacturing a semiconductor device, and an integrated circuit. Background Art

[0002] In integrated circuits, gate-grounded N-type metal oxide semiconductor devices are commonly used for ESD protection. When an ESD event occurs, the gate-grounded N-type metal oxide semiconductor device enters the on state, forming a lateral conductive path from the drain to the source. This conducts the ESD current to ground, thereby preventing high voltage damage to the internal circuitry. Summary of the Invention

[0003] In a first aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes: a substrate having a recess; a first region located at the bottom of the recess, the first region forming a first electrode; a second region located on the inner sidewall of the recess, the second region including a first segment extending toward the upper surface of the substrate and a second segment extending toward the first region, the first segment forming a second electrode, and the second segment forming a channel region; and a gate disposed within the recess and adjacent to the second segment, the gate being separated from the first and second regions by an isolation layer.

[0004] In some embodiments, the second region is disposed in the substrate at the bottom of the recess.

[0005] In some embodiments, the aspect ratio of the groove is in a range of 3:1 to 5:1.

[0006] In some embodiments, the first region and the first segment include dopants of a first conductivity type, and the second segment includes dopants of a second conductivity type.

[0007] In some embodiments, the dopant of the first conductivity type includes at least one of phosphorus and arsenic; and / or the dopant of the second conductivity type includes boron.

[0008] In some embodiments, the second region includes a first subportion and a second subportion, the first subportion and the second subportion are respectively arranged at opposite side walls of the groove, each of the first subportion and the second subportion includes a first segment and a second segment, the gate is arranged between the first subportion and the second subportion, and the isolation layer surrounds the gate.

[0009] In a second aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method includes: forming a recess in a substrate from the upper surface of the substrate; forming a first region at the bottom of the recess, the first region forming a first electrode; forming a second region at the sidewalls of the recess; forming a first segment and a second segment in the second region, the first segment extending toward the upper surface of the substrate and the second segment extending toward the first region, the first segment forming a second electrode and the second segment forming a channel region; forming an isolation layer at the bottom of the recess and on the second region; and forming a gate within the recess adjacent to the second segment, wherein the gate is separated from the first and second regions by the isolation layer.

[0010] In some embodiments, the method further includes: filling the groove with the same material as the isolation layer to surround the gate.

[0011] In some embodiments, forming the first region at the bottom of the groove includes: implanting dopants of the first conductivity type into the substrate at the bottom of the groove by an ion implantation process to form the first region.

[0012] In some embodiments, forming the first and second segments in the second region includes: implanting dopants of the first conductivity type into a portion adjacent to the upper surface of the second region by an ion implantation process to form the first and second segments.

[0013] In some embodiments, the energy of the ion implantation process is in the range of 10 keV to 50 keV, and the dose of the dopant is in the range of to within the range.

[0014] In some embodiments, the second region is formed at the sidewall of the recess by an epitaxial growth process.

[0015] In some embodiments, the second region is doped with a second conductivity type opposite to the first conductivity type during epitaxial growth.

[0016] In some embodiments, the concentration of the second conductivity type dopant in the second region is to within the range.

[0017] In a third aspect of the present disclosure, an integrated circuit is provided, comprising: the semiconductor device according to the first aspect of the present disclosure.

[0018] In an embodiment of the present disclosure, the semiconductor device includes a substrate, a first region, a second region, and a gate. The substrate includes a recess. The first region is located at the bottom of the recess. The first region forms a first electrode of the semiconductor device. The second region is located on the inner sidewall of the recess. The second region includes a first segment extending toward the upper surface of the substrate and a second segment extending toward the first region. The first segment forms a second electrode. The second segment forms a channel region. The gate is arranged within the recess and adjacent to the second segment. The gate is separated from the first and second regions by an isolation layer. With this arrangement, the first electrode, second electrode, and gate of the semiconductor device are arranged in the recess of the substrate, thereby forming a vertical channel structure. When the voltage between the first electrode and the second electrode rises to the breakdown voltage, current flows from the first electrode to the second segment and then along the second segment to the second electrode. The semiconductor device meets the current discharge requirement by establishing a vertical conductive path in the second region, eliminating the need to establish a lateral current discharge path in the substrate adjacent to the upper surface, thereby reducing the lateral size of the semiconductor device.

[0019] It should be understood that the content described in this content section is not intended to limit the key features or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0021] Figure 1 A schematic diagram showing a semiconductor device according to an embodiment of the present disclosure is shown;

[0022] Figure 2 A flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown;

[0023] Figure 3A A schematic diagram illustrating a process of forming a groove in a substrate according to some embodiments of the present disclosure;

[0024] Figure 3B A schematic diagram illustrating a process of forming a first region in a substrate by an ion implantation process according to some embodiments of the present disclosure;

[0025] Figure 3C A schematic diagram showing a substrate including a first region according to some embodiments of the present disclosure;

[0026] Figure 3D A schematic diagram illustrating a process of forming a second region on an inner sidewall of a groove according to some embodiments of the present disclosure;

[0027] Figure 3E A schematic diagram illustrating a process of coating a photoresist layer on an upper surface of a substrate according to some embodiments of the present disclosure is shown;

[0028] Figure 3F A schematic diagram illustrating a process of filling a groove with an insulating material according to some embodiments of the present disclosure;

[0029] Figure 3G A schematic diagram illustrating a process of implanting a first conductivity type dopant into a portion of a groove close to an upper surface of a substrate through an ion implantation process according to some embodiments of the present disclosure;

[0030] Figure 3H A schematic diagram illustrating a process of forming a first segment in a partial area on top of a second area according to some embodiments of the present disclosure;

[0031] Figure 3I A schematic diagram illustrating a process of removing a filled insulating material from a groove according to some embodiments of the present disclosure;

[0032] Figure 3J A schematic diagram illustrating a process of forming an isolation layer on the bottom of the groove and the second region according to some embodiments of the present disclosure;

[0033] Figure 3K A schematic diagram illustrating a process of forming a gate adjacent to a second section in a recess according to some embodiments of the present disclosure;

[0034] Figure 3L A schematic diagram illustrating a process of filling a groove with the same insulating material as the isolation layer to surround a gate according to some embodiments of the present disclosure; and

[0035] Figure 3M A schematic diagram illustrating a process of removing excess isolation layer on the upper surface of a substrate according to some embodiments of the present disclosure is shown.

[0036] Description of reference numerals:

[0037] 100, substrate; 101, groove; 110, upper surface;

[0038] 10. First area;

[0039] 20. Second area; 21. First section; 22. Second section;

[0040] 30. Gate;

[0041] 40. Isolation layer;

[0042] 201. Photoresist layer; 202. Insulating material. DETAILED DESCRIPTION

[0043] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0044] As used herein, the term "including" and its variations represent open inclusion, i.e., "including but not limited to." Unless otherwise stated, the term "or" means "and / or." The term "based on" means "based at least in part on." The terms "one example embodiment" and "an embodiment" mean "at least one example embodiment." The term "another embodiment" means "at least one additional embodiment." The terms "first," "second," etc. may refer to different or identical objects.

[0045] In some conventional gate-grounded NMOS structures, such as planar devices, ESD current primarily relies on lateral current paths for discharge. To achieve a high ESD current carrying capacity, these devices typically require a larger chip area, resulting in a larger lateral size for the entire device, limiting the layout and integration density of other circuit components on the chip.

[0046] Embodiments of the present disclosure provide a semiconductor device, a method for manufacturing a semiconductor device, and an integrated circuit. The semiconductor device includes a substrate, a first region, a second region, and a gate. The first region is located at the bottom of a groove. The first region is located at the bottom of the groove. The first region forms a first electrode of the semiconductor device. The second region is located at the inner sidewall of the groove. The second region includes a first segment extending toward the upper surface of the substrate and a second segment extending toward the first region. The first segment forms a second electrode. The second segment forms a channel region. The gate is separated from the first region and the second region by an isolation layer. With this arrangement, the first electrode, the second electrode, and the gate of the semiconductor device are arranged in the groove of the substrate, thereby forming a vertical channel structure. When the voltage between the first electrode and the second electrode rises to the breakdown voltage, the current flows from the first electrode to the second segment, and then passes along the second segment to the second electrode. The semiconductor device meets the current discharge requirement by establishing a vertical conductive path in the second region, and there is no need to establish a lateral current discharge path in the substrate adjacent to the upper surface, thereby reducing the lateral size of the semiconductor device and helping to increase the layout and integration density of other circuit elements on the chip. The following will be combined with Figure 1 To describe the principles of the present disclosure in detail.

[0047] like Figure 1As shown, the semiconductor device includes a substrate 100, a first region 10, a second region 20, a gate 30, and an isolation layer 40. The substrate 100 is the basic supporting structure of the semiconductor device and can be made of a semiconductor material such as silicon. The substrate 100 can play a role in fixing the conductive layer, isolating different regions, and participating in current conduction or voltage regulation in the semiconductor device. The substrate 100 has an upper surface 110, and the substrate 100 includes a groove 101 extending from the upper surface 110 into the substrate 100. As an example, the groove 101 can be formed by performing photolithography and deep hole etching on the silicon substrate 100. In this way, the groove 101 can provide a layout space for other parts of the semiconductor device.

[0048] like Figure 1 As shown, the first region 10 is located at the bottom of the groove 101. As an example, the first region 10 can be disposed in the substrate 100 at the bottom of the groove 101. As another example, the first region 10 can also be formed at the bottom of the groove 101 through an epitaxial growth process. The first region 10 can be doped with a first conductivity type (e.g., N-type) dopant to impart good electrical conductivity, thereby constituting the first region 10 as a first electrode of the semiconductor device, such as a source.

[0049] like Figure 1 As shown, the second region 20 is located on the inner sidewall of the recess 101. The second region 20 includes a first segment 21 extending toward the upper surface 110 of the substrate 100 and a second segment 22 extending toward the first region 10. As an example, the first segment 21 may include dopants of a first conductivity type, thereby forming a second electrode of the semiconductor device, such as a drain. The first segment 21 is located near the opening of the recess 101 and can be electrically connected to an external circuit. The second segment 22 may be doped with dopants of a second conductivity type (e.g., p-type), opposite to the first conductivity type, thereby forming a channel region.

[0050] like Figure 1 As shown, gate 30 is disposed within recess 101 and adjacent to second region 22. Gate 30 is separated from first region 10 and second region 20 by an insulating isolation layer 40 (e.g., silicon dioxide, silicon oxynitride, or other dielectric layer). In this manner, gate 30 can modulate the electrical characteristics of second region 22, thereby controlling the on / off state of the channel.

[0051] In some embodiments, as described above, the first electrode can serve as a source electrode, and the second electrode can serve as a drain electrode. In other embodiments, the first electrode can serve as a drain electrode, and the second electrode can serve as a source electrode. This article uses the first electrode serving as a source electrode and the second electrode serving as a drain electrode as an example to illustrate the operating principle of a semiconductor device. This does not limit the structure of the semiconductor device. In practical applications, these electrodes can be interchanged as needed.

[0052] With this arrangement, the first electrode, second electrode, and gate 30 of the semiconductor device are arranged in the recess 101 of the substrate 100, thereby forming a vertical channel structure. When the voltage between the first electrode and the second electrode rises to the breakdown voltage, current flows from the first electrode to the second section 22, and then along the second section 22 to the second electrode. The semiconductor device satisfies the current discharge requirement by establishing a vertical conductive path in the second region 20, eliminating the need to establish a lateral current discharge path in the substrate 100 adjacent to the upper surface 110. This reduces the lateral size of the semiconductor device and helps increase the layout and integration density of other circuit components on the chip.

[0053] In some embodiments, as Figure 1 As shown, the aspect ratio of the recess 101 is in the range of 3:1 to 5:1. In this way, the semiconductor device can fully utilize the vertical space of the substrate 100. The source electrode is located at the bottom of the recess 101, the drain electrode is arranged on the sidewall of the recess 101 and close to the opening of the recess 101, and the gate 30 is located within the recess 101 and separated from the doped region by the isolation layer 40, thereby forming a vertical channel. This high aspect ratio layout can reduce the lateral size of the semiconductor device, thereby improving the utilization of the chip surface.

[0054] In some embodiments, as Figure 1 As shown, the first conductivity type dopant can be phosphorus and / or arsenic. The first conductivity type dopant is doped into the first region 10 adjacent to the bottom of the recess 101 and into the first section 21 of the second region 20. Phosphorus or arsenic can form a high-concentration, uniform N-type doping region, thereby improving the conductivity of the source and drain.

[0055] In some embodiments, as Figure 1 As shown, the second conductivity type dopant can be boron. Boron is doped into the second segment 22 of the second region 20. Boron atoms contribute to the formation of a P-type channel. When the voltage between the source and drain reaches the breakdown voltage, the gate 30 can regulate the P-type channel, allowing current to flow from the source to the drain along a vertical conductive path.

[0056] In some embodiments, as Figure 1 As shown, the isolation layer 40 can be made of silicon dioxide. Silicon dioxide has high insulation and stability. In this way, the isolation layer 40 can separate the gate 30 from the source, drain, and p-type channel region. In other embodiments, the isolation layer 40 can also be made of silicon oxynitride. Silicon oxynitride can improve dielectric strength and reduce leakage current.

[0057] In some embodiments, as Figure 1As shown, the gate 30 can be made of polysilicon. The polysilicon gate 30 has good compatibility with the silicon substrate 100. In some embodiments, as Figure 1 As shown, the gate 30 may also be made of polycrystalline metal, such as titanium nitride. In other embodiments, the gate 30 may include any other known or future available materials.

[0058] In some embodiments, as Figure 1 As shown, the second region 20 includes a first sub-portion and a second sub-portion. The first sub-portion and the second sub-portion are respectively arranged at opposite side walls of the groove 101. For example, the first sub-portion is arranged at the left side wall of the groove 101, and the second sub-portion is arranged at the right side wall of the groove 101. The first sub-portion and the second sub-portion are symmetrically arranged along the opposite side walls of the groove 101, thereby forming a double-sided channel structure. Each of the first sub-portion and the second sub-portion includes a first section 21 and a second section 22 arranged in sequence from the opening to the bottom of the groove 101. The first section 21 can be doped with a dopant of the first conductivity type to form the drain of the semiconductor device. The second section 22 is doped with a dopant of the second conductivity type to form the channel region of the semiconductor device.

[0059] like Figure 1 As shown, the gate 30 is arranged between the first sub-section and the second sub-section. The isolation layer 40 completely surrounds the gate 30, thereby isolating the gate 30 from the source, drain and channel region. The isolation layer 40 can make the electric field of the gate 30 evenly distributed on the double-sided channels. When the voltage between the source and the drain reaches the breakdown value, the gate 30 regulates the double-sided P-type channel, which can drive the current from the source along two symmetrical vertical conductive paths to the drain on both sides, thereby achieving efficient current transmission. With this arrangement, the dual-channel structure can improve the current carrying capacity, thereby increasing the driving current density. Secondly, in terms of manufacturing, the symmetrical structure can simplify the photolithography and etching processes, which helps to reduce production costs.

[0060] Figure 2 A flowchart of an example process 200 for fabricating a semiconductor device according to some embodiments of the present disclosure is shown. It should be understood that process 200 may include additional blocks not shown and / or may omit one (or some) of the blocks shown, and the scope of the present disclosure is not limited in this respect.

[0061] At block 210, a recess 101 is formed in the substrate 100 from the upper surface 110 of the substrate 100. As an example, Figure 3AAs shown, a photoresist layer 201 is coated on the upper surface 110 of the substrate 100. The photoresist layer 201 can protect the substrate 100 below the covering position from being etched during the subsequent etching process. Next, a mask with a specific pattern is aligned with the substrate 100, and the photoresist layer 201 is exposed using photolithography. The mask has a pattern corresponding to the groove 101 to be formed. During the exposure process, the pattern on the mask is transferred to the photoresist layer 201, so that the area of ​​the photoresist layer 201 corresponding to the position of the groove 101 is irradiated. Next, the irradiated area of ​​the photoresist layer 201 is removed through a development process, thereby exposing the surface of the substrate 100 below. Next, a deep hole etching process is used to etch along the exposed area, thereby forming a groove 101 of the desired size and shape in the substrate 100.

[0062] At block 220, a first region 10 is formed in the substrate 100 adjacent to the bottom of the recess 101. As an example, the first region 10 may include a dopant of the first conductivity type, thereby serving as a first electrode of the semiconductor device. As an example, Figure 3B and Figure 3C As shown, doping the first conductive type dopant in the first region 10 can be achieved by an ion implantation process. In some embodiments, the first conductive type dopant is an N-type dopant, and the dopant used can be at least one of phosphorus or arsenic. Through the ion implantation process, a region with a high carrier concentration can be formed in the substrate 100 adjacent to the bottom of the groove 101, so that the first region 10 has good conductivity. The first region 10 can serve as the first electrode of a semiconductor device, such as the source of an NMOS transistor. During the ion implantation process, the dopant ions are accelerated under a high voltage electric field and enter the interior of the substrate 100. The implantation energy can be controlled in the range of 10keV to 50keV to ensure that the dopant can reach the required depth in the substrate 100 at the bottom of the groove 101.

[0063] In some embodiments, the dosage of the dopant can be controlled to to Within a certain range, the dosage of the dopant can adjust the carrier concentration and resistivity of the first region 10 .

[0064] In some embodiments, after the ion implantation is completed, annealing treatment may be performed to repair lattice damage caused by ion bombardment and activate the doped atoms so that they stably occupy silicon lattice positions, thereby effectively improving the conductivity and uniformity of the material.

[0065] At block 230, a second region 20 extending from the opening of the groove 101 to the bottom of the groove 101 is formed at the inner sidewall of the groove 101. As an example, the second region 20 may include dopants of a second conductivity type opposite to the first conductivity type. As an example, Figure 3D As shown, after forming the first region 10, the photoresist layer 201 covering the upper surface 110 of the substrate 100 needs to be removed to provide a clean upper surface 110 for subsequent processes. Next, the second region 20 is formed on the sidewalls of the recess 101 through an epitaxial growth process. During the epitaxial growth process, a low concentration of a second conductivity type dopant, such as boron (B), may be doped to impart P-type conductivity to the second region 20.

[0066] In some embodiments, the epitaxial growth process can be achieved by using low pressure chemical vapor deposition technology. Specifically, low pressure chemical vapor deposition is performed at a temperature of 900 degrees Celsius to 1000 degrees Celsius, and boron particles can be doped during the growth, with a doping concentration of to within the range.

[0067] In some embodiments, boron may exist in the form of plasma, and the plasma may be made more uniform by adjusting the electromagnetic field distribution, thereby improving doping uniformity and crystal quality.

[0068] In some embodiments, before starting the epitaxial growth, the surface may be cleaned with deionized water to remove possible impurities or residues.

[0069] At block 240, a first section 21 and a second section 22 are formed in the second region 20. The first section 21 extends toward the upper surface 110 of the substrate 100. The second section 22 extends toward the first region 10. The first section 21 may form a second electrode of the semiconductor device. The second section 22 may form a channel region of the semiconductor device.

[0070] As an example, Figure 3E As shown, first, a photoresist layer 201 is coated on the upper surface 110 of the substrate 100 and covered with a mask layer. Then, a portion of the photoresist layer 201 located above the groove 101 is removed by a photolithography process to expose the groove 101.

[0071] Next, if Figure 3F As shown, the insulating material 202, such as silicon dioxide ( ) or silicon oxynitride (SiON), etc. The filled insulating material 202 can serve as a temporary blocking layer in the subsequent ion implantation process to protect the first region 10 from being doped.

[0072] Next, if Figure 3G and Figure 3HAs shown, a first conductive type dopant, such as phosphorus or arsenic, is implanted into the portion of the groove 101 close to the upper surface 110 of the substrate 100 through an ion implantation process. At this time, a portion of the top of the second region 20 will be doped to form a first segment 21.

[0073] Next, if Figure 3I As shown, the previously filled insulating material 202 is removed from the groove 101. For example, this can be accomplished through a dry etching process, using a reactive gas with a high etching rate for insulating material 202, such as silicon dioxide. Furthermore, the selectivity of the etching process can be controlled by adjusting the gas ratio to avoid damaging surrounding semiconductor materials.

[0074] like Figure 3I As shown, the section of the second region 20 near the opening of the groove 101 includes dopants of the first conductivity type and becomes the first section 21. The first section 21 can form the second electrode of the semiconductor device. The section of the second region 20 near the bottom of the groove 101 becomes the second section 22. The second section 22 can form the channel region of the semiconductor device.

[0075] In some embodiments, the ion implantation energy for forming the first section 21 is in the range of 10keV to 50keV. In this way, the dopant can penetrate into the first section 21. The dose of the dopant is controlled within to range, so that the first section 21 has good conductivity.

[0076] At block 250, an isolation layer 40 is formed on the bottom of the groove 101 and the second region 20. As an example, Figure 3J As shown, an isotropic deposition method can be used to form a layer of oxide as an isolation layer 40 on the second region 20 at the bottom and sidewalls of the recess 101. In this way, the isotropic deposition method can uniformly cover all exposed surfaces, including the bottom and sidewalls of the recess 101 and the upper surface 110 of the substrate 100. In some embodiments, the material of the isolation layer 40 includes silicon dioxide or silicon oxynitride. The isolation layer 40 can prevent direct contact between the gate 30 and the substrate 100, thereby preventing current leakage or short circuit phenomena.

[0077] At block 260, a gate 30 is formed adjacent to the second section 22 in the recess 101, wherein the gate 30 is separated from the first region 10 and the second region 20 by the isolation layer 40. As an example, Figure 3K As shown, a gate 30 having a certain thickness can be formed by a deposition process. The gate 30 can be made of polysilicon or polycrystalline metal.

[0078] In some embodiments, the polysilicon gate 30 may be formed by chemical vapor deposition technology. The polysilicon gate 30 has good compatibility with the silicon substrate 100.

[0079] In some embodiments, a metal such as titanium nitride can be used as the material of the gate 30. The metal gate 30 can be prepared by a physical vapor deposition process. In this way, the performance of the semiconductor device can be improved.

[0080] In some embodiments, as Figure 3L As shown, after forming the gate 30, the groove 101 may be filled with the same insulating material 202 as the isolation layer 40 to surround the gate 30. In this way, additional support can be provided for the gate 30, thereby preventing damage to the gate 30 during subsequent processes or use.

[0081] In some embodiments, as Figure 3M As shown, after the groove 101 is filled with the same material as the isolation layer 40 to surround the gate 30, the excess isolation layer 40 on the upper surface 110 of the substrate 100 can be removed by a planarization process such as chemical mechanical polishing or dry etching, thereby forming a semiconductor device with a complete structure and a flat surface.

[0082] The present disclosure also provides an integrated circuit. The integrated circuit includes any one of the semiconductor devices described above. The drain of the semiconductor device can be connected to the input or output circuit of the chip, thereby providing a low-impedance current discharge path when an electrostatic discharge event occurs. In this way, the internal circuit of the chip can be protected from electrostatic damage. At the same time, the first electrode, the second electrode and the gate 30 of the semiconductor device are arranged in the groove 101 of the substrate 100, thereby forming a vertical channel structure. When the voltage between the first electrode and the second electrode rises to the breakdown voltage, the current flows from the first electrode to the second section 22, and then passes along the second section 22 to the second electrode. The semiconductor device meets the current discharge requirements by establishing a vertical conductive path in the second region 20, and there is no need to establish a lateral current discharge path in the substrate 100 adjacent to the upper surface 110, thereby reducing the lateral size of the semiconductor device and helping to increase the layout density of electronic components in the integrated circuit.

[0083] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technological improvements in the marketplace, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor device comprising: A substrate (100) having a groove (101); a first region (10) located at the bottom of the groove (101), the first region (10) forming a first electrode; a second region (20) located on the inner sidewall of the groove (101), the second region (20) comprising a first section (21) extending toward the upper surface (110) of the substrate (100) and a second section (22) extending toward the first region (10), the first section (21) forming a second electrode, and the second section (22) forming a channel region; as well as A gate (30) is arranged in the groove (101) and adjacent to the second section (22), and the gate (30) is separated from the first region (10) and the second region (20) by an isolation layer (40).

2. The semiconductor device according to claim 1, wherein the second region (20) is at the bottom of the groove (101) and is arranged in the substrate (100).

3. The semiconductor device according to claim 1, wherein the aspect ratio of the groove (101) is in the range of 3:1 to 5:

1.

4. The semiconductor device according to claim 1, wherein the first region (10) and the first section (21) comprise dopants of a first conductivity type, and the second section (22) comprises dopants of a second conductivity type. 5 . The semiconductor device according to claim 4 , wherein the first conductivity type dopant comprises at least one of phosphorus and arsenic; and / or the second conductivity type dopant comprises boron.

6. The semiconductor device according to any one of claims 1 to 5, wherein the second region (20) includes a first sub-portion and a second sub-portion, the first sub-portion and the second sub-portion are respectively arranged at opposite side walls of the groove (101), each of the first sub-portion and the second sub-portion includes the first segment (21) and the second segment (22), the gate (30) is arranged between the first sub-portion and the second sub-portion, and the isolation layer (40) surrounds the gate (30).

7. A method for manufacturing a semiconductor device, comprising: forming a groove in the substrate from an upper surface of the substrate; forming a first region at the bottom of the groove, wherein the first region forms a first electrode; forming a second region at an inner sidewall of the groove; forming a first section and a second section in the second region, wherein the first section extends toward the upper surface of the substrate, the second section extends toward the first region, the first section forms a second electrode, and the second section forms a channel region; forming an isolation layer on the bottom of the groove and the second region; as well as A gate is formed in the recess adjacent to the second section, wherein the gate is spaced apart from the first region and the second region by the isolation layer.

8. The method according to claim 7, further comprising: The groove is filled with the same material as that of the isolation layer to surround the gate.

9. The method according to claim 7, wherein forming the first region at the bottom of the groove comprises: Dopants of the first conductive type are implanted into the substrate at the bottom of the groove by an ion implantation process to form the first region.

10. The method of claim 9, wherein forming the first segment and the second segment in the second region comprises: Dopants of the first conductivity type are implanted into a portion of the second region adjacent to the upper surface by an ion implantation process to form the first segment and the second segment.

11. The method according to claim 9 or 10, wherein the energy of the ion implantation process is in the range of 10 keV to 50 keV, and the dose of the dopant is in the range of to within the range. 12 . The method according to claim 9 , wherein the second region is formed at a sidewall of the groove by an epitaxial growth process. 13 . The method according to claim 12 , wherein the second region is doped with a second conductivity type opposite to the first conductivity type during epitaxial growth.

14. The method according to claim 13 , wherein the concentration of the second conductive type dopant in the second region is to within the range.

15. An integrated circuit comprising: A semiconductor device according to any one of claims 1 to 6.

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