Silicon carbide device and forming method thereof
By forming a super junction structure in silicon carbide devices, the problem of insufficient performance in the prior art is solved, and the heat dissipation ability and overall performance of the device are improved.
Patent Information
- Application Number
- CN202510614938.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-13
- Publication Date
- 2025-08-12
AI Technical Summary
The super junction structure application of silicon carbide devices in the prior art is immature, resulting in insufficient device performance.
The silicon carbide doped layer is formed in the trench in the drift region, the doping type is opposite to the drift region, and the isolation structure is filled to form a superjunction structure, combined with the MOS transistor structure, improve device performance.
By forming a superjunction structure in the trench in the drift region, the performance of silicon carbide devices, especially the heat dissipation capability, is significantly improved.
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Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a silicon carbide device and a method for forming the same. Background Art
[0002] Silicon carbide (SiC) MOSFETs are semiconductor devices that differ from traditional silicon substrates and horizontal channels. However, the current manufacturing process for SiC devices still has flaws. For example, the application of superjunction structures in SiC devices has not yet emerged and developed.
[0003] Therefore, it is necessary to provide a more effective and reliable technical solution to realize the formation of super junction structure in silicon carbide devices. Summary of the Invention
[0004] The present application provides a silicon carbide device and a method for forming the same, which forms a super junction structure in a trench in a drift region, thereby improving device performance.
[0005] One aspect of the present application provides a method for forming a silicon carbide device, comprising: providing a silicon carbide substrate, a silicon carbide epitaxial layer formed on the surface of the silicon carbide substrate, a drift region formed in the silicon carbide epitaxial layer, and a groove formed in the drift region; forming a silicon carbide doped layer on the bottom and sidewalls of the groove and on the surface of the drift region, the doping type of the silicon carbide doped layer being opposite to the doping type of the drift region; forming an isolation structure filling the trench; and forming a MOS transistor structure using the silicon carbide doped layers on the surfaces of the drift regions on both sides of the isolation structure as channels.
[0006] In some embodiments of the present application, the doping concentration of the silicon carbide doping layer is 6E16 to 1E19 cm -3 .
[0007] In some embodiments of the present application, the doping concentration of the silicon carbide doping layer is the same as the doping concentration of the drift region.
[0008] In some embodiments of the present application, the material of the isolation structure includes any one or more of aluminum oxide and silicon oxide.
[0009] In some embodiments of the present application, the isolation structure includes a first isolation layer and a second isolation layer sequentially located on the surface of the silicon carbide doped layer, the material of the first isolation layer includes silicon oxide, and the material of the second isolation layer includes aluminum oxide.
[0010] One aspect of the present application also provides a silicon carbide device, comprising: a silicon carbide substrate, a silicon carbide epitaxial layer formed on the surface of the silicon carbide substrate, a drift region formed in the silicon carbide epitaxial layer, and a groove formed in the drift region; a silicon carbide doped layer located at the bottom and sidewalls of the groove and the surface of the drift region, the doping type of the silicon carbide doped layer being opposite to the doping type of the drift region; an isolation structure filling the groove; and a MOS transistor structure, with the silicon carbide doped layers on the surfaces of the drift regions on both sides of the isolation structure serving as channels.
[0011] In some embodiments of the present application, the doping concentration of the silicon carbide doping layer is 6E16 to 1E19 cm -3 .
[0012] In some embodiments of the present application, the doping concentration of the silicon carbide doping layer is the same as the doping concentration of the drift region.
[0013] In some embodiments of the present application, the material of the isolation structure includes any one or more of aluminum oxide and silicon oxide.
[0014] In some embodiments of the present application, the isolation structure includes a first isolation layer and a second isolation layer sequentially located on the surface of the silicon carbide doped layer, the material of the first isolation layer includes silicon oxide, and the material of the second isolation layer includes aluminum oxide.
[0015] The present application provides a silicon carbide device and a method for forming the same, which forms a super junction structure in a trench in a drift region, thereby improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The following figures describe in detail exemplary embodiments disclosed in this application. Like reference numerals denote similar structures throughout the several views of the drawings. Those skilled in the art will appreciate that these embodiments are non-limiting, exemplary embodiments, and that the drawings are provided for illustration and description purposes only and are not intended to limit the scope of this application. Other embodiments may also achieve the inventive intent of this application. It should be understood that the drawings are not drawn to scale.
[0017] in:
[0018] Figures 1 to 5 This is a schematic structural diagram of each step in the method for forming a silicon carbide device described in an embodiment of the present application. DETAILED DESCRIPTION
[0019] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but is intended to be of the widest scope consistent with the claims.
[0020] The technical solution of the present invention is described in detail below with reference to the embodiments and drawings.
[0021] Figures 1 to 5 The following is a structural diagram of each step in the method for forming a silicon carbide device according to an embodiment of the present application. The method for forming a silicon carbide device according to an embodiment of the present application is described in detail with reference to the accompanying drawings.
[0022] refer to Figure 1 As shown, a silicon carbide substrate 100 is provided. A silicon carbide epitaxial layer 110 is formed on the surface of the silicon carbide substrate 100 . A drift region 120 is formed in the silicon carbide epitaxial layer 110 . A trench 130 is formed in the drift region 120 .
[0023] The semiconductor structure described in the embodiments of the present application is a silicon carbide device MOSFET with a super junction structure. The material of the silicon carbide substrate 100 is silicon carbide material, and the material of the silicon carbide epitaxial layer 110 is also silicon carbide material. In some embodiments of the present application, the silicon carbide substrate 100 and the silicon carbide epitaxial layer 110 may have doping ions, such as N-type doping ions. The drift region 120 (drift area) can be formed by an ion implantation process in the silicon carbide epitaxial layer 110, and the doping type of the drift region 120 is the same as that of the silicon carbide epitaxial layer 110, for example, N-type. The doping concentration of the drift region 120 is lower than the doping concentration of the silicon carbide epitaxial layer 110.
[0024] refer to Figure 2 As shown, a silicon carbide doped layer 140 is formed at the bottom and sidewalls of the trench 130 and on the surface of the drift region 120 . The doping type of the silicon carbide doped layer 140 is opposite to that of the drift region 120 (eg, P-type).
[0025] In some embodiments of the present application, the material of the doping layer 140 includes boron-doped crystalline silicon carbide or aluminum-doped crystalline silicon carbide.
[0026] In some embodiments of the present application, the thickness of the portion of the silicon carbide doped layer 140 located on the surface of the drift region 120 is greater than the thickness of the portion of the silicon carbide doped layer 140 located at the bottom and sidewalls of the trench 120. This is because a MOS transistor structure will be subsequently formed on the portion of the silicon carbide doped layer 140 located on the surface of the drift region 120.
[0027] In some embodiments of the present application, the doping concentration of the silicon carbide doping layer 140 is 6E16 to 1E19 cm -3 .
[0028] In some embodiments of the present application, the doping concentration of the silicon carbide doping layer 140 is the same as the doping concentration of the drift region.
[0029] refer to Figure 3 As shown, an isolation structure 150 is formed to fill the trench 130 .
[0030] In some embodiments of the present application, the material of the isolation structure 150 includes any one or more of aluminum oxide and silicon oxide.
[0031] In some embodiments of the present application, the isolation structure 150 includes a first isolation layer and a second isolation layer sequentially located on the surface of the silicon carbide doped layer 140 . The material of the first isolation layer includes silicon oxide, and the material of the second isolation layer includes aluminum oxide.
[0032] refer to Figure 4 As shown, a MOS transistor structure 170 is formed by using the silicon carbide doped layer 140 on the surface of the drift region 120 on both sides of the isolation structure 150 as a channel.
[0033] In some embodiments of the present application, the MOS transistor structure 170 includes a gate structure 172 located on the surface of the silicon carbide doped layer 140, source regions 171 located in the silicon carbide doped layer 140 on both sides of the gate structure 172, and isolation regions (not shown) that isolate adjacent source regions 171. The gate structure 172 may include a gate located on the surface of the silicon carbide doped layer 140 and an insulating layer covering the sidewalls and top surface of the gate. The insulating layer is used to insulate and isolate the gate from subsequent metal layers, so that the metal layers can be electrically connected to the source regions 151 but not electrically connected to the gate.
[0034] refer to Figure 5 As shown, a metal layer 180 is formed on the silicon carbide doped layer 140 to cover the MOS transistor structure 170 and the silicon carbide doped layer 140. The metal layer 180 acts as a source metal to electrically connect the source region 151 and the silicon carbide doped layer 140, but is not electrically connected to the gate in the gate structure 152.
[0035] In some embodiments of the present application, the material of the metal layer 180 includes any one or more of titanium nitride, tungsten, or titanium silicide. The metal layer 180 can solve the heat dissipation problem of the device and improve the device performance.
[0036] The present application provides a method for forming a silicon carbide device, which forms a super junction structure in a trench in a drift region, thereby improving device performance.
[0037] The embodiment of the present application also provides a silicon carbide device, referring to Figure 5 As shown, it includes: a silicon carbide substrate 100, a silicon carbide epitaxial layer 110 is formed on the surface of the silicon carbide substrate 100, a drift region 120 is formed in the silicon carbide epitaxial layer 110, and a groove is formed in the drift region 120; a silicon carbide doped layer 140 is located at the bottom and sidewalls of the groove and the surface of the drift region 120, and the doping type of the silicon carbide doped layer 140 is opposite to the doping type of the drift region 120; an isolation structure 150, filling the groove; and a MOS transistor structure 170, with the silicon carbide doped layer 140 on the surface of the drift region 120 on both sides of the isolation structure 150 as a channel.
[0038] The semiconductor structure described in the embodiments of the present application is a silicon carbide device MOSFET with a super junction structure. The material of the silicon carbide substrate 100 is silicon carbide material, and the material of the silicon carbide epitaxial layer 110 is also silicon carbide material. In some embodiments of the present application, the silicon carbide substrate 100 and the silicon carbide epitaxial layer 110 may have doping ions, such as N-type doping ions. The drift region 120 (drift area) can be formed by an ion implantation process in the silicon carbide epitaxial layer 110, and the doping type of the drift region 120 is the same as that of the silicon carbide epitaxial layer 110, for example, N-type. The doping concentration of the drift region 120 is lower than the doping concentration of the silicon carbide epitaxial layer 110.
[0039] In some embodiments of the present application, the doping type of the silicon carbide doped layer 140 is opposite to the doping type of the drift region 120 (for example, P-type).
[0040] In some embodiments of the present application, the material of the doping layer 140 includes boron-doped crystalline silicon carbide or aluminum-doped crystalline silicon carbide.
[0041] In some embodiments of the present application, the thickness of the portion of the silicon carbide doped layer 140 located on the surface of the drift region 120 is greater than the thickness of the portion of the silicon carbide doped layer 140 located at the bottom and sidewalls of the trench 120. This is because a MOS transistor structure will be subsequently formed on the portion of the silicon carbide doped layer 140 located on the surface of the drift region 120.
[0042] In some embodiments of the present application, the doping concentration of the silicon carbide doping layer 140 is 6E16 to 1E19 cm -3 .
[0043] In some embodiments of the present application, the doping concentration of the silicon carbide doping layer 140 is the same as the doping concentration of the drift region.
[0044] In some embodiments of the present application, the silicon carbide device further includes an isolation structure 150 filling the trench 130 .
[0045] In some embodiments of the present application, the material of the isolation structure 150 includes any one or more of aluminum oxide and silicon oxide.
[0046] In some embodiments of the present application, the isolation structure 150 includes a first isolation layer and a second isolation layer sequentially located on the surface of the silicon carbide doped layer 140 . The material of the first isolation layer includes silicon oxide, and the material of the second isolation layer includes aluminum oxide.
[0047] In some embodiments of the present application, the MOS transistor structure 170 includes a gate structure 172 located on the surface of the silicon carbide doped layer 140, source regions 171 located in the silicon carbide doped layer 140 on both sides of the gate structure 172, and isolation regions (not shown) that isolate adjacent source regions 171. The gate structure 172 may include a gate located on the surface of the silicon carbide doped layer 140 and an insulating layer covering the sidewalls and top surface of the gate. The insulating layer is used to insulate and isolate the gate from subsequent metal layers, so that the metal layers can be electrically connected to the source regions 151 but not electrically connected to the gate.
[0048] refer to Figure 5 As shown, a metal layer 180 is formed on the silicon carbide doped layer 140 to cover the MOS transistor structure 170 and the silicon carbide doped layer 140. The metal layer 180 acts as a source metal to electrically connect the source region 151 and the silicon carbide doped layer 140, but is not electrically connected to the gate in the gate structure 152.
[0049] In some embodiments of the present application, the material of the metal layer 180 includes any one or more of titanium nitride, tungsten, or titanium silicide. The metal layer 180 can solve the heat dissipation problem of the device and improve the device performance.
[0050] The present application provides a silicon carbide device and a method for forming the same, which forms a super junction structure in a trench in a drift region, thereby improving device performance.
[0051] In summary, after reading the contents of this application, those skilled in the art will understand that the foregoing contents are presented by way of example only and are not intended to be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of this application.
[0052] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may also be present.
[0053] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In contrast, the term "directly" indicates that there are no intervening elements. It should also be understood that the terms "comprising," "including," "include," or "comprising," when used in this specification, indicate the presence of recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.
[0054] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference designators represent the same elements throughout the specification.
[0055] In addition, this specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a silicon carbide device, characterized in that: include: Providing a silicon carbide substrate, wherein a silicon carbide epitaxial layer is formed on a surface of the silicon carbide substrate, a drift region is formed in the silicon carbide epitaxial layer, and a trench is formed in the drift region; forming a silicon carbide doped layer on the bottom and sidewalls of the trench and the surface of the drift region, wherein the doping type of the silicon carbide doped layer is opposite to the doping type of the drift region; forming an isolation structure filling the trench; A MOS transistor structure is formed by using the silicon carbide doped layers on the surfaces of the drift regions on both sides of the isolation structure as channels.
2. The method for forming a semiconductor structure according to claim 1, wherein: The doping concentration of the silicon carbide doping layer is 6E16 to 1E19 cm -3 .
3. The method for forming a semiconductor structure according to claim 1, wherein: The doping concentration of the silicon carbide doping layer is the same as the doping concentration of the drift region.
4. The method for forming a silicon carbide device according to claim 1, wherein: The material of the isolation structure includes any one or more of aluminum oxide and silicon oxide.
5. The method for forming a silicon carbide device according to claim 1, wherein: The isolation structure includes a first isolation layer and a second isolation layer sequentially located on the surface of the silicon carbide doped layer. The material of the first isolation layer includes silicon oxide, and the material of the second isolation layer includes aluminum oxide.
6. A silicon carbide device, characterized in that: include: A silicon carbide substrate, wherein a silicon carbide epitaxial layer is formed on a surface of the silicon carbide substrate, a drift region is formed in the silicon carbide epitaxial layer, and a trench is formed in the drift region; a silicon carbide doped layer, located at the bottom and sidewalls of the trench and the surface of the drift region, wherein the doping type of the silicon carbide doped layer is opposite to the doping type of the drift region; an isolation structure filling the trench; The MOS transistor structure uses the silicon carbide doped layers on the surfaces of the drift regions on both sides of the isolation structure as channels.
7. The silicon carbide device according to claim 6, wherein: The doping concentration of the silicon carbide doping layer is 6E16 to 1E19 cm -3 .
8. The silicon carbide device according to claim 6, wherein The doping concentration of the silicon carbide doping layer is the same as the doping concentration of the drift region.
9. The silicon carbide device according to claim 6, wherein: The material of the isolation structure includes any one or more of aluminum oxide and silicon oxide.
10. The silicon carbide device according to claim 6, wherein: The isolation structure includes a first isolation layer and a second isolation layer sequentially located on the surface of the silicon carbide doped layer. The material of the first isolation layer includes silicon oxide, and the material of the second isolation layer includes aluminum oxide.