Preparation method of stacked transistor, stacked transistor, device and electronic equipment
By forming straight through holes and coupling through holes in stacked transistors, the complex wiring of self-aligned flip transistors is solved, and flexible decoupling capacitor design and circuit performance improvement are achieved.
Patent Information
- Application Number
- CN202510427270.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-07
- Publication Date
- 2025-08-12
Smart Images
Figure CN120475763A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductors, and in particular to a method for preparing a stacked transistor, a stacked transistor, a device, and an electronic device. Background Art
[0002] As Moore's Law continues to deepen, further advancing transistor scaling is a hot topic in the industry. Stacked transistors, by integrating two or more layers of transistors vertically, further increase transistor integration density and become a key technology for further scaling integrated circuits.
[0003] In some stacked transistor fabrication schemes, active regions of two layers of transistors with the same source are formed by etching, and then the stacked transistors are fabricated on the front and back sides of the wafer by flipping the wafer. This is also known as a "self-aligned flip-chip transistor" scheme. However, the process of forming decoupling capacitors (decap cells) based on "self-aligned flip-chip transistors" is extremely complex due to the complex internal wiring of the transistors and the difficulty of fabrication, which is not conducive to the miniaturization of integrated circuits. Summary of the Invention
[0004] The present application provides a method for preparing a stacked transistor, a stacked transistor, a device, and an electronic device, which can make the design of the stacked transistor more flexible on the basis of realizing the decoupling capacitor function.
[0005] In a first aspect, an embodiment of the present application provides a method for preparing a stacked transistor, the method comprising: forming an active structure on a substrate; the active structure comprising a front active structure and a back active structure stacked in a first direction; performing a front-end process based on the front active structure to form a front front-end device layer of the front transistor; the front front-end device layer comprising a front gate structure and a front source-drain structure; flipping the substrate and thinning the substrate; performing a front-end process based on the back active structure to form a back front-end device layer of the back transistor; the back front-end device layer comprising a back gate structure and a back source-drain structure; the front transistor and the back transistor are stacked in the first direction; forming a first straight connecting hole penetrating the front front device layer and the back front device layer; the first straight connecting hole is electrically connected to the front gate structure; performing a back-end process on the back front device layer to form a back transistor a back-end interconnection layer; a first type of power rail, a back-end signal line and a back-end through-hole are provided in the back-end interconnection layer; the first type of power rail is electrically connected to the first straight through-hole through the back-end signal line and the back-end through-hole; the first type of power rail is electrically connected to the back-end source-drain structure through the back-end through-hole; the wafer where the back transistor is located is flipped; a second straight through-hole is formed that passes through the back-end front-end device layer and the front-end front-end device layer; the second straight through-hole is electrically connected to the back-end gate structure; back-end process processing is performed on the front-end front-end device layer to form a front-end back-end interconnection layer of the front transistor; a second type of power rail, a front signal line and a front-end through-hole are provided in the front-end back-end interconnection layer; the second type of power rail is electrically connected to the second straight through-hole through the front signal line and the front-end through-hole; the second type of power rail is electrically connected to the front-end source-drain structure through the front-end through-hole.
[0006] In some possible embodiments, the method for preparing a stacked transistor further includes: forming a first dielectric layer on the front-end device layer; the first dielectric layer is located between the front-end device layer and the front-end interconnection layer; forming a first coupling through hole in the first dielectric layer; the first coupling through hole contacts the front gate structure; and the first straight through hole is electrically connected to the front gate structure through the first coupling through hole.
[0007] In some possible embodiments, the method for preparing a stacked transistor further includes: forming a second dielectric layer on the back front-end device layer; the second dielectric layer is located between the back front-end device layer and the back back-end interconnection layer; forming a second coupling through hole in the second dielectric layer; the second coupling through hole is in contact with the back gate structure; and the second straight through hole is electrically connected to the back gate structure through the second coupling through hole.
[0008] In some possible implementations, the front transistor is a transistor of a first polarity; the back transistor is a transistor of a second polarity; and the first polarity and the second polarity are complementary.
[0009] In some possible embodiments, the method for preparing a stacked transistor further includes: removing the front gate structure and the front active structure located in the front gate region of the front transistor to expose the front gate region; filling the front gate region with insulating material to form a front single diffusion isolation structure; or, removing the back gate structure and the back active structure located in the back gate region of the back transistor to expose the back gate region; filling the back gate region with insulating material to form a back single diffusion isolation structure.
[0010] In some possible embodiments, the back side signal line includes a first back side signal line and a second back side signal line; performing back side processing on the back side front side device layer to form a back side back side interconnection layer of the back side transistor, including: depositing a dielectric material on the back side front side device layer to form a first back side dielectric layer; forming a back side back side through hole in the first back side dielectric layer; depositing a dielectric material on the first back side dielectric layer to form a second back side dielectric layer; forming a first type power rail and a first back side signal line in the second back side dielectric layer; the first back side signal line is electrically connected to the first straight through hole through the back side back side through hole; the first type power rail is electrically connected to the back side source and drain structure through the back side back side through hole; depositing a dielectric material on the second back side dielectric layer to form a third back side dielectric layer; forming a second back side signal line on the third back side dielectric layer; the second back side signal line is electrically connected to the first type power rail and the first back side signal line.
[0011] In some possible embodiments, the front signal line includes a first front signal line and a second front signal line; performing back-end processing on the front front device layer to form a front back-end interconnection layer of the front transistor, including: depositing a dielectric material on the front front device layer to form a first front dielectric layer; forming a front back-end through hole in the first front dielectric layer; depositing a dielectric material on the first front dielectric layer to form a second front dielectric layer; forming a first type power rail and a first front signal line in the second front dielectric layer; the first front signal line is electrically connected to the first straight through hole through the front back-end through hole; the first type power rail is electrically connected to the front source and drain structure through the front back-end through hole; depositing a dielectric material on the second front dielectric layer to form a third front dielectric layer; forming a second front signal line on the third front dielectric layer; the second front signal line is electrically connected to the first type power rail and the first positive signal line.
[0012] In a second aspect, an embodiment of the present application provides a stacked transistor, which is prepared by the method of the first aspect, and the stacked transistor includes: a front transistor; the front transistor includes a front front device layer and a front back interconnection layer, the front front device layer includes a back gate structure and a back source and drain structure, and the front back interconnection layer includes a second type of power rail, a front signal line and a front back through-hole; the second type of power rail is electrically connected to the front source and drain structure through the front back through-hole; a back transistor; the front transistor and the back transistor are stacked in a first direction; the back transistor includes a back front device layer and a back back interconnection layer, and the back front device layer includes a back gate structure and A back-side source-drain structure, wherein the back-side back-end interconnection layer includes a first type of power rail, a back-side signal line, and a back-side back-end through-hole; the first type of power rail is electrically connected to the back-side source-drain structure through the back-side back-end through-hole; a first straight connecting hole; the first straight connecting hole passes through the front-side front-end device layer and the back-side front-end device layer; the first straight connecting hole is electrically connected to the front-side gate structure, and the first straight connecting hole is electrically connected to the first type of power rail through the back-side signal line and the back-side back-end through-hole; a second straight connecting hole; the second straight connecting hole passes through the front-side front-end device layer and the back-side front-end device layer; the second straight connecting hole is electrically connected to the back-side gate structure; the second straight connecting hole is electrically connected to the second type of power rail through the front signal line and the front-side back-end through-hole.
[0013] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a stacked transistor as described in the above embodiment.
[0014] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board.
[0015] In the present application, by forming a first straight through hole, a second straight through hole, a first coupling through hole and a second coupling through hole, wherein the first straight through hole is electrically connected to the front gate structure through the first coupling through hole, the second straight through hole is electrically connected to the back gate structure through the second coupling through hole, the first straight through hole is electrically connected to the first type of power rail, the first type of power rail is electrically connected to the back source and drain metal, the second straight through hole is electrically connected to the second type of power rail, and the second type of power rail is electrically connected to the front source and drain metal; two decoupling capacitor units are realized in parallel, making the design of stacked transistors more flexible.
[0016] Furthermore, the first straight via and the second straight via with a large aspect ratio can simplify the implementation of the decoupling capacitor.
[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0019] Figure 1 This is a schematic diagram of a first circuit structure of a stacked transistor in an embodiment of the present application;
[0020] Figure 2 This is a schematic diagram of a second circuit structure of a stacked transistor in an embodiment of the present application;
[0021] Figure 3 A design layout of a stacked transistor in an embodiment of the present application;
[0022] Figure 4 This is a schematic diagram of the structure of the stacked transistor in an embodiment of the present application;
[0023] Figure 5 A schematic diagram of an implementation process of a method for preparing a stacked transistor in an embodiment of the present application;
[0024] Figures 6A to 6G A schematic diagram of a process for preparing a stacked transistor in an embodiment of the present application;
[0025] Figure 7 Schematic diagram of a third circuit structure of stacked transistors in an embodiment of the present application;
[0026] The above pictures:
[0027] 10. Stacked transistor; 11. Front transistor; 111. Front source and drain epitaxy; 112. Front interlayer dielectric layer; 113. Front gate dielectric layer; 114. Front gate structure; 115. Front spacer; 116. Front source and drain metal; 117. Front back-end interconnect layer; 12. Back transistor; 121. Back source and drain epitaxy; 122. Back interlayer dielectric layer; 123. Back gate dielectric layer; 124. Back gate structure; 125. Back spacer; 126. Back source and drain metal; 127. Back back-end interconnect layer; 13. First insulating layer; 14. First carrier wafer; 15. Second insulating layer; 16. Second carrier wafer; 21. Substrate; 22. Active structure; 221. Front active structure; 222. Back active structure; 23. Shallow trench isolation structure; 231. Shallow trench isolation layer; 24. Front Surface pseudo gate structure; 311, first dielectric layer; 312, second dielectric layer; 321, first coupling through hole; 322, second coupling through hole; 331, first straight through hole; 332, second straight through hole; 41, first back dielectric layer; 411, back-end through hole; 42, second back dielectric layer; 421, first back signal line; 43, back signal line interconnection dielectric layer; 431, back signal line interconnection structure; 44, third back dielectric layer; 441, second back signal line; 51, first front dielectric layer; 511, front-end through hole; 52, second front dielectric layer; 521, first front signal line; 53, front signal line interconnection dielectric layer; 531, front signal line interconnection structure; 54, third front dielectric layer; 541, second front signal line; 61, first type power rail; 62, second type power rail. DETAILED DESCRIPTION
[0028] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this application.
[0029] As Moore's Law continues to deepen, furthering transistor scaling is a hot topic in the industry. Stacked transistors, through three-dimensional transistor stacking, enable the integration of two or more layers of transistors in a vertical space, helping to further increase transistor integration density and improve circuit performance. This is considered a key technology for continuing the scaling of integrated circuits.
[0030] In one embodiment, there are two schemes for manufacturing stacked transistors. The first scheme is a monolithic scheme, and the second scheme is a sequential scheme.
[0031] The first solution is to make N-type field effect transistors (NFET) and P-type field effect transistors (PFET) on the same substrate without using wafer bonding technology. This means that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layers of transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied upon to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.
[0032] The second solution is based on wafer bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by bonding the wafer on top of the already fabricated lower transistor, and the two transistors are stacked vertically. However, this solution requires strict temperature control during the thermal process of processing the upper transistor to avoid affecting the lower transistor and interconnects. The advantage of this solution is that thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used in the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance.
[0033] To address the technical issues of the two aforementioned solutions, a "flip-effect transistor" (FFET) solution was proposed. This "FFET" solution forms active regions of upper and lower layers of transistors with the same source by etching, and then flips the wafer to create stacked transistors on the front and back sides, overcoming the shortcomings of the two aforementioned solutions.
[0034] In some embodiments, a decoupling capacitor is a capacitor installed at the power supply terminal of a component in a circuit. This capacitor can provide a more stable power supply and can also reduce the noise coupled from the component to the power supply terminal, indirectly reducing the impact of the component noise on other components.
[0035] For complementary field-effect transistors (CFETs) formed using the above-mentioned "stacked transistor" scheme, the power lines and signal lines are both arranged on the front side of the transistor, and the gates and source and drain of the upper and lower transistors are aligned, which makes the self-aligned flip-chip transistor difficult to wire, especially the more complex metal interconnections, and thus it is impossible to simply implement the design of decoupling capacitors through contact vias or through layer vias (TLVs) between gates.
[0036] For stacked transistors formed using the above-mentioned “self-aligned flip-chip transistor”, Figure 1 This is a schematic diagram of a first circuit structure of stacked transistors in an embodiment of the present application. Figure 1 (a) is the first circuit diagram of stacked transistors. Figure 1 (b) is a first combined schematic diagram of the structure and circuit of stacked transistors. Figure 1 As shown, VSS and node 2 correspond to the front transistor in the stacked transistor, and VDD and node 1 correspond to the back transistor in the stacked transistor; wherein the front transistor is an N-type metal oxide semiconductor (NMOS) and the back transistor is a P-type metal oxide semiconductor (PMOS). Figure 1 As shown in (b), an electrical isolation structure is provided on both sides of the stacked transistor. The electrical isolation structure can be realized by single diffusion break (SDB) technology. The electrical isolation structure is used to realize electrical isolation between adjacent units, which can reduce leakage and improve performance. Figure 1 The front transistor and the back transistor shown are connected in series to realize the decoupling capacitor function, so NMOS and PMOS must be used at the same time to realize the decoupling capacitor function. This structural design cannot meet the needs of using only NMOS or PMOS alone in some special scenarios.
[0037] In order to solve the above technical problems, an embodiment of the present application provides a method for preparing a stacked transistor, which can make the design of the stacked transistor more flexible on the basis of realizing the decoupling capacitor function.
[0038] In some embodiments, the stacked transistor may include a front-side transistor and a back-side transistor in a stacked, "back-to-back" arrangement. The front-side transistor includes a front-side front-end device layer and a front-side back-end interconnect layer, wherein the front-side front-end device layer includes a front-side source and drain structure, a front-side gate structure, a front-side interlayer dielectric (ILD) layer and other structures, and the front-side back-end interconnect layer includes a second-type power rail, a front-side signal line and a front-side back-end via; the back-side front-end device layer includes a back-side source and drain structure, a back-side gate structure, a back-side interlayer dielectric layer and other structures, and the back-side back-end interconnect layer includes a first-type power rail, a back-side signal line and a back-side back-end via.
[0039] In some embodiments, the first type power rail may be VDD (voltage drain drain), and the second type power rail may be VSS (voltage source supply).
[0040] In some embodiments, the stacked transistor further includes a first straight via and a second straight via, wherein the first straight via extends through the front-end device layer and the back-end device layer, and the second straight via extends through the front-end device layer and the back-end device layer. In some embodiments, the first straight via is electrically connected to the front-end gate structure, and the first straight via is electrically connected to the first type power rail via a back-end signal line and a back-end via; the second straight via is electrically connected to the back-end gate structure; and the second straight via is electrically connected to the second type power rail via a front-end signal line and a front-end via.
[0041] In some embodiments, the first type power rail is electrically connected to the back side source and drain structure through a back side back-end via, and the second type power rail is electrically connected to the front side source and drain structure through a front side back-end via.
[0042] It should be noted that, in the embodiments of the present application, for the sake of convenience, source and drain are abbreviations of source and / or drain. For example, the front source and drain structure can be a front source structure and / or a front drain structure.
[0043] Figure 2 This is a schematic diagram of the second circuit structure of the stacked transistor in the embodiment of the present application. Figure 2 (a) is the second circuit diagram of stacked transistors. Figure 2 (b) is a second combined schematic diagram of the stacked transistor structure and circuit. Figure 2As shown in (b), the dashed line to the right of the front gate structure represents the first straight via, and the dashed line to the left of the back gate structure represents the second straight via. The solid line between the front gate structure and the first straight via represents the first coupling via, and the solid line between the back gate structure and the second straight via represents the second coupling via. The front and back transistors are connected in parallel and are independent of each other, each capable of performing decoupling capacitor functions.
[0044] It can be understood that in the embodiment of the present application, the connection method between the first straight via, the back source and drain structure, the first type of power rail, the back signal line, the back back through hole and the front gate structure realizes electrical interconnection and forms a cross-coupled decoupling capacitor unit (cross couple decap cell), thereby achieving high-frequency decoupling and reducing power supply noise. The connection method between the second straight via, the front source and drain structure, the second type of power rail, the front signal line, the front back through hole and the back gate structure realizes electrical interconnection and forms a cross-coupled decoupling capacitor unit, thereby achieving high-frequency decoupling and reducing power supply noise.
[0045] Figure 3 This is a design layout of stacked transistors in an embodiment of the present application. Figure 4 This is a schematic diagram of the structure of the stacked transistor in the embodiment of the present application. Figure 4 The stacked transistors shown are arranged in accordance with Figure 3 The design layout shown is prepared. Figure 4 (a) is a cross-sectional view of the stacked transistor along the AA' direction in the design layout; Figure 4 (b) is a cross-sectional view of the stacked transistor along the BB' direction in the design layout; Figure 4 (c) is a cross-sectional view of the stacked transistor along the CC' direction in the design layout; Figure 4 (d) is a cross-sectional view of the stacked transistor along the DD' direction in the design layout. Figure 4 (e) is a cross-sectional view of the stacked transistor along the EE' direction in the design layout.
[0046] The following combination Figure 3 and Figure 4 The method for preparing the stacked transistor provided in the embodiment of the present application is described.
[0047] Figure 5 This is a schematic diagram of an implementation process of the method for preparing a stacked transistor in an embodiment of the present application. Figure 5 As shown, the method for preparing the stacked transistor may include:
[0048] Step S501: forming an active structure on a substrate, wherein the active structure includes a front active structure and a back active structure stacked in a first direction.
[0049] At the beginning of preparing the stacked transistor, a substrate (also called a wafer) is first provided. The active structure is patterned on the substrate, and then the active structure is etched on the substrate through an etching process. Since the stacked transistor includes at least two stacked transistors (i.e., the front transistor and the back transistor), and the active structures of the front transistor and the back transistor are formed in the same process, it is necessary to control the etching depth to ensure that the height of the active structure can prepare two stacked transistors at the same time. For example, the height of the etched active structure can be greater than 100nm. The active structure can be composed of a front active structure and a back active structure. The front active structure is used to prepare the front transistor, and the back active structure is used to prepare the back transistor.
[0050] In some embodiments, the substrate may be a silicon (Si) substrate or a silicon-on-insulator (SOI) substrate. The specific selection may be based on actual needs and is not specifically limited in the embodiments of the present application.
[0051] In some embodiments, when an SOI substrate is used as the substrate, the BOX layer in the SOI substrate can achieve electrical isolation between the front active structure and the back active structure. In some embodiments, when the substrate is not an SOI substrate, ion implantation or other means can be used to achieve electrical isolation between the front active structure and the back active structure.
[0052] In some embodiments, since the front active structure and the back active structure are formed through the same process, the active area of the front transistor corresponding to the front active structure and the active area of the back transistor corresponding to the back active structure are self-aligned.
[0053] In some embodiments, Figure 4 The stacked transistor shown is composed of two fin field-effect transistors (FinFET). It should be noted that the fin field-effect transistor is only one example. The stacked transistor described in the embodiment of the present application can also be formed by stacking other types of transistors, such as; gate-all-around field-effect transistor (GAAFET), planar metal-oxide-semiconductor field-effect transistor, etc.
[0054] Step S502 : performing front-end process based on the front active structure to form a front-end device layer of the front transistor, wherein the front-end device layer includes a front gate structure and a front source-drain structure.
[0055] As you can understand, the front-end of line (FEOL) process is the first major stage in integrated circuit manufacturing. Its main goal is to complete the manufacturing and patterning of various devices on the wafer. These devices include source, drain, gate, etc., which are the basic units that constitute the circuit function.
[0056] In some embodiments, the front-end device layer may include a front interlayer dielectric (ILD) layer, a front spacer, a front gate dielectric layer, and other structures in addition to the front gate structure and the front source / drain structure.
[0057] In some embodiments, the front source and drain structure includes a front source and drain epitaxy and a front source and drain metal.
[0058] In some embodiments, the above step S502 may include: photolithographically opening the front gate region, and depositing semiconductor material (such as polysilicon (poly Si)) in the front gate region to form a front dummy gate structure. Depositing insulating material on the sidewalls of the front dummy gate structure to form a front spacer. Forming a front source and drain groove by etching a portion of the front active structure located in the front source and drain region, and performing source and drain epitaxial growth in the front source and drain groove to form a front source and drain epitaxy. Depositing dielectric material in the front source and drain region to form a front interlayer dielectric layer. Then, removing the front dummy gate structure to expose the front gate region, depositing insulating material on the front active structure in the front gate region to form a front gate dielectric layer; and depositing metal material in the front gate region to form a front gate structure. Etching the front interlayer dielectric layer to form a front source and drain metal groove, and depositing metal material in the front source and drain metal groove to form a front source and drain metal.
[0059] In some possible embodiments, after step S502, the method may further include: forming a first dielectric layer on the front-end device layer; the first dielectric layer is located between the front-end device layer and the front-end interconnect layer; forming a first coupling through hole in the first dielectric layer; and the first coupling through hole is in contact with the front gate structure.
[0060] As can be understood, a dielectric material is deposited on the front-end device layer to form a first dielectric layer. A first coupling via can be formed in the first dielectric layer through processes such as photolithography, etching, and deposition. The first coupling via contacts the front-end gate structure, achieving electrical connection with the front-end gate structure.
[0061] Step S503: flip the wafer over and thin the substrate.
[0062] It can be understood that the wafer is flipped and the substrate is thinned until the back active structure is exposed, so that the back active structure is placed upward to facilitate the preparation of the back transistor.
[0063] In some embodiments, the substrate may be thinned by a chemical-mechanical planarization (CMP) process.
[0064] In some possible embodiments, before the above-mentioned step S503, the above-mentioned method for preparing the stacked transistor may further include: depositing an insulating material on the surface of the front transistor away from the back active structure to form a first insulating layer; and bonding the first insulating layer to the first carrier wafer.
[0065] In an embodiment of the present application, the bonded first carrier wafer can provide physical support for the flipped front transistor after flipping over, effectively preventing the front transistor from being broken by external force during the preparation of the back transistor.
[0066] Step S504: Perform front-end processing based on the backside active structure to form a backside front-end device layer of the backside transistor. The backside front-end device layer includes a backside gate structure and a backside source and drain structure; the frontside transistor and the backside transistor are stacked in the first direction.
[0067] In some embodiments, the back front-end device layer may include a back interlayer dielectric layer, a back spacer, a back gate dielectric layer, and other structures in addition to the back gate structure and the back source and drain structure.
[0068] In some embodiments, the back side source and drain structure includes a back side source and drain epitaxy and a back side source and drain metal.
[0069] In some embodiments, the above step S504 may include: photolithographically opening the back gate region, and depositing a semiconductor material (such as polysilicon) in the back gate region to form a back dummy gate structure. Depositing an insulating material on the sidewalls of the back dummy gate structure to form a back spacer. Forming a back source and drain groove by etching a portion of the back active structure located in the back source and drain region, and performing source and drain epitaxial growth in the back source and drain groove to form a back source and drain epitaxy. Depositing a dielectric material in the back source and drain region to form a back interlayer dielectric layer. Then, removing the back dummy gate structure to expose the back gate region, depositing an insulating material on the back active structure in the back gate region to form a back gate dielectric layer; and depositing a metal material in the back gate region to form a back gate structure. Etching the back interlayer dielectric layer to form a back source and drain metal groove, and depositing a metal material in the back source and drain metal groove to form a back source and drain metal.
[0070] Step S505: forming a first straight via penetrating the front-end device layer and the back-end device layer, wherein the first straight via is electrically connected to the front-end gate structure.
[0071] It can be understood that a first straight connecting hole can be formed through processes such as photolithography, etching and deposition, and the first straight connecting hole penetrates the front interlayer dielectric layer in the front-end device layer and the back interlayer dielectric layer in the back-end device layer.
[0072] In some embodiments, a photoresist is applied above the back-side interlayer dielectric layer and developed to form a photomask. Using the photomask as a mask, the back-side interlayer dielectric layer and the front-side dielectric layer are etched to form a first groove. A metal material is deposited in the first groove to form a first direct via. The first direct via contacts the first coupling via and is electrically connected to the front-side gate structure through the first coupling via.
[0073] In some possible implementations, after step S506, the method may further include: forming a second dielectric layer on the back front-end device layer; the second dielectric layer is located between the back front-end device layer and the back back-end interconnection layer; forming a second coupling via in the second dielectric layer; and the second coupling via is in contact with the back gate structure.
[0074] As can be understood, a dielectric material is deposited on the backside front-end device layer to form a second dielectric layer. A second coupling via can be formed in the second dielectric layer through processes such as photolithography, etching, and deposition. The second coupling via contacts the backside gate structure, achieving electrical connection therewith.
[0075] Step S506 , performing back-end process processing on the back-side front-end device layer to form a back-side back-end interconnection layer of the back-side transistors.
[0076] In some embodiments, a first type power rail, a back side signal line, and a back side through-hole are provided in the back side back-end interconnection layer; the first type power rail is electrically connected to the first straight through hole through the back side signal line and the back side back-end through-hole; the first type power rail is electrically connected to the back side source and drain structure through the back side back-end through-hole.
[0077] As can be understood, the back-end process is the second major stage of integrated circuit manufacturing. Its main goal is to connect the devices manufactured in the front-end by depositing metal interconnect layers to form a complete circuit.
[0078] Step S507 , flipping the wafer where the back-side transistors are located.
[0079] It can be understood that after the back side transistor is formed, the back side transistor can be flipped over so that the front side transistor is placed upward.
[0080] In some embodiments, after flipping the back-side transistor, the first insulating layer and the first carrier wafer on the surface of the front-side transistor may be removed.
[0081] In some possible embodiments, before the above step S507, the above method for preparing the stacked transistor may further include: depositing an insulating material on the surface of the back transistor away from the front active structure to form a second insulating layer; and bonding the second insulating layer to a second carrier wafer.
[0082] In an embodiment of the present application, the bonded second carrier wafer can provide physical support for the flipped back transistor after the wafer is inverted, effectively preventing the back transistor from being broken by external force during the preparation of the front back-end interconnection layer of the front transistor.
[0083] Step S508 , forming a second straight via penetrating the back front-end device layer and the front front-end device layer; the second straight via is electrically connected to the back gate structure.
[0084] It can be understood that a second straight connecting hole can be formed through processes such as lithography, etching and deposition, and the second straight connecting hole penetrates the front interlayer dielectric layer in the front-end device layer and the back interlayer dielectric layer in the back-end device layer.
[0085] In some embodiments, a photoresist is applied over the second dielectric layer and developed to form a photoresist. Using the photoresist mask, the second dielectric layer, the back-side interlayer dielectric layer, and the front-side interlayer dielectric layer are etched to form a second groove. A metal material is deposited in the second groove to form a second straight via. The second straight via contacts the second coupling via and is electrically connected to the back gate structure through the second coupling via.
[0086] Step S509 , performing back-end process processing on the front-end device layer to form a front-end back-end interconnection layer of the front-side transistors.
[0087] In some embodiments, a second type of power rail, a front side signal line, and a front side back-end through-hole are provided in the front side back-end interconnection layer; the second type of power rail is electrically connected to the second straight through-hole through the front side signal line and the front side back-end through-hole; and the second type of power rail is electrically connected to the front side source and drain structure through the front side back-end through-hole.
[0088] In some possible implementations, the front transistor is a transistor of a first polarity; the back transistor is a transistor of a second polarity; and the first polarity and the second polarity are complementary.
[0089] It is understood that the first polarity can be one of N-type or P-type, and the second polarity can be the other of N-type or P-type; for example, the front transistor is NMOS and the back transistor is PMOS; or, the front transistor is PMOS and the back transistor is NMOS. The polarity of the front transistor and the back transistor can be set according to actual needs and is not specifically limited in the embodiments of the present application.
[0090] In some possible embodiments, the above method may also include: removing the front gate structure and the front active structure located in the front gate region of the front transistor to expose the front gate region; filling the front gate region with insulating material to form a front single diffusion isolation structure; or, removing the back gate structure and the back active structure located in the back gate region of the back transistor to expose the back gate region; filling the back gate region with insulating material to form a back single diffusion isolation structure.
[0091] Understandably, see Figure 3 The circuit diagram shown and Figure 4 As shown in the structural diagram, the connection method of each device in the stacked transistor realizes the parallel connection between the two decoupling capacitor units. This parallel connection method further increases the coupling capacitance between the power lines. At the same time, based on this parallel connection method, the front transistor and the back transistor are independent in the dimension of the decoupling capacitor unit, and a single-transistor decoupling capacitor unit design can be realized. For example, when the front transistor is NMOS and the back transistor is PMOS, and only the N-type field-effect transistor needs to be retained, the gate structure and active area of the gate region of the back transistor can be removed using a single diffusion isolation (SDB) process to obtain a decoupling capacitor unit design implemented only by NMOS.
[0092] In some possible embodiments, the above-mentioned step S506 may include: depositing a dielectric material on the back-side front-end device layer to form a first back-side dielectric layer; forming a back-side back-end through hole in the first back-side dielectric layer; depositing a dielectric material on the first back-side dielectric layer to form a second back-side dielectric layer; forming a first type of power rail and a first back-side signal line in the second back-side dielectric layer; the first back-side signal line is electrically connected to the first straight connecting hole through the back-side back-end through hole; the first type of power rail is electrically connected to the back-side source-drain structure through the back-side back-end through hole; depositing a dielectric material on the second back-side dielectric layer to form a third back-side dielectric layer; forming a second back-side signal line on the third back-side dielectric layer; the second back-side signal line is electrically connected to the first type of power rail and the first back-side signal line.
[0093] In some embodiments, the first backside signal line is an M0 (metal 0) signal line in a backside back-end interconnection layer, and the second backside signal line is an M1 (metal 1) signal line in a backside back-end interconnection layer.
[0094] In some embodiments, a back side signal line interconnection dielectric layer is provided between the second back side dielectric layer and the third back side dielectric layer, and the back side signal line interconnection dielectric layer is used to realize the interconnection between the first back side signal line and the second back side signal line.
[0095] In one example, using VDD as the first type power rail, a second dielectric layer is formed on the back front device layer after the back front device layer is formed. A dielectric material is deposited on the second dielectric layer to form a first back dielectric layer. Back back vias are formed in the first back dielectric layer through processes such as photolithography, etching, and deposition. The back back vias include source / drain back back vias and direct back back vias. The source / drain back back vias contact the back source / drain structures, and the direct back back vias contact the first direct back vias. Dielectric material is deposited on the first back dielectric layer to form a second back dielectric layer. VDD and M0 are formed in the second back dielectric layer through processes such as photolithography, etching, and deposition. Dielectric material is deposited on the second back dielectric layer to form a back signal line interconnect dielectric layer. Multiple back signal line interconnect structures are formed in the back signal line interconnect dielectric layer through processes such as photolithography, etching, and deposition. At least two of the multiple back signal line interconnect structures are in contact with VDD and M0, respectively. A dielectric material is deposited on the back signal line interconnect dielectric layer to form a third back dielectric layer. M1 is formed in the third back dielectric layer through processes such as photolithography, etching, and deposition. M1 is in contact with multiple back signal line interconnect structures. M0 and M1 in the back transistor are electrically connected through the back signal line interconnect structure.
[0096] In this way, the signal lines and the through holes in the back-end interconnection layer are interconnected to realize the electrical connection between the back-side source-drain structure and the first straight through hole.
[0097] In some possible embodiments, the above-mentioned step S509 may include: depositing a dielectric material on the front-end device layer to form a first front dielectric layer; forming a front-end through hole in the first front dielectric layer; depositing a dielectric material on the first front dielectric layer to form a second front dielectric layer; forming a first type of power rail and a first front signal line in the second front dielectric layer; the first front signal line is electrically connected to the first straight through hole through the front-end through hole; the first type of power rail is electrically connected to the front source and drain structure through the front-end through hole; depositing a dielectric material on the second front dielectric layer to form a third front dielectric layer; forming a second front signal line on the third front dielectric layer; the second front signal line is electrically connected to the first type of power rail and the first front signal line.
[0098] In some embodiments, the first front-side signal line is an M0 (metal 0) signal line in a front-side back-end interconnection layer, and the second front-side signal line is an M1 (metal 1) signal line in a front-side back-end interconnection layer.
[0099] In some embodiments, a front signal line interconnection dielectric layer is provided between the second front signal line and the third front signal line. The front signal line interconnection dielectric layer is used to realize the interconnection between the first front signal line and the second front signal line.
[0100] In one example, taking the second type power rail VSS as an example, after the front-end device layer is formed, a first dielectric layer is formed on the front-end device layer. A dielectric material is deposited on the first dielectric layer to form a first front dielectric layer. Front-end vias are formed in the first front dielectric layer through processes such as photolithography, etching, and deposition. The front-end vias include source-drain front-end vias and direct-connect front-end vias. The source-drain front-end vias contact the front source-drain structure, and the direct-connect front-end vias contact the second direct-connect vias. A dielectric material is deposited on the first front dielectric layer to form a second front dielectric layer. VSS and M0 are formed in the second front dielectric layer through processes such as photolithography, etching, and deposition. A dielectric material is deposited on the second front dielectric layer to form a front signal line interconnect dielectric layer. Multiple front signal line interconnect structures are formed in the front signal line interconnect dielectric layer through processes such as photolithography, etching, and deposition. At least two of the multiple front signal line interconnect structures are in contact with VSS and M0, respectively. A dielectric material is deposited on the front signal line interconnect dielectric layer to form a third front dielectric layer. M1 is formed in the third front dielectric layer through processes such as photolithography, etching, and deposition. M1 is in contact with multiple front signal line interconnect structures. M0 and M1 in the front transistor are electrically connected through the front signal line interconnect structure.
[0101] In this way, the interconnection between the signal line and the through hole in the front back-end interconnection layer realizes the electrical connection between the front source-drain structure and the second straight through hole.
[0102] In some possible implementations, the above Figure 4 The stacked transistor shown is only a pair of transistors (i.e., two stacked transistors) as an example. Depending on actual needs, the stacked transistor can be configured to include multiple pairs of transistors. The multiple pairs of transistors are arranged side by side in a second direction, which is perpendicular to the first direction. Each pair of transistors includes a front-side transistor and a back-side transistor.
[0103] Below, the stacked transistor provided in the embodiment of the present application is described by taking the front transistor and the back transistor as fin-type field-effect transistors and the stacked transistor including only one pair of transistors as an example.
[0104] Figure 4The stacked transistor 10 shown may be Figures 6A to 6G The process shown is prepared Figures 6A to 6G A schematic diagram of the preparation process of the stacked transistor in an embodiment of the present application.
[0105] Step 1: Provide a substrate 21. The substrate 21 is an SOI substrate. Etch an active structure 22 on the substrate 21. The active structure 22 includes a front active structure 221 and a back active structure 222 (see FIG. Figure 6A (a)).
[0106] Step 2: Deposit insulating material on the substrate 21 and the active structure 22 to form a shallow trench isolation (STI) structure 23. The STI structure 23 wraps the active structure 22 and covers the substrate 21. The STI structure 23 is etched back to expose the front active structure 221 (see Figure 6A (b)).
[0107] Step 3: Photolithography opens the front gate region of the front transistor 11, deposits polysilicon in the front gate region to form a front dummy gate structure 24, and deposits insulating material on the sidewalls of the front dummy gate structure 24 to form a front spacer 115 (see Figure 6A (c)).
[0108] Step 4: Etch back a portion of the front active structure 221 located in the front source and drain region (see Figure 6B (a)).
[0109] Step 5: Perform source and drain epitaxy growth in the area where the front active structure 221 is etched back to form the front source and drain epitaxy 111. Deposit dielectric material on the shallow trench isolation structure 23 to form the front interlayer dielectric layer 112 (see Figure 6B (b)).
[0110] Step 6: Remove the front dummy gate structure 24 to expose the front gate region. In the front polar region, an insulating material is deposited on the surface of the shallow trench isolation structure 23 and the front active structure 221 to form a front gate dielectric layer 113. Metal material is deposited in the front gate region to form a front gate structure 114 (see Figure 6B (c)).
[0111] Step 7: Etch the front interlayer dielectric layer 112 to form a front source / drain metal groove, and deposit metal material in the front source / drain metal groove to form a front source / drain metal 116 (see Figure 6C (a)).
[0112] Step 8: Deposit dielectric material on the front gate structure 114, the front source / drain metal 116, and the front interlayer dielectric layer 112 to form a first dielectric layer 311. By performing processes such as photolithography, etching, and deposition on the first dielectric layer 311, a first coupling via 321 is formed. The first coupling via 321 contacts the front gate structure 114 and does not contact the front source / drain metal 116 (see FIG. Figure 6C (b)).
[0113] Step 9: Deposit insulating material on the first dielectric layer 311 to form a first insulating layer 13, and bond the first insulating layer 13 to the first carrier wafer 14. Then, flip the wafer and thin the substrate 21 so that the end of the back active structure 222 away from the front active structure 221 is placed upward (see Figure 6D (a)).
[0114] Step 10: Etch a portion of the shallow trench isolation structure 23 to expose the back active structure 222 while retaining the shallow trench isolation structure 23 of a preset height. The retained shallow trench isolation structure 23 is the shallow trench isolation layer 231 (see Figure 6D (b)).
[0115] Step 11: Follow the same steps as the front transistor 11 to form the back source and drain epitaxy 121, back gate structure 124, back interlayer dielectric layer 122, back spacer 125, and back gate dielectric layer 123 in the back transistor 12 (see Figure 6D (c)).
[0116] Step 12: A first groove is formed in the back interlayer dielectric layer 122 and on one side of the back source / drain metal 126 by photolithography and etching processes; the first groove penetrates the back interlayer dielectric layer 122 and the front interlayer dielectric layer 112, and a metal material is deposited in the first groove to form a first straight through hole 331 (see Figure 6E (a)).
[0117] Step 13: Deposit dielectric material on the back gate structure 124, the back source / drain metal 126, and the back interlayer dielectric layer 122 to form a second dielectric layer 312. Perform photolithography, etching, and deposition processes on the second dielectric layer 312 to form a second coupling via 322. The second coupling via 322 contacts the back gate structure 124 and does not contact the back source / drain metal 126 (see Figure 6E (b)).
[0118] Step 14: Deposit dielectric material on the second dielectric layer 312 to form the first back-end dielectric layer 41 in the back-end interconnection layer 127; form back-end through holes 411 in the first back-end dielectric layer 41 (see Figure 6E (c)).
[0119] Step 15: Deposit dielectric material on the first back dielectric layer 41 to form a second back dielectric layer 42; form a first type power rail 61 and a first back signal line 421 in the second back dielectric layer 42 (see Figure 6F (a)).
[0120] Step 16: Deposit dielectric material on the second back dielectric layer 42 to form a back signal line interconnect dielectric layer 43; form a back signal line interconnect structure 431 in the back signal line interconnect dielectric layer 43; deposit dielectric material on the back signal line interconnect dielectric layer 43 to form a third back dielectric layer 44, and form a second back signal line 441 in the third back dielectric layer 44 (see Figure 6F (b)).
[0121] Step 17: Deposit insulating material on the back-end interconnect layer 127 to form a second insulating layer 15, and bond the second insulating layer 15 to the second carrier wafer 16. Then, flip the wafer and remove the first insulating layer 13 and the first carrier wafer 14, so that the first dielectric layer 311 is placed upward (see Figure 6F (c)).
[0122] Step 18: On the first dielectric layer 311, a second groove is formed by photolithography and etching processes; the second groove penetrates the front interlayer dielectric layer 112 and the back interlayer dielectric layer 122, and a metal material is deposited in the second groove to form a second straight through hole 332 (see Figure 6G (a)).
[0123] Step 19: Deposit dielectric material on the first dielectric layer 311 to form the first front dielectric layer 51 in the front back-end interconnection layer 117; form a front back-end through hole 511 in the first front dielectric layer 51 (see Figure 6G (b)).
[0124] Step 20: Deposit dielectric material on the first front dielectric layer 51 to form a second front dielectric layer 52; form a second type power rail 62 and a first front signal line 521 in the second front dielectric layer 52; deposit dielectric material on the second front dielectric layer 52 to form a front signal line interconnection dielectric layer 53; form a front signal line interconnection structure 531 in the front signal line interconnection dielectric layer 53; deposit dielectric material on the front signal line interconnection dielectric layer 53 to form a third front dielectric layer 54, and form a second front signal line 541 in the third front dielectric layer 54.
[0125] At this point, the stacked transistor 10 is completed according to the above manufacturing method.
[0126] Figure 7This is a schematic diagram of a third circuit structure of stacked transistors in an embodiment of the present application. Figure 7 (a) is the third circuit diagram of stacked transistors. Figure 7 (b) is a third combined schematic diagram of the stacked transistor structure and circuit. Figure 7 As shown in (b), the PMOS in the rightmost pair of transistors is removed by performing SDB processing on the PMOS.
[0127] In an embodiment of the present application, a first straight via, a second straight via, a first coupling via and a second coupling via are formed, wherein the first straight via is electrically connected to the front gate structure through the first coupling via, the second straight via is electrically connected to the back gate structure through the second coupling via, the first straight via is electrically connected to the first type of power rail, the first type of power rail is electrically connected to the back source and drain metal, the second straight via is electrically connected to the second type of power rail, and the second type of power rail is electrically connected to the front source and drain metal; two decoupling capacitor units are realized in parallel, making the design of stacked transistors more flexible.
[0128] Furthermore, the first straight via and the second straight via with a large aspect ratio can simplify the implementation of the decoupling capacitor.
[0129] Furthermore, the stacked transistor provided in the embodiments of the present application can be inspected using an inspection and analysis instrument, such as a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscopy (STEM), etc. Taking TEM as an example, the stacked transistor provided in the embodiments of the present application can be inspected using a TEM sectioning method, for example, the first straight via contacts the first coupling via, the first coupling via contacts the front gate structure, the second straight via contacts the second coupling via, and the second coupling via contacts the back gate structure.
[0130] The present application provides a semiconductor device, including: a stacked transistor as described in the above embodiment. The specific definition of the stacked transistor can be found in the above Figure 4 The structure shown is not described in detail here.
[0131] The present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the stacked transistor described above. The specific definition of the stacked transistor can be found in the above Figure 4 , I will not go into details here.
[0132] In the description of this application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In this application, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine different embodiments or examples described in this application and features of different embodiments or examples without contradiction.
[0133] The above are merely preferred embodiments of the present application and are not intended to limit the present application. Persons skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.
Claims
1. A method for preparing a stacked transistor, characterized in that: The method for preparing the stacked transistor includes: forming an active structure on a substrate; the active structure comprising a front active structure and a back active structure stacked in a first direction; Performing front-end process processing based on the front active structure to form a front-end device layer of the front transistor; the front-end device layer includes a front gate structure and a front source and drain structure; flipping and thinning the substrate; Performing front-end process processing based on the back active structure to form a back front-end device layer of the back transistor; the back front-end device layer includes a back gate structure and a back source and drain structure; the front transistor and the back transistor are stacked in the first direction; forming a first straight through hole penetrating the front-end device layer and the back-end device layer; the first straight through hole is electrically connected to the front-end gate structure; Performing back-end processing on the back-end front-end device layer to form a back-end back-end interconnection layer of the back-end transistor; the back-end back-end interconnection layer is provided with a first-type power rail, a back-end signal line, and a back-end back-end through-hole; the first-type power rail is electrically connected to the first straight through-hole through the back-end signal line and the back-end back-end through-hole; the first-type power rail is electrically connected to the back-end source-drain structure through the back-end back-end through-hole; Flipping the wafer where the backside transistor is located; forming a second straight through hole penetrating the back front-end device layer and the front front-end device layer; the second straight through hole is electrically connected to the back gate structure; Back-end processing is performed on the front-end device layer to form a front-end back-end interconnection layer of the front transistor; a second type of power rail, a front signal line and a front-end back-end through-hole are provided in the front-end back-end interconnection layer; the second type of power rail is electrically connected to the second straight through-hole through the front signal line and the front-end back-end through-hole; the second type of power rail is electrically connected to the front source-drain structure through the front-end back-end through-hole.
2. The method for preparing a stacked transistor according to claim 1, wherein: The method for preparing the stacked transistor further includes: forming a first dielectric layer on the front-end device layer; the first dielectric layer is located between the front-end device layer and the front-end interconnect layer; A first coupling through-hole is formed in the first dielectric layer; the first coupling through-hole is in contact with the front gate structure; and the first straight through-hole is electrically connected to the front gate structure through the first coupling through-hole.
3. The method for preparing a stacked transistor according to claim 1, wherein: The method for preparing the stacked transistor further includes: forming a second dielectric layer on the backside front-end device layer; the second dielectric layer is located between the backside front-end device layer and the backside back-end interconnection layer; A second coupling through-hole is formed in the second dielectric layer; the second coupling through-hole is in contact with the back gate structure; and the second straight through-hole is electrically connected to the back gate structure through the second coupling through-hole.
4. The method for preparing a stacked transistor according to claim 1, wherein: The front transistor is a transistor of a first polarity; The back side transistor is a transistor of a second polarity; the first polarity and the second polarity are complementary.
5. The method for preparing a stacked transistor according to claim 1, wherein: The method for preparing the stacked transistor further includes: Removing the front gate structure and the front active structure located in the front gate region of the front transistor to expose the front gate region; filling the front gate region with an insulating material to form a front single diffusion isolation structure; or, The back gate structure and the back active structure located in the back gate region of the back transistor are removed to expose the back gate region; and an insulating material is filled in the back gate region to form a back single diffusion isolation structure.
6. The method for preparing a stacked transistor according to claim 1, wherein: The back signal line includes a first back signal line and a second back signal line; The back-end process is performed on the back-end device layer to form a back-end interconnection layer of the back-end transistor, comprising: Depositing a dielectric material on the back front-end device layer to form a first back dielectric layer; forming the back-end through hole in the first back-end dielectric layer; depositing a dielectric material on the first back dielectric layer to form a second back dielectric layer; forming the first type power rail and the first back signal line in the second back dielectric layer; the first back signal line is electrically connected to the first straight via through the back back through hole; and the first type power rail is electrically connected to the back source and drain structure through the back back through hole; depositing a dielectric material on the second back dielectric layer to form a third back dielectric layer; The second back side signal line is formed on the third back side dielectric layer; the second back side signal line is electrically connected to the first type power rail and the first back side signal line.
7. The method for preparing a stacked transistor according to claim 1, wherein: The front signal line includes a first front signal line and a second front signal line; The back-end process is performed on the front-end device layer to form a front-end back-end interconnection layer of the front transistor, comprising: Depositing a dielectric material on the front-end device layer to form a first front-end dielectric layer; forming the front back-end through hole in the first front dielectric layer; depositing a dielectric material on the first front dielectric layer to form a second front dielectric layer; forming the first type power rail and the first front signal line in the second front dielectric layer; the first front signal line is electrically connected to the first straight via through the front back-end via; and the first type power rail is electrically connected to the front source / drain structure through the front back-end via; depositing a dielectric material on the second front dielectric layer to form a third front dielectric layer; The second front signal line is formed on the third front dielectric layer; the second front signal line is electrically connected to the first type power rail and the first front signal line.
8. A stacked transistor, characterized in that: Prepared by the method for preparing a stacked transistor according to any one of claims 1 to 7, the stacked transistor comprises: A front-side transistor; the front-side transistor includes a front-side front-end device layer and a front-side back-end interconnection layer, the front-side front-end device layer includes a back-side gate structure and a back-side source-drain structure, the front-side back-end interconnection layer includes a second-type power rail, a front-side signal line, and a front-side back-end through-hole; the second-type power rail is electrically connected to the front-side source-drain structure through the front-side back-end through-hole; A backside transistor; the frontside transistor and the backside transistor are stacked in a first direction; the backside transistor comprises a backside front-end device layer and a backside backside interconnection layer, the backside front-end device layer comprises a backside gate structure and a backside source-drain structure, the backside backside interconnection layer comprises a first type power rail, a backside signal line, and a backside backside via; the first type power rail is electrically connected to the backside source-drain structure through the backside backside via; a first straight via; the first straight via penetrates the front-end device layer and the back-end device layer; the first straight via is electrically connected to the front-end gate structure, and the first straight via is electrically connected to the first type power rail through the back-end signal line and the back-end via; A second straight via; the second straight via passes through the front-end device layer and the back-end device layer; the second straight via is electrically connected to the back gate structure; the second straight via is electrically connected to the second type power rail through the front signal line and the front back-end via.
9. A semiconductor device, characterized in that: include: The stacked transistor as claimed in claim 8.
10. An electronic device, characterized in that: include: A circuit board and the semiconductor device according to claim 9, wherein the semiconductor device is provided on the circuit board.