Semiconductor processing chamber and thin film deposition equipment

Abstract

The invention discloses a semiconductor processing chamber and thin film deposition equipment, which can be used in the field of semiconductor preparation, and the semiconductor processing chamber comprises a base, an inner cavity lower polar plate and an inner cavity upper polar plate, a purging gas path is arranged in the lower polar plate of the inner cavity and / or the base; an air inlet of the purging air path is positioned on one side, deviating from the inner cavity, of the inner cavity lower polar plate or on one side, deviating from the inner cavity, of the base; and an air outlet of the purging air path is positioned on one side, close to the inner cavity, of the inner cavity lower polar plate or on one side, close to the inner cavity, of the base. Therefore, the purging gas can be sprayed to the back of the wafer located in the inner cavity through the purging gas path from the side, close to the inner cavity, of the inner cavity lower polar plate or the side, close to the inner cavity, of the base, the back of the wafer is purged through the purging gas, and the problem of film formation of the back of the wafer in the thin film deposition process can be solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor preparation technology, and in particular to a semiconductor processing chamber and thin film deposition equipment. Background Art

[0002] With the rapid development of the semiconductor industry, market competition is becoming increasingly fierce, and higher requirements are placed on the performance and reliability of semiconductor devices.

[0003] Thin film deposition is one of the main processes for preparing semiconductor devices. At present, in thin film deposition equipment, the reaction chamber is usually composed of an upper electrode plate and a lower electrode plate of the inner cavity. The wafer is placed on a base, and thin film deposition is carried out in the reaction chamber. However, since the wafers used to prepare semiconductor devices are not all neatly shaped cylinders, some wafers have edge warping problems, which causes the process gas that is blown laterally to easily form a film on the back of the wafer during thin film deposition on the wafer surface. On the one hand, the film formation on the back of the wafer will affect the performance of semiconductor devices located in the edge area of the wafer, resulting in a decrease in the production yield of semiconductor devices and an increase in production costs; on the other hand, during the thin film deposition process, the friction between the edge of the wafer and the wafer limiting component will also produce particulate contaminants, further affecting the performance and reliability of the semiconductor devices produced.

[0004] Therefore, how to form less film layer on the back of the wafer during the thin film deposition process becomes a problem that needs to be solved. Summary of the Invention

[0005] Based on the above problems, the present application provides a semiconductor processing chamber and a thin film deposition device, which can form a smaller film layer on the back of the wafer during the thin film deposition process.

[0006] The embodiments of this application disclose the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a semiconductor processing chamber comprising a base, an inner cavity lower plate, and an inner cavity upper plate, wherein a purge gas path is provided inside the inner cavity lower plate and / or the base;

[0008] The air inlet of the purge air circuit is located on the side of the lower electrode plate of the inner cavity facing away from the inner cavity, or on the side of the base facing away from the inner cavity; the air outlet of the purge air circuit is located on the side of the lower electrode plate of the inner cavity close to the inner cavity, or on the side of the base close to the inner cavity.

[0009] Optionally, the base and the inner cavity lower plate are axially engaged with each other through mutually fitting stepped flanges;

[0010] The stepped flange of the base includes an upper step flange and a lower step flange;

[0011] The upper step flange is the side of the base close to the inner cavity; the lower step flange is the side of the base away from the inner cavity.

[0012] Optionally, the purge gas path includes a first gas path located inside the lower plate of the inner cavity, and a second gas path located inside the base;

[0013] The air inlet of the first air path is located on the side of the lower plate of the inner cavity away from the inner cavity and is connected to the air inlet pipeline;

[0014] The gas outlet of the first gas path is located on the side of the lower plate of the inner cavity close to the inner cavity, and is connected to the gas inlet of the second gas path located on the lower step flange;

[0015] The air outlet of the second air path is located on a side of the upper step flange close to the inner cavity.

[0016] Optionally, there are two first gas paths arranged opposite to each other.

[0017] Optionally, the inner diameter of the first gas path ranges from 3 mm to 5 mm.

[0018] Optionally, the second air path includes: an air groove boss located on the lower step flange, L-shaped air grooves having the same number as the air groove bosses, an annular air groove located inside the upper step flange, and a plurality of spray holes located on the surface of the upper step flange;

[0019] The air groove boss is fitted with the air outlet of the first air path; the first end of the L-shaped air groove is connected to the air groove boss, and the second end of the L-shaped air groove is connected to the first end of the annular air groove; the second end of the annular air groove is connected to the spray hole.

[0020] Optionally, the number of the air groove bosses is four; the angle between the line connecting two adjacent air groove bosses and the center of the base is 90°.

[0021] Optionally, the height of the air groove boss in the thickness direction of the base ranges from 0.1 mm to 2 mm.

[0022] Optionally, the inner diameter of the L-shaped air groove ranges from 2 mm to 4 mm.

[0023] Optionally, the number of the nozzle holes is 30 to 60.

[0024] Optionally, the plurality of spray holes are evenly spaced and distributed on the surface of the upper step flange.

[0025] Optionally, an exhaust gas path is provided between the inner cavity lower plate and the base.

[0026] Optionally, a pressure ring is fixed on the lower electrode plate of the inner cavity;

[0027] The pressure ring is used to fix the wafer on the base.

[0028] Optionally, the outer ring of the pressure ring is fixed on the lower electrode plate of the inner cavity; the inner ring of the pressure ring extends from the inner ring edge of the lower electrode plate of the inner cavity toward the center of the base;

[0029] The inner ring is inclined downward; and a first angle between an extension surface of an upper surface of the inner ring and a surface of the base is greater than a second angle between an extension surface of a lower surface of the inner ring and a surface of the base.

[0030] Optionally, the first angle ranges from 10° to 45°.

[0031] Optionally, the second angle ranges from 1° to 5°.

[0032] Optionally, the outer ring of the pressure ring is fixed to the lower electrode plate of the inner cavity in an integral or detachable manner.

[0033] In a second aspect, an embodiment of the present application provides a thin film deposition device, comprising a semiconductor processing chamber as described in any embodiment of the first aspect.

[0034] Compared with the existing technology, this application has the following beneficial effects:

[0035] On the one hand, the purge gas can be sprayed from the side of the lower electrode plate of the inner cavity close to the inner cavity or the side of the base close to the inner cavity through the purge gas path to the back of the wafer located in the inner cavity, so that the back of the wafer is purged by the purge gas, which can improve the problem of film formation on the back of the wafer during thin film deposition, improve the yield of semiconductor devices, reduce wafer edge loss, and reduce production costs; on the other hand, the purge gas sprayed from the outlet of the purge gas path can also purge particulate contaminants generated by the friction between the edge of the wafer and the wafer limiting component, thereby improving the performance and reliability of the semiconductor device obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0037] Figure 1 A cross-sectional view of a semiconductor thin film deposition device provided in an embodiment of the present application;

[0038] Figure 2 A schematic diagram of wafer edge warping provided in an embodiment of the present application;

[0039] Figure 3 A top view of a thin film deposition device provided in an embodiment of the present application;

[0040] Figure 4 A cross-sectional view of a thin film deposition device along section BB provided in an embodiment of the present application;

[0041] Figure 5 A partially enlarged view of a semiconductor processing chamber provided in an embodiment of the present application;

[0042] Figure 6 A cross-sectional view of a thin film deposition device along section AA provided in an embodiment of the present application;

[0043] Figure 7 A structural diagram of a base provided in an embodiment of the present application;

[0044] Figure 8 A cross-sectional view of a pressure ring provided in an embodiment of the present application;

[0045] Figure 9 A top view of a pressure ring provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The thin film deposition device provided in the present application can be used in the field of semiconductor preparation. The above is only an example and does not limit the application field of the thin film deposition device provided in the present application.

[0047] The terms "first", "second", "third" and "fourth" in the specification, claims and drawings of this application are used to distinguish different objects rather than to limit a specific order.

[0048] In the embodiments of this application, words such as "as an example" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described in the embodiments of this application as "as an example" or "for example" should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "as an example" or "for example" is intended to present the relevant concepts in a concrete manner.

[0049] The terms used in the implementation section of this application are only used to explain the specific embodiments of this application and are not intended to limit this application.

[0050] See also Figure 1 This figure is a cross-sectional view of a semiconductor thin film deposition apparatus provided in an embodiment of the present application. The semiconductor thin film deposition apparatus mainly comprises a gas mixing block 01, a gas chamber cover plate 02, an inner cavity upper plate 03, an inner cavity lower plate 04, a base 05, a tail exhaust 06, and a gas chamber 07.

[0051] The gas chamber cover plate 02 is arranged above the inner cavity upper electrode plate 03, and together with the inner cavity upper electrode plate 03 constitutes the gas chamber 07; the gas mixing block 01 is located at the air inlet of the gas chamber 07, and is connected to the external air inlet pipeline of the process gas; the inner cavity upper electrode plate 03 and the inner cavity lower electrode plate 04 together constitute the reaction chamber, which is the space for thin film deposition on the wafer; the base 05 is used to support the wafer and fits tightly with the inner cavity lower electrode plate 04 to form a mechanical seal; the tail exhaust 06 is connected to the reaction chamber and is used to discharge the gas in the reaction chamber.

[0052] The process gas used for depositing the thin film enters the gas chamber 07 through the gas mixing block 01 and then reaches the reaction chamber. The gas from the gas chamber 07 forms a film on the surface of the wafer located in the reaction chamber, thereby achieving thin film deposition.

[0053] However, since the wafers used to prepare semiconductor devices are not all neatly shaped cylinders, some wafers have edge warping problems, such as Figure 2 As shown, during thin film deposition on the wafer surface, the process gas purged laterally tends to form a film on the backside of the wafer. This backside film formation can affect the performance of semiconductor devices located near the wafer edge, reducing the production yield of these devices and increasing production costs. Furthermore, during thin film deposition, friction between the wafer edge and the wafer retaining components can generate particulate contaminants, further impacting the performance and reliability of the resulting semiconductor devices.

[0054] In view of this, an embodiment of the present application provides a semiconductor processing chamber, comprising: a base 10, an inner cavity lower electrode plate 20 and an inner cavity upper electrode plate 30; wherein, a purge gas path 40 is arranged inside the inner cavity lower electrode plate 20 and / or the base 10; the air inlet of the purge gas path 40 is located on the side of the inner cavity lower electrode plate 20 facing away from the inner cavity, or on the side of the base 10 facing away from the inner cavity; the air outlet of the purge gas path 40 is located on the side of the inner cavity lower electrode plate 20 close to the inner cavity, or on the side of the base 10 close to the inner cavity.

[0055] Therefore, on the one hand, the purge gas can be sprayed from the side of the lower electrode plate of the inner cavity close to the inner cavity or the side of the base close to the inner cavity through the purge gas path to the back of the wafer located in the inner cavity, so that the back of the wafer is purged by the purge gas, which can improve the problem of film formation on the back of the wafer during thin film deposition, improve the yield of semiconductor devices, reduce wafer edge loss, and reduce production costs; on the other hand, the purge gas sprayed from the outlet of the purge gas path can also purge particulate contaminants generated by the friction between the edge of the wafer and the wafer limiting component, thereby improving the performance and reliability of the semiconductor device obtained.

[0056] In order to help those skilled in the art better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0057] Figure 3 A top view of a thin film deposition device provided in an embodiment of the present application, Figure 4 This is a cross-sectional view of a thin film deposition device along section BB provided in an embodiment of the present application.

[0058] The semiconductor processing chamber of the thin film deposition equipment includes a base 10 , an inner cavity lower plate 20 and an inner cavity upper plate 30 .

[0059] A purge gas path 40 is provided inside the inner cavity lower electrode plate 20 and / or the base 10 .

[0060] The air inlet of the purge air path 40 is located on the side of the lower electrode plate 20 of the inner cavity away from the inner cavity, or on the side of the base 10 away from the inner cavity; the air outlet of the purge air path 40 is located on the side of the lower electrode plate 20 of the inner cavity close to the inner cavity, or on the side of the base 10 close to the inner cavity.

[0061] Optionally, the base 10 and the inner cavity lower electrode plate 20 are axially engaged through mutually cooperating stepped flanges; the stepped flange of the base 10 includes an upper step flange 101 and a lower step flange 102; the upper step flange 101 is the side of the base 10 close to the inner cavity; the lower step flange 102 is the side of the base 10 away from the inner cavity; the base 10, the inner cavity lower electrode plate 20 and the inner cavity upper electrode plate 30 are bonded together to form a hollow semiconductor processing chamber.

[0062] As an example, the base 10 , the inner cavity lower plate 20 and the inner cavity upper plate 30 can all be made of metal titanium to withstand higher deposition temperatures and avoid metal contamination, thereby ensuring a higher cleanliness level in the reaction chamber.

[0063] Taking into account the error when the base 10 and the wafer are matched and the deformation caused by thermal expansion of the two at high temperatures, in order to reduce the probability of wafer damage, the diameter of the groove in the base 10 for placing the wafer can be larger than the diameter of the wafer.

[0064] For example, see Figure 5, this figure is a partial enlarged view of a semiconductor processing chamber provided by an embodiment of the present application, wherein the purge gas path 40 includes a first gas path 401 located inside the lower electrode plate 20 of the inner cavity, and a second gas path 402 located inside the base 10; the air inlet of the first gas path 401 is located on the side of the lower electrode plate 20 of the inner cavity away from the inner cavity, and is connected to the air inlet pipeline 70; the air outlet of the first gas path 401 is located on the side of the lower electrode plate 20 of the inner cavity close to the inner cavity, and is connected to the air inlet of the second gas path 402 located on the lower step flange 102; the air outlet of the second gas path 402 is located on the side of the upper step flange 101 close to the inner cavity.

[0065] Optionally, the semiconductor processing chamber may have two opposing first gas paths 401. The inner diameter of the first gas path 401 may range from 3 mm to 5 mm, and may also be designed based on the size of a 1 / 4 inch pipe to match the first gas path 401 with the 1 / 4 inch pipe.

[0066] Optionally, the air inlet line 70 is arranged in parallel with the air inlet lines for other process gases. The air inlet line 70 is used to introduce a purge gas such as nitrogen into the reaction chamber, while the air inlet lines for other process gases are used to introduce process gases for forming a thin film into the reaction chamber.

[0067] For example, see Figure 6 This figure is a cross-sectional view of a thin film deposition device provided in an embodiment of the present application along the AA section. The second gas path 402 may include: an air groove boss 103 located on the lower step flange 102, L-shaped air grooves 104 with the same number as the air groove boss 103, an annular air groove 105 located inside the upper step flange 101, and a plurality of nozzles 106 located on the surface of the upper step flange 101.

[0068] Among them, the air groove boss 103 is in contact with the air outlet of the first air path 401; the first end of the L-shaped air groove 104 is connected to the air groove boss 103, and the second end of the L-shaped air groove 104 is connected to the first end of the annular air groove 105; the second end of the annular air groove 105 is connected to the spray hole 106.

[0069] Optionally, the number of the air groove bosses 103 is four; the angle between the line connecting two adjacent air groove bosses 103 and the center of the base 10 is 90°, thereby matching the 90° rotation angle of the wafer each time.

[0070] Optionally, the number of the air groove bosses 103 is equal to the number of the L-shaped air grooves 104. In this embodiment, the number of the L-shaped air grooves 104 can also be four, and they are connected to the air groove bosses 103 in a one-to-one correspondence. The inner diameter of the L-shaped air groove 104 can range from 2mm to 4mm.

[0071] For ease of processing, the cross section of the annular air groove 105 can be set to be a square, and the side length of the square is the same as the inner diameter of the L-shaped air groove 104 .

[0072] As an example, the number of the nozzle holes 106 can be 30 to 50. The nozzle holes 106 can be evenly spaced on the surface of the upper step flange 101. For example, the nozzle holes 106 are evenly spaced on the surface of the upper step flange 101 in a circular shape. Figure 7 shown.

[0073] See also Figure 7 The base 10 may further include three PIN holes 107 arranged in an equilateral triangle. The PIN pins may extend through the PIN holes 107 to lift the wafer from the base 10, so that the robot can place and remove the wafer.

[0074] Optionally, a gap serving as an exhaust gas path 60 is provided between the inner cavity lower electrode plate 20 and the base 10. Thus, after the purge gas is ejected from the nozzle 106, it can be discharged to the outer cavity through the exhaust gas path 60 and then extracted from the outer cavity without the need for an additional exhaust gas path.

[0075] The size of the exhaust gas path 60 will affect the airflow state. The size of the exhaust gas path 60 is determined by the height of the gas groove boss 103. As an example, according to the working conditions and the structure of the thin film deposition equipment, the height range of the gas groove boss 103 in the thickness direction of the base 10 is 0.1mm~2mm.

[0076] Thus, the purge gas can start from the air inlet pipe 70, pass through the first air path 401, pass through the air outlet of the first air path 401, and enter the second air path 402 from the air groove boss 103. Then, the purge gas enters the annular air groove 105 through the L-shaped air groove 104, flows along the annular air groove 105, and finally is sprayed into the inner cavity 110 through multiple nozzles 106 located on the surface of the upper step flange 101.

[0077] In the case where a film layer may be formed on the back of the wafer during the thin film deposition process, there is a gap between the edge of the wafer and the base 10. The purge gas is ejected from the nozzle 106 to purge the back of the wafer in the inner cavity 110 to avoid the formation of a film layer on the back of the wafer, thereby improving the yield of semiconductor devices and reducing edge loss. For example, due to factors such as poor mask quality at the edge of the wafer and abnormal film thickness, semiconductor devices 2mm or even 3mm away from the edge of the wafer usually have a low yield, and due to the influence of film formation on the back of the wafer, the edge loss may reach 5mm, resulting in a waste of wafer area, low production yield and high production cost. The thin film deposition equipment provided by the embodiment of the present application can purge the back of the wafer during the thin film deposition process, thereby avoiding film formation on the back of the wafer, thereby improving the performance of these semiconductor devices that were originally affected by the back film formation, reducing yield loss and reducing production costs.

[0078] On the other hand, the purge gas ejected from the nozzle 106 can also purge particulate contaminants generated by the friction between the wafer edge and the wafer limiting component, thereby improving the performance and reliability of the manufactured semiconductor device.

[0079] In other embodiments provided in this application, see Figure 6 A pressure ring 50 is fixed to the lower plate 20 of the inner cavity; the pressure ring 50 is used to fix the wafer on the base 10. Therefore, the pressure ring fixes the wafer on the base, eliminating the need for wafer retaining components such as retaining bosses on the base, avoiding asymmetric warping of the wafer due to three-point support, and eliminating local stress concentration caused by the three retaining bosses.

[0080] See also Figure 8 , this figure is a cross-sectional view of a pressure ring provided in an embodiment of the present application, wherein the outer ring 501 of the pressure ring 50 is fixed on the lower electrode plate 20 of the inner cavity; the inner ring 502 of the pressure ring 50 extends from the inner ring edge of the lower electrode plate 20 of the inner cavity toward the center of the base 10.

[0081] The inner ring of the pressure ring 50 is tilted downward to play the role of pressing the wafer, making the warped wafer edge smoother, further reducing the possibility and area of film formation on the back of the wafer, and having a better clamping effect on the wafer while causing less damage to the wafer. Figure 8 As shown, the cross section of the pressure ring 50 may be "Z" shaped.

[0082] A first angle between an upper surface extension of the inner ring 502 of the pressure ring 50 and the surface of the base 10 is greater than a second angle between a lower surface extension of the inner ring 502 of the pressure ring 50 and the surface of the base 10 .

[0083] As a result, both the inner and outer rings of the pressure ring 50 are inclined surfaces, which can guide the airflow and reduce airflow obstruction. Specifically, the inclined surface of the inner ring of the pressure ring 50 forms a flexible clamp for the wafer and can guide the purge gas to purge the back of the warped wafer; the inclined surface of the outer ring of the pressure ring 50 can guide the airflow on the surface of the wafer and accelerate gas discharge. In addition, with the pressure ring 50 as the wafer limiting component, there is no need to set wafer limiting components such as limiting bosses on the base 10, which can avoid asymmetric warping of the wafer due to three-point support and eliminate the local stress concentration caused by the three limiting bosses.

[0084] As an example, the first angle ranges from 10° to 45°; the second angle ranges from 1° to 5°.

[0085] Optionally, the outer ring 501 of the pressure ring 50 can be fixed to the inner cavity lower plate 20 in an integral or detachable manner.

[0086] For example, see Figure 9The pressure ring 50 can be detachably fixed to the inner cavity lower plate 20 by screws 503. Thus, the pressure ring 50 is detachably connected and fixed to the inner cavity lower plate 20, and the pressure ring 50 can be easily assembled or replaced. For example, the outer ring of the pressure ring 50 can be fixed to the inner cavity lower plate 20 by four screws 503.

[0087] Optionally, in order to further reduce the obstruction of the pressure ring 50 to the airflow, the thickness of the pressure ring 50 can be selected from 0.1 mm to 2 mm.

[0088] In addition, see Figure 6 The thin film deposition equipment provided in the embodiment of the present application may further include: a gas chamber cover plate 80, a gas mixing block 801, a gas chamber 802 and a tail exhaust 00.

[0089] Among them, the gas chamber cover plate 80 is installed above the inner cavity upper electrode plate 30, forming a hollow gas chamber 802 with the inner cavity upper electrode plate 30; the gas mixing block 801 is located at the air inlet of the gas chamber 802, and is connected to the external air inlet pipeline of the process gas, and is used to mix the various process gases input into the gas chamber; the tail exhaust 00 is connected to the semiconductor processing chamber, and is used to discharge the gas in the chamber.

[0090] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referenced to each other. Each embodiment focuses on the differences from other embodiments. Some or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment. Those of ordinary skill in the art can understand and implement the present invention without inventive effort.

[0091] The above is merely one specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A semiconductor processing chamber comprising a base (10), an inner cavity lower plate (20), and an inner cavity upper plate (30), characterized in that: A purge gas path (40) is provided inside the inner cavity lower electrode plate (20) and / or the base (10); The air inlet of the purge air path (40) is located on the side of the inner cavity lower plate (20) facing away from the inner cavity, or on the side of the base (10) facing away from the inner cavity; the air outlet of the purge air path (40) is located on the side of the inner cavity lower plate (20) close to the inner cavity, or on the side of the base (10) close to the inner cavity.

2. The semiconductor processing chamber according to claim 1, wherein The base (10) and the inner cavity lower electrode plate (20) are axially engaged with each other through mutually matching stepped flanges; The stepped flange of the base (10) comprises an upper step flange (101) and a lower step flange (102); The upper step flange (101) is the side of the base (10) close to the inner cavity; the lower step flange (102) is the side of the base (10) away from the inner cavity.

3. The semiconductor processing chamber according to claim 2, wherein: The purge gas path (40) includes a first gas path (401) located inside the inner cavity lower plate (20) and a second gas path (402) located inside the base (10); The air inlet of the first air path (401) is located on the side of the inner cavity lower plate (20) facing away from the inner cavity, and is connected to the air inlet pipeline (70); The gas outlet of the first gas path (401) is located on a side of the inner cavity lower plate (20) close to the inner cavity, and is connected to the gas inlet of the second gas path (402) located on the lower step flange (102); The air outlet of the second air path (402) is located on a side of the upper step flange (101) close to the inner cavity.

4. The semiconductor processing chamber according to claim 3, wherein: It has two first gas paths (401) arranged opposite to each other.

5. The semiconductor processing chamber according to claim 3, wherein: The inner diameter of the first gas path (401) ranges from 3 mm to 5 mm.

6. The semiconductor processing chamber according to claim 3, wherein: The second air path (402) comprises: an air groove boss (103) located on the lower step flange (102), L-shaped air grooves (104) having the same number as the air groove boss (103), an annular air groove (105) located inside the upper step flange (101), and a plurality of spray holes (106) located on the surface of the upper step flange (101); The air groove boss (103) is fitted with the air outlet of the first air path (401); the first end of the L-shaped air groove (104) is connected to the air groove boss (103), and the second end of the L-shaped air groove (104) is connected to the first end of the annular air groove (105); and the second end of the annular air groove (105) is connected to the spray hole (106).

7. The semiconductor processing chamber according to claim 6, wherein: The number of the air groove bosses (103) is four; the angle between the line connecting two adjacent air groove bosses (103) and the center of the base (10) is 90°.

8. The semiconductor processing chamber according to claim 6, wherein: The height of the air groove boss (103) in the thickness direction of the base (10) ranges from 0.1 mm to 2 mm.

9. The semiconductor processing chamber according to claim 6, wherein: The inner diameter of the L-shaped air groove (104) ranges from 2 mm to 4 mm.

10. The semiconductor processing chamber according to claim 6, wherein: The number of the spray holes (106) is 30 to 50.

11. The semiconductor processing chamber according to claim 6, wherein: The plurality of spray holes (106) are distributed at equal intervals on the surface of the upper step flange (101).

12. The semiconductor processing chamber according to claim 1, wherein: An exhaust gas path (60) is provided between the inner cavity lower plate (20) and the base (10).

13. The semiconductor processing chamber according to claim 1, wherein: A pressure ring (50) is fixed on the inner cavity lower electrode plate (20); The pressure ring (50) is used to fix the wafer on the base (10).

14. The semiconductor processing chamber according to claim 13, wherein: The outer ring (501) of the pressure ring (50) is fixed on the inner cavity lower plate (20); the inner ring (502) of the pressure ring (50) extends from the inner ring edge of the inner cavity lower plate (20) toward the center of the base (10); The inner ring (502) is tilted downward; a first angle between an extension of the upper surface of the inner ring (502) and the surface of the base (10) is greater than a second angle between an extension of the lower surface of the inner ring (502) and the surface of the base (10).

15. The semiconductor processing chamber according to claim 14, wherein: The first angle ranges from 10° to 45°.

16. The semiconductor processing chamber according to claim 14, wherein: The second angle ranges from 1° to 5°.

17. The semiconductor processing chamber according to claim 14, wherein: The outer ring (501) of the pressure ring (50) is fixed to the inner cavity lower plate (20) in an integral or detachable manner.

18. A thin film deposition device, characterized in that: A semiconductor processing chamber comprising the semiconductor processing chamber according to any one of claims 1 to 17.

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