Single-core cable logging coding method based on FPGA

Abstract

The invention provides a single-core cable logging coding method based on an FPGA. The single-core cable logging coding method comprises the steps that whether the edge of an original sending signal changes or not is detected; if the edge of the original sending signal changes, the original sending signal is coded through the two paths of pulse signals, and a final output signal with positive and negative levels counteracting each other is obtained. According to the invention, the FPGA module and the external driving circuit cooperate to code the original sending signal, so that a final output signal with positive and negative levels counteracting each other can be obtained. According to the invention, the interference of burrs generated by baseline drift on signals and the influence on data accuracy can be effectively avoided, and the influence of level fluctuation on the signals in the transmission of the petroleum logging single-core cable is solved.

Description

Technical Field

[0001] The invention belongs to the technical field of petroleum logging signal processing, and in particular relates to a single-core cable logging coding method based on FPGA. Background Art

[0002] Oil well logging uses single-core cables to transmit data. Single-core cables are responsible for both power supply and signal transmission. The reasons for using single-core cables for well logging are: ① Reduce signal transmission errors. The logging depth can reach 4000-7000m. Using multi-core cable signals will produce reactance differences between different cable cores, and adjacent cable cores are prone to electromagnetic coupling interference. There will be a certain delay in transmission and inconsistency, resulting in measurement errors. Single-core cable transmits data through a single path, which can effectively avoid these phenomena. ② Structural dimensions and installation requirements. Because oil well tubing, wellheads, and instrumentation often face strict size restrictions (e.g., an outer diameter of no more than 42mm), the slim design of single-core cables makes them more suitable for use within wells, meeting space constraints while reducing access difficulties and installation risks. Single-core cables generally have a simple structure, reducing inconsistencies between the different cores in multi-core cables caused by vibration and minor bending, thereby improving the long-term reliability and stability of the overall system.

[0003] ③ Environmental adaptability and system redundancy. In harsh environments such as deep wells, the effects of high temperatures, high pressures, and chemical media (corrosive fluids in oil wells) must also be considered. Single-core cables can typically adapt to these environments and ensure long-term stable transmission through optimized outer sheath and insulation material design. Multi-core cables may increase the risk of additional failures in connectors and wiring. The single-core design simplifies the overall wiring structure, reduces the number of connection points, and mitigates the problem of inconsistent logging data caused by poor contact or connector failure.

[0004] Since single-core cable transmission requires anti-interference measures, if the power signal has burrs, it will have a great impact on the signal. To eliminate this impact, refer to Figure 1 As shown, existing technologies use FPGA chips or single-chip microcomputers in conjunction with peripheral modules to encode the high-level portion of the original transmitted signal using AMI coding, converting it into high and low levels. However, this may not be completely offset from the overall power signal, resulting in baseline drift. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a single-core cable logging encoding method based on FPGA. The technical problem to be solved by the present invention is achieved through the following technical solutions: A single-core cable logging coding method based on FPGA includes: Detect whether the edge of the original transmitted signal changes; If the edge of the original transmission signal changes, the original transmission signal is encoded using two pulse signals to obtain a final output signal in which the positive and negative levels cancel each other out.

[0006] Beneficial effects: The present invention provides an FPGA-based single-core cable logging encoding method, comprising: detecting whether the edge of an original transmitted signal changes; if so, encoding the original transmitted signal using two pulse signals to produce a final output signal in which the positive and negative levels cancel each other out. The present invention uses an FPGA module in conjunction with an external driver circuit to encode the original transmitted signal, producing a final output signal in which the positive and negative levels cancel each other out. This method effectively prevents signal interference caused by baseline drift glitches, which can affect data accuracy, and addresses the impact of level fluctuations on signals during single-core cable transmission in oil well logging.

[0007] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 Schematic diagram of the original waveform of the original transmission signal in the prior art and the AMI code waveform obtained through AMI encoding; Figure 2 This is a flow chart of a single-core cable logging encoding method based on FPGA provided by the present invention; Figure 3 This is a comparison diagram of the waveform of the original transmitted signal and the waveform of the final transmitted signal provided by the present invention; Figure 4 Schematic diagram of a single-core cable logging coding circuit based on FPGA provided by the present invention; Figure 5 It is a schematic diagram of the detection process of the FPGA module provided by the present invention. DETAILED DESCRIPTION

[0009] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0010] like Figure 2 As shown, the present invention provides a single-core cable logging encoding method based on FPGA, including: S100, detecting whether the edge of the original transmission signal changes; S200 , if the edge of the original transmission signal changes, encoding the original transmission signal is performed using two pulse signals to obtain a final output signal in which positive and negative levels cancel each other out.

[0011] The FPGA-based single-core cable logging coding method of the present invention utilizes an FPGA-based single-core cable logging coding circuit to encode the original transmission signal to obtain the final output signal. Figure 2 As shown, the FPGA-based single-core cable logging encoding circuit includes an FPGA module and a driving circuit; wherein the FPGA module inputs the original transmission signal, the system clock signal and the asynchronous reset signal, and outputs two pulse signals; and under the control of the two pulse signals, the driving circuit outputs a final output signal in which the positive and negative levels cancel each other out.

[0012] refer to Figure 3 As shown, Figure 3 The original waveform above is the waveform of the original transmitted signal. The processed waveform below is the waveform of the final output signal obtained by processing the original transmitted signal using the method of the present application. As can be seen from the figure, the positive and negative levels of the waveform processed by the scheme of the present application cancel each other out.

[0013] The FPGA module is used to detect whether the edge of the original transmission signal changes. If so, it generates two pulse signals pos and neg, and outputs V POS and V NEG , where V POS =3V, V NEG =0V, otherwise, V POS =0V, V NEG =3V, the pulse signal neg is a pulse signal outputted in the same clock cycle as the edge change of the original transmitted signal in is detected, and the pulse signal pos is a pulse signal outputted in the next clock cycle in response to the delayed edge change.

[0014] FPGA outputs two signals, neg and pos, corresponding to the output V POS and V NEG , which can be realized by Verilog coding. The specific coding logic can be as follows: (1) The main function of the FPGA module is to convert the edge changes of the input signal in (the original transmitted signal) into a pair of continuous pulse signal outputs to facilitate subsequent circuit triggering.

[0015] (2) Input system clock signal clk, asynchronous reset signal rst (active low), and input signal in.

[0016] FPGA outputs two signals, neg and pos. neg is a pulse signal generated in the same clock cycle when the in edge change is detected, and pos is a pulse signal generated in the next clock cycle when the edge change is delayed. That is, when neg is 1, the output V NEG =3V; when neg is 0, the output VNEG =0V. When pos is 1, the output V POS =3V; when pos is 0, output V POS =0V.

[0017] like Figure 2 As shown, the driving circuit includes resistors R1-R4, a differential amplifier U1, and transistors N1-N2; wherein the first end of the resistor R1 inputs V NEG The second end is connected to the negative input terminal of the differential amplifier and the first end of the resistor R4; the first end of the resistor R2 inputs V POS The second end is connected to the positive input terminal of the differential amplifier and the first end of the resistor R3, and the second end of the resistor R3 is connected to the power supply V SS The second end of the resistor R4 is connected to the emitters of the transistors N1 and N2, the output end of the differential amplifier is connected to the bases of the transistors N1 and N2, the collector of the transistor N1 is connected to the +15V voltage, the collector of the transistor N2 is connected to the -15V voltage, and the source output levels of the transistors N1 and N2 are offset to form the final output signal.

[0018] The subsequent transistor driving circuit of the present invention ensures that the signal output by the amplifier can reach the required voltage level and has sufficient load capacity.

[0019] The FPGA module of the present invention includes two registers, namely in_prev and delay_flag; Among them, the register in_prev is used to store the state of the original transmission signal in sampled in the previous clock cycle, so as to compare it with the original transmission signal of the current clock cycle to determine whether an edge change has occurred; the register delay_flag is used to store the delay control flag. When an input edge change is detected, the delay control flag is set to generate a pulse signal pos in the next clock cycle, and after the generation is completed, the delay control flag is cleared.

[0020] When the asynchronous reset signal takes effect, the FPGA module clears the registers in_prev and delay_flag, and both pulse signals to zero to complete the reset, and enters the initial state after the reset, waiting for the original transmission signal to arrive and detecting whether the edge changes.

[0021] It is worth noting that after the FPGA module of the present invention is reset, that is, when the asynchronous reset signal rst is at a high level, whenever the rising edge of the system clock signal clk arrives, the FPGA module updates the sampling state, clears the pulse output, detects the delay control flag and detects the edge change in sequence to obtain the detection result of whether the edge of the original transmitted signal has changed.

[0022] Wherein, updating the sampling state includes: storing the original transmission signal of the current clock cycle into the register in_prev for comparison detection in the next clock cycle; Clearing the pulse output includes resetting the pulse signals neg and pos to 0, ensuring that pulses are not mistakenly generated when the condition is not triggered; Detecting the delay control flag includes checking the status of the register delay_flag: If the register delay_flag is 1, it means that the detection result is that an edge change of the original transmission signal has been detected in the previous clock cycle and a delayed pulse has been scheduled, then the pulse signal pos is set to 1, and a delayed pulse is generated in the current cycle, that is, the corresponding output V POS ; and immediately clear delay_flag; Detecting edge changes includes: when the register delay_flag is not activated, detecting whether the edge of the original transmission signal has changed (i.e. comparing the current in with the last stored in_prev to see if they are different), and if so, outputting a pulse signal neg (either a rising edge or a falling edge); setting the pulse signal neg to 1, which corresponds to outputting V NEG , synchronously set the delay control flag and set the register delay_flag to 1, thereby triggering the generation of the POS pulse signal in the next clock cycle.

[0023] See also Figure 5 , the FPGA module detects whether the edge of the input signal in changes. If it changes, the two pulse signals output by the FPGA module make V POS =0V and V NEG =3V, , when R1=R2, R3=R4, V O =R4 / R1×(V POS -V NEG ), so the final output voltage V O =50 / 10×(0-3)=-15V; V POS =3V and V NEG =0V, the final output signal voltage V O =50 / 10×(3-0)=+15V; if it does not change, then V POS =0V and V NEG =0V, the final output signal voltage V O =0V.

[0024] Although the present application is described herein with reference to various embodiments, those skilled in the art will be able to understand and implement other variations of the disclosed embodiments in practicing the claimed application by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0025] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A single-core cable logging coding method based on FPGA, characterized in that: include: Detect whether the edge of the original transmitted signal changes; If the edge of the original transmission signal changes, the original transmission signal is encoded using two pulse signals to obtain a final output signal in which the positive and negative levels cancel each other out.

2. The FPGA-based single-core cable logging coding method according to claim 1, characterized in that: The FPGA-based single-core cable logging coding method utilizes an FPGA-based single-core cable logging coding circuit to encode an original transmission signal to obtain a final output signal.

3. The FPGA-based single-core cable logging coding method according to claim 2, characterized in that: The FPGA-based single-core cable logging encoding circuit includes an FPGA module and a drive circuit; wherein the FPGA module inputs the original transmission signal, the system clock signal and the asynchronous reset signal, and outputs two pulse signals; and under the control of the two pulse signals, the drive circuit outputs a final output signal in which the positive and negative levels cancel each other out.

4. The FPGA-based single-core cable logging coding method according to claim 3, characterized in that: The FPGA module is used to detect whether the edge of the original transmission signal changes. If so, it generates two pulse signals pos and neg, which correspond to the output V POS and V NEG , where V POS =3V, then V NEG =0, otherwise, V POS =0V, then V NEG =3V, the pulse signal neg is a pulse signal outputted in the same clock cycle as the edge change of the original transmitted signal in is detected, and the pulse signal pos is a pulse signal outputted in the next clock cycle in response to the delayed edge change.

5. The FPGA-based single-core cable logging coding method according to claim 4, characterized in that: The driving circuit includes resistors R1-R4, a differential amplifier U1, and transistors N1-N2; wherein the first end of the resistor R1 inputs V NEG The second end is connected to the negative input terminal of the differential amplifier and the first end of the resistor R4; the first end of the resistor R2 inputs V POS The second end is connected to the positive input terminal of the differential amplifier and the first end of the resistor R3, and the second end of the resistor R3 is connected to the power supply V SS The second end of the resistor R4 is connected to the emitters of the transistors N1 and N2, the output end of the differential amplifier is connected to the bases of the transistors N1 and N2, the collector of the transistor N1 is connected to the +15V voltage, the collector of the transistor N2 is connected to the -15V voltage, and the source output levels of the transistors N1 and N2 are offset to form the final output signal.

6. The FPGA-based single-core cable logging coding method according to claim 4, characterized in that: The FPGA module includes two registers, namely in_prev and delay_flag; Among them, the register in_prev is used to store the state of the original transmission signal in sampled in the previous clock cycle, so as to compare it with the original transmission signal of the current clock cycle to determine whether an edge change has occurred; the register delay_flag is used to store the delay control flag. When an input edge change is detected, the delay control flag is set to generate a pulse signal pos in the next clock cycle, and after the generation is completed, the delay control flag is cleared.

7. The FPGA-based single-core cable logging coding method according to claim 6, characterized in that: When the asynchronous reset signal takes effect, the FPGA module clears the registers in_prev and delay_flag, and both pulse signals to zero to complete the reset, and enters the initial state after the reset, waiting for the original transmission signal to arrive.

8. The FPGA-based single-core cable logging coding method according to claim 6, characterized in that: When the system clock signal is activated, the FPGA module sequentially executes the steps of updating the sampling state, clearing the pulse output, detecting the delay control flag, and detecting the edge change, and obtains the detection result of whether the edge of the original transmission signal has changed.

9. The FPGA-based single-core cable logging coding method according to claim 8, characterized in that: Updating the sampling state includes storing the original transmission signal of the current clock cycle into the register in_prev for comparison detection in the next clock cycle; Clearing the pulse output includes resetting the pulse signals neg and pos to 0 to ensure that the pulse is not mistakenly generated when the condition is not triggered; detecting the delay control flag includes checking the status of the register delay_flag: if the register delay_flag is 1, it means that the detection result is that an edge change of the original transmission signal has been detected in the previous clock cycle and a delayed pulse has been scheduled, then the pulse signal pos is set to 1, a delayed pulse is generated in the current clock cycle, and the corresponding output V POS ; And immediately clear delay_flag; Detecting edge changes includes: when the register delay_flag is not activated, detecting whether the edge of the original transmission signal changes, and outputting a pulse signal neg if it changes; setting the pulse signal neg to 1 and outputting V accordingly. NEG , synchronously set the delay control flag and set the register delay_flag to 1, thereby triggering the generation of the POS pulse signal in the next clock cycle.

10. The FPGA-based single-core cable logging coding method according to claim 4, characterized in that: When the two pulse signals output by the FPGA module make V POS =0V and V NEG =3V, the final output signal voltage V O =50 / 10×(0-3)=-15V; V POS =3V and V NEG =0V, the final output signal voltage V O =50 / 10×(3-0)=+15V; V POS =0V and V NEG =0V, the final output signal voltage V O =0V.

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