Sub-resolution graph adding method and system for logic region hole layer

Abstract

The invention provides an adding method and system for a sub-resolution graph of a logic region hole layer. The adding method for the sub-resolution graph of the logic region hole layer comprises the steps that a to-be-processed region in the logic region hole layer is obtained; wherein the hole density in the to-be-processed area is lower than the preset density; screening out a plurality of similar environment areas in the to-be-processed area; based on the similarities in the similar environment areas, the similar environment areas fall into different mark layers; according to a preset sequence, adding sub-resolution graphs to the similar environment areas in the plurality of mark layers in sequence; wherein the similar environment areas in the same mark layer are synchronously subjected to sub-resolution graph addition; and supplementing and adding a sub-resolution graph to the whole logic region hole layer. According to the configuration, the adding effect of the SRAF graph can be more stable, and meanwhile, large-area SRAF adding difference and OPC correction difference caused by layout design or structure change can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method and system for adding sub-resolution graphics to a hole layer in a logic area. Background Art

[0002] During Optical Proximity Correction (OPC), sub-resolution assist features (SRAFs) are often inserted into sparse regions to improve the lithography process window, bringing the process window of the sparse pattern closer to that of the dense pattern. The presence of sparse patterns in aperture layers, especially at advanced nodes, often necessitates the addition of numerous SRAFs. Due to cost and lead time considerations, a rule-based SRAF addition method is currently widely used.

[0003] For the Static Random-Access Memory (SRAM) area, since the standard SRAM cell has a standard design and high repetition, the consistency and stability of SRAF addition and OPC correction are relatively high. For the hole graphics in the logic area, there are often a large number of designs with high structural similarity. However, the existing method for the logic area hole layer is usually to perform indiscriminate SRAF addition based on a unified rule. For the logic area hole layer graphics with the same or similar environment, this method often cannot obtain relatively stable SRAF addition and OPC correction results, and its effect is easily affected by changes in the graphic structure. When the GDS (Graphic Data System) is revised, the SRAF addition effect and OPC correction results often show large-scale differences.

[0004] Based on this, how to optimize the SRAF adding method of the logic area hole layer with the same or similar environment to improve the SRAF adding effect and OPC correction effect in the corresponding area has become a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of the present invention is to provide a method and system for adding sub-resolution graphics to the logic area hole layer, so as to solve the problem that the existing SRAF adding method has poor SRAF adding effect and OPC correction effect for logic area hole layer graphics with the same or similar environment.

[0006] In order to achieve the above object, the present invention provides a method for adding sub-resolution patterns to a hole layer in a logic area, comprising:

[0007] Acquire a region to be processed in the hole layer of the logic area; wherein the hole density in the region to be processed is lower than a preset density;

[0008] Screening out multiple similar environmental areas in the area to be processed;

[0009] Based on the similarity in each of the similar environmental regions, the similar environmental regions are placed into different marking layers;

[0010] Adding sub-resolution graphics to the similar environment areas in the plurality of the marking layers in sequence according to a preset order; wherein the sub-resolution graphics are added to the similar environment areas in the same marking layer simultaneously;

[0011] Sub-resolution graphics are added to the entire hole layer of the logic area.

[0012] Optionally, the screening of multiple similar environmental areas in the area to be processed includes:

[0013] Obtaining the center point coordinates of each hole in the area to be processed;

[0014] Counting the number of holes within a preset range of each of the holes;

[0015] If the number of the holes is consistent, it is determined that the area to be processed is the similar environment area;

[0016] If the number of the holes is inconsistent, sub-resolution graphics are directly added to the entire hole layer of the logic area.

[0017] Optionally, the preset range includes an area centered on the hole and within 10 times the diameter of the hole.

[0018] Optionally, the similarity based on each similar environment area includes:

[0019] Obtaining relative positions of a central hole and surrounding adjacent holes in the similar environment area, calibrating the central hole and the adjacent holes to form a plurality of relative position vectors;

[0020] The similarity is obtained based on the relative position vector.

[0021] Optionally, obtaining the similarity based on the relative position vector includes:

[0022] Connecting the central hole with the adjacent holes respectively to form a plurality of relative position vectors;

[0023] The similarity is obtained based on the number, module length and angle of the relative position vectors.

[0024] Optionally, obtaining the similarity based on the number, module length, and angle of relative position vectors includes:

[0025] comparing a first relative position vector formed by the current center hole with a second relative position vector formed by an adjacent center hole;

[0026] If the number, modulus, and included angle of the first relative position vectors and the second relative position vectors are all equal, it is determined that the current center hole is similar to the adjacent center hole;

[0027] If any one of the number, modulus, and included angle of the first relative position vector and the second relative position vector is not equal, it is determined that the current center hole is not similar to the adjacent center hole;

[0028] The similarity is the ratio of the number of the holes determined to be similar to the number of the center holes adjacent to the current center hole.

[0029] Optionally, the spacing between the adjacent holes and the central hole is within a range of a line width or twice the diameter of the central hole.

[0030] Optionally, the adding of sub-resolution graphics to similar environmental areas in a plurality of marker layers in sequence according to a preset order includes:

[0031] Sub-resolution graphics are added to the similar environment areas in the plurality of marking layers in descending order of similarity, and only sub-resolution graphics that intersect with the marking layer are retained each time the sub-resolution graphics are added.

[0032] Optionally, the step of supplementing the sub-resolution pattern to the entire logic area hole layer includes:

[0033] On the basis of sequentially completing the addition of sub-resolution graphics to the similar environment areas in the plurality of mark layers, the sub-resolution graphics are supplementarily added to the entire logic area hole layer.

[0034] To achieve the above-mentioned object, the present invention further provides a system for adding sub-resolution patterns to a hole layer in a logic area, which uses the above-mentioned method for adding sub-resolution patterns to a hole layer in a logic area, comprising:

[0035] A screening module is used to obtain a region to be processed in the hole layer of the logic area, and screen out a plurality of similar environment regions in the region to be processed;

[0036] A classification module, configured to obtain similarities between the similar environmental regions and place the similar environmental regions into different marking layers;

[0037] The execution module is used to add sub-resolution graphics to the similar environment areas in the multiple marking layers in sequence according to a preset order, and after completion, supplement the addition of sub-resolution graphics to the entire logic area hole layer.

[0038] Compared with the existing SRAF addition method, the method and system for adding sub-resolution patterns to the logic area hole layer provided by this application have the following advantages:

[0039] The method for adding sub-resolution graphics to the logic area hole layer provided in this application classifies similar environmental areas by similarity and assigns them to different markup layers. SRAF (Sub-Resolution Assist Feature) is then added to the similar environmental areas in multiple markup layers in a predetermined order. After the corresponding similar environmental areas are added, the entire logic area hole layer is supplemented with SRAF. Compared to the existing method of indiscriminately adding SRAF, the SRAF adding method provided in this application can make the addition of SRAF to the hole pattern in the similar environmental areas of the logic area more stable, while reducing the large-area SRAF addition differences and OPC correction differences caused by layout design or structural changes, thereby further improving the consistency and stability of SRAF addition and OPC correction in the logic area hole layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 This is a schematic diagram of the effect after adding sub-resolution graphics in the prior art;

[0041] Figure 2 A flow chart of a method for adding sub-resolution graphics to a hole layer in a logic area provided by an embodiment of the present invention;

[0042] Figure 3 A schematic diagram showing the effect of adding a sub-resolution pattern to the hole layer in the logic area according to an embodiment of the present invention;

[0043] Figure 4 A schematic diagram of step S1 in a method for adding a sub-resolution pattern to a hole layer in a logic area provided by an embodiment of the present invention;

[0044] Figure 5 A schematic diagram of step S21 in a method for adding a sub-resolution pattern to a hole layer in a logic area provided by an embodiment of the present invention;

[0045] Figure 6 A schematic diagram of step S30 in a method for adding a sub-resolution pattern to a hole layer in a logic area according to an embodiment of the present invention;

[0046] Figure 7A schematic diagram of step S4 in a method for adding a sub-resolution pattern to a hole layer in a logic area provided by an embodiment of the present invention;

[0047] Figure 8 A schematic diagram of a system for adding sub-resolution patterns to a hole layer in a logic area according to an embodiment of the present invention.

[0048] The description of each reference numeral is as follows:

[0049] 1-Center hole; 2-Adjacent holes; 3-Sub-resolution pattern;

[0050] 10-screening module; 20-classification module; 30-execution module. DETAILED DESCRIPTION

[0051] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0052] As used in this specification, the singular forms "a", "an", and "the" include plural referents, the term "or" is generally used to include "and / or", the term "several" is generally used to include "at least one", and the term "at least two" is generally used to include "two or more". In addition, the terms "first", "second", and "third" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features specified as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, "one end" and "the other end" and "proximal end" and "distal end" generally refer to two corresponding parts, which include not only endpoints, and the terms "mounted", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication between two elements or the interaction relationship between two elements. In addition, as used in this specification, an element disposed on another element generally only indicates that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the connection, coupling, cooperation or transmission between the two elements may be direct or indirect through an intermediate element, and it cannot be understood as indicating or implying a spatial positional relationship between the two elements, that is, one element may be in any orientation such as inside, outside, above, below or to one side of another element, unless otherwise clearly indicated in the content. The terms "upper", "lower", "top" and "bottom" are generally relative positional relationships arranged in the direction of gravity; the terms "vertical" and "vertical direction" generally refer to the direction of gravity, which is generally perpendicular to the ground, and "horizontal" and "horizontal plane direction" generally refer to the direction parallel to the ground; for ordinary technicians in this field, the specific meanings of the above terms in this specification can be understood according to specific circumstances.

[0053] The purpose of the present invention is to provide a method and system for adding sub-resolution graphics to the logic area hole layer, so as to solve the problem that the existing SRAF adding method has poor SRAF adding effect and OPC correction effect for logic area hole layer graphics with the same or similar environment.

[0054] As those skilled in the art will understand, in Optical Proximity Correction (OPC), the rule-based SRAF addition method (Rule-Based Sub-Resolution Assist Feature) is a technology that inserts sub-resolution auxiliary patterns around key patterns using predefined rules. Its core purpose is to improve lithography imaging quality through a simple and fast rule-driven approach. SRAFs (Sub-Resolution Assist Features) are tiny structures (such as lines or squares) smaller than the resolution of the lithography machine. They themselves will not be developed onto the photoresist, but can optimize the imaging of the main pattern by enhancing light intensity contrast, suppressing line width deviation, and improving pattern symmetry. In the rule-based SRAF addition method, key rules need to be formulated based on process experience and experimental data. For example, the addition of SRAFs is triggered when the size, spacing, or density of the main pattern reaches a certain threshold. At the same time, it is also necessary to match the corresponding rules based on the design layer (such as the metal layer, contact hole layer) and pattern type (isolated line, dense array). In the prior art, when facing the logic area hole layer, a rule-based SRAF addition method is usually used to achieve indiscriminate addition of the entire logic area hole layer (such as Figure 1 As shown in the figure, this results in unstable SRAF addition within similar environmental regions in the logic area, and is easily affected by layout design or structural changes, resulting in large-area SRAF addition and OPC correction differences. Based on this, this embodiment provides a method and system for adding sub-resolution patterns to the via layer in the logic area. By classifying similar environmental regions and sequentially adding SRAF to similar environmental regions of different similarities, SRAF is added to the entire logic via layer after the corresponding similar environmental regions are added. This further improves the consistency and stability of SRAF addition and OPC correction in the via layer logic area.

[0055] Please refer to Figures 2 to 3 The present invention provides a method for adding sub-resolution graphics to a hole layer in a logic area, comprising:

[0056] Step S1: obtaining a region to be processed in the hole layer of the logic area; wherein the hole density in the region to be processed is lower than a preset density;

[0057] Step S2: screening out multiple similar environmental areas in the area to be processed;

[0058] Step S3: Based on the similarity in each similar environment area, similar environment areas are placed into different marking layers;

[0059] Step S4: adding sub-resolution graphics 3 to similar environmental regions in multiple marker layers in sequence according to a preset order; wherein, sub-resolution graphics 3 are added to similar environmental regions in the same marker layer simultaneously;

[0060] Step S5: Supplement and add the sub-resolution pattern 3 to the entire logic area hole layer.

[0061] It should be noted that in step S1, the operator can use the pattern density algorithm to select the area to be processed in the hole layer of the logic area (such as Figure 4 (as shown). In this embodiment, the area to be processed refers to a sparse pore region with a pore density lower than a preset density. As will be appreciated by those skilled in the art, when performing the above steps, an operator can select an area and set a density threshold. The pattern density algorithm can then filter out areas with a pore density lower than the threshold for subsequent processing. The processing steps and principles of the pattern density algorithm can be referenced in the prior art and will not be further elaborated in this embodiment.

[0062] In step S2, please refer to Figure 5 , mainly by obtaining the number of the center point and the number of adjacent points around it to determine whether it is a similar environment area. As an optional embodiment, it may specifically include:

[0063] Step S20: obtaining the center point coordinates of each hole in the area to be processed;

[0064] Step S21: Count the number of holes within the preset range of each hole; if the number of holes is consistent, the area to be processed is determined to be a similar environment area; if the number of holes is inconsistent, directly add sub-resolution graphics 3 to the entire logic area hole layer.

[0065] The preset range can be an area within 10 times the diameter of the hole, centered on the hole. The area can be a circular area or a rectangular area. Those skilled in the art will appreciate that the preset range can be a range selected by the operator based on experience. Figure 5 For example, A1, A2, A3 and A4 are all center points, and the number of adjacent points around these four center points is 3. Therefore, the four center points A1, A2, A3 and A4 and their adjacent points can be determined as similar environmental areas. Figure 5 There are no adjacent points around points A5, A6, and A7. Therefore, these areas are not similar to the four aforementioned areas. The addition of SRAFs to these areas can be performed in step S5 along with the addition of additional holes to the logic area. Optionally, the spacing between adjacent holes 2 and the center hole 1 is within a range of 1 to 2 times the pitch.

[0066] In step S3, please refer to Figure 6In an optional embodiment, the similarity comparison of each similar environment area can be achieved by using the relative position vector formed between the center point and the adjacent points, which can specifically include:

[0067] Step S30: obtaining the relative positions of the central hole 1 and the surrounding adjacent holes 2 in the similar environment area, calibrating the central hole 1 and the adjacent holes 2 to form a plurality of relative position vectors;

[0068] Step S31: Obtain similarity based on the relative position vector.

[0069] Optional, in Figure 6 In the example, the central hole 1 in each similar environment area is connected to the adjacent holes 2 to form multiple relative position vectors. For example, the central hole A1 can be connected to the adjacent holes B1, C1 and D1 to form the first relative position vectors A1B1, A1C1 and A1D1, which can be further converted into the first relative position coordinates (X B1-A1 , Y B1-A1 )、(X C1-A1 , Y C1-A1 )、(X D1-A1 , Y D1-A1 ); Similarly, the center hole A2 is connected to the adjacent holes B2, C2 and D2 to form a second relative position vector A2B2, A2C2, A2D2, which can be further converted into a second relative position coordinate (X B2-A2 , Y B2-A2 )、(X C2-A2 , Y C2-A2 )、(X D2-A2 , Y D2-A2 ). At this time, the number, module length, and included angle of the relative position vectors can be combined. If the number, module length, and included angle of the first relative position vector and the second relative position vector are equal, then the area where the center hole A1 is located is determined to be similar to the area where the center hole A2 is located; if any one of the number, module length, and included angle of the first relative position vector and the second relative position vector is not equal, then the area where the center hole A1 is located is determined to be dissimilar to the area where the center hole A2 is located. Then, the area where the center hole A1 is located is compared with the area where the center hole A3 is located, and the area where the center hole A1 is located is compared with the area where the center hole A4 is located. When all the areas where the center holes 1 are located are compared, the similarity is the ratio of the number of similar areas to the number of center holes 1 adjacent to the current center hole 1. That is, if the area where the center hole A1 is located is similar to the areas where the center holes A2, A3, and A4 are located, then the similarity is 100%; if the area where the center hole A1 is located is similar only to the areas where the center holes A2 and A3 are located, then the similarity is 66.7%.

[0070] In an alternative embodiment, three marking layers can be provided, wherein the first marking layer can be similar environmental areas with a similarity of 100%; the second marking layer can be similar environmental areas with a similarity greater than or equal to 80% and less than 100%; and the third marking layer can be similar environmental areas with a similarity greater than or equal to 60% and less than 80%. In other embodiments, the number of marking layers and the division criteria can be reasonably configured by the operator based on actual conditions, and this embodiment does not impose any restrictions on this.

[0071] In step S4, please refer to Figure 7 Sub-resolution patterns 3 can be added to similar environmental regions in multiple marker layers in descending order of similarity, retaining only those sub-resolution patterns 3 that intersect with the marker layer during each addition. With this arrangement, when adding sub-resolution patterns 3 to similar environmental regions in different marker layers, the sub-resolution pattern 3 added in the previous step will influence the subsequent addition of sub-resolution patterns 3, further increasing the consistency and stability of SRAF addition in the logic region hole layer based on differences in similarity. Furthermore, in the above steps, the SRAF addition rules for different marker layers can be the same or different. The operator can adopt different addition rules for different pattern structures. The preset order can also be based on descending similarity, or other order, which is not limited in this embodiment.

[0072] In step S5, after the sub-resolution pattern 3 is added to the similar environment areas in the multiple marking layers in sequence, the sub-resolution pattern 3 is added to the entire logic area hole layer, and finally the following is formed: Figure 3 Added effects shown.

[0073] With this configuration, similar environmental regions are classified by similarity and assigned to different marker layers. SRAFs are then added to the similar environmental regions in multiple marker layers in a predetermined order. After the addition of the corresponding similar environmental regions is completed, SRAFs are added to the entire logic area via layer. Compared to existing methods of indiscriminately adding SRAFs, the SRAF addition method provided in this application can achieve a more stable SRAF addition effect for the via pattern in similar environmental regions of the logic area. It can also reduce large-area SRAF addition differences and OPC correction differences caused by layout design or structural changes, thereby further improving the consistency and stability of SRAF addition and OPC correction in the logic area via layer.

[0074] Please refer to Figure 8In another embodiment, the present invention further provides a system for adding sub-resolution graphics to the logic area hole layer, which applies the method for adding sub-resolution graphics to the logic area hole layer as described above, including: a screening module 10, used to obtain the area to be processed in the logic area hole layer, and screen out multiple similar environmental areas in the area to be processed; a classification module 20, used to obtain the similarity of each similar environmental area, and place the similar environmental areas into different marking layers; an execution module 30, used to add sub-resolution graphics 3 to the similar environmental areas in multiple marking layers in sequence according to a preset order, and after completion, supplement the sub-resolution graphics 3 to the entire logic area hole layer.

[0075] It should be noted that the screening module 10, the classification module 20, and the execution module 30 can be communicatively connected to each other. Specifically, the screening module 10 can, based on a preset condition (e.g., a density threshold), screen out sparse hole areas in the logic area hole layer where the hole density is lower than the density threshold as areas to be processed, and further screen out similar environment areas from the areas to be processed based on the number of the center hole 1 and the number of surrounding adjacent holes 2. The classification module 20 can calculate the corresponding similarity based on the relative position vector formed by the center hole 1 and the adjacent holes 2, and then classify the similar environment areas into corresponding marker layers based on the different similarities. The execution module 30 can perform rule-based SRAF addition operations on similar environment areas in different marker layers in a certain order, and after completing the SRAF addition of all similar environment areas, it can, on this basis, supplement the SRAF addition of the entire logic area hole layer, and finally merge and output them.

[0076] In summary, in the method and system for adding sub-resolution graphics to the logic area hole layer provided in the embodiment of the present invention, the method for adding sub-resolution graphics to the logic area hole layer includes: obtaining the area to be processed in the logic area hole layer; wherein the hole density in the area to be processed is lower than the preset density; screening out multiple similar environment areas in the area to be processed; based on the similarity in each similar environment area, the similar environment areas are placed in different marking layers; according to a preset order, sub-resolution graphics are added to the similar environment areas in multiple marking layers in turn; wherein sub-resolution graphics are added synchronously to similar environment areas located in the same marking layer; and supplementary sub-resolution graphics are added to the entire logic area hole layer.

[0077] With this configuration, similar environmental regions are classified by similarity and assigned to different marker layers. SRAFs are then added to the similar environmental regions in multiple marker layers in a predetermined order. After the addition of the corresponding similar environmental regions is completed, SRAFs are added to the entire logic area via layer. Compared to existing methods of indiscriminately adding SRAFs, the SRAF addition method provided in this application can achieve a more stable SRAF addition effect for the via pattern in similar environmental regions of the logic area. It can also reduce large-area SRAF addition differences and OPC correction differences caused by layout design or structural changes, thereby further improving the consistency and stability of SRAF addition and OPC correction in the logic area via layer.

[0078] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for adding sub-resolution graphics to a hole layer in a logic area, characterized in that: include: Acquire a region to be processed in the hole layer of the logic area; wherein the hole density in the region to be processed is lower than a preset density; Screening out multiple similar environmental areas in the area to be processed; Based on the similarity in each of the similar environmental regions, the similar environmental regions are placed into different marking layers; Adding sub-resolution graphics to the similar environment areas in the plurality of the marking layers in sequence according to a preset order; wherein the sub-resolution graphics are added to the similar environment areas in the same marking layer simultaneously; Sub-resolution graphics are added to the entire hole layer of the logic area.

2. The method for adding sub-resolution patterns to the hole layer of the logic area according to claim 1, characterized in that: The screening process includes multiple similar environmental areas in the area to be processed, including: Obtaining the center point coordinates of each hole in the area to be processed; Counting the number of holes within a preset range of each of the holes; If the number of the holes is consistent, it is determined that the area to be processed is the similar environment area; If the number of the holes is inconsistent, sub-resolution graphics are directly added to the entire hole layer of the logic area.

3. The method for adding sub-resolution patterns to the hole layer of the logic area according to claim 2, characterized in that: The preset range includes an area centered at the hole and within 10 times the diameter of the hole.

4. The method for adding sub-resolution patterns to a hole layer in a logic area according to claim 1, wherein: The similarity based on each similar environment area includes: Obtaining relative positions of a central hole and surrounding adjacent holes in the similar environment area, calibrating the central hole and the adjacent holes to form a plurality of relative position vectors; The similarity is obtained based on the relative position vector.

5. The method for adding sub-resolution patterns to the hole layer of the logic area according to claim 4, characterized in that: The similarity is obtained based on the relative position vector, including: Connecting the central hole with the adjacent holes respectively to form a plurality of relative position vectors; The similarity is obtained based on the number, module length and angle of the relative position vectors.

6. The method for adding sub-resolution patterns to the hole layer of the logic area according to claim 5, characterized in that: The similarity is obtained based on the number, module length and angle of relative position vectors, including: comparing a first relative position vector formed by the current center hole with a second relative position vector formed by an adjacent center hole; If the number, modulus, and included angle of the first relative position vectors and the second relative position vectors are all equal, it is determined that the current center hole is similar to the adjacent center hole; If any one of the number, modulus, and included angle of the first relative position vector and the second relative position vector is not equal, it is determined that the current center hole is not similar to the adjacent center hole; The similarity is the ratio of the number of the holes determined to be similar to the number of the center holes adjacent to the current center hole.

7. The method for adding sub-resolution patterns to a hole layer in a logic area according to claim 4, wherein: The spacing between the adjacent holes and the central hole is within a range of one line width or twice the diameter of the central hole.

8. The method for adding sub-resolution patterns to a hole layer in a logic area according to claim 1, wherein: The adding of sub-resolution graphics to similar environmental areas in multiple marker layers in a preset order includes: Sub-resolution graphics are added to the similar environment areas in the plurality of marking layers in descending order of similarity, and only sub-resolution graphics that intersect with the marking layer are retained each time the sub-resolution graphics are added.

9. The method for adding sub-resolution patterns to a hole layer in a logic area according to claim 1, wherein: The method of supplementing and adding sub-resolution graphics to the entire logic area hole layer includes: On the basis of sequentially completing the addition of sub-resolution graphics to the similar environment areas in the plurality of mark layers, the sub-resolution graphics are supplementarily added to the entire logic area hole layer.

10. A system for adding sub-resolution patterns to a hole layer in a logic area, characterized in that: The method for adding sub-resolution patterns to a hole layer in a logic area according to any one of claims 1 to 9 comprises: A screening module is used to obtain a region to be processed in the hole layer of the logic area, and screen out a plurality of similar environment regions in the region to be processed; A classification module, configured to obtain similarities between the similar environmental regions and place the similar environmental regions into different marking layers; The execution module is used to add sub-resolution graphics to the similar environment areas in the multiple marking layers in sequence according to a preset order, and after completion, supplement the addition of sub-resolution graphics to the entire logic area hole layer.

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