Multiple output fast start limiting circuit

Abstract

The application relates to a multi-output fast-starting limiting-amplitude circuit. The circuit mainly comprises a first-stage circuit and a second-stage circuit. In the first-stage circuit, capacitors C1 and C2 are connected in series through a resistor R1 and are connected between an input voltage VIN1 and the ground. When the VIN1 is instantaneously powered on, the C1 and C2 rapidly respond, the gate voltage of a power tube M7 rapidly rises, and an output OUT1 changes along with the VIN1; when the gate voltage of the M7 reaches a certain value, a diode D1 clamps the gate voltage, and the OUT1 outputs a fixed voltage value. In the second-stage circuit, the current generated by the M7 is transmitted to the subsequent stage through a current mirror, and a diode D2 stabilizes the voltage of a node Y, and an output OUT2 is generated. When the VIN1 is removed and the VIN2 still works, a power tube M14 can maintain the stable output of the OUT1 and the OUT2. The application has the advantages of fast starting, independently adjustable output, compact structure and the like, and can be widely applied to electronic equipment requiring multi-output voltage stabilization.

Description

Technical Field

[0001] This application relates to the field of analog integrated circuit design, and more particularly to the field of power management circuits. Background Technology

[0002] With the continuous development of electronic technology, various complex integrated circuit systems are placing higher demands on power supply circuits. In many applications, such as automotive electronics and industrial control, circuits need to operate under high-voltage environments and require rapid startup and the provision of multiple stable outputs. Traditional power supply circuits, such as linear regulators, suffer from slow startup speeds, unstable output voltages, and difficulty in flexible adjustment, and can no longer meet the needs of modern complex electronic systems.

[0003] To address these issues, various limiting circuits have been proposed. However, existing limiting circuit solutions still have some shortcomings. For example, while some limiting circuits can achieve rapid startup, the stability and reliability of the output voltage are difficult to guarantee; others, although stable in output, have slow startup speeds, affecting the overall system efficiency; and some multi-output limiting circuits have output voltages that are difficult to adjust flexibly, failing to adapt to the needs of different loads.

[0004] Furthermore, limiting circuits operating under high voltage conditions also face the problem of high power consumption. To reduce power consumption, some designs employ complex circuit structures, leading to increased area and cost. How to reduce the power consumption and cost of limiting circuits while ensuring performance is a pressing issue that needs to be addressed. Summary of the Invention

[0005] The purpose of this application is to provide a multi-output fast start-up limiting circuit to solve the problems mentioned in the background art.

[0006] This application discloses a multi-output fast-start limiting circuit, including:

[0007] First-level circuit and second-level circuit, wherein:

[0008] The first stage circuit includes:

[0009] The first capacitor C1 and the second capacitor C2 are connected in series through the first resistor R1, and their two ends are respectively connected to the first input voltage VIN1 and the ground wire avss.

[0010] The first diode D1 has one end connected to the first node X through the first set of back-to-back connected MOS transistors M3-M4, and the other end connected to the ground line avss, which is used to clamp the first node X.

[0011] The first power transistor M7 has its drain connected to the first input voltage VIN1, its gate connected to the first node X, and its source connected to the first output OUT1 through the third set of back-to-back MOS transistors M5-M6.

[0012] The second-stage circuit includes:

[0013] The first current mirror structures M8, M9, and M10 have their sources connected to ground avss. The drain of M8 is connected to the first output OUT1 through the third resistor R3, and the drain of M10 is connected to the second output OUT2.

[0014] The sources of the second current mirror structures M11 and M12 are both connected to the second input voltage VIN2.

[0015] The second diode D2 has its anode connected to the fourth node Y and its cathode connected to the ground wire avss, and is used to clamp the fourth node Y; the second power transistor M13 has its drain connected to the second input voltage VIN2, its gate connected to the fourth node Y, and its source connected to the second output OUT2.

[0016] In a preferred embodiment, the first stage circuit further includes a second set of back-to-back connected MOSFET pairs M1-M2, whose gates are connected to the first input voltage VIN1 through a second resistor R2 to prevent current from flowing back from the first node X to the first input voltage VIN1; wherein the first set of MOSFET pairs M3-M4 is used to simulate the working state of the third set of MOSFET pairs M5-M6.

[0017] In the second-stage circuit:

[0018] In the first current mirror structure, the drain of M9 is connected to the gate and drain of M11 in the second current mirror, and the gates of all three are connected to the second node Vn.

[0019] In the second current mirror structure, the drain of M12 is connected to the fourth node Y, and the gates of both are connected to the third node Vp.

[0020] It also includes a third power transistor M14, whose drain is connected to the second input voltage VIN2, whose gate is connected to the fourth node Y through a low-pass filter composed of the fourth resistor R4 and the third capacitor C5, and whose source is connected to the first output OUT1 through the MOS transistor M15.

[0021] In this circuit, the first capacitor C1 and the second capacitor C2 satisfy the voltage division relationship C1 / (C1+C2)>OUT1 / VIN1. When the first input voltage VIN1 is powered on instantaneously, the first input voltage VIN1 is quickly divided, causing the gate voltage of the first power transistor M7 to rise rapidly. The first output OUT1 follows suit, achieving rapid startup. When the gate voltage of the first power transistor M7 rises to a certain value, the first diode D1 plays a voltage stabilizing role, so that the first output OUT1 outputs a stable fixed voltage value. The current generated by the operation of the first power transistor M7 is provided to the second stage circuit through the first and second current mirror structures. It is also regulated by the second diode D2, so that the second stage circuit outputs the second output OUT2.

[0022] In a preferred embodiment, the stable voltage value of the first output OUT1 approximately satisfies:

[0023] VOUT1≈VD1-Vth,M7

[0024] Where VD1 is the regulated voltage of the first diode D1, and Vth,M7 is the threshold voltage of the first power transistor M7.

[0025] In a preferred embodiment, when the first output OUT1 provides a stable voltage, it provides current to the first current mirror bus M8 through the third resistor R3. The first current mirror structure and the second current mirror structure replicate the current to each branch of the second-stage limiting circuit.

[0026] When the first input voltage VIN1 is removed while the second input voltage VIN2 is still working, the second-stage circuit maintains stable output of the first output OUT1 and the second output OUT2 through the third power transistor M14 and the MOSFET M15, thereby reducing the overall circuit power consumption.

[0027] In a preferred embodiment, the first group of M3-M4, the second group of M1-M2, and the third group of M5-M6 MOS transistor pairs are all connected back-to-back to block reverse current and prevent current backflow.

[0028] In a preferred embodiment, when the first input voltage VIN1 and the second input voltage VIN2 are connected to the same voltage source, the stable voltage value of the second output OUT2 can be made different from that of the first output OUT1 by adjusting the size of the second power transistor M13.

[0029] When the second input voltage VIN2 signal is slower than the first input voltage VIN1, the signal establishment time of the second output OUT2 can differ from that of the first output OUT1, providing more flexible options for subsequent devices.

[0030] In summary, the multi-output fast-start limiting circuit proposed in this application has the following beneficial effects:

[0031] Fast startup speed: The first capacitor C1 and the second capacitor C2 respond quickly to the instantaneous change of the first input voltage VIN1. By satisfying the voltage division relationship of C1 / (C1+C2)>OUT1 / VIN1, the voltage of the first node X rises rapidly, the first power transistor M7 is turned on immediately, and the first output OUT1 is established quickly, thereby significantly improving the startup speed of the circuit.

[0032] Stable and reliable output: The first diode D1 and the second diode D2 clamp the first node X and the fourth node Y respectively, ensuring that the first output OUT1 and the second output OUT2 are stable at the required fixed voltage values. At the same time, the three sets of back-to-back connected MOSFETs M1-M2, M3-M4, and M5-M6 effectively prevent current backflow. Among them, the first set of M3-M4 simulates the working state of the third set of M5-M6, minimizing its impact on OUT1.

[0033] Multiple outputs are flexible and adjustable: The current is copied from the first stage to the second stage through the first current mirror structure M8-M9-M10 and the second current mirror structure M11-M12. Combined with different connection methods of the first input voltage VIN1 and the second input voltage VIN2, the voltage difference or settling time difference between the second output OUT2 and the first output OUT1 can be realized, providing more flexible options for subsequent circuits. At the same time, there is no need to design a separate limiting circuit for each output, which simplifies the design.

[0034] Low power consumption: When the first input voltage VIN1 is disconnected, the RC filter (including R4 and C5) of the third power transistor M14 and its gate can continue to maintain the stability of the first output OUT1 and the second output OUT2, effectively reducing the overall circuit power consumption.

[0035] Wide range of applications: This application proposes a simple and efficient technical solution for the actual needs of limiting circuits under high voltage environment. It can be widely used in various high voltage and multi-output occasions and has significant practical value.

[0036] In summary, this application, through the ingenious combination of technologies such as capacitor voltage division, diode clamping, power transistor control, and current mirror, breaks through the limitations of traditional limiting circuits and achieves advantages such as fast start-up, stable output, multi-channel adjustability, and low power consumption, providing an excellent solution for power management under high-voltage environments.

[0037] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which are considered to have been described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0038] Figure 1 This is an overall circuit diagram of a fast-start limiting circuit for multiple outputs according to an embodiment of this application.

[0039] Figure 2 This is a schematic diagram of a common limiting circuit in existing technology.

[0040] Figure 3 This is a schematic diagram showing the current flow of the multi-output fast-start limiting circuit in operation, according to an embodiment of this application. Detailed Implementation

[0041] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0042] Explanation of some concepts:

[0043] Clipper circuit: A clamping circuit is a circuit used to limit an input signal to a specific voltage range. It is commonly used in power management and signal processing to prevent signals from exceeding safe limits.

[0044] MOS transistors (metal-oxide-semiconductor field-effect transistors) are commonly used semiconductor devices widely applied in integrated circuits. The MOS transistors used in this application include both NMOS and PMOS types.

[0045] Current mirror: A circuit structure that uses the characteristics of a transistor to accurately replicate the current of one branch to one or more other branches, for precise current distribution and control.

[0046] Back-to-back connection: A structure in which two MOS transistors are connected back to back, that is, the sources of the two transistors are connected together, forming bidirectional control of the current.

[0047] Clamping: A technique that limits voltage to a specific range using a specific component (such as a diode). In this invention, diodes D1 and D2 clamp nodes X and Y respectively to ensure the stability of the output voltage.

[0048] Power transistor: A transistor used to handle larger power or current. In this application, M7, M13 and M14 are used as power transistors to control the output current.

[0049] The following is a brief summary of some of the innovative aspects of this application:

[0050] In summary, this application proposes a creative solution to address the technical shortcomings of complex integrated circuits requiring rapid startup and multiple outputs in high-voltage power supply environments. Based on the principle of capacitor voltage division, this application cleverly introduces a first capacitor C1 and a second capacitor C2, enabling them to respond rapidly to instantaneous changes in the first input voltage VIN1. By precisely satisfying the critical voltage division relationship C1 / (C1+C2)>OUT1 / VIN1, the voltage at the first node X is driven to rise rapidly to the threshold required for the first power transistor M7 to conduct, thereby driving the first output OUT1 to achieve high-speed establishment. This effectively solves the problem of slow startup speed in existing limiting circuits.

[0051] Meanwhile, this application achieves flexible control of multiple outputs through a streamlined yet innovative two-stage circuit architecture. In the first-stage circuit, the first diode D1, through a clever clamping action, works in conjunction with three sets of back-to-back connected MOSFETs (M1-M2, M3-M4, M5-M6) to precisely regulate the current, ensuring that the first output OUT1 remains stable at a voltage value conforming to the relationship VOUT1≈VD1-Vth,M7. Specifically, the first set of MOSFETs (M3-M4) simulates the operating state of the third set of MOSFETs (M5-M6), minimizing the impact on the first output OUT1 and highlighting the inventor's unique design concept for circuit stability. Building upon this, the introduction of the first current mirror structure (M8-M9-M10) and the second current mirror structure (M11-M12) in the second-stage circuit acts like a precise current distribution network, accurately replicating and transmitting the current generated by the first-stage circuit to each branch of the second stage. By precisely designing the dimensions of the second power transistor M13 and using the clamping effect of the second diode D2 on the fourth node Y, differentiated control of the second output OUT2 and the first output OUT1 is achieved, providing ample flexibility for the selection of interfaces in subsequent circuits. Particularly ingenious is the collaborative mechanism constructed in this application between the third power transistor M14 and the low-pass filter composed of the fourth resistor R4 and the third capacitor C5. Even when the first input voltage VIN1 is disconnected while the second input voltage VIN2 is maintained, both outputs can be continuously maintained, effectively reducing the overall circuit power consumption.

[0052] In summary, the series of technical features adopted in this application are interconnected and indispensable, collectively forming a highly integrated, fast-starting, and flexibly controllable limiting circuit. Its perfect fusion of multiple technologies, including capacitor voltage division, diode clamping, power transistor control, and current mirror, presents a unique technical concept and innovative path. It not only breaks through the inherent limitations of traditional limiting circuits but also provides a practical solution for the actual needs of high-voltage environments. This application achieves a qualitative leap in startup speed, output stability, multi-output flexibility, and power consumption control, and significantly reduces chip area and cost through a compact structural design.

[0053] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0054] In this application's specification, to make the description clearer and more concise, some technical features are represented using English letter codes. It should be clarified that the technical features represented solely by letter codes in this application have the same meaning as the corresponding technical features represented by their Chinese names plus letter codes. For example, "VIN1" and "first input voltage VIN1" refer to the same technical feature, and "OUT1" and "first output OUT1" refer to the same technical feature. Other similar technical features represented by English letter codes are also equivalent to their corresponding technical features represented by their Chinese names plus letter codes. When reading and understanding this application, please treat the technical features represented solely by letter codes as equivalent to their corresponding technical features represented by their Chinese names plus letter codes. The technical features involving English letter codes include, but are not limited to:

[0055] I. Power Supply and Output Signals:

[0056] First input voltage: VIN1

[0057] Second input voltage: VIN2

[0058] First output: OUT1

[0059] Second output: OUT2

[0060] II. Voltage Regulators:

[0061] First diode (for voltage regulation): D1

[0062] Second diode (for voltage regulation): D2

[0063] III. Power transistors:

[0064] First power transistor: M7

[0065] Second power transistor: M13

[0066] Third power transistor: M14

[0067] IV. Capacitors:

[0068] First capacitor: C1

[0069] Second capacitor: C2

[0070] Third capacitor: C5

[0071] V. Resistors:

[0072] First resistor: R1 (current limiting)

[0073] Second resistor: R2 (voltage divider)

[0074] Third resistor: R3 (controls the power consumption of the second-stage circuit)

[0075] Fourth resistor: R4 (low-pass filter)

[0076] VI. Voltage Node / Control Node:

[0077] First node: X

[0078] Fourth node: Y

[0079] Second node (current mirror node): Vn

[0080] Third node (current mirror node): Vp

[0081] VII. MOS Transistor:

[0082] Transistors 1 to 6: M1-M6 (as part of three back-to-back connection structures)

[0083] Seventh transistor (first power transistor): M7

[0084] Fifteenth transistor: M15

[0085] Eighth transistor: M8 (first current mirror structure)

[0086] Ninth transistor: M9 (first current mirror structure)

[0087] Tenth transistor: M10 (first current mirror structure)

[0088] Eleventh transistor: M11 (second current mirror structure)

[0089] Twelfth transistor: M12 (second current mirror structure)

[0090] Thirteenth transistor (second power transistor): M13

[0091] Fourteenth transistor (third power transistor): M14

[0092] Fifteenth transistor: M15

[0093] VIII. Combined Structure Modules (Functional Combinations):

[0094] The second pair of MOSFETs connected back-to-back: M1-M2

[0095] The first pair of MOSFETs connected back-to-back: M3-M4

[0096] The third group of back-to-back connected MOSFET pairs: M5-M6

[0097] First current mirror structure: M8-M9-M10

[0098] Second current mirror structure: M11-M12

[0099] IX. Filter Structure:

[0100] Low-pass filter (composed of R4 and C5): LPF

[0101] The first embodiment of this application relates to a multi-output fast-start limiting circuit, the structure of which is as follows: Figure 1 As shown, it includes:

[0102] First-level circuit and second-level circuit, wherein:

[0103] The first stage circuit includes:

[0104] The first capacitor C1 and the second capacitor C2 are connected in series through the first resistor R1, and their two ends are respectively connected to the first input voltage VIN1 and the ground wire avss.

[0105] The first diode D1 has one end connected to the first node X through the first set of back-to-back connected MOS transistors M3-M4, and the other end connected to the ground line avss, which is used to clamp the first node X.

[0106] The first power transistor M7 has its drain connected to the first input voltage VIN1, its gate connected to the first node X, and its source connected to the first output OUT1 through the third set of back-to-back MOS transistors M5-M6.

[0107] The second-stage circuit includes:

[0108] The first current mirror structures M8, M9, and M10 have their sources connected to ground avss. The drain of M8 is connected to the first output OUT1 through the third resistor R3, and the drain of M10 is connected to the second output OUT2.

[0109] The sources of the second current mirror structures M11 and M12 are both connected to the second input voltage VIN2.

[0110] The second diode D2 has its anode connected to the fourth node Y and its cathode connected to the ground wire avss, and is used to clamp the fourth node Y; the second power transistor M13 has its drain connected to the second input voltage VIN2, its gate connected to the fourth node Y, and its source connected to the second output OUT2.

[0111] Optionally, the first stage circuit also includes a second set of back-to-back connected MOSFET pairs M1-M2, whose gates are connected to the first input voltage VIN1 through a second resistor R2 to prevent current from flowing back from the first node X to the first input voltage VIN1; wherein the first set of MOSFET pairs M3-M4 is used to simulate the working state of the third set of MOSFET pairs M5-M6.

[0112] In the second-stage circuit:

[0113] In the first current mirror structure, the drain of M9 is connected to the gate and drain of M11 in the second current mirror, and the gates of all three are connected to the second node Vn.

[0114] In the second current mirror structure, the drain of M12 is connected to the fourth node Y, and the gates of both are connected to the third node Vp.

[0115] It also includes a third power transistor M14, whose drain is connected to the second input voltage VIN2, whose gate is connected to the fourth node Y through a low-pass filter composed of the fourth resistor R4 and the third capacitor C5, and whose source is connected to the first output OUT1 through the MOS transistor M15.

[0116] In this circuit, the first capacitor C1 and the second capacitor C2 satisfy the voltage division relationship C1 / (C1+C2)>OUT1 / VIN1. When the first input voltage VIN1 is powered on instantaneously, the first input voltage VIN1 is quickly divided, causing the gate voltage of the first power transistor M7 to rise rapidly. The first output OUT1 follows suit, achieving rapid startup. When the gate voltage of the first power transistor M7 rises to a certain value, the first diode D1 plays a voltage stabilizing role, so that the first output OUT1 outputs a stable fixed voltage value. The current generated by the operation of the first power transistor M7 is provided to the second stage circuit through the first and second current mirror structures. It is also regulated by the second diode D2, so that the second stage circuit outputs the second output OUT2.

[0117] Optionally, the stable voltage value of the first output OUT1 approximately satisfies:

[0118] VOUT1≈VD1-Vth,M7

[0119] Where VD1 is the regulated voltage of the first diode D1, and Vth,M7 is the threshold voltage of the first power transistor M7.

[0120] Optionally, when the first output OUT1 provides a stable voltage, it provides current to the first current mirror bus M8 through the third resistor R3. The first current mirror structure and the second current mirror structure replicate the current to each branch of the second-stage limiting circuit.

[0121] When the first input voltage VIN1 is removed while the second input voltage VIN2 is still working, the second-stage circuit maintains stable output of the first output OUT1 and the second output OUT2 through the third power transistor M14 and the MOSFET M15, thereby reducing the overall circuit power consumption.

[0122] Optionally, the first group of M3-M4, the second group of M1-M2, and the third group of M5-M6 MOS transistor pairs all adopt a back-to-back connection structure to block reverse current and prevent current backflow.

[0123] Optionally, when the first input voltage VIN1 and the second input voltage VIN2 are connected to the same voltage source, the stable voltage value of the second output OUT2 can be made different from that of the first output OUT1 by adjusting the size of the second power transistor M13.

[0124] When the second input voltage VIN2 signal is slower than the first input voltage VIN1, the signal establishment time of the second output OUT2 can differ from that of the first output OUT1, providing more flexible options for subsequent devices.

[0125] To make the technical solution of the present invention clearer and more understandable, it is now combined with Figures 1 to 3 Preferred embodiments of the present invention will be described in detail, but it should be understood that the described embodiments are merely exemplary and not restrictive.

[0126] like Figure 1As shown, the limiting circuit in this embodiment adopts a two-stage structure design, including a first-stage circuit Stage-I and a second-stage circuit Stage-II connected in series. The first-stage circuit mainly realizes the fast start-up function, and the second-stage circuit realizes the multi-output function through a current mirror structure. The first-stage circuit includes: a first capacitor C1 and a second capacitor C2 connected in series through a first resistor R1, with their two ends connected to the first input voltage VIN1 and the ground avss, respectively; a first diode D1, one end of which is connected to the first node X through a first set of back-to-back connected MOSFET pairs M3-M4, and the other end is connected to the ground avss; a second set of back-to-back connected MOSFET pairs M1-M2, the gate of which is connected to the first input voltage VIN1 through a second resistor R2; a first power transistor M7, the drain of which is connected to the first input voltage VIN1, the gate of which is connected to the first node X, and the source of which is connected to the first output OUT1 through a third set of back-to-back connected MOSFET pairs M5-M6. The second-stage circuit includes: first current mirror structures M8, M9, and M10, wherein the drain of M8 is connected to the first output OUT1 through the third resistor R3, the drain of M9 is connected to the gate and drain of M11 in the second current mirror, and the drain of M10 is connected to the second output OUT2. The sources of all three are connected to ground avss, and the gates of all three are connected to the second node Vn; second current mirror structures M11 and M12, wherein the drain of M11 is connected to the drain of M9, the drain of M12 is connected to the fourth node Y, the sources of both are connected to the second input voltage VIN2, and the gates of both are connected to the third node Vp; second diode D2, whose anode is connected to the fourth node Y and whose cathode is connected to ground avss; second power transistor M13, whose drain is connected to the second input voltage VIN2, whose gate is connected to the fourth node Y, and whose source is connected to the second output OUT2; third power transistor M14, whose drain is connected to the second input voltage VIN2, whose gate is connected to the fourth node Y through a low-pass filter composed of the fourth resistor R4 and the third capacitor C5, and whose source is connected to the first output OUT1 through a MOSFET M15. The first current mirror structures M8, M9, and M10, and the second current mirror structures M11 and M12 form a current replication network, replicating the current generated by the first-stage circuit into each branch of the second-stage circuit. In the above circuit structure, the three sets of MOSFETs M1-M2, M3-M4, and M5-M6 are all connected back-to-back. The first set of M3-M4 is used to simulate the working state of the third set of M5-M6, minimizing the impact of M5-M6 on the first output OUT1; the third set of M5-M6 is located between the source of the first power transistor M7 and the first output OUT1 to prevent current backflow; the second set of M1-M2 is located between the second resistor R2 and the first input voltage VIN1 to prevent current from flowing back from the first node X to VIN1.It should be noted that the parameter settings and specific connection methods of each device in the circuit of this embodiment can be adjusted according to actual application requirements to achieve different output characteristics. For example, by adjusting the size of the second power transistor M13, the stable voltage value of the second output OUT2 can be made different from that of the first output OUT1; if the second input voltage VIN2 signal is slower than the first input voltage VIN1, the signal settling time of the second output OUT2 can be made different from that of the first output OUT1, providing more flexible options for subsequent circuits.

[0127] Figure 3 This is a schematic diagram showing the current flowing through the circuit during operation of the first-stage circuit in this embodiment.

[0128] like Figure 3 As shown, the operation of the first-stage limiting circuit mainly consists of two stages:

[0129] Phase 1①, when the first input voltage VIN1 is instantaneously powered on, such as Figure 3 As shown by the red arrow, the first capacitor C1 and the second capacitor C2 are sensitive to instantaneously changing power signals. At this time, the capacitor impedance is relatively high, and they perform voltage division, causing the voltage at the first node X to rapidly follow the changes in VIN1 within a short period. When the voltage at the first node X reaches a certain value, the first diode D1 begins to stabilize, and current begins to flow into the branch containing D1, keeping the voltage at the first node X stable. During this stage, the first output OUT1 follows the changes in VIN1 for a short time and reaches a stable voltage value after a period of time, achieving a rapid start-up effect.

[0130] In the second stage ②, after the first input voltage VIN1 stabilizes, as follows: Figure 3 As shown by the green arrow, the current mainly flows through the second resistor R2, the voltage at the first node X is stable, and the first output OUT1 outputs a stable voltage value. At this time, the function of the second capacitor C2 becomes to filter out high-frequency interference at the first node X.

[0131] It should be noted that the capacitance values ​​of the first capacitor C1 and the second capacitor C2 must satisfy the voltage divider relationship: C1 / (C1+C2)>OUT1 / VIN1, where OUT1 is the stable voltage value of the first output and VIN1 is the first input voltage value. When the circuit is operating stably, the stable voltage value of the first output OUT1 approximately satisfies: VOUT1≈VD1-Vth,M7, where VD1 is the regulated voltage value of the first diode D1 and Vth,M7 is the threshold voltage of the first power transistor M7.

[0132] The working principle of the multi-output, fast-start limiting circuit provided in this embodiment is as follows:

[0133] See Figure 1 and Figure 3When the first input voltage VIN1 is instantaneously powered on, the first capacitor C1 and the second capacitor C2 are sensitive to the instantaneously changing power signal. At this time, the capacitor impedance is relatively large and performs voltage division, causing the voltage at the first node X to quickly follow the change of VIN1 within a short period of time. At the same time, the gate voltage of the first power transistor M7 also rises rapidly, and the first output OUT1 follows the change of the gate voltage of the first power transistor M7, realizing rapid startup.

[0134] When the voltage at the first node X rises to the regulated voltage of the first diode D1, D1 clamps the voltage, stabilizing the voltage at the regulated value of D1. At this time, the first output OUT1 also outputs a relatively stable fixed voltage value. This voltage value is mainly determined by the regulated voltage VD1 of the first diode D1 and the threshold voltage Vth of the first power transistor M7, approximately satisfying: VOUT1≈VD1-Vth,M7.

[0135] Once the first input voltage VIN1 stabilizes, the current mainly flows to the first node X through the second resistor R2. Under the clamping effect of the first diode D1, the first output OUT1 continuously outputs a stable fixed voltage. Simultaneously, the function of the second capacitor C2 becomes filtering out high-frequency interference at the first node X.

[0136] It should be noted that, to ensure rapid startup, the first capacitor C1 and the second capacitor C2 must satisfy a suitable voltage division relationship, i.e., C1 / (C1+C2)>OUT1 / VIN1. This relationship ensures that when power is applied instantaneously at VIN1, the gate voltage of the first power transistor M7 can quickly rise to a level that turns M7 on. Furthermore, the three back-to-back connected MOSFET pairs—the second group M1-M2, the first group M3-M4, and the third group M5-M6—adopt a reverse current blocking structure, effectively preventing current backflow. The similar connection methods of the first group M3-M4 and the third group M5-M6 minimize the impact of the third group M5-M6 on the first output OUT1.

[0137] The current from the first output OUT1 passes through the third resistor R3 and the current mirror bus M8, and is replicated to the various branches of the second-stage circuit by the first current mirror structures M8, M9, and M10 and the second current mirror structures M11 and M12. Under the voltage regulation of the second diode D2, the second output OUT2 also outputs a relatively independent and adjustable stable voltage.

[0138] It is worth mentioning that different output characteristics can be achieved by reasonably setting the connection method and signal timing of the first input voltage VIN1 and the second input voltage VIN2. For example, when VIN1 and VIN2 are connected to the same voltage source, the stable voltage values ​​of OUT2 and OUT1 can be different by adjusting the size of the second power transistor M13; if the VIN2 signal is slower than VIN1, the settling time of OUT2 can be different from that of OUT1, providing more flexible options for subsequent circuits.

[0139] Furthermore, with VIN1 disconnected, the third power transistor M14 and its gate RC filter (including R4 and C5) can continue to maintain stable output of OUT1 and OUT2, thereby effectively reducing the power consumption of the overall circuit.

[0140] To better understand the technical solution of this application, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0141] This example provides a fast-start limiting circuit with multiple outputs, such as... Figure 1 As shown, the circuit includes:

[0142] The power transistor M7 has its drain connected to the input power supply voltage point VIN1, its source connected to the output OUT1 through transistors M5-M6, and its gate connected to the Zener point X of diode D1.

[0143] The power transistor M14 has its drain connected to the input power supply voltage point VIN2, its source connected to the output OUT1 through M15, and its gate connected to the Zener point Y of diode D2 through a low-pass filter composed of resistor R4 and capacitor C5.

[0144] The power transistor M13 has its drain connected to the input power supply voltage point VIN2, its source connected to the output OUT2, and its gate connected to the Zener voltage point Y of diode D2.

[0145] Capacitors C1 and C2 are connected in series through a current-limiting resistor R1, and their other two ends are connected to the input power supply voltage point VIN1 and the ground wire avss, respectively.

[0146] High-voltage resistor R2 has one end connected to the input power supply voltage point VIN1 and the other end connected to the gate of transistors M1-M2.

[0147] Diode D1 has one end connected to the Zener point X through transistors M3-M4, and the other end connected to ground avss;

[0148] Diode D2 has one end connected to the Zener point Y and the other end connected to ground avss;

[0149] The current mirror structure M8-M9-M10 has its source connected to ground avss and its gate connected to voltage Vn. The drain of M8 is connected to the output OUT1 through resistor R3, the drain of M9 is connected to the gate and drain of the mother tube M11 in another current mirror structure, and the drain of M10 is connected to the output OUT2.

[0150] The current mirror structures M11-M12 have their sources connected to the input power supply voltage point VIN2 and their gates connected to the voltage Vp. The drain of M11 is connected to the drain of M9 in another current mirror structure, and the drain of M12 is connected to the regulated point Y.

[0151] The working principle and steps of this example are as follows:

[0152] When VIN1 is momentarily powered on, capacitors C1 and C2 respond quickly, causing the gate voltage Vx of transistor M7 to rise rapidly. Output OUT1 follows the changes in VIN1, thus achieving rapid startup. When voltage Vx rises to a certain value, diode D1 acts as a voltage regulator, clamping Vx and resulting in a fixed output voltage value for OUT1. When VIN1 stabilizes, OUT1 maintains a fixed output voltage. Simultaneously, the current generated by the power transistor flows through a current mirror to power the next stage circuit, ultimately outputting OUT2.

[0153] It should be noted that the input and output pins include the first-stage power supply VIN1, the second-stage power supply VIN2, the first-stage limiting circuit output OUT1, and the second-stage limiting circuit output OUT2.

[0154] The first-stage limiting circuit consists of capacitors C1, C2, and C3, resistors R1, R2, and R3, diode D1, and MOS transistors M1 to M7. Specifically:

[0155] The main function of capacitors C1 and C2 is to divide the transient voltage when the power supply VIN1 is instantly powered on, according to the capacitance impedance relationship (1):

[0156] X C =1 / ωC (1)

[0157] In the formula, X C ω is the capacitive reactance that impedes the current during the transient change of VIN1, and C is the capacitance value.

[0158] Resistor R1 is used to limit the current in its branch, reduce power consumption, and protect C1 and C2. The resistance of R1 is very small and can be ignored when calculating the impedance. To ensure that the capacitor voltage divider satisfies the relationship between VIN1 and OUT1, equation (2) is:

[0159]

[0160] In the formula, Xc1 is the capacitive reactance of the first capacitor (C1), and Xc2 is the capacitive reactance of the second capacitor (C2).

[0161] Substituting equation (1) into equation (2), we obtain equation (3) relating the capacitance value to VIN1 and OUT1:

[0162]

[0163] In the formula, C1 refers to the first capacitor, which is connected between the first node (X) and the first resistor (R1), and C2 refers to the second capacitor, which is connected between the ground wire (avss) and the first resistor (R1).

[0164] The high-voltage resistor R2 acts as a voltage divider when VIN1 is stable. Diode D1 is reverse-connected to form a Zener diode, ensuring the gate voltage of M7 is stable, and is one of the core modules of the clipper. M1-M2, M3-M4, and M5-M6 are all back-to-back connected, but their functions are slightly different: M1-M2 and M5-M6 prevent current backflow from affecting the power supply and output; M3-M4 simulates the working state of M5-M6, minimizing its impact on OUT1. M7 is the main power transistor, and the relationship between the stable voltage of OUT1 and the circuit components satisfies equation (4):

[0165] V OUT1 ≈V D1 -V th,M7 (4)

[0166] Where VD1 is the regulated voltage of D1, and Vth,M7 is the threshold voltage of M7. Although there are M3-M4 and M5-M6 between D1 and OUT1, their influence can be approximated because the operating states and voltages of the two groups of transistors are similar.

[0167] The second-stage clipping circuit includes filter capacitors C4 and C5, diode D2, and MOS transistors M8 to M15. It can be seen that during normal operation, the second-stage clipping circuit relies on the output OUT1 of the first-stage clipping circuit for current. Specifically, when OUT1 has a stable voltage, current flows through resistor R3 and the current mirror bus M8, and then is replicated to the branches of the second-stage clipper by two sets of current mirrors M8-M9-M10 and M11-M12. This results in a significantly slower settling time for the second-stage output OUT2 compared to the first-stage output.

[0168] While this design cannot achieve the same rapid startup as the first-stage limiting circuit, it offers unique advantages. It reduces the overall circuit area and lowers component costs while meeting diverse needs in more complex environments. If VIN2 and VIN1 are connected to the same voltage source, the stable voltage values ​​of OUT2 and OUT1 can be differentiated by adjusting the size of M13; if the VIN2 signal is slower than VIN1, the signal settling times of OUT2 and OUT1 can differ, providing more flexible options for subsequent components.

[0169] It is worth noting that the low-pass filter formed by resistor R4 and capacitor C5 is connected to the gate of M14, allowing the second-stage clipper circuit to also output from OUT1. This ensures that even when VIN1 stops working, the second-stage clipper can still maintain the outputs of OUT1 and OUT2, reducing overall power consumption without changing the output.

[0170] Furthermore, the operation of the first-stage limiting circuit can be divided into two stages:

[0171] Phase 1, such as Figure 3 As shown in ①, when VIN1 is instantaneously powered on, the capacitor branch is sensitive to transient signals. At this time, the capacitor impedance is relatively large and performs voltage division, causing the node X voltage to rapidly follow the changes in VIN1 within a short period of time. When the node X voltage reaches a certain value, diode D1 acts as a voltage regulator, and current begins to flow into the D1 branch, keeping the node X voltage stable. During this stage, OUT1 follows the changes in VIN1 for a short period of time and reaches a stable voltage value after a period of time, achieving rapid startup.

[0172] Phase Two, such as Figure 3 As shown in Figure ②, when VIN1 is stable, the current mainly flows through the high-voltage resistor R1, the voltage at node X is stable, and the output OUT2 also stabilizes accordingly. At this time, the function of capacitor C2 becomes to filter out high-frequency interference at node X.

[0173] The second-stage limiting circuit maintains its normal operation by replicating the branch current of the first-stage clipper through a current mirror, thus its startup time is relatively slow. Once the current mirror current is established, OUT2 can output relatively independently. When the VIN1 signal is removed but the VIN2 signal still exists, M14 can maintain the output of OUT1, thereby ensuring the normal operation of the second-stage limiting circuit.

[0174] In summary, this example uses a capacitor-divided voltage supply, which enables rapid startup, shortens output settling time, and improves operating efficiency; it eliminates the need for multiple limiting circuits to achieve multiple outputs, enhancing circuit flexibility and reducing the required area; and it can maintain output under specific conditions, reducing circuit power consumption.

[0175] The above embodiments have the following technical effects:

[0176] Fast startup speed: The first capacitor C1 and the second capacitor C2 respond quickly to the instantaneous change of the first input voltage VIN1. By satisfying the voltage division relationship of C1 / (C1+C2)>OUT1 / VIN1, the voltage of the first node X rises rapidly, the first power transistor M7 is turned on immediately, and the first output OUT1 is established quickly, thereby significantly improving the startup speed of the circuit.

[0177] Stable and reliable output: The first diode D1 and the second diode D2 clamp the first node X and the fourth node Y respectively, ensuring that the first output OUT1 and the second output OUT2 are stable at the required fixed voltage values. At the same time, the three sets of back-to-back connected MOSFETs M1-M2, M3-M4, and M5-M6 effectively prevent current backflow. Among them, the first set of M3-M4 simulates the working state of the third set of M5-M6, minimizing its impact on OUT1.

[0178] Multiple outputs are flexible and adjustable: The current is copied from the first stage to the second stage through the first current mirror structure M8-M9-M10 and the second current mirror structure M11-M12. Combined with different connection methods of the first input voltage VIN1 and the second input voltage VIN2, the voltage difference or settling time difference between the second output OUT2 and the first output OUT1 can be realized, providing more flexible options for subsequent circuits. At the same time, there is no need to design a separate limiting circuit for each output, which simplifies the design.

[0179] Low power consumption: When the first input voltage VIN1 is disconnected, the RC filter (including R4 and C5) of the third power transistor M14 and its gate can continue to maintain the stability of the first output OUT1 and the second output OUT2, effectively reducing the overall circuit power consumption.

[0180] Wide range of applications: The above embodiments propose a simple and efficient technical solution for the actual needs of limiting circuits under high voltage environment. It can be widely used in various high voltage and multi-output occasions and has significant practical value.

[0181] In summary, the above embodiments, through the ingenious combination of technologies such as capacitor voltage division, diode clamping, power transistor control, and current mirror, overcome the limitations of traditional limiting circuits and achieve advantages such as fast start-up, stable output, multi-channel adjustability, and low power consumption, providing an excellent solution for power management under high-voltage environments.

[0182] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0183] All documents mentioned in this application are considered to be incorporated in their entirety into the disclosure of this application so that they can serve as a basis for modifications if necessary. Furthermore, it should be understood that after reading the foregoing disclosure of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A multi-output fast-start limiting circuit, characterized in that, include: First-level circuit and second-level circuit, wherein: The first stage circuit includes: The first capacitor (C1) and the second capacitor (C2) are connected in series through the first resistor (R1), and their two ends are respectively connected to the first input voltage (VIN1) and the ground wire (avss); The second pair of back-to-back MOSFETs (M1-M2) has its gate connected to the first input voltage (VIN1) through a second resistor (R2) to prevent current from flowing back from the first node (X) to the first input voltage (VIN1). The first diode (D1) has one end connected to the first node (X) through the first set of back-to-back connected MOS transistor pairs (M3-M4), and the other end connected to the ground wire (avss), which is used to clamp the first node (X); The first power transistor (M7) has its drain connected to the first input voltage (VIN1), its gate connected to the first node (X), and its source connected to the first output (OUT1) through a third set of back-to-back MOS transistor pairs (M5-M6). The first pair of MOSFETs (M3-M4) is used to simulate the working state of the third pair of MOSFETs (M5-M6); The second-stage circuit includes: The first current mirror structure includes M8, M9, and M10, wherein the sources of M8, M9, and M10 are all connected to ground (avss), and the gates of M8, M9, and M10 are all connected to the second node (Vn). The drain of M8 is connected to the first output (OUT1) through the third resistor (R3). The drain of M9 is connected to the gate and drain of M11 in the second current mirror structure, and the drain of M10 is connected to the second output (OUT2). The second current mirror structure includes M11 and M12, wherein the sources of M11 and M12 are both connected to the second input voltage (VIN2), the gates of M11 and M12 are both connected to the third node (Vp), and the drain of M12 is connected to the fourth node (Y). The second diode (D2) has its anode connected to the fourth node (Y) and its cathode connected to the ground wire (avss), and is used to clamp the fourth node (Y); The second power transistor (M13) has its drain connected to the second input voltage (VIN2), its gate connected to the fourth node (Y), and its source connected to the second output (OUT2). The third power transistor (M14) has its drain connected to the second input voltage (VIN2), its gate connected to the fourth node (Y) through a low-pass filter composed of the fourth resistor (R4) and the third capacitor (C5), and its source connected to the first output (OUT1) through a MOSFET (M15). In this circuit, the first capacitor (C1) and the second capacitor (C2) satisfy the voltage divider relationship C1 / (C1+C2)>OUT1 / VIN1. When the first input voltage (VIN1) is instantaneously powered on, the first input voltage (VIN1) is rapidly divided, causing the gate voltage of the first power transistor (M7) to rise rapidly, and the first output (OUT1) follows suit, achieving rapid startup. When the gate voltage of the first power transistor (M7) rises to a certain value, the first diode (D1) plays a voltage stabilizing role, so that the first output (OUT1) outputs a stable fixed voltage value. The current generated by the operation of the first power transistor (M7) is provided to the second stage circuit through the first and second current mirror structures, and is also stabilized by the second diode (D2), so that the second stage circuit outputs the second output (OUT2). When the first output (OUT1) provides a stable voltage, it supplies current to the first current mirror bus (M8) through the third resistor (R3). The first current mirror structure and the second current mirror structure replicate the current to each branch of the second-stage limiting circuit. When the first input voltage (VIN1) is removed but the second input voltage (VIN2) is still working, the second-stage circuit maintains the stable output of the first output (OUT1) and the second output (OUT2) through the third power transistor (M14) and the MOSFET (M15), thereby reducing the overall circuit power consumption.

2. The limiting circuit according to claim 1, characterized in that, The stable voltage value of the first output (OUT1) approximately satisfies: in This is the regulated voltage of the first diode (D1). This is the threshold voltage of the first power transistor (M7).

3. The limiting circuit according to claim 1, characterized in that, The first group (M3-M4), the second group (M1-M2), and the third group (M5-M6) of MOS transistors all adopt a back-to-back connection structure to block reverse current and prevent current backflow.

4. The limiting circuit according to claim 1, characterized in that: When the first input voltage (VIN1) and the second input voltage (VIN2) are connected to the same voltage source, the stable voltage value of the second output (OUT2) can be made different from that of the first output (OUT1) by adjusting the size of the second power transistor (M13). When the second input voltage (VIN2) signal is slower than the first input voltage (VIN1), the signal setup time of the second output (OUT2) can differ from that of the first output (OUT1), providing more flexible options for subsequent devices.

Images