Integrated circuit with high-speed clock bypass before reset

Abstract

An integrated circuit with a high-speed clock bypass before reset includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a frequency divider having a frequency divider input and a frequency divider output, the frequency divider input coupled to the PLL clock output; and a bypass logic having a first clock input coupled to the divider output, a second clock input coupled to the reference clock input, a bypass control input, and a bypass logic output coupled to the clock domain input. The bypass logic selectively bypasses the PLL and the frequency divider in response to a bypass control signal triggered by the reset signal. The reset signal also triggers a reset control signal that is delayed relative to the bypass control signal.

Description

[0001] This application is a divisional application of the Chinese invention patent application (application number: 202080097859.2) filed on December 29, 2020 and entitled "Integrated circuit with high-speed clock bypass before reset". Technical Field

[0002] The present application relates to an integrated circuit, and more particularly, to an integrated circuit with a high-speed clock bypass before reset. Background Art

[0003] The proliferation of electronic devices and integrated circuit (IC) technology has led to the commercialization of IC products. As new electronic devices are developed and IC technology advances, new IC products are commercialized. One example of an IC product required for electronic devices is a multimedia or infotainment system-on-chip (SoC).

[0004] In an example infotainment SoC, there are numerous different clock domains and various operating modes to conserve power. Example operating modes include functional mode and low-power mode. Furthermore, the example infotainment SoC offers both full and partial reset options, with partial reset providing lower-frequency clock signals to some of the different clock domains. With synchronous reset mechanisms (e.g., partial reset), many clock domains consume more power during the reset interval than during functional mode. As a result, the SoC's power consumption during the reset interval can be 1.5 to 4 times that of functional mode. This increased power consumption could trigger power failures and / or potentially fail to meet customer specifications for the infotainment SoC. Summary of the Invention

[0005] According to at least one example of the present disclosure, an integrated circuit includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to the divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The integrated circuit also includes reset management logic, the logic including: a controller including a controller input; and delay logic coupled to the controller. The delay logic includes a reset input, a first delay logic output, and a second delay logic output, the reset input being configured to receive a reset signal, the first delay logic output coupled to the bypass control input, and the second delay logic output coupled to the controller input. The reset management logic is configured to: provide a bypass control signal at a first reset output in response to the reset signal; and provide a reset control signal delayed relative to the bypass control signal at a second reset output in response to the reset signal.

[0006] According to at least one example of the present disclosure, an infotainment circuit includes: a first clock domain having a first clock domain input; a second clock domain having a second clock domain input; and clock management logic coupled to the first and second clock domains. The clock management logic includes: a first PLL having a first reference clock input and a first PLL clock output; a first divider having a first divider input and a first divider output, the first divider input coupled to the first PLL clock output; a second PLL having a second reference clock input and a second PLL clock output; a second divider having a second divider input and a second divider output, the second divider input coupled to the second PLL clock output, and the second divider output coupled to the second clock domain input; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to the first divider output, the second clock input coupled to the first reference clock input, and the bypass logic output coupled to the first clock domain input. The infotainment circuit further includes reset management logic having: a controller including a controller input; and delay logic coupled to the controller, the delay logic including a reset input configured to receive a reset signal, a first delay logic output coupled to a bypass control input, and a second delay logic output coupled to the controller input. The reset management logic is configured to: provide a bypass control signal at the first reset output in response to the reset signal; and provide a reset control signal delayed relative to the bypass control signal at the second reset output in response to the reset signal.

[0007] According to at least one example of the present disclosure, a system includes: an infotainment chip; and a peripheral device coupled to the infotainment chip. The infotainment chip includes: a first clock domain having a first clock domain input; a second clock domain having a second clock domain input, the second clock domain including an output pin to the peripheral device; and clock management logic coupled to the first and second clock domains. The clock management logic includes: a first PLL having a first reference clock input and a first PLL clock output; a first divider having a first divider input and a first divider output, the first divider input coupled to the first PLL clock output; a second PLL having a second reference clock input and a second PLL clock output; a second divider having a second divider input and a second divider output, the second divider input coupled to the second PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to the first divider output, the second clock input coupled to the first reference clock input, and the bypass logic output coupled to the first clock domain input. The infotainment chip also includes reset management logic having: a controller including a controller input; and delay logic coupled to the controller, the delay logic including a reset input, a first delay logic output, and a second delay logic output, wherein the reset input is configured to receive a reset signal, the first delay logic output is coupled to a bypass control input, and the second delay logic output is coupled to the controller input. The reset management logic is configured to: provide a bypass control signal at the first reset output in response to the reset signal; and provide a reset control signal delayed relative to the bypass control signal at the second reset output in response to the reset signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] For a detailed description of various examples, reference will now be made to the accompanying drawings, in which:

[0009] Figure 1 is a diagram illustrating a system according to an example embodiment;

[0010] Figure 2 is a flowchart illustrating a partial reset method according to an example embodiment;

[0011] Figure 3 is a diagram illustrating a reset management system according to an example embodiment;

[0012] Figure 4 is a timing diagram illustrating reset management and clock management signals according to an example embodiment;

[0013] Figure 5 is a diagram illustrating a clock management system according to an example embodiment; and

[0014] Figure 6is a table illustrating phase-locked loop (PLL) bypass options for an integrated circuit (IC) according to example embodiments. DETAILED DESCRIPTION

[0015] Described herein is an integrated circuit (IC) with a phase-locked loop (PLL) and frequency divider bypass mechanism that incorporates a delayed partial reset (sometimes referred to as a warm reset). By bypassing the PLL and frequency divider before executing a partial reset, the IC's current level during the partial reset is reduced compared to previous partial reset techniques. Using the described bypass mechanism, the clock frequency provided to at least some of the IC's clock domains is reduced from a functional clock frequency (e.g., in the gigahertz range) to a lower clock frequency (e.g., in the megahertz range). As used herein, "clock domain" refers to one or more components that utilize a specific functional clock frequency provided by a PLL and possibly other components (e.g., frequency dividers). In some example embodiments, the IC includes a first set of clock domains affected by the bypass mechanism and a second set of clock domains not affected by the bypass mechanism. In some example embodiments, staggered bypass control signals are used to bypass the PLL and frequency divider associated with the first set of clock domains in a staggered (multi-stage) manner before initiating a partial reset. During the partial reset, a bypass control shadow value is set in memory. Once the partial reset is complete, the bypass control shadow value in memory is cleared, and the IC resumes normal function.

[0016] In an example embodiment, an IC includes: a clock domain having a clock domain input; and clock management logic coupled to the clock domain. The clock management logic includes: a PLL having a reference clock input and a PLL clock output; a divider having a divider input and a divider output, the divider input coupled to the PLL clock output; and bypass logic having a first clock input, a second clock input, a bypass control input, and a bypass logic output, the first clock input coupled to the divider output, the second clock input coupled to the reference clock input, and the bypass logic output coupled to the clock domain input. The IC also includes reset management logic, including: a controller having a controller input; and delay logic coupled to the controller. The delay logic includes a reset input, a first delay logic output, and a second delay logic output, the reset input being configured to receive a reset signal, the first delay logic output coupled to the bypass control input, and the second delay logic output coupled to the controller input. The reset management logic is configured to: provide a bypass control signal at a first reset output in response to the reset signal; and provide a reset control signal delayed relative to the bypass control signal at a second reset output in response to the reset signal. The described IC uses a PLL combined with a partial reset delay and a divider bypass mechanism to reduce the IC's current level during a partial reset. To provide a better understanding, various IC options and the associated clock management options, reset management options, and system usage are described in the following figure.

[0017] Figure 1 is a diagram illustrating a system 100 according to an example embodiment. In some example embodiments, system 100 is a vehicle having a graphical user interface (GUI) or display. As shown, system 100 includes an infotainment chip 102 coupled to a peripheral device 154. Furthermore, a power supply 160 having a first power output 162 and a second power output 166 is shown in system 100. First power output 162 is coupled to a power input 157 of peripheral device 154 and provides a power supply voltage 164. Meanwhile, second power output 166 is coupled to a power input 170 of infotainment chip 102 and provides a power supply voltage 168. In examples where system 100 is a vehicle, power supply 160 includes a battery, one or more voltage regulators, and / or a current loop.

[0018] like Figure 1 As shown, the infotainment chip 102 includes clock management logic 104 coupled to a first set of clock domains 134 and a second set of clock domains 136. More specifically, the clock management logic 104 includes a first set of PLLs 106, a first set of frequency dividers 112, bypass logic 118, a second set of PLLs 126, and a second set of frequency dividers 130. In operation, the clock management logic 104 controls the clock frequency for each of the first and second clock domains 134, 136. Without limitation, in some embodiments, the first set of PLLs 106 includes a microprocessor (MCU) PLL, an audio subsystem PLL, a video subsystem PLL, an accelerator subsystem PLL, and / or other subsystem PLLs. Furthermore, the second set of PLLs includes one or more peripheral subsystem PLLs, an Ethernet subsystem PLL, and a display subsystem PLL configured to provide limited display functionality (e.g., information display but no video).

[0019] In some example embodiments, each PLL in the first group of PLLs 106 includes a corresponding reference clock input 109 and a corresponding PLL clock output 111, wherein each reference clock input 109 receives the reference clock signal 108, and wherein each PLL clock output 111 provides a corresponding PLL clock signal 110. Furthermore, each divider in the first group of frequency dividers 112 includes a corresponding divider input 113 and a corresponding divider output 115, wherein each divider input 113 in the first group of frequency dividers 112 is coupled to a corresponding PLL clock output 111 in the first group of PLLs 106 and is configured to receive a corresponding PLL clock signal 110. Furthermore, each PLL in the second group of PLLs 126 includes a corresponding reference clock input 127 and a corresponding PLL clock output 129, wherein each reference clock input 127 receives the reference clock signal 108, and wherein each PLL clock output 129 provides a corresponding PLL clock signal 128. Furthermore, each divider in the second set of frequency dividers 126 includes a corresponding divider input 131 and a corresponding divider output 133. Each divider input 131 is coupled to a corresponding PLL clock output 128 in the second set of PLLs 126 and is configured to receive the corresponding PLL clock output 128. Furthermore, each divider output 133 is coupled to a corresponding clock domain input 137 in the second set of clock domains 136 and is configured to provide a corresponding divided PLL clock signal 132 to each clock domain input 137. Figure 1 In an example, the operation of the bypass logic 118 does not affect the second group of clock domains 136. Example clock domains of the second group of clock domains 136 include peripherals 154, a display subsystem, and an Ethernet subsystem.

[0020] In some example embodiments, the second group of clock domains 136 includes a clock output 139 coupled to a clock input 155 of a peripheral device 154, wherein the clock output 139 is configured to forward one or more clock signals 156 to the clock input 155 of the peripheral device 154. In other words, the peripheral device 154 is an external component that is included with the second group of clock domains 136 or receives the same clock signal as one or more clock domains of the second group of clock domains 136.

[0021] exist Figure 1In this example, clock management logic 104 also includes bypass logic 118, having a respective first clock input 119, a respective second clock input 123, a respective bypass control input 125, and a respective bypass logic output 121 for each PLL, and a divider combination associated with first group of PLLs 106 and first group of frequency dividers 112. Each respective first clock input 119 is coupled to a respective frequency divider output 115 and configured to receive a respective divided PLL clock signal 116. Furthermore, each respective second clock input 123 is coupled to a reference clock input 109, and each bypass logic output 121 is coupled to a respective clock domain input 135 of first group of clock domains 134. Furthermore, each respective bypass control input 125 is configured to receive a bypass control signal 120. In operation, bypass logic 118 enables first group of PLLs 106 and first group of frequency dividers 112 to be bypassed. When bypassed, first group of clock domains 134 receive reference clock signal 108 at each respective clock domain input 135. When not bypassed, the first set of clock domains 134 receives a corresponding divided PLL clock signal 116 at each corresponding clock domain input 135. Without limitation to other example embodiments, in some examples, the first set of clock domains 134 includes a microprocessor (MCU), an audio subsystem, a video subsystem, an accelerator subsystem, and / or other subsystems.

[0022] exist Figure 1In the embodiment of the present invention, the infotainment chip 104 further includes reset management logic 140 having a controller 141 including a controller input 152 and delay logic 142 coupled to the controller 141. More specifically, the delay logic 142 includes a reset input 143, a first delay logic output 145, a second delay logic output 147, and a third delay logic output 149. The reset input 143 is configured to receive one or more reset signals or requests 114 provided to the reset management logic 140. The first delay logic output 145 is coupled to at least some of the corresponding bypass control inputs 125 of the bypass logic 118, and the second delay logic output 147 is coupled to the controller input 152. In operation, the reset management logic is configured to provide a bypass control signal 146 at the first reset output 145 in response to the reset signal 114 and to provide a reset control signal 148 delayed relative to the bypass control signal 146 at the second reset output 147 in response to the reset signal 114. In some example embodiments, the third delay logic output 149 is coupled to some of the corresponding bypass control inputs 125 in the bypass logic 118, and the first delay logic output 145 and the third delay logic output 149 are coupled to different subsets of the corresponding bypass control inputs 125. In operation, the reset management logic 140 is configured to provide a first bypass control signal 146 to the first delay logic output 145 and a second bypass control signal 150 to the third delay logic output 149, wherein the second bypass control signal 150 is delayed or staggered relative to the first bypass control signal 146.

[0023] After the bypass process is completed (after the first group of PLLs 106 and the first group of frequency dividers 112 are bypassed), the reset control signal 148 causes the controller 141 to initiate a warm reset. During the warm reset, various warm reset operations are performed according to a conventional warm reset procedure. In some example embodiments, the controller 141 includes a memory 144, wherein the controller 141 is configured to: store a bypass value in the memory 144 in response to the initiation of the warm reset; and clear the bypass value in the memory after the warm reset is completed. Figure 1In the embodiment of the present invention, the controller 141 includes a processor, a computer-readable memory (e.g., memory 144) with instructions and values, and / or other components that perform a warm reset operation. Using the described clock management logic 104 and reset management logic 140, the infotainment chip 102 can respond to a partial reset request by delaying the partial reset request, performing a bypass operation for some clock domains of the infotainment chip 102 (using one or more bypass control signals, such as staggered bypass control signals), initiating a partial reset after the bypass operation is complete, performing the partial reset operation, tracking when a partial reset condition exists or does not exist, and ending the partial reset if the partial reset condition does not exist. Using the described clock management logic 104 and reset management logic 140, the current level of the infotainment chip 102 during a partial reset is reduced compared to previous ICs.

[0024] Figure 2 2 is a flow chart illustrating a partial reset method 200 according to an example embodiment. As shown, the partial reset method 200 includes detecting a partial reset request or signal (WRST, Figure 1 ). At block 204, the propagation of WRST is delayed and two staggered bypass control signals are generated (e.g., Figure 1 At block 206, the bypass control signal is used to bypass (e.g., from Figure 1 At block 208, WRST propagates to the reset controller (e.g., Figure 1 141 in the controller 141), causing a partial reset. At block 210, a new bypass control shadow value (bypass-ctrl-shadow-MMR) is set in memory. At block 212, a change in WRST is detected (e.g., WRST ends at its source or under an associated condition). At block 214, bypassing of the PLL and HSDIV clocks continues. At block 216, the IC is released from the partial reset associated with the WRST detected at block 202. At block 218, the bypass control shadow value is cleared from memory. The partial reset method 200 is repeated as needed for ICs with different WRST sources. Example WRST sources for an IC (e.g., infotainment chip 102) include master reset logic, device management logic, voltage thermal manager, and debug logic.

[0025] Figure 3 is a diagram illustrating a reset management system 300 according to an example embodiment. Figure 3 , the reset management system 300 includes a reset management logic 301 (eg, Figure 1Reset sources 302, 304, 306, and 307 (part of the reset management logic 140 in FIG) are shown. More specifically, reset source 302 is the master reset logic configured to receive reset requests (e.g., mcu_porz, RESET_REQz, SW_MAIN_WARMRESETz, mcu_resetz_final, CLK_12RC, MAIN_PLLCRTL_1_RST_n). As shown, SW_MAIN_WARMRESETz is an inverted signal based on another signal (SW_MAIN_WARMRESET) passing through inverter 303. In response to one or more reset requests, master reset logic 302 outputs a reset signal (main_resetz). Reset source 304 is a device manager configured to assert a partial reset signal (warm_reset) in response to a request or condition. Reset source 306 is a thermal manager 306 configured to assert a reset signal (maxtemp_alert) in response to an overtemperature condition. Reset source 308 is debug logic configured to assert a reset signal (reset_n) in response to a debug option of the IC.

[0026] As shown, the reset management logic 301 includes delay blocks 312, 314, 316, 318 coupled to respective reset sources 302, 304, 306, and 308 and configured to receive reset signals (e.g., main_resetz, warm_reset, maxtemp_alert, and reset_n). The outputs of the delay blocks 312, 314, 316, and 318 are provided to a reset controller (e.g., Figure 1 During this delay, reset signals (eg, main_resetz, warm_reset, maxtemp_alert, and reset_n) are input to a controller configured to provide a bypass control signal ("force_main_pll_bypass," Figure 1 In some example embodiments, the reset management logic 301 further includes a delay block 322 after the gate 320, wherein the delay block 322 is configured to provide the bypass control signal (“force_main_pll_bypass_dly”, Figure 1). In some example embodiments, force_main_pll_bypass is used to bypass some PLLs and dividers associated with the first group of PLLs 106 and the first group of frequency dividers 112. In one example, force_main_pll_bypass is used to bypass all PLLs and dividers associated with the first group of PLLs 106 and the first group of frequency dividers 112, except for the main PLL (MAIN_PLL0) and the partial reset isolated PLL. After a delay, force_main_pll_bypass_dly is used to bypass the main PLL and associated dividers, where the bypass operations of force_main_pll_bypass and force_main_pll_bypass_dly are interleaved and occur before the partial reset controller is triggered by the delayed reset signal.

[0027] Figure 4 FIG4 is a diagram 400 illustrating a timing diagram of reset management and clock management signals according to an example embodiment. Figure 4 In the example, signals are shown for the reference clock signal (CLK_12M_RC), main_resertz, force_main_pll_bypass, force_main_pll_bypass_dly, main_resertz_dly, chip_rst (e.g., from a reset controller such as Figure 1 controller 114 in the main_pll_bypass_warmrst [n] (MMR bit reset on mod_g_rst_n), main_pll_extbypass(n) (MMR bit reset on mod_por_rst_n), MAIN_PLL(n)_HSDIV, and MAIN PLL0_HSDIVs. Figure 4As shown, CLK_12M_RC maintains a given clock frequency over time, while MAIN PLL0_HSDIVs through MAIN PLL(n)_HSDIVs vary over time according to the bypass operations described herein. More specifically, main_resetz is deasserted at time t1. Once main_resetz is deasserted, force_main_pll_bypass is asserted to enable bypass operation for selected PLLs (e.g., processor, accelerator, non-reset isolator PLLs) starting at time t2. This bypass operation bypasses the PLLs and any associated dividers to reduce MAIN_PLL[n]_HSDIVs from the functional clock frequency to a lower clock frequency. At time t3, force_main_pll_bypass_dly is asserted to initiate bypass operation for the remaining selected PLLs (e.g., main PLL and associated dividers) to reduce MAIN_PLL0_HSDIVs from the functional clock frequency to a lower clock frequency, as described herein. At time t4, main_resetz_dly is deasserted, main_pll_bypass_warmrst[n] is asserted, and a partial reset (e.g., warm reset) is initiated. Additionally, chip_rst is deasserted at time t4. At time t5, main_resetz is asserted and force_main_pll_bypass is deasserted. At time t6, force_main_pll_bypass_dly is deasserted. At time t7, main_resetz_dly and chip_rst are asserted. At time t8, software disables bypass operation, causing MAIN_PLL[n]_HSDIVs and MAIN_PLL0_HSDIVs to return to their functional clock frequencies at t9.

[0028] Figure 5 1 is a diagram illustrating a clock management system 500 according to an example embodiment. As shown, the clock management system 500 includes a clock management logic 104A ( Figure 1 104 ) and a PLL memory mapped register (MMR) controller 502 and a PLL spread spectrum modulator (SSMOD) 504 (labeled “PLL[m]_SSMOD”). Figure 5, a PLL MMR controller 502 provides a first control signal 505 to a control input ("PLL_CONTROLS") of a PLL 106A (labeled "PLL[m]") to enable or disable the PLL 106A. Additionally, a PLL SSMOD 504 provides a second control signal 507 to a control input ("FBDIV[11:0]") of the PLL 106A to adjust the feedback divider value based on the SSMOD operation.

[0029] exist Figure 5 In the example of FIG. 1 , clock management logic 104A includes PLL 106A and a plurality of divider blocks 510A-510N, wherein each of divider blocks 510A-510N includes a respective divider 112A-112N and a respective bypass circuitry 512A-512N (the combined bypass circuitry 512A-512N is Figure 1 18). As shown, each of the bypass circuit systems 512A-512N includes a corresponding multiplexer 518A-518N, a corresponding OR gate 516A-516N, and a corresponding AND gate 514A-514N. In addition, each of the bypass circuit systems 512A-512N is connected to an OR gate 508, which provides an external bypass control signal (EXTBYPASS). As shown, the inputs to the OR gate 508 include main_pll_bypass_warmrst[m], force_main_pll_bypass, and PLL[m]_EXTBYPASS. Figure 5 In the example shown, each of OR gates 516A-516N is configured to receive EXTBYPASS as an input. Another input to each of OR gates 516A-516N is derived from the output of each corresponding AND gate 514A-514N. As shown, the inputs to the corresponding AND gates 514A-514N include a loss of lock control signal (BYPASS_ON_LOCKLOSS, where the value at PORz = 1) and a lock signal (LOCK) based on the PLL output. The output of each OR gate 516A-516N is a bypass control signal for each corresponding multiplexer 518A-518N. When the bypass control signal from OR gates 516A-516N is low, the output from dividers 112A-112N is output from multiplexers 518A-518N. In some examples, a respective integrated clock gating (ICG) block 520A-520N is used at the output of each of the multiplexers 518A-518N. When bypassing is not performed, the output of each divider block 510A-510N is based on the PLL 106A and the respective divider 112A-112N (e.g., various options are possible and are provided in the example). Figure 510N). When a bypass operation is performed (either based on EXTBYPASS or based on the outputs of AND gates 514A-514N), reference clock signal (FREF) 108 input to PLL 106A is output from divider blocks 510A-510N. In other words, the bypass operation causes PLL 106A and dividers 112A-112B to be bypassed, resulting in a lower clock frequency (reference clock signal 108) being output from divider blocks 510A-510N.

[0030] exist Figure 5 In the example of FIG. 5 , PLL 106A is used with multiple divider blocks 510A-510N. In addition to the PLL clock signal output to divider blocks 510A-510N, PLL 106A also outputs an SSMOD control signal (from an output labeled “CLKSSCG”) and a lock control signal (PLL_LOCK) from an output labeled “LOCK”. Additionally, in some example embodiments, all components in system 500 are replicated for a given IC. In one example, an IC includes up to 20 PLLs, each with one or more associated divider blocks. Furthermore, an IC may include PLLs and dividers without bypass circuitry (e.g., Figure 1 The second set of PLLs 126 and the second set of frequency converters 130 in FIG.

[0031] Utilizing the described clock management system 500 and reset management logic (e.g., Figure 1 Reset management logic 140 in or Figure 3 reset management system 300 in the IC or infotainment chip (e.g., Figure 1 The infotainment circuit 102 in FIG. 1 can respond to a partial reset request by delaying the partial reset request, bypassing some clock domains of the IC or infotainment chip (using one or more bypass control signals, such as staggered bypass control signals), initiating a partial reset after the bypass operation is complete, performing the partial reset operation, tracking when a partial reset condition exists or does not exist, and ending the partial reset if the partial reset condition does not exist. The described clock management system 500 and reset management logic reduce the current level of the IC or infotainment chip during a partial reset compared to previous ICs.

[0032] like Figure 6Tables 602 and 604 illustrate bypass options for an IC according to an example embodiment. As shown, Table 602 includes the MCU PLLs (MCU_PLL0 through MCU_PLL2) that are bypassed by the bypass operation described herein. Furthermore, Table 604 includes various main PLLs (MAIN_PLL0 through MAIN_PLL25), many of which are bypassed by the bypass operation (e.g., MAIN_PLL0, MAIN_PLL4 through MAIN_PLL15, MAIN_PLL24, and MAIN_PLL25). In one example, the types of bypassed main PLLs include audio subsystem PLLs, video subsystem PLLs, processor PLLs, and accelerator PLLs. Furthermore, in Table 604, some main PLLs are not bypassed by the bypass operation. For example, MAIN_PLL1 and MAIN_PLL2 support peripheral devices and are not bypassed by the bypass operation. Furthermore, MAIN_PLL3 supports the Ethernet subsystem and is not bypassed by the bypass operation. Additionally, MAIN_PLL 16 through MAIN_PLL 20 support one or more display subsystems that are not bypassed by the bypass operation. Table 604 includes various reserved PLLs (e.g., MAIN_PLL 9 through MAIN_PLL 11 and MAIN_PLL 20 through MAIN_PLL 22), where MAIN_PLL 9 through MAIN_PLL 11 are bypassed and where MAIN_PLL 20 through MAIN_PLL 22 are not bypassed. Figure 6 The example is for illustration only and is not intended to limit the bypass operation to a specific set of PLLs. Figure 6 In the example given in Figure 1, the PLLs supporting peripherals and external communications are not bypassed (to ensure continued communication with external components). Additionally, the PLLs supporting the display subsystem are not bypassed (to ensure some display functionality).

[0033] Certain terms are used throughout the specification and claims to refer to specific system components. As will be appreciated by those skilled in the art, different parties may refer to a component by different names.

[0034] As used herein, the term "coupled" may encompass any connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B via a direct connection; or (b) in a second example, if intermediate component C does not alter the functional relationship between device A and device B, device A is coupled to device B via intermediate component C, such that device B is controlled by device A via the control signal generated by device A.

[0035] The described embodiments are capable of modification within the scope of the claims, and other embodiments are possible. For example, the described embodiments refer to a partial reset scenario, where only a portion of the IC components are reset. In other example embodiments, the described clock bypass and reset delay are used for a full chip reset scenario, where the chip can be bypassed and fully reset when a reset request is detected.

Claims

1. An integrated circuit comprising: a clock domain with clock domain inputs; A clock management circuit coupled to the clock domain, the clock management circuit comprising: a PLL with a reference clock input and a PLL clock output; a frequency divider having a frequency divider input and a frequency divider output, the frequency divider input being coupled to the PLL clock output; and a bypass circuit having a first clock input coupled to the divider output, a second clock input coupled to the reference clock input, a bypass control input, and a bypass circuit output coupled to the clock domain input; and A reset management circuit includes a controller having a controller input, wherein the reset management circuit has a reset signal input, a first reset output coupled to the bypass control input, and a second reset output coupled to the controller input.

2. The integrated circuit of claim 1 , wherein: The reset management circuit includes reset management logic; The reset signal input is configured to receive a reset signal; and The reset management circuit is configured to: providing a bypass control signal at the first reset output in response to the reset signal; and A reset control signal delayed relative to the bypass control signal is provided at the second reset output in response to the reset signal.

3. The integrated circuit of claim 2 , further comprising: a first group of clock domains including the clock domain, each clock domain in the first group of clock domains having a corresponding clock domain input; as well as a second group of clock domains, each clock domain in the second group of clock domains having a corresponding clock domain input, the clock management circuit being coupled to each corresponding clock domain input of the first group of clock domains and the second group of clock domains, and the clock management circuit comprising: a first group of PLLs including the PLL, each PLL in the first group of PLLs having a corresponding reference clock input and a corresponding PLL clock output; a first set of frequency dividers, each frequency divider in the first set of frequency dividers having a corresponding frequency divider input and a corresponding frequency divider output, each frequency divider input in the first set of frequency dividers being coupled to a corresponding PLL clock output in the first set of PLLs; a second set of PLLs, each PLL in the second set of PLLs having a respective reference clock input and a respective PLL clock output; and a second set of frequency dividers, each frequency divider in the second set of frequency dividers having a corresponding frequency divider input and a corresponding frequency divider output, each frequency divider input in the second set of frequency dividers being coupled to a corresponding PLL clock output in the second set of PLLs, The bypass circuit has a corresponding first clock input, a corresponding second clock input, a corresponding bypass control input and a corresponding bypass output for each divider in the first group of dividers, each first clock input is connected to a corresponding divider output, each second clock input is connected to a corresponding reference clock input, each bypass output is connected to a corresponding clock domain input, and the first reset output of the reset management circuit is connected to each corresponding bypass control input.

4. The integrated circuit according to claim 3, wherein: The first group of PLLs includes a microprocessor PLL (MCU PLL) and an audio subsystem PLL, and the second group of PLLs includes a peripheral subsystem PLL and a display subsystem PLL configured to display information without video.

5. The integrated circuit according to claim 3, wherein: The first set of PLLs includes video subsystem PLLs, and the second set of PLLs includes Ethernet subsystem PLLs.

6. The integrated circuit according to claim 2, wherein: The bypass circuit comprises: a multiplexer having the first clock input, the second clock input, the bypass control input, and the bypass circuit output; and An OR gate having a first gate input coupled to the reset output, a second gate input configured to receive the bypass control signal, and a gate output coupled to the bypass control input.

7. The integrated circuit according to claim 3, wherein: The reset control signal causes the controller to initiate a warm reset after the first set of PLLs and the first set of frequency converters are bypassed.

8. The integrated circuit according to claim 7, wherein: The controller includes a memory, and is configured to: storing a bypass value in the memory in response to initiation of the warm reset; and The bypass value in the memory is cleared after the warm reset is completed.

9. An integrated circuit comprising: A phase-locked loop circuit, i.e., a PLL circuit, comprising: an input coupled to receive a reference clock, and an output, wherein the PLL circuit is configured to provide a first clock at the output of the PLL circuit based on the reference clock; a bypass circuit comprising: a first input coupled to the output of the PLL circuit, a second input coupled to receive the reference clock, a control input, and an output; a clock divider coupled between the PLL circuit and the bypass circuit, the clock divider comprising: an input coupled to the output of the PLL circuit, and an output coupled to the first input of the bypass circuit, wherein the clock divider is configured to provide a second clock at the output of the clock divider based on the first clock; a set of circuits arranged in a clock domain and coupled to the output of the bypass circuit; and A reset management circuit includes an output coupled to the control input of the bypass circuit.

10. The integrated circuit according to claim 9, wherein: The bypass circuit is configured to select between providing the reference clock and providing the second clock at the output of the bypass circuit.

11. The integrated circuit of claim 10, wherein: The reset management circuit includes an input coupled to receive a reset signal; and The reset management circuit is configured to cause the bypass circuit to provide the reference clock to the group of circuits in the clock domain in response to the reset signal.

12. The integrated circuit of claim 11 , wherein: The reset management circuit includes a controller configured to perform a reset of the set of circuits in response to the reset signal; and The reset management circuit includes a delay circuit coupled to the controller and configured to cause the controller to perform the reset after the bypass circuit is caused to provide the reference clock.

13. The integrated circuit of claim 11 , wherein: The set of circuits is a first set of circuits; The clock domain is a first clock domain; and The integrated circuit also includes a second set of circuits arranged in the clock domain and coupled to receive a clock independent of the reset signal.

14. The integrated circuit of claim 13, wherein: The PLL circuit is a first PLL circuit; The clock divider is a first clock divider; and The integrated circuit further comprises: a second PLL circuit, the second PLL circuit comprising: an input coupled to receive the reference clock, and an output; and A second clock divider includes an input coupled to the output of the second PLL and an output coupled to the second set of circuits to provide the clock independent of the reset signal.

15. An integrated circuit comprising: The phase-locked loop circuit is a PLL circuit, and the PLL circuit includes: an input connected to receive a reference clock, and an output; a bypass circuit comprising: a first input coupled to the output of the PLL circuit, a second input coupled to receive the reference clock, a control input, and an output; a set of circuits arranged in a clock domain and coupled to the output of the bypass circuit; and a reset management circuit comprising an output coupled to the control input of the bypass circuit, wherein: The reset management circuit includes an input coupled to receive a reset signal; and The reset management circuit is configured to cause the bypass circuit to provide the reference clock to the group of circuits in the clock domain in response to the reset signal.

16. The integrated circuit of claim 15, wherein: The reset management circuit includes a controller configured to perform a reset of the set of circuits in response to the reset signal; and The reset management circuit includes a delay circuit coupled to the controller and configured to cause the controller to perform the reset after the bypass circuit is caused to provide the reference clock.

17. The integrated circuit of claim 15, wherein: The set of circuits is a first set of circuits; The clock domain is a first clock domain; and The integrated circuit also includes a second set of circuits arranged in the clock domain and coupled to receive a clock independent of the reset signal.

18. The integrated circuit of claim 17, wherein: The PLL circuit is a first PLL circuit; and The integrated circuit further comprises: a second PLL circuit, the second PLL circuit comprising: an input coupled to receive the reference clock, and an output; and A clock divider includes an input coupled to the output of the second PLL and an output coupled to the second set of circuits to provide the clock independent of the reset signal.

19. A method comprising: Receive reference clock; generating a first clock signal based on the reference clock; receiving a reset signal; Based on the reset signal, selecting between providing the reference clock and providing the first clock signal to a group of circuits arranged in a clock domain, wherein the selecting comprises: providing the reference clock to the group of circuits based on the reset signal being asserted; and Based on the reset signal being asserted, a reset operation is performed on the group of circuits after the reference clock is provided.

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