Semiconductor device and operating method thereof

Abstract

The invention discloses a semiconductor device and an operation method thereof. The semiconductor device comprises a first register, a second register, a third register and a first logic element. The first register is used for storing first input data. The second register is used for storing the first weight data. The third register is used for outputting first output data according to each of the first input data and the first weight data. The first logic element is configured to control the first register according to each of the first bit data and the second bit data. The first bit data and the second bit data respectively correspond to the first input data and the first weight data.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and an operating method thereof. Background Art

[0002] Some semiconductor devices include a systolic array that performs matrix multiplication by streaming input data to an array of processing elements. Some input data contains a large number of zero-valued elements. However, once the data is in the input stream, the systolic array operation is performed on each element of the data, and the semiconductor device consumes high power. Summary of the Invention

[0003] One embodiment of the present disclosure provides a semiconductor device, characterized by including a first register, a second register, a third register, and a first logic element. The first register is used to store first input data. The second register is used to store first weight data. The third register is used to output first output data based on each of the first input data and the first weight data. The first logic element is used to control the first register based on each of first bit data and second bit data. The first bit data and the second bit data correspond to the first input data and the first weight data, respectively.

[0004] One embodiment of the present disclosure provides a semiconductor device, characterized by including a first processing element, a second logic element, and a third logic element. The first processing element is used to store first output data based on each of first input data, first weight data, first bit data, and second bit data, and the first processing element includes a first register and a first logic element. The first register is used to output the first output data. The first logic element is used to control the first register based on each of the first bit data and the second bit data. The second logic element is used to generate the first bit data based on the first input data. The third logic element is used to generate the second bit data based on the first weight data.

[0005] One embodiment of the present disclosure provides an operating method for a semiconductor device, characterized in that it includes the following steps: storing first input data in a first register; generating first bit data based on the first input data; generating second bit data based on first weight data; controlling the first register according to each of the first bit data and the second bit data by a first logic element; and calculating the first input data and first weight data based on the first bit data and the second bit data. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure are best understood from the following detailed description in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A is a schematic diagram of a processing element according to some embodiments of the present disclosure;

[0008] Figure 1B is a schematic diagram of a logic element according to some embodiments of the present disclosure;

[0009] Figure 2 is a schematic diagram of a systolic array according to some embodiments of the present disclosure;

[0010] Figure 3 is a schematic diagram of a systolic array according to some embodiments of the present disclosure;

[0011] Figure 4 For operation according to some embodiments of the present disclosure Figure 1A 、 Figure 2 and Figure 3 A flowchart of a method of at least one processing element shown in;

[0012] Figure 5 For operation according to some embodiments of the present disclosure Figure 1A 、 Figure 2 and Figure 3 A flowchart of a method of at least one processing element shown in; and

[0013] Figure 6 For operation according to some embodiments of the present disclosure Figure 1A 、 Figure 2 and Figure 3 A flowchart of a method of at least one processing element shown in FIG.

[0014]

Explanation of symbols

[0015] 100: Processing element

[0016] 200, 300: Systolic array

[0017] 400, 500, 600: Method

[0018] A11, A12, A21, A22: adders

[0019] AND1~AND3: AND gate

[0020] CK: clock signal

[0021] LW11, LW12, LW21, LW22, LW1, LW2, LWN, LX1, LX2, LXN, LX11, LX12, LX21, LX22, LY11, LY12, LY21, LY22: logical elements

[0022] pieces

[0023] M11, M12, M21, M22: Multipliers

[0024] NOR1~NOR3:NOR gate

[0025] O41~O43, O51~O59, O61~O65: Operation

[0026] P11, P12, P1N, P21, P22, P2N, PN1, PN2, PNN: processing elements

[0027] R11W, R11X, R12W, R12X, RW11, RW12, RWZ11, RX11, RXZ11, RY11, R21W, R22W, R21X, R22X, RW12, RW21, RW22, RW22, RWZ12, RWZ21, RWZ22, RX12, RX21, RX22, RXZ12, RXZ21, RXZ22, RY11, RY12, RY21, RY22: registers

[0028] W, W1, W2, WN: weight data

[0029] WZ1, XZ1, WZ2, WZN: bit data

[0030] X, X1, X2, XN: input data

[0031] XZ1, XZ2, XZN: bit data

[0032] Y, Y11, Y12, Y21, Y22: output data DETAILED DESCRIPTION

[0033] The following disclosure provides different embodiments or examples for implementing the features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. Other components, materials, values, steps, arrangements, etc. can be expected. For example, in the description below, forming a first feature above or on a second feature may include embodiments in which the first and second features are directly in contact with each other, and may also include embodiments in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat element symbols and / or letters in each example. This repetition is for simplicity and clarity purposes and does not, in itself, specify the relationship between the various embodiments or configurations discussed.

[0034] In addition, for ease of description, spatial relative terms such as "below," "beneath," "below," "above," and "above" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. As used herein, "about," "approximately," or "substantially" may generally mean within 20%, or within 10%, or within 5% of a given value or range. The values given herein are approximate, meaning that the terms "about," "about," "approximately," or "substantially" may be inferred unless explicitly stated. However, those skilled in the art will recognize that the values or ranges listed throughout the description are merely examples and may decrease as integrated circuits shrink.

[0035] The terms used in the following description and patent claims generally have their ordinary meanings as they are used in the art or in the specific context in which each term is used. A person skilled in the art will appreciate that a component or process may be referred to by different names. The numerous different embodiments detailed in this specification are for illustrative purposes only and are not intended to limit the scope or spirit of the disclosure or any exemplary term.

[0036] It is important to note that terms such as "first" and "second" are used herein to describe various elements or processes to distinguish between the elements or processes. However, the elements, processes, and their order are not limited by these terms. For example, a first element can be referred to as a second element, and a second element can be similarly referred to as a first element without departing from the scope of this disclosure.

[0037] In the following discussion and in the scope of the invention claims, the terms "comprising," "including," "containing," "having," "involving," etc. should be understood as open-ended, that is, interpreted as including but not limited to. As used herein, the term "and / or" is not mutually exclusive and includes any relevant listed items and all combinations of one or more relevant listed items.

[0038] Figure 1A FIG. 1 is a schematic diagram of a processing element 100 according to some embodiments of the present disclosure. Figure 1AAs illustratively shown, processing element 100 includes registers R11X, R11W, RX11, RW11, RXZ11, RWZ11, and RY11, logic elements LX11, LW11, and LY11, a multiplier M11, and an adder A11. In some embodiments, register R11X is referred to as the input X register. Register R11W is referred to as the input W register. Register RX11 is referred to as the clock-gated X register. Register RW11 is referred to as the clock-gated W register. Register RXZ11 is referred to as the X-zero register. Register RWZ11 is referred to as the W-zero register. Register RY11 is referred to as the accumulation register or the clock-gated Y register. The combination of multiplier M11 and adder A11 is referred to as a multiply-accumulate (MAC) unit.

[0039] In some embodiments, register R11X is used to store input data X1 and output the input data X1 according to the clock signal CK. Register R11W is used to store weight data W1 and output the weight data W1 according to the clock signal CK. Register RX11 is used to store input data X1 and output the input data X1 to the multiplier M11 according to each of the bit data XZ1, WZ1 and the clock signal CK. Register RW11 is used to store weight data W1 and output the weight data W1 to the multiplier M11 according to each of the bit data XZ1, WZ1 and the clock signal CK. Register RXZ11 is used to store bit data XZ1 and output the bit data XZ1 according to the clock signal CK. Register RWZ11 is used to store bit data WZ1 and output the bit data WZ1 according to the clock signal CK. The register RY11 is used to store each of the output data Y11 and AD11 from the adder A11 , and output the output data Y11 and AD11 to the adder A11 according to each of the bit data XZ1 , WZ1 and the clock signal CK.

[0040] In some embodiments, logic element LX11 is configured to receive each of bit data XZ1, WZ1, and a clock signal CK, and to control register RX11 to output input data X1 to multiplier M11 based on each of bit data XZ1, WZ1, and clock signal CK. Logic element LW11 is configured to receive each of bit data XZ1, WZ1, and clock signal CK, and to control register RW11 to output weight data W1 to multiplier M11 based on each of bit data XZ1, WZ1, and clock signal CK. Logic element LY11 is configured to receive each of bit data XZ1, WZ1, and clock signal CK, and to control register RX11 to output output data Y11 to adder A11 based on each of bit data XZ1, WZ1, and clock signal CK.

[0041] In some embodiments, multiplier M11 is configured to receive each of input data X1 and weight data W1, multiply input data X1 and weight data W1 to generate output data MD11, and output output data MD11 to adder A11. Adder A11 is configured to receive each of output data MD11 and Y11, add output data MD11 and Y11 to generate output data AD11, and output output data AD11 to register RY11.

[0042] In some embodiments, each of the input data X1 and the weight data W1 is multi-bit data, such as 32-bit data. In some embodiments, each of the input data X1 and the weight data W1 is data other than 32-bit data. In some embodiments, each of the bit data XZ1 and the bit data WZ1 is 1-bit data. In some embodiments, each of the bit data XZ1 and the bit data WZ1 is data other than 1-bit data. In some embodiments, the bit data XZ1 and the bit data WZ1 represent zero flags for the input data X1 and the weight data W1, respectively. Specifically, the bit data XZ1 represents whether each bit of the input data X1 has a logical value of 0, and the weight data W1 represents whether each bit of the weight data W1 has a logical value of 0. For example, in response to each bit of the input data X1 having a logical value of 0, the bit data XZ1 has a logical value of 1. In response to at least one bit of the input data X1 having a logical value of 1, the bit data XZ1 has a logical value of 0. In response to each bit of the weight data W1 having a logical value of 0, the bit data WZ1 has a logical value of 1. In response to at least one bit of the weight data W1 having a logic value of 1, the bit data WZ1 has a logic value of 0.

[0043] It should be noted that when the data value of the input data X1 is equal to 0, each bit of the input data X1 has a logic value of 0. When the data value of the input data X1 is not equal to 0, at least one bit of the input data X1 has a logic value of 1. When the data value of the weight data W1 is equal to 0, each bit of the weight data W1 has a logic value of 0. When the data value of the weight data W1 is not equal to 0, at least one bit of the weight data W1 has a logic value of 1.

[0044] In some embodiments, the clock signal CK has a plurality of clock cycles including a first clock cycle and a second clock cycle, and each of the logic elements LX11 and LW11 operates in the first clock cycle, and the logic element LY11 operates in the second clock cycle.

[0045] In some embodiments, when at least one of the bit data XZ1 and WZ1 has a logic value of 1, each of registers RX11, RW11, and RY11 is clock-gated, and the data stored in register RY11 is not updated. Specifically, when at least one of the bit data XZ1 and WZ1 has a logic value of 1, logic elements LX11, LW11, and LY11 disable registers RX11, RW11, and RY11, respectively.

[0046] For example, in the first clock cycle, in response to bit data XZ1 having a logic value of 1, logic elements LX11, LW11, and LY11 disable registers RX11, RW11, and RY11, respectively, causing each of registers RX11, RW11, and RY11 to be turned off. Therefore, in the first clock cycle, registers RX11 and RW11 do not output input data X1 and weight data W1, respectively, to multiplier M11.

[0047] In this example, during the first clock cycle, multiplier M11 is disabled. Alternatively, multiplier M11 does not perform a multiplication operation, does not generate output data MD11, and does not output output data MD11 to adder A11. Subsequently, during the second clock cycle, register RY11 does not output output data Y11 to adder A11, and adder A11 does not perform an addition operation, does not generate output data AD11, and instead outputs output data AD11 to register RY11. Therefore, the data stored in register RY11 remains as output data Y11 and remains unchanged.

[0048] For example, in the first clock cycle, in response to bit data WZ1 having a logic value of 1, logic elements LX11, LW11, and LY11 disable registers RX11, RW11, and RY11, respectively, causing each of registers RX11, RW11, and RY11 to be turned off. Therefore, in the first clock cycle, registers RX11 and RW11 do not output input data X1 and weight data W1, respectively, to multiplier M11.

[0049] In this example, during the first clock cycle, multiplier M11 is disabled. Alternatively, multiplier M11 does not perform a multiplication operation, does not generate output data MD11, and does not output output data MD11 to adder A11. Subsequently, during the second clock cycle, register RY11 does not output output data Y11 to adder A11, and adder A11 does not perform an addition operation, does not generate output data AD11, and instead outputs output data AD11 to register RY11. Therefore, the data stored in register RY11 remains as output data Y11 and remains unchanged.

[0050] In some embodiments, when each of the bit data XZ1 and WZ1 has a logic value of 0, each of registers RX11, RW11, and RY11 is enabled, and the data stored in register RY11 is updated. For example, when each of the bit data XZ1 and WZ1 has a logic value of 0, logic elements LX11, LW11, and LY11 activate registers RX11, RW11, and RY11, respectively. Therefore, during the first clock cycle, registers RX11 and RW11 output input data X1 and weight data W1, respectively, to multiplier M11. Multiplier M11 then multiplies input data X1 by weight data W1 to generate output data MD11, and outputs output data MD11 to adder A11. Then, during the second clock cycle, register RY11 stops outputting output data Y11 to adder A11. Adder A11 adds output data MD11 and Y11 to generate output data AD11, and then outputs output data AD11 to register RY11. Therefore, the data stored in register RY11 is updated and changed from output data Y11 to output data AD11.

[0051] Figure 1B According to some embodiments of the present disclosure Figure 1A Schematic diagram of logic elements LX11, LW11 and LY11. Figure 1B illustratively shown in FIG, logic element LX11 includes an AND gate AND1 and a NOR gate NOR1, logic element LW11 includes an AND gate AND2 and a NOR gate NOR2, and logic element LY11 includes an AND gate AND3 and a NOR gate NOR3.

[0052] In some embodiments, each of logic elements LX11, LW11, and LY11 is implemented as a combination of a NOR gate and an AND gate. Specifically, in logic element LX11, the two inputs of NOR gate NOR1 are respectively used to receive bit data XZ1 and WZ1. An input of AND gate AND1 is used to receive the clock signal CK, and the other input of AND gate AND1 is coupled to the output of NOR gate NOR1. The output of AND gate AND1 is coupled to register RX11. In logic element LW11, the two inputs of NOR gate NOR2 are respectively used to receive bit data XZ1 and WZ1. An input of AND gate AND2 is used to receive the clock signal CK, and the other input of AND gate AND2 is coupled to the output of NOR gate NOR2. The output of AND gate AND2 is coupled to register RW11. In logic element LY11, the two inputs of NOR gate NOR3 are respectively used to receive bit data XZ1 and WZ1. An input of AND gate AND3 receives a clock signal CK, and another input of AND gate AND3 is coupled to the output of NOR gate NOR3. The output of AND gate AND3 is coupled to register RY11. In some embodiments, each of logic elements LX11, LW11, and LY11 is implemented as a logic element rather than a combination of a NOR gate and an AND gate that perform similar logic operations.

[0053] Figure 2 FIG. 2 is a schematic diagram of a systolic array 200 according to some embodiments of the present disclosure. Figure 2 As illustratively shown in FIG, systolic array 200 includes at least processing elements P11, P12, P21, and P22. In some embodiments, systolic array 200 includes processing elements other than processing elements P11, P12, P21, and P22. Figure 2 and Figure 1A , processing element 100 is an embodiment of each of processing elements P11 , P12 , P21 , and P22 , as well as other processing elements in systolic array 200 . Figure 2 Follow and Figure 1A Similar sign conventions. In some embodiments, Figure 1A The processing elements 100 in are embedded in a systolic array, such as Figure 2 The systolic array 200 in FIG.

[0054] like Figure 2As illustratively shown, processing element P11 includes registers R11X, R11W, RX11, RW11, RXZ11, RWZ11, and RY11, logic elements LX11, LW11, and LY11, a multiplier M11, and an adder A11. Processing element P12 includes registers R12X, R12W, RX12, RW12, RXZ12, RWZ12, and RY12, logic elements LX12, LW12, and LY12, a multiplier M12, and an adder A12. Processing element P21 includes registers R21X, R21W, RX21, RW21, RXZ21, RWZ21, and RY21, logic elements LX21, LW21, and LY21, a multiplier M21, and an adder A21. The processing element P22 includes registers R22X, R22W, RX22, RW22, RXZ22, RWZ22, and RY22, logic elements LX22, LW22, and LY22, a multiplier M22, and an adder A22.

[0055] In some embodiments, in processing element P12, register R12X is used to store input data X2 and output the input data X2 according to clock signal CK. Register R12W is used to store weight data W1 and output the weight data W1 according to clock signal CK. Register RX12 is used to store input data X2 and output the input data X2 to multiplier M12 according to each of bit data XZ2, WZ1, and clock signal CK. Register RW12 is used to store weight data W1 and output the weight data W1 to multiplier M12 according to each of bit data XZ2, WZ1, and clock signal CK. Register RXZ12 is used to store bit data XZ2 and output the bit data XZ2 according to clock signal CK. Register RWZ12 is used to store bit data WZ1 and output the bit data WZ1 according to clock signal CK. The register RY12 is used to store each of the output data Y12 and AD12 from the adder A12, and output the output data Y12 and AD12 to the adder A12 according to each of the bit data XZ2, WZ1 and the clock signal CK.

[0056] In some embodiments, logic element LX12 is configured to receive each of the bit data XZ2, WZ1, and a clock signal CK, and to control register RX12 to output input data X2 to multiplier M12 based on each of the bit data XZ2, WZ1, and clock signal CK. Logic element LW12 is configured to receive each of the bit data XZ2, WZ1, and clock signal CK, and to control register RW12 to output weight data W1 to multiplier M12 based on each of the bit data XZ2, WZ1, and clock signal CK. Logic element LY12 is configured to receive each of the bit data XZ2, WZ1, and clock signal CK, and to control register RX12 to output output data Y12 to adder A12 based on each of the bit data XZ2, WZ1, and clock signal CK.

[0057] In some embodiments, multiplier M12 is configured to receive each of input data X2 and weight data W1, multiply input data X2 and weight data W1 to generate output data MD12, and output output data MD12 to adder A12. Adder A12 is configured to receive each of output data MD12 and Y12, add output data MD12 and Y12 to generate output data AD12, and output output data AD12 to register RY12.

[0058] In some embodiments, in processing element P21, register R21X is used to store input data X1 and output the input data X1 according to clock signal CK. Register R21W is used to store weight data W2 and output the weight data W2 according to clock signal CK. Register RX21 is used to store input data X1 and output the input data X1 to multiplier M21 according to each of bit data XZ1, WZ2 and clock signal CK. Register RW21 is used to store weight data W2 and output the weight data W2 to multiplier M21 according to each of bit data XZ1, WZ2 and clock signal CK. Register RXZ21 is used to store bit data XZ1 and output the bit data XZ1 according to clock signal CK. Register RWZ21 is used to store bit data WZ2 and output the bit data WZ2 according to clock signal CK. The register RY21 is used to store each of the output data Y21 and AD21 from the adder A21, and output the output data Y21 and AD21 to the adder A21 according to each of the bit data XZ1, WZ2 and the clock signal CK.

[0059] In some embodiments, logic element LX21 is configured to receive each of the bit data XZ1, WZ2 and the clock signal CK, and to control register RX21 to output input data X1 to multiplier M21 based on each of the bit data XZ1, WZ2 and the clock signal CK. Logic element LW21 is configured to receive each of the bit data XZ1, WZ2 and the clock signal CK, and to control register RW21 to output weight data W2 to multiplier M21 based on each of the bit data XZ1, WZ2 and the clock signal CK. Logic element LY21 is configured to receive each of the bit data XZ1, WZ2 and the clock signal CK, and to control register RX21 to output output data Y21 to adder A21 based on each of the bit data XZ1, WZ2 and the clock signal CK.

[0060] In some embodiments, multiplier M21 is configured to receive each of input data X1 and weight data W2, multiply input data X1 and weight data W2 to generate output data MD21, and output output data MD21 to adder A21. Adder A21 is configured to receive each of output data MD21 and Y21, add output data MD21 and Y21 to generate output data AD21, and output output data AD21 to register RY21.

[0061] In some embodiments, in processing element P22, register R22X is used to store input data X2 and output the input data X2 according to clock signal CK. Register R22W is used to store weight data W2 and output the weight data W2 according to clock signal CK. Register RX22 is used to store input data X2 and output the input data X2 to multiplier M22 according to each of bit data XZ2, WZ2 and clock signal CK. Register RW22 is used to store weight data W2 and output the weight data W2 to multiplier M22 according to each of bit data XZ2, WZ2 and clock signal CK. Register RXZ22 is used to store bit data XZ2 and output the bit data XZ2 according to clock signal CK. Register RWZ22 is used to store bit data WZ2 and output the bit data WZ2 according to clock signal CK. The register RY22 is used to store each of the output data Y22 and AD22 from the adder A22, and output each of the output data Y22 and AD22 to the adder A22 according to each of the bit data XZ2, WZ2 and the clock signal CK.

[0062] In some embodiments, logic element LX22 is configured to receive each of the bit data XZ2, WZ2, and the clock signal CK, and to control register RX22 to output input data X2 to multiplier M22 based on each of the bit data XZ2, WZ2, and the clock signal CK. Logic element LW22 is configured to receive each of the bit data XZ2, WZ2, and the clock signal CK, and to control register RW22 to output weight data W2 to multiplier M22 based on each of the bit data XZ2, WZ2, and the clock signal CK. Logic element LY22 is configured to receive each of the bit data XZ2, WZ2, and the clock signal CK, and to control register RX22 to output output data Y22 to adder A22 based on each of the bit data XZ2, WZ2, and the clock signal CK.

[0063] In some embodiments, multiplier M22 is configured to receive each of input data X2 and weight data W2, multiply input data X2 and weight data W2 to generate output data MD22, and output output data MD22 to adder A22. Adder A22 is configured to receive each of output data MD22 and Y22, add output data MD22 and Y22 to generate output data AD22, and output output data AD22 to register RY22.

[0064] In some embodiments, each of the input data X2 and the weight data W2 is multi-bit data, such as 32-bit data. In some embodiments, each of the input data X2 and the weight data W2 is data other than 32-bit data. In some embodiments, each of the bit data XZ2 and the bit data WZ2 is 1-bit data. In some embodiments, each of the bit data XZ2 and the bit data WZ2 is data other than 1-bit data. In some embodiments, the bit data XZ2 and the bit data WZ2 represent zero flags for the input data X2 and the weight data W2, respectively. Specifically, the bit data XZ2 indicates whether each bit of the input data X2 has a logical value of 0, and the weight data W2 indicates whether each bit of the weight data W2 has a logical value of 0. For example, in response to each bit of the input data X2 having a logical value of 0, the bit data XZ2 has a logical value of 1. In response to at least one bit of the input data X2 having a logical value of 1, the bit data XZ2 has a logical value of 0. In response to each bit of the weight data W2 having a logical value of 0, the bit data WZ2 has a logical value of 1. In response to at least one bit of the weight data W2 having a logic value of 1, the bit data WZ2 has a logic value of 0.

[0065] In some embodiments, each of processing elements P11 and P12 is arranged in a first row horizontally. Each of processing elements P21 and P22 is arranged in a second row horizontally. Each of processing elements P11 and P21 is arranged in a first column vertically. Each of processing elements P12 and P22 is arranged in a second column vertically. Other processing elements are arranged in different rows horizontally and in different columns vertically.

[0066] In some embodiments, the systolic array 200 is configured to perform matrix multiplication. Specifically, during the matrix multiplication, the processing element P11 operates in a first clock cycle, the processing elements P12 and P21 operate in a second clock cycle following the first clock cycle, and the processing element P22 operates in a third clock cycle following the second clock cycle. Each operation of the processing elements P11, P12, P21, and P22 corresponds to Figure 1A Therefore, for the sake of brevity, similar descriptions of the operations of processing elements P11, P12, P21, and P22 are omitted.

[0067] Figure 3 FIG. 3 is a schematic diagram of a systolic array 300 according to some embodiments of the present disclosure. Figure 3 As illustratively shown in FIG, systolic array 300 includes processing elements P11, P12, ..., P1N, P21, P22, ..., P2N, ..., PN1, PN2, ..., PNN and logic elements LX1, LX2, ..., LXN and LW1, LW2, ..., LWN, where N is an integer greater than 2. Figure 1A 、 Figure 2 and Figure 3 , processing element 100 is an embodiment of each of processing elements P11, P12, . . . , P1N, P21, . . . , P2N, . . . , PN1, PN2, . . . , PNN of systolic array 300. Figure 3 Follow and Figure 1A and Figure 2 Similar logo conventions.

[0068] In some embodiments, each of processing elements P11, P12, ..., P1N is arranged in a first row horizontally. Each of processing elements P21, P22, ..., P2N is arranged in a second row horizontally. Each of processing elements PN1, PN2, ..., PNN is arranged in the Nth row horizontally. Each of processing elements P11, P21, ..., PN1 is arranged in a first column vertically. Each of processing elements P12, P22, ..., PN2 is arranged in a second column vertically. Each of processing elements P1N, P2N, ..., PNN is arranged in the Nth column vertically.

[0069] In some embodiments, processing element P11 is configured to operate based on each of input data X1, weight data W1, bit data XZ1, and WZ1, and output the input data X1 and bit data XZ1 to processing element P21, and output the weight data W1 and bit data WZ1 to processing element P12. Processing element P12 is configured to operate based on each of input data X2, bit data XZ2, weight data W1, and bit data WZ1, and output the input data X2 and bit data XZ2 to processing element P22, and output the weight data W1 and bit data WZ1 to processing element P13. Processing element P1N is configured to operate based on each of input data XN, bit data XZN, weight data W1, and bit data WZ1, and output the input data XN and bit data XZN to processing element P2N.

[0070] In some embodiments, processing element P21 is configured to operate according to each of input data X1, bit data XZ1, weight data W2, and bit data WZ2, and output the input data X1 and bit data XZ1 to processing element P31, and output the weight data W2 and bit data WZ2 to processing element P22. Processing element P22 is configured to operate according to each of input data X2, bit data XZ2, weight data W2, and bit data WZ2, and output the input data X2 and bit data XZ2 to processing element P32, and output the weight data W2 and bit data WZ2 to processing element P23. Processing element P2N is configured to operate according to each of input data XN, bit data XZN, weight data W2, and bit data WZ2, and output the input data XN and bit data XZN to processing element P3N.

[0071] In some embodiments, processing element PN1 is configured to perform an operation based on each of input data X1, bit data XZ1, weight data WN, and bit data WZN, and output weight data WN and bit data WZN to processing element PN2. Processing element PN2 is configured to perform an operation based on each of input data X2, bit data XZ2, weight data WN, and bit data WZN, and output input data XN and bit data XZN to processing element PN3. Processing element PNN is configured to perform an operation based on each of input data XN, bit data XZN, weight data WN, and bit data WZN.

[0072] During matrix multiplication in the systolic array 300, in the first clock cycle, processing element P11 performs Figure 1A In a second clock cycle following the first clock cycle, each of the processing elements P12 and P21 performs Figure 1A In the third clock cycle after the second clock cycle, each of the processing elements P13, P22 and P31 performs Figure 1A In the Nth clock cycle after the N-1th clock cycle, each of the processing elements P1N, P2(N-1), P3(N-2), ..., P(N-1)2 and PN1 performs Figure 1A In the N+1th clock cycle after the Nth clock cycle, each of the processing elements P2N, P3(N-1), P4(N-2), ..., P(N-1)3 and PN2 performs Figure 1A In the 2N-1th clock cycle after the 2N-2th clock cycle, the processing element PNN performs Figure 1A The operations described in .

[0073] In some embodiments, processing elements P11 and P12-P1N are coupled to logic elements LX1 and LX2-LXN, respectively, and processing elements P11 and P21-PN1 are coupled to logic elements LW1-LWN, respectively. In some embodiments, each of logic elements LX1-LXN and LW1-LWN is implemented as a NOR gate. In some embodiments, each of logic elements LX1-LXN and LW1-LWN is implemented as another logic element that is logically equivalent to a NOR gate.

[0074] In some embodiments, logic element LX1 is configured to receive input data X1, generate bit data XZ1 based on input data X1, and output bit data XZ1 to processing element P11. Logic element LX2 is configured to receive input data X2, generate bit data XZ2 based on input data X2, and output bit data XZ2 to processing element P12. Logic element LXN is configured to receive input data XN, generate bit data XZN based on input data XN, and output bit data XZN to processing element P1N. Logic element LW1 is configured to receive weight data W1, generate bit data WZ1 based on weight data W1, and output bit data WZ1 to processing element P11. Logic element LW2 is configured to receive weight data W2, generate bit data WZ2 based on weight data W2, and output bit data WZ2 to processing element P21. Logic element LWN is configured to receive weight data WN, generate bit data WZN based on weight data WN, and output bit data WZN to processing element P1N.

[0075] Figure 4 For operation according to some embodiments of the present disclosure Figure 1A 、 Figure 2 and Figure 3 A flow chart of a method 400 for processing at least one of the processing elements 100, P11, P12-P1N, P21, P22-P2N, PN1, PN2-PNN is shown. Figure 4 As illustratively shown in FIG. 4 , method 400 includes operations O41 - O43 .

[0076] During operation O41, each of the input data X and the weight data W is input into the processing element, and the processing element determines whether at least one of each bit of the input data X and each bit of the weight data W has a logic value of 0. If at least one of each bit of the input data X and each bit of the weight data W has a logic value of 0, operation O42 is performed after operation O41. If at least one bit of the input data X and at least one bit of the weight data W has a logic value of 1, operation O43 is performed after operation O41. For example, each of the input data X1 and the weight data W1 is input into registers R11X, R11W, RX11, and RW11 in the processing element 100, and the processing element 100 determines whether at least one of the bit data XZ1 and WZ1 has a logic value of 1 by logic elements LX11 and LW11. In some embodiments, the input data X corresponds to input data X1, X2, ..., XN, and the weight data W corresponds to Figure 1A 、 Figure 2 and Figure 3 The weight data W1, W2, ..., WN in.

[0077] During operation O42, the output data Y in the processing element is not changed or updated. For example, in response to each of the registers RX11, RW11, and RY11 being clock-gated by the logic elements LX11, LW11, and LY11, the output data Y11 stored in the register RY11 of the processing element 100 is not changed or updated. In some embodiments, the output data Y corresponds to Figure 1A 、 Figure 2 and Figure 3 The output data Y11, Y12, ..., Y1N, Y21, Y22, ..., Y2N, YN1, YN2, ..., YNN.

[0078] During operation O43, the output data Y in the processing element is changed or updated from the output data Y to the input data X multiplied by the weight data W and added to the output data Y. For example, in the processing element 100, in response to the multiplier M11 receiving the input data X1 and the weight data W1, the multiplier M11 multiplies the input data X1 by the weight data W1 to generate output data MD11, and outputs the output data MD11 to the adder A11. The adder A11 adds the output data MD11 and Y11 to generate output data AD11, and outputs the output data AD11 to the register RY11.

[0079] Figure 5 For operation according to some embodiments of the present disclosure Figure 1A 、 Figure 2 and Figure 3 A flow chart of a method 500 of processing at least one of the processing elements 100, P11, P12-P1N, P21, P22-P2N, PN1, PN2-PNN is shown. Figure 5 As illustratively shown in FIG. 5 , method 500 includes operations O51 - O59 .

[0080] During the O51 operation, the systolic array starts a matrix multiplication. For example, the systolic array 200 starts a matrix multiplication.

[0081] During operation O52, a processing element in a systolic array receives input data, weight data, and bit data. For example, processing element P11 in systolic array 200 receives input data X1, weight data W1, and bit data XZ1 and WZ1.

[0082] During operation O53, the processing element determines whether at least one of the data values of the input data and the weight data is equal to a logical value of 0. When at least one of the data values of the input data and the weight data is equal to a logical value of 0, operation O54 is performed after operation O53. When each of the data values of the input data and the weight data is not equal to a logical value of 0, operation O56 is performed after operation O53. For example, processing element P11 determines whether at least one of the data values of input data X1 and weight data W1 is equal to a logical value of 0. When at least one of the bit values of bit data XZ1 and WZ1 is equal to a logical value of 1, operation O54 is performed after operation O53. When each of the bit values of bit data XZ1 and WZ1 is equal to a logical value of 0, operation O56 is performed after operation O53.

[0083] During operation O54 , the registers are clock-gated. For example, in the first clock cycle, the registers RX11 and RW11 are clock-gated and do not output the input data X1 and the weight data W1 to the multiplier M11 .

[0084] During operation O55 , the register is clock-gated in the next clock cycle. For example, in the second clock cycle after the first clock cycle, the register RY11 is clock-gated and does not output the output data Y11 to the adder A11.

[0085] During operation O56 , the processing element latches and updates the input data and weight data. For example, in processing element P11 , registers RX11 and RW11 store input data X1 and weight data W1 , respectively, and output the input data X1 and weight data W1 to multiplier M11 .

[0086] During operation O57 , the processing element multiplies the input data with the weight data. For example, in processing element P11 , multiplier M11 multiplies input data X1 with weight data W1 to generate output data MD11 .

[0087] During operation O58 , the processing element updates output data. For example, in processing element P11 , adder A11 adds output data MD11 from multiplier M11 and output data Y11 from register RY11 to generate output data AD11 and outputs output data AD11 to register RY11 .

[0088] During operation O59, the processing element forwards the input data, weight data, and bit data to the next processing element. For example, processing element P11 forwards input data X1 and bit data XZ1 to processing element P21, and forwards weight data W1 and bit data WZ1 to processing element P12.

[0089] Figure 6 For operation according to some embodiments of the present disclosure Figure 1A 、 Figure 2 and Figure 3 A flow chart of a method 600 of processing at least one of the processing elements 100, P11, P12-P1N, P21, P22-P2N, PN1, PN2-PNN is shown. Figure 6 As illustratively shown in FIG, method 600 includes operations O61 - O65 .

[0090] During operation O61 , the first register stores first input data. For example, register RX11 stores input data X1 .

[0091] During operation O62, first bit metadata is generated according to first input data, for example, bit metadata XZ1 is generated according to input data X1.

[0092] During operation O63, second bit data is generated according to the first weight data. For example, bit data WZ1 is generated according to the weight data W1.

[0093] During operation O64, the first logic element controls the first register according to each of the first bit data and the second bit data. For example, the logic element LX11 controls the register RX11 according to each of the bit data XZ1 and the bit data WZ1.

[0094] During operation O65 , first input data and first weight data are calculated based on the first bit data and the second bit data, for example, input data X1 and weight data W1 are calculated based on bit data XZ1 and bit data WZ1 .

[0095] In some approaches, some semiconductor devices include a systolic array that performs matrix multiplication by streaming input data to an array of processing elements. Some input data contains a large number of zero-valued elements. Once the data is in the input stream, the systolic array operation is performed on each element of the data. As a result, the semiconductor device consumes high power.

[0096] Compared to the above method, in some embodiments of the present disclosure, when at least one of the bit data XZ1 and WZ1 has a logic value of 1, registers RX11, RW11, and RY11 are clock-gated or disabled by logic elements LX11, LW11, and LY11, respectively. This allows the output data of the processing element 100 to not be updated when at least one of the input data X1 and the weight data W1 has a logic value of 0. This reduces power consumption and improves power efficiency.

[0097] A semiconductor device is also disclosed. The semiconductor device includes a first register, a second register, a third register, and a first logic element. The first register is used to store first input data. The second register is used to store first weight data. The third register is used to output first output data based on each of the first input data and the first weight data. The first logic element is used to control the first register based on each of the first bit data and the second bit data. The first bit data and the second bit data correspond to the first input data and the first weight data, respectively.

[0098] In some embodiments, the semiconductor device further includes a second logic element configured to control the second register according to each of the first bit data and the second bit data.

[0099] In some embodiments, the semiconductor device further includes a fourth register, a fifth register, and a third logic element. The fourth register is configured to store the first bit of data. The fifth register is configured to store the second bit of data. The third logic element is configured to control the third register based on each of the first bit of data and the second bit of data.

[0100] In some embodiments, when at least one of the first input data and the first weight data has a first data value, the first register is disabled.

[0101] In some embodiments, when each of the first input data and the first weight data has a second data value different from the first data value, the first register is activated.

[0102] In some embodiments, the first logic element is further configured to control the first register according to a clock signal, the second logic element is further configured to control the second register according to the clock signal, and the third logic element is further configured to control the third register according to the clock signal.

[0103] In some embodiments, when the first bit metadata has a first logic value, the first input data has a first data value equal to a second logic value different from the first logic value, and when the first bit metadata has a second logic value, the first input data has a second data value different from the second logic value.

[0104] In some embodiments, when the second bit data has a first logic value, the first weight data has a first data value equal to a second logic value different from the first logic value, and when the first bit data has a second logic value, the first input data has a second data value different from the second logic value.

[0105] In some embodiments, the third register is disabled when at least one of the first input data and the first weight data has a first data value, and the third register is activated when each of the first input data and the first weight data has a second data value different from the first data value.

[0106] A semiconductor device is also disclosed. The semiconductor device includes a first processing element, a second logic element, and a third logic element. The first processing element includes a first register and a first logic element. The first register is configured to output first output data. The first logic element is configured to control the first register based on each of first bit data and second bit data. The second logic element is configured to generate first bit data based on first input data. The third logic element is configured to generate second bit data based on first weight data.

[0107] In some embodiments, the semiconductor device further includes a second processing element and a fourth logic element. The second processing element is configured to store second output data based on each of the second input data, the first weight data, the third bit data, and the second bit data. The fourth logic element is configured to generate the third bit data based on the second input data.

[0108] In some embodiments, the semiconductor device further includes a second processing element and a fourth logic element. The second processing element is configured to store second output data based on each of the second weight data, the first input data, the third bit data, and the first bit data. The fourth logic element is configured to generate the third bit data based on the second weight data.

[0109] In some embodiments, the first register is disabled when at least one of the first bit data and the second bit data has a first logic value, and the first register is enabled when each of the first bit data and the second bit data has a second logic value different from the first logic value.

[0110] In some embodiments, the first processing element further includes a second register and a fourth logic element, wherein the second register is configured to output the first input data, and the fourth logic element is configured to control the second register according to each of the first bit data and the second bit data.

[0111] In some embodiments, when the first bit metadata has a first logic value, the first input data has a first data value equal to a second logic value different from the first logic value, and when the first bit metadata has a second logic value, the first input data has a second data value different from the second logic value.

[0112] In some embodiments, the second register is disabled when at least one of the first bit data and the second bit data has a first logic value, and is enabled when each of the first bit data and the second bit data has a second logic value.

[0113] A method for operating a semiconductor device is also disclosed. The method includes the following steps: storing first input data in a first register; generating first bit data based on the first input data; generating second bit data based on first weight data; controlling the first register by a first logic element based on each of the first bit data and the second bit data; and calculating the first input data and first weight data based on the first bit data and the second bit data.

[0114] In some embodiments, the operating method of the semiconductor device further includes the following steps: storing the first weight data in a second register; and controlling the second register according to each of the first bit data and the second bit data by a second logic element.

[0115] In some embodiments, the operating method of the semiconductor device further includes the following steps: disabling each of the first register and the second register when at least one of the first bit data and the second bit data has a first logic value; and activating each of the first register and the second register when each of the first bit data and the second bit data has a second logic value different from the first logic value.

[0116] In some embodiments, when the first bit metadata has a first logic value, the first input data has a first data value equal to a second logic value, and when the first bit metadata has a second logic value, the first input data has a second data value different from the second logic value.

[0117] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made to these equivalent constructions without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: a first register for storing first input data; a second register for storing first weight data; a third register for outputting first output data according to each of the first input data and the first weight data; as well as a first logic element for controlling the first register according to each of the first bit data and the second bit data, The first bit data and the second bit data correspond to the first input data and the first weight data respectively.

2. The semiconductor device according to claim 1, wherein Also includes: A second logic element is used to control the second register according to each of the first bit data and the second bit data.

3. The semiconductor device according to claim 2, wherein Also includes: a fourth register for storing the first bit of metadata; a fifth register for storing the second bit data; and A third logic element is used to control the third register according to each of the first bit data and the second bit data.

4. The semiconductor device according to claim 3, wherein in: The first logic element is further used to control the first register according to a clock signal. The second logic element is further configured to control the second register according to the clock signal, and The third logic element is further configured to control the third register according to the clock signal.

5. A semiconductor device, characterized in that: Include: a first processing element configured to store first output data according to each of the first input data, the first weight data, the first bit data, and the second bit data, the first processing element comprising: a first register, configured to output the first output data; as well as a first logic element for controlling the first register according to each of the first bit data and the second bit data; a second logic element, configured to generate the first bit of data according to the first input data; as well as A third logic element is used to generate the second bit data according to the first weight data.

6. The semiconductor device according to claim 5, wherein Also includes: a second processing element configured to store second output data according to each of the second input data, the first weight data, the third bit data, and the second bit data; as well as A fourth logic element is used to generate the third bit data according to the second input data.

7. The semiconductor device according to claim 6, wherein Also includes: a second processing element configured to store second output data according to each of second weight data, the first input data, third bit data, and the first bit data; and A fourth logic element is used to generate the third bit data according to the second weight data.

8. The semiconductor device according to claim 7, wherein The first processing element further comprises: a second register for outputting the first input data; and A fourth logic element is used to control the second register according to each of the first bit data and the second bit data.

9. A method for operating a semiconductor device, characterized in that: Include: A first register stores first input data; generating a first bit of metadata according to the first input data; generating second bit data according to the first weight data; controlling the first register by a first logic element according to each of the first bit data and the second bit data; as well as The first input data and the first weight data are calculated according to the first bit data and the second bit data.

10. The operating method according to claim 9, characterized in that: Also includes: disabling each of the first register and the second register when at least one of the first bit data and the second bit data has a first logic value; as well as When each of the first bit data and the second bit data has a second logic value different from the first logic value, each of the first register and the second register is activated.

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