Chip test log analysis method and device, storage medium and computer equipment

Abstract

The embodiment of the invention discloses a chip test log analysis method and device, a storage medium and computer equipment. The method comprises the steps of receiving a test log compression package in a communication board, receiving an instruction of the communication board, obtaining a chip test result of a test board in the communication board according to the instruction, determining whether the test log compression package has a first test log package or not based on the test result, and if yes, sending the test log package to the communication board; if yes, analyzing the test log compressed package with the first test log package, and if not, not analyzing the test log compressed package. According to the scheme provided by the embodiment of the invention, the log packets generated after the chip is tested can be screened, so that only the log packets failed in test are analyzed, and the analysis efficiency of the log packets is improved while the calculation amount of a host is reduced.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a chip test log parsing method, device, storage medium and computer equipment. Background Art

[0002] In the field of chip testing, comprehensive and accurate chip testing is crucial. Currently, during the interaction between the test board and the host computer, the chip test establishes command communication and transmits logs in real time to the host computer, which typically refers to a computer or control system. These command packets not only contain control commands for the test board but also provide feedback on various test statuses, including "PASS" (test success) or "NG" (test failure). One of the core tasks of the host computer is to receive test results and test logs.

[0003] Currently, log packages contain both NG test results and a large number of PASS test results. In actual chip testing scenarios, test board testing often generates large amounts of PASS data. When the host receives and parses this massive amount of test data, the system load increases dramatically. As the number of tests continues to increase, processing thousands of test logs significantly increases the host's processing burden, resulting in a decrease in the host's processing capacity, reduced testing efficiency, and even disrupting the normal progress of the entire testing process. Summary of the Invention

[0004] The embodiments of the present application provide a chip test log parsing method, apparatus, storage medium, and computer equipment, which can filter the log packets generated after the chip is tested, so that only the log packets that fail the test are parsed, thereby reducing the host's computing power while improving the parsing efficiency of the log packets.

[0005] The present application provides a chip test log parsing method, which is applied to a chip test log parsing device. The chip test log parsing device includes a host, a communication board, and multiple test boards connected to the communication board, including:

[0006] receiving a test log compressed package in the communication board; and

[0007] receiving an instruction from the communication board, and obtaining a chip test result of the test board in the communication board according to the instruction;

[0008] Based on the test result, determining whether the test log compressed package contains a first test log package;

[0009] If yes, parsing the test log compressed package containing the first test log package;

[0010] If not, the test log compressed package is not parsed.

[0011] The present application also provides a device for parsing a chip test log. The device comprises a host, a communication board, and a plurality of test boards connected to the communication board, including:

[0012] A receiving unit, configured to receive a compressed test log package in the communication board;

[0013] an acquiring unit, configured to receive an instruction from the communication board and acquire a chip test result of each test board on the communication board according to the instruction;

[0014] a determining unit, configured to determine whether the test log compressed package contains a first test log package based on the test result;

[0015] The processing unit is configured to parse the test log compressed package containing the first test log package when the determination module determines that the test log package exists, and not parse the test log compressed package when the determination module determines that the test log package exists.

[0016] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed on a computer, the computer is caused to execute the chip test log parsing method as described above.

[0017] An embodiment of the present application further provides a computer device, comprising a memory and a processor, wherein the processor executes the chip test log parsing method as described above by calling a computer program stored in the memory.

[0018] The chip test log parsing method, device, storage medium and computer equipment provided in the embodiments of the present application can receive a test log compressed package in a communication board, and receive instructions from the communication board, obtain the chip test results of each test board on the communication board according to the instructions, and determine whether the test log compressed package contains a first test log package based on the test results. If so, the test log compressed package containing the first test log package is parsed; if not, the test log compressed package is not parsed. The solution provided in the embodiments of the present application can screen the log packages generated after the test chip is tested, so that only the log packages that failed the test are parsed, thereby improving the parsing efficiency of the log packages while reducing the host's computing power. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 A first flow chart of the chip test log parsing method provided in an embodiment of the present application.

[0021] Figure 2 A schematic diagram of the architecture of a chip test log parsing device provided in an embodiment of the present application.

[0022] Figure 3 A schematic diagram of a process for obtaining chip test results from a test board provided in an embodiment of the present application.

[0023] Figure 4 A second flow chart of the chip test log parsing method provided in an embodiment of the present application.

[0024] Figure 5 A schematic diagram of a scenario for generating a test log compression package provided in an embodiment of the present application.

[0025] Figure 6 This is a third flow chart of the chip test log parsing method provided in an embodiment of the present application.

[0026] Figure 7 A schematic diagram of another scenario for generating a test log compression package provided in an embodiment of the present application.

[0027] Figure 8 A schematic diagram of the structure of a chip test log parsing device provided in an embodiment of the present application.

[0028] Figure 9 A schematic diagram of the computer device structure provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0030] It should be noted that, in this document, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0031] The embodiments of the present application provide a method, apparatus, storage medium, and computer device for parsing a chip test log. Specifically, the chip test log parsing method of the embodiments of the present application can be executed by a computer device or a server, wherein the computer device can be a terminal. The terminal can be a smartphone, a tablet computer, a laptop computer, a touch screen, a game console, a personal computer (PC), a personal digital assistant (PDA), a smart home device, etc. The terminal can also include a client, which can be a media player client or an instant messaging client, etc.

[0032] See also Figure 1 The specific process of parsing the chip test log can be as follows:

[0033] Step 101: Receive a test log compressed package in a communication board.

[0034] In one embodiment, the communication board is connected to the host and then connected to several test boards. The communication board is provided with multiple serial ports and each serial port is connected to a test board. Figure 2 As shown, for example, the communication board is provided with N serial ports, so the communication board can realize the connection with N test boards at most. Figure 2 The N serial ports are numbered 1 to N respectively, and the test boards with the same number are connected to the serial ports in a one-to-one correspondence.

[0035] Furthermore, the communication board may also include a communication board main control unit connected to each serial port, and the communication board performs corresponding operations under the control of the communication board main control unit. The communication board can transmit data with the host via a TCP connection, and multiple test boards on the same communication board share a TCP connection to transmit log packets. For example, the main control unit of the communication board has a TCP port. After the communication board establishes a TCP connection with the host, the communication board will actively transmit the test log compressed package obtained from the test board to the host. The communication board can send the test log compressed package to the host via a TCP connection in the form of a data packet.

[0036] In one embodiment, the communication board may further include a serial port expansion chip, which can communicate with the main control unit via an SPI serial port. For example, the communication board can be connected to two serial port expansion chips via two SPI communications. Since each serial port expansion chip is provided with N serial ports, the communication board can be connected to up to 2N test boards. Other examples may provide a single or more than two serial port expansion chips to meet the needs of other scenarios with a number of test boards, which is not limited in this application. The chip to be tested corresponding to the test board connection may be referred to as a chip to be tested. Here, the connection required for the test can be established between the host and each chip to be tested through the communication board.

[0037] In one embodiment, command data is sent by the host to test the chips connected to each test board. Each test board performs a corresponding test based on the command data it receives and generates a corresponding test log compressed package. Each test board then transmits the test log package to the communication board via the corresponding serial port. The data of each test board is transmitted via the corresponding serial port. Each serial port has a cache function. For example, the maximum cache of a single serial port is 1K. The data cached by each serial port (referred to as "cache data") is read by the communication board to achieve data transmission between the test board and the communication board.

[0038] The compressed test log package can contain information such as test time, test parameters, and chip response data. The host, using the connection channel established by the communication board and following the preset communication protocol, sequentially receives the compressed test log packages from each test board, completing the initial data collection. For example, in a large-scale memory chip testing scenario, multiple test boards simultaneously test different batches of memory chips for read / write speed, storage capacity, and other items, generating compressed test log packages. The host can quickly access this data through the communication board to prepare for subsequent analysis.

[0039] In one embodiment, the communication board can package the log data and then transmit it to the host. The specific packaging process is that after receiving the log data from the test board, the communication board packages the log data according to the log data header + data type + data source number + data length + data content. The corresponding test board can also be distinguished by the data source number, so that the TCP connection can output the log data of the test board, that is, the test log compressed package. When a host needs to connect to many test boards, this method can greatly reduce the number of TCP connections, making it easier for the host to receive large amounts of log data.

[0040] In one embodiment, in order to further improve the efficiency of sending test data packets, a differential compression algorithm can also be used, that is, only the difference data between the current test log compression package and the previous test log compression package (such as only updating the field) is transmitted, thereby reducing bandwidth occupancy, reducing the amount of transmitted data and thus improving the transmission speed.

[0041] Step 102: Receive an instruction from the communication board, and obtain chip test results of each test board on the communication board according to the instruction.

[0042] In one embodiment, a communication board is provided with multiple test ports, each of which is connected to a test board. After the test is completed, each test board will generate a test result based on the chip test situation. The result is generally presented in a specific data format, such as "PASS" indicating that the chip passed the test, and "NG" indicating that the chip failed. After the test board generates the test result, it can be transmitted to the communication board through the test port. At this time, the communication board will send an end instruction to the host to notify the host that the test board has completed the chip test. After receiving the end instruction, the host can further obtain the chip test result of the test board from the communication board according to the instruction. Specifically, the host sends a query instruction to each test port based on the correspondence between the port and the test board. After receiving the instruction, the test port returns the test result of the chip on the corresponding test board to the host. Taking mobile phone chip testing as an example, different test ports are connected to different models of mobile phone chip test boards. In this way, the host can accurately obtain the test result of each chip, which is convenient for subsequent screening of unqualified chips.

[0043] In other embodiments, a unique test board ID can be bound to the physical port (such as a USB 3.0 interface) of each communication board. The host can monitor the port activity in real time through the Port Status Register (PSR), and an FPGA chip can be integrated on the communication board to pre-parse the original log data, extract key fields such as test results or error codes, and generate a lightweight summary (Metadata) to indicate the test results. After obtaining the test results, the communication board can generate an end instruction and transmit it to the host. After receiving the end instruction, the host can further obtain the above test results from the communication board according to the instruction.

[0044] In one embodiment, if Figure 3 As shown, the step of obtaining the chip test results of each test board on the communication board may include:

[0045] 1021, obtain chip specifications and test types on the test board;

[0046] 1022, determining a standard value of a current test parameter according to chip specifications and test type;

[0047] 1023 , based on the chip measurement value and the standard value on the test board, determine whether the test board has the first test result or the second test result.

[0048] Specifically, chip specifications may include model, process technology, storage capacity, operating voltage range, clock frequency, etc. These factors determine the basic performance of the chip, and the test type can be determined based on the application scenario and quality requirements of the chip, such as functional testing, performance testing, reliability testing and other different categories. After determining the chip specifications and test types, the corresponding test parameter standard values can be determined based on relevant industry standards, chip design documents or product specifications. The standard values of test parameters for chips with different specifications and test types vary significantly.

[0049] Next, when testing the chip, the test equipment collects various measured values from the chip on the test board. These values reflect the chip's performance during the actual test. The measured values are carefully compared with previously determined standard values to determine the test results of the test board. If the chip's measured values fail to meet the standard values—for example, if the data processing speed of the computing chip is lower than the standard value, or if the data read and write error rate of the memory chip is higher than the standard value—this indicates that the chip has a performance or functional issue. In this case, the test board's test result is determined as the first test result, meaning the test failed. Conversely, if the chip's measured values fully meet or even exceed the standard values, this indicates that the chip's performance and functionality meet the standards. The test board's test result is determined as the second test result, meaning the test succeeded. By obtaining the chip specifications and test type, the standard values of the current test parameters are determined, providing an accurate basis for subsequent test judgments. In actual use, the performance requirements for chips of different specifications and test types vary. Only by clarifying these differences and setting corresponding standard values can we accurately determine whether the chip meets the requirements. This embodiment specifies different standards when testing different chips and different test types, thereby ensuring accurate and reliable test results and avoiding misjudgments.

[0050] Step 103 : Based on the test result, determine whether the test log compression package contains the first test log package. If so, execute step 104 ; if not, execute step 105 .

[0051] In one embodiment, after the host obtains the chip test results of each test board, it can be traversed and checked to determine the first test result that represents a failure. Specifically, a hardware trigger (Hardware Trigger) can be pre-buried on the communication board side. When the test result in the log packet is detected to be NG, the test result is determined to be the first test result of a test failure, and the first test log packet exists in the test log compression packet. Then, an interrupt signal (Interrupt) can be sent to the host, and the cache log area of the test board is marked as a "pending extraction" state. Correspondingly, when the test result in the log packet is detected to be PASS, the test result can be determined to be the second test result of a successful test, and the second test log packet exists in the test log compression packet.

[0052] Furthermore, once a chip with an "NG" test result is discovered, the host computer can determine the presence of a first test log package within the compressed test log package. These first test log packages record detailed information about the failed chip's testing process, providing key data for subsequent in-depth analysis. During chip testing, if a control chip tests "NG," the host computer can quickly identify its corresponding test port and extract the relevant first test log package, providing a basis for locating the cause of the chip failure.

[0053] In one embodiment, after determining that the first test log package exists in the test log compression package, the method may further include: extracting the test time, communication board address, and test board port of the first test log package, and naming the first test log package according to the test time, communication board address information, and test board port. Specifically, the test time information can clearly identify the specific moment of the chip test, and the communication board address information identifies the source of the test data. In order to facilitate the management and identification of the target log package, the host generates a unique file name for the first test log package based on the extracted test time information, communication board address information, and test board port. Specifically, the naming format can be "test time-communication board address-test board port". For example, if the address of the communication board is 192.168.1.100 and the start time of the NG test for test board 1 and test board 5 is 20250201 03:15:08, the corresponding files can be named 20250201_03-15-08_01_01.log and 20250201_03-15-08_02_05.log.

[0054] Archiving the first test log package to the host's flash memory establishes an organized, visual data storage system. Furthermore, a reasonable naming convention and storage structure facilitate subsequent querying and tracing of test data. When reviewing chip test results for a specific time period or batch, the corresponding log package can be quickly located.

[0055] Step 104: Parse the test log compressed package containing the first test log package.

[0056] In one embodiment, in order to obtain valuable information, the host needs to process the test log compression package containing the first test log package according to the preset parsing rules. During the parsing process, key data will be extracted, such as abnormal parameters, error codes, abnormal chip response time points, etc. during the test process. By analyzing these data, technicians or automation systems can gain an in-depth understanding of the reasons for the failure of the chip test, and determine whether it is a quality problem of the chip itself, interference from the test environment, or a loophole in the test program. For example, in the chip test of smart wearable devices, by parsing the first test log package, it was found that a certain chip had a data transmission error under a specific frequency signal test. After analysis, it was found that there was a defect in the RF module inside the chip, which provided strong support for improving chip design or optimizing the test process.

[0057] For example, the integrity of the log format of the first test log packet can be verified (such as a CRC check), and the structured fields can be extracted to filter out invalid log packet data. Next, the specific error cause can be analyzed based on a preset rule base (Rule Base). For example, if the error code = 0xE001, it is mapped to "power supply voltage out of limit"; if the error code = 0xE002, it is mapped to "signal timing deviation". This embodiment does not further limit this.

[0058] In one embodiment, after parsing the first test log packet, the parsed results can be further compared with preset test standards, and a visual report can be generated to indicate the location and type of abnormal test bits. The preset test standards are a series of performance indicators, parameter thresholds, and functional requirements established based on the chip's design specifications, industry standards, and actual application needs. After obtaining the parsed results of the first test log packet, the host compares each test data item with the corresponding test standard. For example, for a chip's clock frequency test, the standard stipulates that its operating frequency should be stable within a specific range. If the actual frequency in the parsed results exceeds this range, the system will record this discrepancy. Similarly, in a chip's voltage test, if the parsed chip operating voltage is not within the preset normal range, it will also be marked as abnormal. The above-mentioned visual report can graphically present the chip's test layout. For example, when a test bit is abnormal, the system will highlight the abnormal test bit using a special color (such as red), a marker, or a flashing effect. In addition to marking the location of the abnormal test bit, the visual report can also clearly indicate the type of abnormality. Abnormal types may include electrical performance abnormalities (such as voltage, current, and resistance exceeding the standard range), functional abnormalities (such as a certain function of the chip cannot be implemented normally), timing abnormalities (such as excessive signal transmission delay or timing confusion), etc.

[0059] Step 105: Do not parse the test log compressed package.

[0060] In one embodiment, the chip test log parsing method provided in this embodiment does not parse the test log compression package containing the second test log package, that is, the PASS log after the chip test is successful, when it is saved. Only the NG log package needs to be parsed, thereby greatly reducing the parsing load of the system and making the host processing more efficient. This avoids the host's real-time parsing and the need to process large log files, which causes jamming and performance issues, thereby affecting the operation of the host.

[0061] As can be seen from the above, the chip test log parsing method provided by the embodiment of the present application can receive the test log compressed package in the communication board, and receive the instruction of the communication board, obtain the chip test result of each test board on the communication board according to the instruction, and determine whether the test log compressed package contains the first test log package based on the test result. If so, the test log compressed package containing the first test log package is parsed, and if not, the test log compressed package is not parsed. The solution provided by the embodiment of the present application can screen the log packages generated after the test chip is tested, so that only the log packages that failed the test are parsed, thereby improving the parsing efficiency of the log packages while reducing the host computing load.

[0062] See also Figure 4 , which is a second flow chart of the chip test log parsing method provided in the embodiment of the present application. The specific process of this method can be as follows:

[0063] Step 201: Receive a test log compression package, where the test log compression package contains multiple test log packages and has at least one first test log package and / or at least one second test log package.

[0064] The test log compressed package contains multiple test log packages, and the test log compressed package is a collection of the first test log packages or the second test log packages corresponding to all the test boards connected to the current communication board. Figure 5 As shown, each test board will generate a first test log package or a second test log package after the test is completed. When the chips on all test boards have completed the test, these multiple first test log packages and / or second test log packages can be packaged into a test log compression package. Each communication board can correspond to a test log compression package. After the communication board generates a test log compression package from the test log packages of multiple test boards, it is transmitted to the host for subsequent operations.

[0065] Step 202: Receive an instruction from a communication board, and obtain chip test results of multiple test boards on the communication board according to the instruction.

[0066] The host receives an instruction sent by the communication board, which is an instruction for completing the log compression package test. After the host receives the instruction from the communication board, the host obtains the chip test results of multiple test boards in the communication board.

[0067] In step 203, the test results include test results of multiple test boards, and the test results of the multiple test boards in the test results correspond to multiple test log packages in the log compression package. Based on the test results, it is determined whether the first test log package exists in the multiple test log packages in the test log compression package.

[0068] The host obtains the test results in the communication board, each test result corresponds to a test log compression package, the test results include the test results of multiple test boards, and the test results of multiple test boards in the test results correspond to multiple test log packages in the log compression package. For example, the test results contain the test results of four test boards, and there are also four test log packages in the log compression package. The four test log packages correspond to the test results of the four test boards respectively. Based on the test results, the host determines whether the first test log package exists in the multiple test log packages in the log compression package.

[0069] The communication board receives the test results of multiple test boards after the test is completed, packages the test results of the multiple test boards into a total test result, and sends a test completion instruction to the host after the communication board completes the packaging.

[0070] Step 204: If yes, parse the test log compressed package containing the first test log package.

[0071] The host determines whether a log compression package contains the first test log package according to the test result, and parses the test log compression package if the first test log package exists in the test log compression package.

[0072] Since a test log compressed package contains multiple test log packages, the test log packages in the test log compressed package cannot be parsed separately. Therefore, even if there is a first test log package in the test log compressed package, the test log compressed package still needs to be parsed.

[0073] Step 205: If not, the test log compressed package is not parsed.

[0074] The host determines whether the first test log package exists in the log compression package according to the test result. If the first test log package does not exist in the test log compression package, the host does not parse the test log compression package.

[0075] Among them, the host receives the test log compressed package of the communication board, such as Figure 5As shown, the test log compression package contains multiple test log packages, which correspond to corresponding test boards respectively, and the corresponding test boards generate corresponding test log packages and send them to the communication board. The communication board packages the multiple test log packages into a total test log compression package and transmits it to the host. In addition, the communication board receives the test results of multiple test boards and packages them into a total test result. When the packaging is completed, the test completion instruction is sent to the host. The host obtains the test results in the communication board according to the test completion instruction. The test results include the test results of multiple test boards and correspond to the test log packages in the test log compression package respectively. The host determines whether there is a first test log package in the test log compression package based on the test results. If it exists, the test log compression package is parsed. If it does not exist, the test log compression package is not parsed.

[0076] To supplement, the communication board has multiple test ports, each connected to a test board. After the test is completed, each test board generates the corresponding chip test results and notifies the communication board. For example, the test results are displayed as status indicators such as "PASS" (passed) or "NG" (failed).

[0077] For example, the host receives a test log compression package from the communication board. There are four test log packages in one test log compression package. The four test log packages correspond to the four test boards respectively. The test log packages of the four test boards are transmitted to the communication board. The communication board packages the four test log packages into one test log compression package. The communication board also transmits one test log compression package to the host. In addition, the communication board also receives four test results corresponding to the four test boards. The communication board packages the four test results into a total test result and sends a test completion instruction to the host. The host obtains the test results of the four test boards according to the test completion instruction. If test board 1 is the first test log package (test log package of failed test) in the test result, it means that the chip test in test board 1 fails. At this time, the test data of test board 1 needs to be parsed. Since the four test boards are in one test log compression package, the entire test log compression package needs to be parsed to extract the data of the first test log package. If the first test log package does not exist in the four communication boards in the test result, the test log compression package will not be parsed.

[0078] It should be noted that in the actual situation of chip automated testing, the test equipment will have multiple communication boards, and the communication board will have multiple test boards. The test equipment will continuously perform chip testing and continuously generate new test results and log packages. If the test log compression package of each communication board is parsed, it will undoubtedly increase the processing burden of the host, resulting in a decrease in the host processing performance, thereby affecting the test efficiency. The success rate of chip testing in the automated testing process is as high as over 90%. During the chip testing process, most of the log compression packages are in the state of test pass (second test log package). Judging whether the log compression package is parsed based on the test results can effectively reduce the processing pressure on the host caused by parsing each log compression package, avoid reducing the host's processing performance, reduce the host's processing burden, and improve test efficiency.

[0079] As described above, the embodiment of the present application can receive a test log compression package, the test log compression package has at least one first test log package and / or at least one second test log package, obtain the chip test results of each test board on the communication board, if the chip test results of all test boards on the communication board include at least one first test result, then determine that the test log compression package has the first test log package, if the chip test results of all test boards on the communication board are all second test results, then determine that the test log compression package does not have the first test log package, parse the test log compression package with the first test log package, and store the test log compression package without the first test log package. This embodiment can parse the test log compression package with the first test log package after all test boards complete the chip test, without the need to confirm after each test board completes the test, which can reduce the frequent communication between the host and the communication board and reduce the bus bandwidth occupancy.

[0080] In one embodiment, since the test log compressed packages received by the host come from multiple test boards, the first test log package or the second test log package corresponding to each test board is stored in a cache file for ease of management and subsequent processing.

[0081] In one embodiment, the host can further parse the compressed test log package for which the first test log package is determined to be present. This parsing can yield detailed test failure information, such as the test board number corresponding to the failed chip and specific test parameter anomalies. For compressed test log packages that do not contain the first test log package, the host can directly store them without parsing, thus avoiding wasting host resources on parsing large amounts of successful test data.

[0082] See also Figure 6 , which is a third flow chart of the chip test log parsing method provided in the embodiment of the present application. The specific flow of this method can be as follows:

[0083] Step 301: Receive multiple test log compression packages, each of which contains a first test log package or a second test log package.

[0084] The host receives multiple test log compressed packages, each of which is generated by the corresponding test board, such as Figure 7 As shown, each test board will generate a test log package after the test is completed. The test log package may include a first test log package or a second test log package. A test log package corresponding to each test board is transmitted to the communication board. The communication board compresses each test log package into a test log compression package, and the communication board transmits the test log compression package corresponding to each test board to the host.

[0085] For example, if test board 1 fails a test, a test log package containing the first test log package is generated. If test board 2 succeeds, a test log package containing the second test log package is generated, and so on. The communication board compresses each test log package into a test log compressed package. Step 302 receives multiple commands sent by the communication board and, based on the multiple commands, obtains multiple chip test results corresponding to the commands from the communication board.

[0086] The host receives multiple commands sent by the communication board. The commands are commands for completing the log compression package test. When the host receives a command from the communication board, the host obtains the chip test result corresponding to the command in the communication board.

[0087] Each test board within a communication board generates a test result. Multiple communication board commands correspond to the test results of each test board within the communication board. Each test result is transmitted to the communication board. Each time the communication board receives a test result, it sends a command to the host indicating that the corresponding test board has completed the test. The host then retrieves the test result corresponding to the command. For example, if the host receives four commands from the communication board, it will retrieve the test results corresponding to each of the four commands.

[0088] Step 303: Based on the plurality of test results, determine whether the log compression packages corresponding to the plurality of test boards contain the first test log package.

[0089] The host obtains multiple test results, each corresponding to a test board. The host determines whether the log compression packages corresponding to the multiple test boards contain the first test log package according to the multiple test results.

[0090] Step 304: If yes, parse the test log compressed package containing the first test log package;

[0091] The host determines whether the corresponding log compression package contains the first test log package according to each test result, and parses the test log compression package if the first test log package exists in the corresponding test log compression package.

[0092] Step 305: If not, the test log compressed package is not parsed.

[0093] The host determines whether the corresponding log compression package contains the first test log package according to each test result. If the first test log package does not exist in the corresponding test log compression package, the corresponding test log compression package is not parsed.

[0094] Among them, the host receives multiple test log compressed packages from a communication board, such as Figure 7 As shown, each test board generates a corresponding test log package, each test board transmits the corresponding test log package to the communication board, the communication board compresses each test log package into a test log compression package, and the communication board transmits multiple log compression packages to the host. In addition, the communication board receives multiple test results generated by multiple test boards, the communication board sends multiple test results to the host, and the host receives multiple test results, each test result corresponds to the test board, and the host determines whether the corresponding log compression package contains the first test log package based on the multiple test results. If the corresponding test log compression package contains the first test log package, the corresponding test log compression package will be parsed. If not, the corresponding test log compression package will not be parsed.

[0095] For example, the host receives four test log packages from a communication board. There are four test boards in the communication board. The four test boards generate four test log packages respectively and transmit them to the communication board respectively. The communication board compresses the four test log packages into four test log compression packages respectively, and the communication board transmits the four test log compression packages to the host. In addition, the communication board receives four test results generated by the four test boards respectively. The communication board sends the four test results to the host. The host determines whether the four test log compression packages corresponding to the four test results contain the first test log package based on the four test results. If the test log compression package generated by test board 1 contains the first test log package, the test log compression package generated by test board 1 will be parsed. If the test log compression package generated by test board 2 does not contain the first test log package, it will not be parsed.

[0096] It should be noted that the chip testing time on each test board is different. The loading and unloading time, the quality of the chip and the quality of the test board will affect the chip testing time. Some test boards can complete the test earlier, and some test boards complete the test later. If the test log packages of multiple test boards are all in one test log compression package, the test board that completes the test earlier needs to wait for the test board that completes the test later. Only after all test boards send test log packages to the communication board can the communication board send test log packages to the host. The host instantly receives and determines whether the test log compression packages of multiple test log packages are parsed, causing the host to suddenly occupy a large amount of memory processing, the host performance is greatly reduced, and the test efficiency is affected.

[0097] As described above, the communication board compresses a test log of each test board and transmits it to the host, and transmits the test results corresponding to the test log compression in real time, and determines whether the corresponding test log compression package is parsed based on the test results. By transmitting the test log compression package of a single test board in real time and the test results of the corresponding test log compression package, it avoids the instantaneous host receiving and judging multiple test log packages, causing the host to suddenly occupy a large amount of memory processing, the host performance is greatly reduced, and the test efficiency is affected.

[0098] It should also be noted that the communication board transmits a test log compressed package of a test board to the communication board, and transmits the test result corresponding to the test log compressed package to the communication board. The communication board transmits the test log compressed package and the test result to the host respectively. The host receives a test log compressed package and the test result corresponding to the test log compressed package. The test log compressed package includes a first test log package or a second test log package. The host determines whether the test log compressed package is parsed based on the test result. After each test board completes its own chip test, it can directly send the generated test log compressed package to the communication board, which then sends it to the host. There is no need to wait for all multiple test boards connected to the communication board to complete testing before sending the test log compressed package to the host.

[0099] In one embodiment, after the test board completes the test, the communication board can obtain the test results on the test board, wherein each test board will generate test results based on the chip test situation, and the results are generally presented in a specific data format, wherein the test results of the above-mentioned chip may include a first test result and a second test result, such as "PASS" indicating that the chip passes the test, which serves as the second test result, and "NG" indicating that the chip fails the test, which can be used as the first test result.

[0100] In one embodiment, each test board generates a test log package, and the communication board compresses the test log package generated by each test board into a test log compression package to ensure effective transmission of the TCP port.

[0101] In one embodiment, during the process of chip testing on multiple test boards, once a chip with a test result of the first test result (i.e., NG) is found, it can be determined that the test board where the chip is located is the target test board. Next, based on the identification information of the target test board (such as the test board number or test port, etc.), the multiple test log compressed packages received are screened. Because each test log compressed package corresponds to the test result record of a test board, the target test log compressed package corresponding to the target test board can be accurately found and immediately parsed.

[0102] For example, if a test chip is detected as "NG" during testing on multiple test boards, the host can quickly identify the corresponding test port and extract the relevant target test log compressed package for analysis, providing a basis for finding the cause of the chip failure. Since the logs of test failures can be analyzed without waiting for all test boards to complete testing, the test board can be dynamically debugged based on the NG logs during the test process, improving the immediacy of problem feedback and ensuring that testers can quickly identify the chip with test anomalies and solve them in a targeted manner.

[0103] In one embodiment, the communication board can also monitor the status of each test board in real time. When the test completion flag of a test board is 1, it indicates that the test of the test board is completed, and its test result can be obtained immediately. If the chip test result is the first test result that represents a failure, the target test log compressed package can be determined from multiple test log compressed packages based on the port information of the current test board for parsing. In this way, the chip test result can be reported in seconds after the completion of a single test board, thereby supporting rapid shutdown and maintenance. The test log compressed packages remaining after screening do not need to be parsed and can be directly stored, which can avoid the host wasting resources on parsing a large amount of successful test data.

[0104] It's important to note that the data in the target test log compressed package is typically stored in a specific format, such as text, structured data, or binary. To extract valuable information, the host must parse it according to pre-set parsing rules. This parsing process extracts key data, such as abnormal parameters and error codes during the test.

[0105] In one embodiment, the remaining test log compressed packages after screening do not require parsing and can be directly stored. Specifically, if the test results of all chips on the test board are the second test results indicating success, the compressed test log packages can be archived and stored in the host's flash memory without parsing, allowing the host to allocate more computing resources and processing power to other critical tasks, thereby improving overall operational efficiency.

[0106] As shown above, the embodiment of the present application can receive multiple test log compression packages, each test log compression package has a first test log package or a second test log package, obtain the chip test results of each test board on the communication board, determine the target test board corresponding to the first test result, filter the target test log compression package from the multiple test log compression packages according to the identification information of the target test board, parse the target test log compression package, and store the remaining test log compression packages after filtering. In this embodiment, after each test board completes its own chip test, the generated test log compression package can be directly sent to the communication board and sent to the host by the communication board. There is no need to wait for all the multiple test boards connected to the communication board to complete the test before parsing the logs of the test failures, so it has higher timeliness and log analysis efficiency.

[0107] All of the above technical solutions can be combined in any way to form optional embodiments of the present application, and will not be described in detail here.

[0108] In order to implement the above method, an embodiment of the present invention further provides a chip test log parsing device, which can be integrated into a computer device such as a mobile phone, a personal computer, a tablet computer, and the like.

[0109] For example, Figure 8 FIG. 1 is a schematic diagram of a first structure of a chip test log parsing device according to an embodiment of the present invention. The chip test log parsing device includes a host, a communication board, and multiple test boards connected to the communication board, and may specifically include:

[0110] A receiving unit, configured to receive a compressed test log package in the communication board;

[0111] an acquiring unit, configured to receive an instruction from the communication board and acquire a chip test result of each test board on the communication board according to the instruction;

[0112] a determining unit, configured to determine whether the test log compressed package contains a first test log package based on the test result;

[0113] The processing unit is configured to parse the test log compressed package containing the first test log package when the determination module determines that the test log package exists, and not parse the test log compressed package when the determination module determines that the test log package exists.

[0114] The chip test log parsing device proposed in the embodiment of the present invention can receive a test log compressed package in a communication board, and receive an instruction from the communication board, obtain the chip test results of each test board on the communication board according to the instruction, and determine whether the test log compressed package contains a first test log package based on the test result. If so, the test log compressed package containing the first test log package is parsed; if not, the test log compressed package is not parsed. The solution provided in the embodiment of the present application can screen the log packages generated after the test chip is tested, so that only the log packages that failed the test are parsed, thereby improving the parsing efficiency of the log packages while reducing the host's computing power.

[0115] All of the above technical solutions can be combined in any way to form optional embodiments of the present application, and will not be described in detail here.

[0116] An embodiment of the present application also provides a computer device, including a memory and a processor, wherein the processor is configured to execute the process in the chip test log parsing method provided in this embodiment by calling a computer program stored in the memory.

[0117] For example, the computer device mentioned above can be a terminal device with corresponding functions such as a mobile phone, tablet computer, personal computer, cloud computer, etc. Figure 9 , Figure 9 A schematic diagram of the structure of a computer provided in an embodiment of the present application.

[0118] The computer device 500 may include components such as a memory 501 and a processor 502. Those skilled in the art will appreciate that Figure 9 The computer device structure shown in the figure does not constitute a limitation to the computer device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0119] Memory 501 can be used to store applications and data. The applications stored in memory 501 include executable code. Applications can be composed of various functional modules. Processor 502 executes various functional applications and data processing by running the applications stored in memory 501.

[0120] The processor 502 is the control center of the computer device. It uses various interfaces and lines to connect the various parts of the entire computer device. By running or executing applications stored in the memory 501 and calling data stored in the memory 501, it performs various functions of the computer device and processes data, thereby monitoring the computer device as a whole.

[0121] In this embodiment, the processor 502 in the computer device loads the executable code corresponding to one or more application processes into the memory 501 according to the following instructions, and the processor 502 runs the application stored in the memory 501 to execute:

[0122] receiving a test log compressed package in the communication board; and

[0123] receiving an instruction from the communication board, and obtaining a chip test result of each test board on the communication board according to the instruction;

[0124] Based on the test result, determining whether the test log compressed package contains a first test log package;

[0125] If yes, parsing the test log compressed package containing the first test log package;

[0126] If not, the test log compressed package is not parsed.

[0127] Those skilled in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be accomplished by instructions, or by controlling related hardware through instructions. The instructions may be stored in a computer-readable storage medium and loaded and executed by a processor.

[0128] To this end, an embodiment of the present application provides a storage medium storing a plurality of instructions that can be loaded by a processor to execute the steps of any of the data calculation methods provided in the embodiments of the present application. For example, the instructions can execute the following steps:

[0129] receiving a test log compressed package in the communication board; and

[0130] receiving an instruction from the communication board, and obtaining a chip test result of each test board on the communication board according to the instruction;

[0131] Based on the test result, determining whether the test log compressed package contains a first test log package;

[0132] If yes, parsing the test log compressed package containing the first test log package;

[0133] If not, the test log compressed package is not parsed.

[0134] The specific implementation of the above operations can be found in the previous embodiments and will not be repeated here.

[0135] The storage medium may include a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0136] Since the instructions stored in the storage medium can execute the steps in any data calculation method provided in the embodiments of the present application, the beneficial effects that can be achieved by any data calculation method provided in the embodiments of the present application can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

[0137] In the embodiments of the computer device and readable storage medium provided in this application, all technical features of the embodiments of the above-mentioned method are included. The expanded and explained contents of the specification are applicable to the embodiments of the above-mentioned positioning method in the same way and will not be repeated here.

[0138] An embodiment of the present application also provides a chip, including a memory and a processor, wherein the memory is used to store programs, and the processor is used to call and run programs from the memory, so that a device equipped with the chip executes the methods in the various possible embodiments above.

[0139] In the above embodiments, the description of each embodiment has its own focus. For the part not described in detail in a certain embodiment, please refer to the detailed description of the chip test log parsing device above, which will not be repeated here.

[0140] The chip test log parsing method provided in the embodiment of the present application and the chip test log parsing device in the above embodiment have the same concept. The specific implementation process is detailed in the embodiment of the chip test log parsing device, which will not be repeated here.

[0141] It should be noted that, for the chip test log parsing method described in the embodiment of the present application, a person of ordinary skill in the art can understand that all or part of the process of implementing the chip test log parsing method described in the embodiment of the present application can be completed by controlling the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium, such as a memory, and executed by at least one processor, and the execution process may include the process of the embodiment of the chip test log parsing method. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory (RAM), etc.

[0142] The above is a detailed introduction to the chip test log parsing method, device, storage medium and computer equipment provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

[0143] The above description is merely an embodiment of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A chip test log parsing method, applied to a chip test device, wherein the chip test log parsing device comprises a host, a communication board, and a plurality of test boards connected to the communication board, characterized in that: include: receiving a test log compressed package in the communication board; as well as receiving an instruction from the communication board, and obtaining a chip test result of the test board in the communication board according to the instruction; Based on the test result, determining whether the test log compressed package contains a first test log package; If yes, parsing the test log compressed package containing the first test log package; If not, the test log compressed package is not parsed.

2. The chip test log parsing method according to claim 1, wherein: The receiving of the test log compressed package in the communication board includes: A test log compression package is received, where the test log compression package contains multiple test log packages and has at least one first test log package and / or at least one second test log package.

3. The chip test log parsing method according to claim 2, characterized in that: The receiving the instruction from the communication board and obtaining the chip test result of the test board on the communication board according to the instruction includes: receiving an instruction from the communication board, and obtaining chip test results of the plurality of test boards on the communication board according to the instruction; Wherein, based on the test result, determining whether the test log compression package contains the first test log package includes: The test results include test results of multiple test boards, and the test results of multiple test boards in the test results respectively correspond to the multiple test log packages in the log compression package. Based on the test results, it is determined whether the first test log package exists in the multiple test log packages in the test log compression package.

4. The chip test log parsing method according to claim 1, wherein: The receiving of the test log compressed package in the communication board includes: A plurality of the test log compressed packages are received, each of the test log compressed packages having one of the first test log package and one of the second test log package.

5. The chip test log parsing method according to claim 4, characterized in that: The receiving the instruction from the communication board and obtaining the chip test result of the test board on the communication board according to the instruction includes: receiving a plurality of instructions sent by the communication board, and obtaining, according to the plurality of instructions, chip test results corresponding to the instructions in the communication board for a plurality of times; Wherein, based on the test result, determining whether the test log compression package contains the first test log package includes: Based on the multiple test results, it is determined whether the log compression packages corresponding to the multiple test boards contain the first test log package.

6. The chip test log parsing method according to claim 1, wherein: The obtaining of chip test results of each test board on the communication board includes: Obtain chip specifications and test types on the test board; Determine the standard value of the current test parameter according to the chip specification and test type; The test board is determined to have a first test result or a second test result based on the chip measurement value on the test board and the standard value.

7. The chip test log parsing method according to claim 1, wherein: After determining that the first test log package exists in the test log compressed package, the method further includes: Extracting the test time, communication board address, and test board port of the first test log packet; The first test log package is named according to the test time, the communication board address information, and the test board port.

8. A chip test log parsing device, comprising a host, a communication board, and a plurality of test boards connected to the communication board, characterized in that: include: A receiving unit, configured to receive a compressed test log package in the communication board; an acquiring unit, configured to receive an instruction from the communication board and acquire a chip test result of each test board on the communication board according to the instruction; a determining unit, configured to determine whether the test log compressed package contains a first test log package based on the test result; The processing unit is configured to parse the test log compressed package containing the first test log package when the determination module determines that the test log package exists, and not parse the test log compressed package when the determination module determines that the test log package exists.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed on a computer, the computer is caused to execute the method according to any one of claims 1 to 7.

10. A computer device comprising a memory and a processor, characterized in that: The processor executes the method according to any one of claims 1 to 7 by calling the computer program stored in the memory.

Images