System and method for realizing wireless signal storage and accumulation based on FPGA (Field Programmable Gate Array)

Abstract

The invention relates to a system for realizing wireless signal storage and accumulation based on an FPGA (Field Programmable Gate Array), which comprises a radio frequency transceiving chip, the FPGA, an Ethernet PHY (Physical Layer) chip, a serial port chip, a serial port upper computer, a network port upper computer and a DDR (Double Data Rate) memory, and is characterized in that the radio frequency transceiving chip is connected with the FPGA, the radio frequency transceiving chip is used for transceiving wireless signals, the FPGA is connected with the serial port upper computer through the serial port chip, and the Ethernet PHY chip is connected with the DDR memory through the Ethernet PHY chip. The FPGA sends the data to a network port upper computer through the Ethernet PHY chip, and the DDR memory stores the data received by the radio frequency transceiver chip. By adopting the system and the method for realizing wireless signal storage and accumulation based on the FPGA, real-time coherent accumulation can be met by utilizing the high-speed read-write characteristic of a DDR (Double Data Rate) memory, the number of taps and the number of storage frames of each tap can be dynamically adjusted according to actual application requirements, the problem of low resource utilization rate caused by a fixed tap architecture is effectively solved, and the system and the method have high practicability. And the method is suitable for burst communication or complex electromagnetic environment. The Microblaze soft core processor receives a control instruction of an upper computer and adjusts tap parameters in real time, so that the real-time defect of a software adjustable scheme is avoided, and the real-time requirement of high-speed signal processing is met.

Description

Technical Field

[0001] The present invention relates to the field of automatic control, in particular to the field of coherent accumulation, and specifically refers to a system and method for realizing wireless signal storage and accumulation based on FPGA. Background Art

[0002] Coherent integration is a signal processing technique primarily used in radar, sonar, and communication systems. It improves signal-to-noise ratio and detection performance by aligning and accumulating multiple signal samples in phase. While traditional coherent integration technology can achieve multi-tap signal processing, it suffers from the following key issues in practical applications:

[0003] (1) Fixed tap architecture: Most hardware implementations use a fixed number of taps (such as ASIC-based or fixed-logic FPGA designs), resulting in low resource utilization and inability to adapt to bursty communications or complex electromagnetic environments.

[0004] (2) Real-time defects of software-adjustable solutions: Some systems rely on software to configure tap parameters, but are limited by processor computing power and communication delays, making it difficult to meet the real-time requirements of high-speed signal processing.

[0005] (3) Rigid storage resources: Existing solutions often allocate a fixed storage capacity to each tap, which can easily lead to storage resource waste or data overflow when the signal pulse width or bandwidth changes (such as in frequency hopping communication systems).

[0006] Scenarios where the number of taps needs to be adjusted include: sudden changes in target speed in a radar system, requiring rapid adjustment of the number of accumulated taps to match the Doppler frequency shift; and dynamic allocation of the number of taps and storage depth based on task priority (e.g., when processing multi-channel signals simultaneously) under limited FPGA resources. Summary of the Invention

[0007] The purpose of the present invention is to overcome the shortcomings of the above-mentioned prior art and provide a system and method for wireless signal storage and accumulation based on FPGA that are simple to operate, have good real-time performance, and have a wide range of applications.

[0008] To achieve the above objectives, the system and method for wireless signal storage and accumulation based on FPGA of the present invention are as follows:

[0009] The system for storing and accumulating wireless signals based on FPGA has the following main features: the system includes a radio frequency transceiver chip, an FPGA, an Ethernet PHY chip, a serial port chip, a serial port host computer, a network port host computer, and a DDR memory; the radio frequency transceiver chip is connected to the FPGA and is used for transmitting and receiving wireless signals; the FPGA is connected to the serial port host computer via the serial port chip and receives control instructions from the serial port host computer; the Ethernet PHY chip is connected to the FPGA and the network port host computer is connected to the Ethernet PHY chip; the FPGA sends data to the network port host computer via the Ethernet PHY chip; and the DDR memory is connected to the FPGA and is used for storing data received by the radio frequency transceiver chip.

[0010] Preferably, the FPGA includes a Microblzae soft-core processor, an AXI interconnection module, an SPI controller, a GPIO controller, a BRAM controller, a Timer controller, an AXI4-lite interface, an XADC module and a UART controller. The Microblzae soft-core processor is connected to the AXI interconnection module. The SPI controller, the GPIO controller, the BRAM controller, the AXI4-lite interface, the XADC module and the UART controller are all connected to the AXI interconnection module. The Microblzae soft-core processor is connected to the SPI interface of the radio frequency transceiver chip through the SPI controller to configure the register of the radio frequency transceiver chip. The Microblzae soft-core processor is connected to the control signal interface of the radio frequency transceiver chip through the GPIO controller. The Microblzae soft-core processor is connected to the control signal interface of the radio frequency transceiver chip through the GPIO controller. The BRAM controller is connected to the data driving module of the RF transceiver chip, and the linear frequency modulation signal generated by the Microblzae soft-core processor is sent to the data driving module of the RF transceiver chip through the BRAM controller. The Microblzae soft-core processor is connected to the data storage and coherent accumulation module through the AXI4-lite interface, and is connected to the network port host computer through the Ethernet data transmission module. The data driving module of the RF transceiver chip is connected to the data storage and coherent accumulation module. The data driving module of the RF transceiver chip transmits the received data to the data storage and coherent accumulation module, and sends the data output by the data storage and coherent accumulation module to the network port host computer through the Ethernet data transmission module. The Microblzae soft-core processor is connected to the serial port host computer through the UART controller, and is used to receive control instructions from the serial port host computer and send system information.

[0011] Preferably, the FPGA includes a data storage and coherent accumulation module, which includes a data writing unit, a coherent data accumulation unit and a data calculation unit. The output end of the data writing unit is connected to the coherent data accumulation unit, and the output end of the coherent data accumulation unit is connected to the data calculation unit. The data writing unit stores the data received by the RF transceiver chip in the FIFO, reads the data and sends it to the coherent data accumulation unit. The coherent data accumulation unit divides the DDR4 memory into 40 tap areas of the same size, each area stores the data of a tap, and adjusts the amount of data stored in each tap area according to the number of frames. The data calculation unit simultaneously reads the data in all FIFOs in the coherent data accumulation unit and adds them in a pipeline manner, and sends the accumulated data to the network port host computer through the Ethernet data transmission module.

[0012] Preferably, when the amount of data in the data writing unit FIFO reaches 2KB, the data is read out in a frame of 2KB and sent to the coherent data accumulation unit.

[0013] Preferably, if the number of frames written into the tap area of the coherent data accumulation unit reaches the set number of frames, it switches to the next tap area. When the number of tap areas written reaches the set number of taps, each time a frame of data is written, the data corresponding to one frame of all tap areas is continuously read out.

[0014] The method for wireless signal storage and accumulation based on FPGA is implemented based on the above system. The main feature is that the method comprises the following steps:

[0015] (1) The serial port host computer configures the number of taps and the number of frames stored in each tap, configures the waveform signal transmitted by the RF transceiver chip, and configures the waveform transmission time interval;

[0016] (2) The RF transceiver chip starts to transmit waveform data regularly;

[0017] (3) FPGA receives the echo signal, and the data storage and coherent accumulation module receives and stores the data;

[0018] (4) The data storage and coherent accumulation module stores the tap data in the tap area and performs coherent accumulation operations;

[0019] (5) Send the data to the network port host computer through the Ethernet data transmission module;

[0020] (6) Determine whether the host computer sends a stop command. If so, end the step; otherwise, continue with step (4).

[0021] Preferably, the step (4) comprises the following steps:

[0022] (4.1) Determine whether a trigger start signal is received. If yes, proceed to step (4.2); otherwise, proceed to step (4.3);

[0023] (4.2) Writing a tap data into the corresponding tap area frame by frame;

[0024] (4.3) Determine whether the number of stored tap data reaches the pre-configured number of taps. If so, proceed to step (4.4); otherwise, proceed to step (4.1);

[0025] (4.4) Each time a frame of data is written, a frame of data corresponding to each tap area is read out to a FIFO;

[0026] (4.5) Read data from multiple FIFOs simultaneously and add them in a pipeline manner.

[0027] Preferably, the step (4.5) specifically includes the following steps:

[0028] The data outputted by every six taps are added together to obtain seven data; the obtained seven data are divided into two groups and added together; and the obtained two data are added together to generate the final output data.

[0029] The system and method for implementing wireless signal storage and accumulation based on FPGA are used, which can dynamically adjust the number of taps and storage time length according to actual application requirements, effectively solving the problem of low resource utilization caused by fixed tap architecture, and adapting to burst communication or complex electromagnetic environments. The Microblaze soft-core processor receives host computer control instructions and adjusts tap parameters in real time, avoiding the real-time defects of software-adjustable solutions and meeting the real-time requirements of high-speed signal processing. The present invention can dynamically adjust the storage capacity of each tap according to changes in signal pulse width or bandwidth, avoiding storage resource waste or data overflow problems, and improving the flexibility and utilization of storage resources. Through the pipeline processing of the coherent data accumulation unit and the data operation unit, the signal-to-noise ratio and detection performance are significantly improved, and the signal processing capability of the system is enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is an overall block diagram of the system for wireless signal storage and accumulation based on FPGA of the present invention.

[0031] Figure 2 This is a logical structure diagram of the system for implementing wireless signal storage and accumulation based on FPGA of the present invention.

[0032] Figure 3 This is a structural diagram of the data storage and coherent accumulation module of the system for realizing wireless signal storage and accumulation based on FPGA of the present invention.

[0033] Figure 4 This is a flow chart of the method for implementing wireless signal storage and accumulation based on FPGA of the present invention.

[0034] Figure 5 This is a flow chart of the operation of the storage and accumulation module of the method for implementing wireless signal storage and accumulation based on FPGA of the present invention.

[0035] Figure 6 This is a schematic diagram of a coherent data accumulation module of a system for implementing wireless signal storage and accumulation based on FPGA of the present invention.

[0036] Figure 7 This is a data operation diagram of the system for implementing wireless signal storage and accumulation based on FPGA of the present invention. DETAILED DESCRIPTION

[0037] In order to more clearly describe the technical content of the present invention, further description is given below in conjunction with specific embodiments.

[0038] The present invention discloses a system for implementing wireless signal storage and accumulation based on an FPGA, comprising a radio frequency transceiver chip, an FPGA, an Ethernet PHY chip, a serial port chip, a serial port host computer, a network port host computer, and a DDR memory. The radio frequency transceiver chip is connected to the FPGA and is used for transmitting and receiving wireless signals. The FPGA is connected to the serial port host computer via the serial port chip and receives control instructions from the serial port host computer. The Ethernet PHY chip is connected to the FPGA, and the network port host computer is connected to the Ethernet PHY chip. The FPGA sends data to the network port host computer via the Ethernet PHY chip. The DDR memory is connected to the FPGA and is used for storing data received by the radio frequency transceiver chip.

[0039] As a preferred embodiment of the present invention, the FPGA includes a Microblzae soft-core processor, an AXI interconnection module, an SPI controller, a GPIO controller, a BRAM controller, a Timer controller, an AXI4-lite interface, an XADC module and a UART controller. The Microblzae soft-core processor is connected to the AXI interconnection module, and the SPI controller, GPIO controller, BRAM controller, AXI4-lite interface, XADC module and UART controller are all connected to the AXI interconnection module. The Microblzae soft-core processor is connected to the SPI interface of the RF transceiver chip through the SPI controller to configure the registers of the RF transceiver chip. The Microblzae soft-core processor is connected to the control signal interface of the RF transceiver chip through the GPIO controller. The Microblzae soft-core processor is connected to the control signal interface of the RF transceiver chip through the GPIO controller. The processor is connected to the data drive module of the RF transceiver chip through the BRAM controller, and sends the linear frequency modulation signal generated by the Microblzae soft-core processor to the data drive module of the RF transceiver chip through the BRAM controller. The Microblzae soft-core processor is connected to the data storage and coherent accumulation module through the AXI4-lite interface, and is connected to the network port host computer through the Ethernet data transmission module. The data drive module of the RF transceiver chip is connected to the data storage and coherent accumulation module. The data drive module of the RF transceiver chip transmits the received data to the data storage and coherent accumulation module, and sends the data output by the data storage and coherent accumulation module to the network port host computer through the Ethernet data transmission module. The Microblzae soft-core processor is connected to the serial port host computer through the UART controller, and is used to receive control instructions from the serial port host computer and send system information.

[0040] As a preferred embodiment of the present invention, the FPGA includes a data storage and coherent accumulation module, which includes a data writing unit, a coherent data accumulation unit and a data calculation unit. The output end of the data writing unit is connected to the coherent data accumulation unit, and the output end of the coherent data accumulation unit is connected to the data calculation unit. The data writing unit stores the data received by the RF transceiver chip in the FIFO, reads the data and sends it to the coherent data accumulation unit. The coherent data accumulation unit divides the DDR4 memory into 40 tap areas of the same size, each area stores the data of a tap, and adjusts the amount of data stored in each tap area according to the number of frames. The data calculation unit simultaneously reads the data in all FIFOs in the coherent data accumulation unit and adds them in a pipeline manner, and sends the accumulated data to the network port host computer through the Ethernet data transmission module.

[0041] As a preferred embodiment of the present invention, when the amount of data in the data writing unit FIFO reaches 2KB, the data is read out in a frame of 2KB and sent to the coherent data accumulation unit.

[0042] As a preferred embodiment of the present invention, if the number of frames written into the tap area of the coherent data accumulation unit reaches the set number of frames, it switches to the next tap area. When the number of tap areas written reaches the set number of taps, each time a frame of data is written, the data corresponding to one frame of all tap areas is continuously read out.

[0043] The present invention implements a method for wireless signal storage and accumulation based on FPGA based on the above-mentioned system, wherein the method comprises the following steps:

[0044] (1) The serial port host computer configures the number of taps and the number of frames stored in each tap, configures the waveform signal transmitted by the RF transceiver chip, and configures the waveform transmission time interval;

[0045] (2) The RF transceiver chip starts to transmit waveform data regularly;

[0046] (3) FPGA receives the echo signal, and the data storage and coherent accumulation module receives and stores the data;

[0047] (4) The data storage and coherent accumulation module stores the tap data in the tap area and performs coherent accumulation operations;

[0048] (5) Send the data to the network port host computer through the Ethernet data transmission module;

[0049] (6) Determine whether the host computer sends a stop command. If so, end the step; otherwise, continue with step (4).

[0050] As a preferred embodiment of the present invention, the step (4) includes the following steps:

[0051] (4.1) Determine whether a trigger start signal is received. If yes, proceed to step (4.2); otherwise, proceed to step (4.3);

[0052] (4.2) Writing a tap data into the corresponding tap area frame by frame;

[0053] (4.3) Determine whether the number of stored tap data reaches the pre-configured number of taps. If so, proceed to step (4.4); otherwise, proceed to step (4.1);

[0054] (4.4) Each time a frame of data is written, a frame of data corresponding to each tap area is read out to a FIFO;

[0055] (4.5) Read data from multiple FIFOs simultaneously and add them in a pipeline manner.

[0056] As a preferred embodiment of the present invention, the step (4.5) specifically includes the following steps:

[0057] The data outputted by every six taps are added together to obtain seven data; the obtained seven data are divided into two groups and added together; and the obtained two data are added together to generate the final output data.

[0058] In a specific embodiment of the present invention, a coherent accumulation method is proposed that allows the number of storage taps and storage time length to be adjusted in real time based on the host computer. The system uses the AD9361 RF transceiver chip to implement wireless data transmission and reception. In the embodiments of the present invention, the RF transceiver chip is typically the AD9361 chip, and the AD9361 mentioned in the specification refers to the RF transceiver chip. A Xilinx Ultrascale series FPGA serves as the control core, and a Microblaze-based BlockDesign (i.e., Microblaze soft-core processor) is built. Register configuration of the AD9361 RF transceiver chip is implemented via the SPI interface. The linear frequency modulation signal generated by Microblaze is sent to the BRAM in the data transmission module via the BRAM controller. A UART controller receives control commands from the serial port host computer and transmits system information. Communication between Microblaze and the FPGA's PL side is achieved via the AXI4-lite interface. The number of taps, the number of frames per tap, and the start storage trigger signal are transmitted to the PL side via the AXI4-lite interface. DDR4 SDRAM is used to store data received by the AD9361 RF transceiver chip. The Microblaze soft-core processor is the PS side, and the rest is the PL side.

[0059] The system's operational flow involves configuring the number of taps and the amount of data stored per tap through a host computer. The Microblaze soft-core processor receives commands from the host computer and sends them to the FPGA's programmable logic (PL) via the AXI4-lite interface. Upon receiving the start signal, the PL transmits the linear frequency modulation (LFM) signal stored in BRAM via the AD9361 RF transceiver chip. The AD9361's receiver then receives the signal and implements storage and accumulation functions using DDR4 SDRAM.

[0060] The data storage and coherent accumulation module of DDR4 SDRAM includes a data writing unit, a coherent data accumulation unit and a data calculation unit.

[0061] The data write unit stores data received by the AD9361 RF transceiver chip in a FIFO. When the data volume in the FIFO reaches 2KB, it reads the data out in 2KB frames and feeds it to the coherent data accumulation unit. The coherent data accumulation unit divides the DDR4 SDRAM into 40 tap areas of equal size, each storing data from a tap. The amount of data stored in each tap area can be adjusted based on the number of frames. When the number of frames written to a tap area reaches the set number, it switches to the next tap area. When the number of tap areas written reaches the set number, the data corresponding to one frame from all tap areas is continuously read out for each frame written. The data read unit instantiates 40 FIFOs to temporarily store data output from the DDR4 SDRAM. Each frame of data is written to a FIFO, and the total number of FIFOs written depends on the number of taps. The data calculation unit simultaneously reads data from all FIFOs in the coherent data accumulation unit and adds them together in a pipelined manner. Finally, the accumulated data is sent to the network port host computer via the Ethernet data transmission module.

[0062] Figure 1 The overall system block diagram includes the AD9361 RF transceiver chip, FPGA, Ethernet PHY chip, serial port chip, serial port host computer, and network port host computer. The AD9361 RF transceiver chip implements wireless signal transmission and reception. The FPGA receives control commands from the serial port host computer through the serial port chip, stores and accumulates them, and then sends the data to the network port host computer through the Ethernet PHY chip.

[0063] Figure 2 A Block Design with Microblzae as the core is built for the overall logic block diagram of the system. Each AXI interface is connected through the AXIInterconnect interconnection IP. The RF transceiver chip AD9361 driver module transmits the received data to the data storage and coherent accumulation module. After storage and accumulation, the data is sent to the network port host computer through the Ethernet data transmission module.

[0064] Figure 3 The data storage and coherent accumulation module structure diagram includes a data writing unit, a coherent data accumulation unit, and a data calculation unit.

[0065] Figure 4This is the overall operation flow chart of the system. After the system is powered on and starts running, the serial port host computer first configures the number of taps and the number of frames stored in each tap, configures the waveform signal transmitted by the RF transceiver chip, and configures the waveform transmission time interval; after configuration, the RF transceiver chip starts to transmit waveform data regularly; and stores the received echo signal in the data storage and coherent accumulation module; when the number of stored tap data reaches the pre-configured number of taps, each time a frame of data is written, the data corresponding to the frames of all taps is read out, and after coherent accumulation, the data is sent to the network port host computer through the Ethernet data transmission module until the stop command sent by the serial port host computer is received and the operation ends. Figure 4 Steps "receiving waveforms and storing them in the data storage and coherent accumulation module" to step "coherent accumulation operation" and Figure 5 The operation steps of the data storage and coherent accumulation modules correspond to each other.

[0066] Figure 5 This is the flow chart for the operation of the data storage and coherent accumulation module. Each time a trigger signal is received, a tap data is written into the corresponding tap area. When the tap area with data has reached the tap number, each time a frame of data is written, the data of all tap areas are read out in a frame manner and added in a pipeline manner.

[0067] Figure 6 This is a schematic diagram of a coherent data accumulation unit. Each time a tap data is received, each frame of data is written into the corresponding tap area. When all tap areas are filled, the data of the corresponding frames of all tap areas are continuously read out each time a frame is written.

[0068] Figure 7 Figure 1 shows a diagram of data operations. The data operation unit adds multiple FIFO data output by the coherent data accumulation unit. Since this involves adding up to 40 tap data, direct addition would make timing convergence difficult. To address this, the data is added in a pipelined manner. The first beat adds the data output from every six taps, yielding a total of seven data points. The second beat adds the seven data points from the first beat in two groups. The third beat adds the two data points from the second beat together to generate the final output data.

[0069] This solution is based on the FPGA wireless signal storage and accumulation method, mainly focusing on real-time coherent accumulation and coherent accumulation with adjustable tap number and adjustable frame number.

[0070] The creative point of this solution also includes writing the data received for a long time in frame mode. When the amount of written data reaches the set number of taps, each time a frame of data is written, the corresponding frame of data of each tap is read out at high speed through DDR4 and the data is added in parallel to ensure the real-time performance of coherent accumulation.

[0071] The specific implementation scheme of this embodiment can be found in the relevant descriptions in the above embodiments and will not be repeated here.

[0072] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0073] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" is at least two.

[0074] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0075] The system and method for implementing wireless signal storage and accumulation based on FPGA are used, which can dynamically adjust the number of taps and storage time length according to actual application requirements, effectively solving the problem of low resource utilization caused by fixed tap architecture, and adapting to burst communication or complex electromagnetic environments. The Microblaze soft-core processor receives host computer control instructions and adjusts tap parameters in real time, avoiding the real-time defects of software-adjustable solutions and meeting the real-time requirements of high-speed signal processing. The present invention can dynamically adjust the storage capacity of each tap according to changes in signal pulse width or bandwidth, avoiding storage resource waste or data overflow problems, and improving the flexibility and utilization of storage resources. Through the pipeline processing of the coherent data accumulation unit and the data operation unit, the signal-to-noise ratio and detection performance are significantly improved, and the signal processing capability of the system is enhanced.

[0076] In this specification, the present invention has been described with reference to specific embodiments thereof. However, it will be apparent that various modifications and variations may be made without departing from the spirit and scope of the present invention. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A system for wireless signal storage and accumulation based on FPGA, characterized in that: The system includes a radio frequency transceiver chip, an FPGA, an Ethernet PHY chip, a serial port chip, a serial port host computer, a network port host computer, and a DDR memory. The radio frequency transceiver chip is connected to the FPGA and is used for transmitting and receiving wireless signals. The FPGA is connected to the serial port host computer through the serial port chip and receives control instructions from the serial port host computer. The Ethernet PHY chip is connected to the FPGA, and the network port host computer is connected to the Ethernet PHY chip. The FPGA sends data to the network port host computer through the Ethernet PHY chip. The DDR memory is connected to the FPGA and is used for storing data received by the radio frequency transceiver chip.

2. The system for wireless signal storage and accumulation based on FPGA according to claim 1, characterized in that: The FPGA includes a Microblzae soft-core processor, an AXI interconnection module, an SPI controller, a GPIO controller, a BRAM controller, a Timer controller, an AXI4-lite interface, an XADC module, and a UART controller. The Microblzae soft-core processor is connected to the AXI interconnection module. The SPI controller, the GPIO controller, the BRAM controller, the AXI4-lite interface, the XADC module, and the UART controller are all connected to the AXI interconnection module. The Microblzae soft-core processor is connected to the SPI interface of the radio frequency transceiver chip through the SPI controller to configure the registers of the radio frequency transceiver chip. The Microblzae soft-core processor is connected to the control signal interface of the radio frequency transceiver chip through the GPIO controller. The Microblzae soft-core processor is connected to the control signal interface of the radio frequency transceiver chip through the BR The AM controller is connected to the data driving module of the RF transceiver chip, and sends the linear frequency modulation signal generated by the Microblzae soft-core processor to the data driving module of the RF transceiver chip through the BRAM controller. The Microblzae soft-core processor is connected to the data storage and coherent accumulation module through the AXI4-lite interface, and is connected to the network port host computer through the Ethernet data transmission module. The data driving module of the RF transceiver chip is connected to the data storage and coherent accumulation module. The data driving module of the RF transceiver chip transmits the received data to the data storage and coherent accumulation module, and sends the data output by the data storage and coherent accumulation module to the network port host computer through the Ethernet data transmission module. The Microblzae soft-core processor is connected to the serial port host computer through the UART controller, and is used to receive control instructions from the serial port host computer and send system information.

3. The system for realizing wireless signal storage and accumulation based on FPGA according to claim 1, characterized in that: The FPGA includes a data storage and coherent accumulation module, which includes a data writing unit, a coherent data accumulation unit and a data calculation unit. The output end of the data writing unit is connected to the coherent data accumulation unit, and the output end of the coherent data accumulation unit is connected to the data calculation unit. The data writing unit stores the data received by the RF transceiver chip in the FIFO, reads the data and sends it to the coherent data accumulation unit. The coherent data accumulation unit divides the DDR4 memory into 40 tap areas of the same size, each area stores the data of a tap, and adjusts the amount of data stored in each tap area according to the number of frames. The data calculation unit simultaneously reads the data in all FIFOs in the coherent data accumulation unit and adds them in a pipeline manner, and sends the accumulated data to the network port host computer through the Ethernet data transmission module.

4. The system for realizing wireless signal storage and accumulation based on FPGA according to claim 3, characterized in that: If the amount of data in the data writing unit FIFO reaches 2KB, the data is read out in a frame of 2KB and sent to the coherent data accumulation unit.

5. The system for implementing wireless signal storage and accumulation based on FPGA according to claim 3, characterized in that: If the number of frames written into the tap area of the coherent data accumulation unit reaches the set number of frames, it switches to the next tap area. When the number of tap areas written reaches the set number of taps, each time a frame of data is written, the data corresponding to one frame of all tap areas is continuously read out.

6. A method for wireless signal storage and accumulation based on FPGA implemented based on the system of claim 1, characterized in that: The method comprises the following steps: (1) The serial port host computer configures the number of taps and the number of frames stored in each tap, configures the waveform signal transmitted by the RF transceiver chip, and configures the waveform transmission time interval; (2) The RF transceiver chip starts to transmit waveform data regularly; (3) FPGA receives the echo signal, and the data storage and coherent accumulation module receives and stores the data; (4) The data storage and coherent accumulation module stores the tap data in the tap area and performs coherent accumulation operations; (5) Send the data to the network port host computer through the Ethernet data transmission module; (6) Determine whether the host computer sends a stop command. If so, end the step; otherwise, continue with step (4).

7. The method for realizing wireless signal storage and accumulation based on FPGA according to claim 6, characterized in that: The step (4) comprises the following steps: (4.1) Determine whether a trigger start signal is received. If yes, proceed to step (4.2); otherwise, proceed to step (4.3); (4.2) Writing a tap data into the corresponding tap area frame by frame; (4.3) Determine whether the number of stored tap data reaches the pre-configured number of taps. If so, proceed to step (4.4); otherwise, proceed to step (4.1); (4.4) Each time a frame of data is written, a frame of data corresponding to each tap area is read out to a FIFO; (4.5) Read data from multiple FIFOs simultaneously and add them in a pipeline manner.

8. The method for realizing wireless signal storage and accumulation based on FPGA according to claim 7, characterized in that: The step (4.5) specifically includes the following steps: The data outputted by each of the six taps are added together to obtain seven data; the obtained seven data are divided into two groups and added together; The two obtained data are added together to generate the final output data.

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