Link parameter optimization method and device, equipment and storage medium

Abstract

The invention discloses a link parameter optimization method and device, equipment and a storage medium, and relates to the technical field of servers, and the method comprises the steps that a signal processing part loads firmware stored by the signal processing part to obtain link parameter mapping information under the condition that the server is powered on; the signal processing part determines the slot position information of the slot position where the signal processing part is installed; the signal processing component searches the link parameter recommendation value mapped by the slot position information of the slot position where the signal processing component is installed based on the stored link parameter mapping information, and performs link parameter configuration based on the searched link parameter recommendation value, so that the problem of difficulty in firmware management is solved, and the firmware management difficulty is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of server technology, and in particular to a link parameter optimization method, apparatus, device, and storage medium. Background Art

[0002] The Open Accelerator Module (OAMM) overcomes the density and interconnection limitations of traditional graphics processing units (GPUs) through standardized and modular design. This allows for the integration of more components (including GPUs) into servers and provides greater flexibility in the interconnection between components. However, this also increases the complexity of the high-speed signal channels between components in the server, making it more difficult to maintain the reliability and stability of high-speed signals.

[0003] Currently, to ensure high-speed signal reliability and stability, server development involves tuning parameters for high-speed signal links (such as PCIe) in the lab. The resulting link parameter values are then embedded into the components via firmware. However, different server components typically require different firmware, and changes to the layout and position of components within the server require firmware updates, making firmware management difficult. Summary of the Invention

[0004] The present application provides a link parameter optimization method, apparatus, device and storage medium to at least solve the problem of firmware management difficulties in related technologies.

[0005] The present application provides a link parameter optimization method, applied to a server, the server including at least one signal processing component group and at least one slot group, the signal processing component group including at least one signal processing component, the slot group including at least one slot, the signal processing component being installed in the slot in the slot group corresponding to the signal processing component group to which it belongs, the firmware of the signal processing component storing link parameter mapping information corresponding to the signal processing component group to which it belongs, the link parameter mapping information being used to characterize a mapping relationship between slot information of the slot in the slot group to which it corresponds and recommended link parameter values, the recommended link parameter values being link parameter values that meet link signal requirements and are pre-derived through link signal testing, wherein the method comprises:

[0006] When the server is powered on, the signal processing component loads the firmware stored therein to obtain the link parameter mapping information;

[0007] The signal processing component determines the slot information of the slot in which the signal processing component is installed;

[0008] The signal processing component searches for the link parameter recommended value mapped by the slot information of the slot where the signal processing component is installed based on the link parameter mapping information stored therein, and performs link parameter configuration based on the found link parameter recommended value.

[0009] The present application also provides a link parameter optimization device, applied to a server, the server including at least one signal processing component group and at least one slot group, the signal processing component group including at least one signal processing component, the slot group including at least one slot, the signal processing component being installed in the slot in the slot group corresponding to the signal processing component group to which it belongs, the firmware of the signal processing component storing link parameter mapping information corresponding to the signal processing component group to which it belongs, the link parameter mapping information being used to characterize a mapping relationship between slot information of the slot in the slot group to which it corresponds and recommended link parameter values, the recommended link parameter values being link parameter values that meet link signal requirements and are pre-derived through link signal testing, wherein the device includes:

[0010] a loading module, configured to cause the signal processing component to load the firmware stored therein to obtain the link parameter mapping information when the server is powered on;

[0011] a determination module, configured for the signal processing component to determine the slot information of the slot in which the signal processing component is installed;

[0012] A configuration module is used for the signal processing component to search for the link parameter recommended value mapped by the slot information of the slot where the signal processing component is installed based on the link parameter mapping information stored therein, and to configure the link parameters based on the found link parameter recommended value.

[0013] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned link parameter optimization methods when executing the computer program.

[0014] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned link parameter optimization methods are implemented.

[0015] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned link parameter optimization methods when executed by a processor.

[0016] In an embodiment of the present application, a server includes at least one signal processing component group and at least one slot group, the signal processing component group includes at least one signal processing component, the slot group includes at least one slot, the signal processing component is installed in the slot in the slot group corresponding to the signal processing component group to which it belongs, and the firmware of the signal processing component stores the link parameter mapping information corresponding to the signal processing component group to which it belongs, the link parameter mapping information is used to characterize the mapping relationship between the slot information of the slot in the corresponding slot group and the recommended link parameter value, and the recommended link parameter value is a link parameter value that meets the link signal requirements obtained in advance through a link signal test. In this way, when the server is powered on, the signal processing component loads the stored link parameter mapping information; the signal processing component determines the slot information of the slot in which it is installed; the signal processing component searches for the recommended link parameter value mapped to the slot information of the slot in which it is installed based on the stored link parameter mapping information, and performs link parameter configuration based on the found recommended link parameter value. It can be seen that by adopting the above technical solution, the signal processing components in the same signal processing component group can use the same firmware, which reduces the difficulty of firmware management. Moreover, by setting a mapping relationship between the slot information of the slot stored in the firmware of the signal processing component and the recommended link parameter value, the signal processing component can determine the recommended link parameter value based on the slot information of the slot in which it is installed. In this way, the decoupling between the signal processing component and its layout position in the server (and the slot in which it is installed) can be achieved. Even if the layout position of the signal processing component in the server changes (i.e., it is moved from one slot to another), the signal processing component can obtain the recommended link parameter value that matches its layout position without changing the firmware, further reducing the difficulty of firmware management and increasing firmware compatibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 This is a flow chart of a link parameter optimization method provided by an embodiment of the present application;

[0019] Figure 2 This is a schematic diagram of the structure of a server provided in an embodiment of the present application;

[0020] Figure 3 This is a schematic diagram of a link where a graphics processor is located, provided in an embodiment of the present application;

[0021] Figure 4This is a schematic diagram of the structure of another server provided in an embodiment of the present application;

[0022] Figure 5 This is a structural diagram of another server provided in an embodiment of the present application;

[0023] Figure 6 This is a structural diagram of another server provided in an embodiment of the present application;

[0024] Figure 7 It is a structural diagram of a link parameter optimization device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0026] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0027] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0028] After research, the applicant found that OAM has broken through the limitations of traditional graphics processing units (GPUs) in density, interconnection, heat dissipation and ecological compatibility through standardized and modular design, providing scalable, energy-efficient, open and flexible accelerator solutions for data centers and supercomputing scenarios. Specifically, by defining a unified mechanical structure, power supply specifications, heat dissipation interface and high-speed interconnection standards, accelerators from different manufacturers (such as GPUs, FPGAs, ASICs) can be compatible with the same server; through modular design, the GPU core is decoupled from functions such as heat dissipation, power supply, and interconnection, supporting a more compact layout (such as vertical stacking of multiple cards), and integrating high-speed interconnection to improve the computing power density per unit space. This design allows more GPUs to be integrated into the server, and the interconnection between components is more flexible, which increases the overall density of the server and the connection flexibility between components. However, the complexity of the high-speed signal channels between the components in the server increases, making it more difficult to maintain the reliability and stability of high-speed signals.

[0029] Currently, to ensure the reliability and stability of high-speed signals, one approach is to decouple high-speed signal links from fixed link parameters and instead use a parameter adaptation strategy, automatically testing parameters to establish the link each time the server is started. However, this only ensures that signal quality and bit error rates meet the relevant specifications for high-speed signal links, but cannot guarantee higher standards. Therefore, another approach has emerged. During server development, parameters for high-speed signal links (such as PCIe) are adjusted in the lab to optimize signal integrity and eye diagrams within the server. These high-speed signal link parameter values are ultimately embedded in the components as firmware and loaded upon startup. While parameter adaptation can achieve better signal quality and lower bit errors than adaptive parameters, different components in a server typically require different firmware, making it difficult to standardize firmware and making management difficult. Furthermore, changes in component layout and interoperability within the server require firmware changes, making firmware management difficult. Even using the wrong firmware can cause other issues.

[0030] In view of this, the present application provides a link parameter optimization method, apparatus, device and storage medium. The link parameter optimization method is first described in detail below.

[0031] Figure 1This is a flowchart of a link parameter optimization method provided by an embodiment of the present application. The method is applied to a server, and the server includes at least one signal processing component group and at least one slot group. The signal processing component group includes at least one signal processing component, and the slot group includes at least one slot. The signal processing component is installed in a slot in the slot group corresponding to the signal processing component group to which it belongs. The firmware of the signal processing component stores link parameter mapping information corresponding to the signal processing component group to which it belongs. The link parameter mapping information is used to characterize the mapping relationship between the slot information of the slot in the corresponding slot group and the recommended link parameter value. The recommended link parameter value is a link parameter value that meets the link signal requirements and is obtained in advance through link signal testing. The method can be executed by an electronic device, which can be exemplarily understood as a device with a link parameter optimization function in the signal processing component.

[0032] Specifically, for each signal processing component group, there is a corresponding slot group, and the multiple signal processing components in the signal processing component group are installed in the multiple slots in the corresponding slot group.

[0033] Specifically, for each signal processing component in each signal processing component group, the signal processing component stores firmware, which stores link parameter mapping information corresponding to the signal processing component group to which the signal processing component belongs. This means that there is a one-to-one correspondence between the signal processing component group, the slot group, and the link parameter mapping information. Furthermore, the link parameter mapping information includes a mapping relationship between slot information and recommended link parameter values for each slot in the corresponding slot group. This means that for each slot in the slot group, slot information and recommended link parameter values for the signal processing component installed therein are provided, and the slot information and recommended link parameter values for the same slot are mapped to each other.

[0034] In one example, the at least one signal processing component group includes at least one of the following: an accelerator group, a retimer group, an expander group, and a central processing unit group.

[0035] Accordingly, at least one slot group includes at least one of the following: an acceleration slot group (including at least one acceleration slot), a retiming slot group (including multiple retiming slots), an expansion slot group (including at least one expansion slot), and a central processing slot group (including at least one central processing slot). For example, the accelerator group includes a graphics processor group, and the corresponding acceleration slot group is a graphics processing slot group. The graphics processing slot group includes multiple graphics processing slots, and the graphics processing slots are also provided with connectors. The graphics processor is installed in the graphics processing slot via the connector in the form of an OAM. This facilitates the installation and removal of the graphics processor.

[0036] Accordingly, the link parameter mapping information corresponding to the accelerator group and the acceleration slot group includes: the mapping relationship between the "slot information" of each acceleration slot and the "recommended link parameter value of the accelerator installed thereon"; the link parameter mapping information corresponding to the retimer group and the acceleration slot group includes: the mapping relationship between the "slot information" of each acceleration slot and the "recommended link parameter value of the retimer installed thereon"; the link parameter mapping information corresponding to the expander group and the acceleration slot group includes: the mapping relationship between the "slot information" of each acceleration slot and the "recommended link parameter value of the expander installed thereon"; the link parameter mapping information corresponding to the central processing unit group and the acceleration slot group includes: the mapping relationship between the "slot information" of each acceleration slot and the "recommended link parameter value of the central processing unit installed thereon".

[0037] For example, Figure 2 As shown, the server includes a graphics processor group, a retimer group, an expander group, a central processing unit group, a graphics processing slot group, a retiming slot group, an expansion slot group, and a central processing slot group. The graphics processor is installed in the graphics processing slot in the form of an OAM. The graphics processors are connected to each other through an internal high-speed interconnect bus and are externally interconnected with the corresponding retimer through a high-speed bus (such as PCIe). The graphics processor and the graphics processing slot are decoupled, that is, the graphics processor can be installed in any graphics processing slot; the retimer is soldered to the retiming slot of the baseboard and is fixed and cannot be moved. It is externally interconnected with the corresponding expander through a high-speed bus; the expander is soldered to the expansion slot of the expansion board and is fixed and cannot be moved. It is externally interconnected with the central processing unit through a high-speed bus; the central processing unit is installed in the central processing slot of the motherboard. The connection between the baseboard where the graphics processing slot group is located and the baseboard where the retimer group is located, between the baseboard where the retimer group is located and the expansion board where the expander group is located, and between the expansion board where the expander group is located and the motherboard where the central processing unit is located can be a hard connection in the form of plug-in or a cable connection, which is not limited to this.

[0038] Specifically, the "recommended link parameter values for the signal processing component installed in the slot" refer to adjusting the parameters of the link where the signal processing component in the slot is located through link signal testing. The recommended link parameter values obtained by adjusting the parameters can make the "signal quality in the entire server (or the link directly connected to the signal processing component) greater than the preset quality threshold and the number of bit errors less than the preset bit error threshold" or "the eye diagram meets the preset requirements."

[0039] Recommended link parameter values for the signal processing component installed in each slot may include recommended link parameter values for signal processing components of multiple different models, or may include recommended link parameter values for signal processing components of multiple different models. The term "model" generally refers to a product series or a general term for a category of products, encompassing a range of different models with similar designs, functions, or target markets. A model is a specific identifier for a particular product, a precise description of a specific configuration or version. Each model typically corresponds to a specific specification, configuration, or version, and may even have subtle design differences.

[0040] In an example, the recommended values of link parameters include at least one of the following: a recommended value of a transmission parameter, a recommended value of an equalizer parameter, a recommended value of a signal amplitude, and a recommended value of a reflection characteristic, wherein the recommended value of the transmission parameter is determined based on the eye diagram of the receiving end, the recommended value of the equalizer parameter is determined based on the compensation of the signal by the transmitting end, the recommended value of the signal amplitude is determined based on the eye diagram of the receiving end, and the recommended value of the reflection characteristic is determined based on the number of bit errors at the receiving end.

[0041] Specifically, the recommended transmission parameter value of a signal processing component refers to the recommended value for the transmission parameter of the signal processing component as a transmitter in a link directly connected to other signal processing components. The recommended transmission parameter value is obtained by adjusting the parameters based on the eye diagram of the receiver. Exemplarily, the transmission parameter candidate value that optimizes the eye diagram of the receiver is selected from multiple transmission parameter candidate values as the recommended transmission parameter value. The transmission parameter includes various transmission settings of the transmitter, such as pre-emphasis and / or de-emphasis, and accordingly, the recommended transmission parameter value includes, but is not limited to, a recommended pre-emphasis value and / or a recommended de-emphasis value.

[0042] Specifically, the recommended equalizer parameter values for a signal processing component refer to the recommended equalizer parameter values for that signal processing component as the receiving end in a link directly connected to other signal processing components. The recommended equalizer parameter values are based on the signal compensation parameters adjusted by the transmitting end.

[0043] Specifically, the recommended signal amplitude value for a signal processing component refers to the recommended signal amplitude value for that signal processing component as the transmitter in a link directly connected to other signal processing components. The recommended signal amplitude value is determined by tuning parameters based on the eye diagram at the receiver.

[0044] Specifically, the recommended reflectivity value for a signal processing component refers to the recommended reflectivity value for that signal processing component as the transmitter in a link directly connected to other signal processing components. This recommended reflectivity value is determined by tuning parameters based on the number of bit errors experienced by the receiver.

[0045] The following uses the graphics processor as an example to illustrate how to adjust the parameters of the signal processing component on the slot through the link signal test to obtain the recommended link parameter values. The same is true for other signal processing components and will not be repeated here. Figure 2 and Figure 3 As shown, the GPUs installed in different GPU slots have different actual high-speed link losses and impedance matching conditions due to their layout positions and routing. To ensure that the signal quality is greater than a preset quality threshold and the number of bit errors is less than a preset bit error threshold, parameters are adjusted for each GPU slot. Specifically, for the link between the GPU and the retimer, multiple candidate transmit parameter values of the retimer are traversed, and the transmit parameter candidate value that optimizes the GPU eye diagram is selected as the recommended transmit parameter value. Based on the selected recommended transmit parameter value, the GPU's equalizer parameters (such as the CTLE gain curve or the DFE feedback coefficient) are further adjusted to optimize the GPU's signal compensation. For the link between the graphics processor and the internal high-speed interconnect, the graphics processor acting as the transmitter adjusts its own transmitter signal amplitude based on the receiver's eye diagram, and adjusts its own transmitter reflection characteristics based on the number of bit errors at the receiver. For the graphics processor acting as the receiver, multiple candidate transmission parameter values of the transmitter are traversed, and the transmission parameter candidate value that optimizes the receiver's eye diagram is selected as the recommended transmission parameter value. Based on the selected recommended transmission parameter value of the transmitter, the equalizer parameters are further adjusted to optimize the receiver's signal compensation.

[0046] like Figure 1 As shown, the method provided in this embodiment includes the following steps:

[0047] S110 : When the server is powered on, the signal processing component loads its stored firmware to obtain link parameter mapping information.

[0048] In the embodiment of the present application, when the server is powered on, for each signal processing component, the signal processing component loads its stored firmware to obtain link parameter mapping information.

[0049] S120: The signal processing component determines the slot information of the slot in which it is installed.

[0050] In an embodiment of the present application, the signal processing components of the signal processing component group share the same set of firmware, and the link parameter mapping information in the firmware includes a mapping relationship between the "slot information" of each slot in the corresponding slot group and the "recommended link parameter value of the signal processing component installed thereon". Therefore, for each signal processing component, the signal processing component needs to determine the slot information of the slot in which it is installed, so as to find the recommended link parameter value of the slot in which it is located from the link parameter mapping information based on the slot information.

[0051] In one example, a slot information generating component is provided on the slot, and the signal processing component is connected to the slot information generating component when installed on the slot, and the slot information output by different slot generating components is different, wherein the signal processing component determines the slot information of the slot in which it is installed, including: the signal processing component receives the slot information output by the slot information generating component to which it is connected.

[0052] Specifically, the slot information generating component is implemented by physical hardware, and the signal processing component and the slot information generating component can be connected by a hard connection in a plug-in manner or by a cable connection, which is not limited.

[0053] As can be appreciated, the slot information generation component can provide hardware-level slot information, enabling a more direct and stable method for slot identification. Furthermore, using the slot information generation component to generate slot information reduces the need for complex software algorithms, lowering the cost of software development and maintenance within the signal processing component and minimizing potential issues caused by software errors. Furthermore, because the slot information is directly provided by the physical hardware, it is difficult to tamper with or forge, thereby enhancing security.

[0054] In one example, the slot information generating component includes a plurality of resistor units, and the plurality of level signals output by the plurality of resistor units are used to represent the slot information.

[0055] Specifically, the number of resistor units included in different slot information generating components may be the same or different, as long as the slot information generated by combining multiple level signals is different.

[0056] Specifically, the plurality of resistor units include pull-up resistor units and / or pull-down resistor units. For example, the plurality of resistor units of some slot information generating components may all be pull-up resistor units (for outputting a high level); the plurality of resistor units of some slot information generating components may all be pull-down resistor units (for outputting a low level); and the plurality of resistor units of some slot information generating components may partially be pull-down resistor units and partially be pull-up resistor units.

[0057] For example, Figure 2 and Figure 4As shown, the graphics processor group includes eight graphics processors, and the graphics processing slot group includes eight graphics processing slots. The connector on the graphics processing slots uses three pins (i.e., Slot_ID2, Slot_ID1, and Slot_ID0), each connected to a resistor unit. The three resistor units generate slot information through a pull-up and pull-down method. Depending on the pull-up and pull-down relationships of R1-R6, eight independent slot information (000, 001, 010, 011, 100, 101, 110, and 111) can be obtained and assigned to the eight graphics processing slots. In this way, when a graphics processor is installed in any graphics processing slot, the slot information of the graphics processing slot in which it is installed can be obtained by reading the level signals of these three pins.

[0058] As you can understand, pull-up and pull-down resistors are relatively inexpensive and easy-to-use electronic components. Designing the slot information generator with them eliminates the need for complex circuit design or expensive dedicated chips, thereby reducing hardware costs and simplifying circuit design. Furthermore, the simple circuit design makes troubleshooting and maintenance of the slot information generator relatively straightforward; checking the resistors and their connections can quickly locate the problem. Furthermore, pull-up and pull-down resistors typically consume very little power, which helps reduce overall server energy consumption, especially when a large number of slots are involved.

[0059] In one example, the server also includes a programmable logic component, which includes multiple independent storage spaces, and slot information of different slots is stored in different independent storage spaces, wherein the signal processing component determines the slot information of the slot in which it is installed, including: when the signal processing component operates in host mode, reading the slot information of the slot in which it is installed from its corresponding independent storage space.

[0060] Optionally, the server further includes a control component and a storage component. Before the signal processing component determines the slot information of the slot in which it is installed, the server further includes: when the control component is operating in host mode, reading configuration information of the slot from the storage component and sending the configuration information to the programmable logic component for storage, wherein the configuration information includes recommended link parameter values. In this manner, if the signal processing component cannot obtain the recommended link parameter values from the firmware, it can still obtain the recommended link parameter values by reading the configuration information, thereby increasing the probability that the signal processing component will successfully obtain the recommended link parameter values.

[0061] Specifically, the control unit and the storage unit are connected via an inter-integrated circuit (I2C), and the control unit and the programmable logic unit are connected via I2C. The storage unit stores configuration information for each slot. Thus, the control unit can read the configuration information for each slot from the storage unit via I2C and store the configuration information for different slots in different independent storage spaces within the programmable logic unit.

[0062] Specifically, an independent I2C connection is used between the programmable logic component and each slot. In this way, for each signal processing component, after the signal processing component is installed in the slot, the signal processing component can read the configuration information and slot information of the slot in which it is installed from its corresponding independent storage space through the independent I2C connected to it.

[0063] It can be understood that by centrally managing the slot information and slot information of all slots through the control component, storage component and programmable logic component, it becomes relatively simple to update or modify this information. It only needs to be updated or modified in the storage component and programmable logic component without changing the hardware, which enhances the maintainability and upgradeability of this information.

[0064] S130. The signal processing component searches for the link parameter recommended values mapped by the slot information of the slot where the signal processing component is installed based on the stored link parameter mapping information, and performs link parameter configuration based on the found link parameter recommended values.

[0065] In one example, link parameter configuration is performed based on the found recommended link parameter values, including: the signal processing component determining its model (or model), and searching the found recommended link parameter values for the recommended link parameter values corresponding to the model (or model) of the signal processing component as the target link parameter value; or, the signal processing component determining its model (or model), and the model (or model) of the signal processing component directly connected thereto, and searching the found recommended link parameter values for the recommended link parameter values corresponding to “the model (or model) of the signal processing component and the model (or model) of the signal processing component directly connected thereto” as the target link parameter value; or, the signal processing component determining the models (or models) of all signal processing components in the server, and searching the found recommended link parameter values for the recommended link parameter values corresponding to “the models (or models) of all signal processing components” as the target link parameter value;

[0066] The signal processing component configures the link parameters based on the link parameter target values.

[0067] It can be understood that determining the link parameter target value based on the model (or model) of the signal processing component itself, determining the link parameter target value based on the model (or model) of the signal processing component itself and the model (or model) of the signal processing component connected to it, or determining the link parameter target value based on the model (or model) of all signal processing components in the server can make the link parameter target value more adapted to the performance of the signal processing component, which is conducive to further improving the signal quality.

[0068] In the embodiment of the present application, since the signal processing components in the same signal processing component group can use the same firmware, the difficulty of firmware management is reduced. In addition, by setting the mapping relationship between the slot information of the slot stored in the firmware of the signal processing component and the recommended link parameter value, the signal processing component can determine the recommended link parameter value based on the slot information of the slot in which it is installed. In this way, the decoupling between the signal processing component and its layout position in the server (and the slot in which it is installed) can be achieved. Even if the layout position of the signal processing component in the server changes (i.e., it is moved from one slot to another), the signal processing component can obtain the recommended link parameter value that matches its layout position without changing the firmware, further reducing the difficulty of firmware management and increasing firmware compatibility.

[0069] To illustrate the link parameter optimization method provided in the embodiments of the present application in detail, two specific examples are provided below.

[0070] For example, Figure 4 As shown, when the server is powered on, the reset signal is first set high after power-on completion (i.e., Power_ON_RST_N is set high). At this time, the graphics processor loads the firmware and runs, reads the slot information bound to the graphics processing slot, and determines the slot information of the graphics processing slot in which it is located. Specifically, the graphics processing slot in which it is located is determined based on the high and low levels collected by the three pipes (Slot_ID2, Slot_ID1, and Slot_ID0). Based on the mapping relationship between the recommended link parameter values of each graphics processing slot and the slot information, parameters are configured for each high-speed signal port of the graphics processor. After that, the global reset signal (PE_RST_N) is released, and each high-speed port with configured parameters starts the link establishment process according to the configured parameters, and the configured parameters take effect and begin operation.

[0071] For example, Figure 5 and Figure 6As shown, after the server is powered on, the baseboard controller (i.e., the control component) operates in master mode and retrieves the graphics processing slot configuration information from the memory (i.e., the storage component) via I2C. It then transmits this configuration information to the programmable logic device (i.e., the programmable logic unit) via I2C. The programmable logic device internally allocates independent registers for each I2C connector interconnected with the connector to store the slot information and the recommended link parameter values written by the baseboard controller. After the server is powered on, the graphics processor completes firmware loading and begins running. The graphics processor's I2C operates in master mode and retrieves the slot information and recommended link parameter values from the independent registers of the programmable logic device via I2C. After the system global reset signal is released, each configured high-speed port initiates the link establishment process according to the configured parameters, and the configured parameters take effect and begin operation. The link parameter optimization process for the timer, expander, and CPU is similar to that for the graphics processor and will not be detailed here.

[0072] In summary, through the embodiments of the present application, the problems of limited performance of adaptive parameters and difficulty in firmware management caused by parameter adjustment of specific links are solved. Precise control of link parameters of movable signal processing components is achieved, that is, the optimization of high-speed link parameters is achieved, while facilitating firmware management and compatibility. Specifically, the present application adjusts parameters of high-speed links according to specific application scenarios and selects optimal parameters, which can effectively improve the long-term stability of the system. Parameter tuning can improve the system's adaptability to material parameter consistency and further improve system reliability. The signal quality of high-speed links is easily affected by link loss and impedance matching. Server-side parameter adjustment can effectively overcome the impact of the above-mentioned channel differences on performance; a mapping relationship is established between the recommended values of link parameters and slot information under different slots. When the server is started, the configuration parameters and high-speed link establishment are carried out separately after the firmware is started, ensuring the accuracy of the link parameters of different signal processing components and also ensuring firmware normalization, so that the high-speed link works at the best performance without affecting firmware management. In addition, the signal processing component module is decoupled from the slot, and the signal processing component can be installed in any slot to ensure the best performance of the high-speed link.

[0073] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0074] The embodiment of the present application also provides a link parameter optimization device, Figure 7It is a structural diagram of a link parameter optimization device provided in an embodiment of the present application, and the link parameter optimization device can be understood as the above-mentioned electronic device or a partial functional module in the above-mentioned electronic device. The device is applied to a server, and the server includes at least one signal processing component group and at least one slot group, the signal processing component group includes at least one signal processing component, the slot group includes at least one slot, the signal processing component is installed on the slot in the slot group corresponding to the signal processing component group to which it belongs, and the firmware of the signal processing component stores link parameter mapping information corresponding to the signal processing component group to which it belongs, and the link parameter mapping information is used to characterize the mapping relationship between the slot information of the slot in the slot group to which it corresponds and the recommended link parameter value, and the recommended link parameter value is a link parameter value that meets the link signal requirements and is obtained in advance through a link signal test, such as Figure 7 As shown, the link parameter optimization device includes:

[0075] A loading module 710 is configured to cause the signal processing component to load the firmware stored therein to obtain the link parameter mapping information when the server is powered on;

[0076] A determination module 720, configured for the signal processing component to determine the slot information of the slot in which the signal processing component is installed;

[0077] The configuration module 730 is used for the signal processing component to search for the link parameter recommended value mapped by the slot information of the slot where the signal processing component is installed based on the link parameter mapping information stored therein, and to perform link parameter configuration based on the found link parameter recommended value.

[0078] Optionally, a slot information generating component is provided on the slot, and the signal processing component is connected to the slot information generating component when installed on the slot, and the slot information output by different slot generating components is different, wherein the determination module 720 is specifically used for the signal processing component to receive the slot information output by the slot information generating component to which it is connected.

[0079] Optionally, the slot information generating component includes a plurality of resistance units, and the plurality of level signals output by the plurality of resistance units are used to represent the slot information.

[0080] Optionally, the server also includes a programmable logic component, which includes multiple independent storage spaces, and the slot information of different slots is stored in different independent storage spaces, wherein the determination module 720 is specifically used to read the slot information of the slot in which the signal processing component is installed from the corresponding independent storage space when the signal processing component operates in host mode.

[0081] Optionally, the server also includes a control component and a storage component, and the device also includes a reading component for reading the configuration information of the slot from the storage component when the control component operates in host mode before the signal processing component determines the slot information of the slot in which it is installed, and sending the configuration information to the programmable logic component for storage, wherein the configuration information includes the recommended values of the link parameters, and the configuration information of different slots is stored in different independent storage spaces.

[0082] Optionally, the configuration module 730 includes a configuration submodule, configured to perform link parameter configuration based on the found recommended link parameter values, wherein the configuration submodule is specifically configured to determine the model of the signal processing component, and search the found recommended link parameter values corresponding to the model of the signal processing component as the target link parameter values;

[0083] The signal processing component performs link parameter configuration based on the link parameter target value.

[0084] Optionally, the at least one signal processing component group includes at least one of the following: a graphics processor group, a retimer group, an expander group, and a central processing unit group;

[0085] The recommended link parameter values include at least one of the following: a recommended transmission parameter value, a recommended equalizer parameter value, a recommended signal amplitude value, and a recommended reflection characteristic value, wherein the recommended transmission parameter value is determined based on an eye diagram of the receiving end, the recommended equalizer parameter value is determined based on compensation of the signal by the transmitting end, the recommended signal amplitude value is determined based on the eye diagram of the receiving end, and the recommended reflection characteristic value is determined based on the number of bit errors at the receiving end;

[0086] The slot group corresponding to the graphics processor group is a graphics processing slot group, which includes multiple graphics processing slots. A connector is also provided on the graphics processing slot, and the graphics processor is installed on the graphics processing slot through the connector in the form of an open accelerator module.

[0087] For the description of the features in the embodiment corresponding to the link parameter optimization device, please refer to the relevant description of the embodiment corresponding to the link parameter optimization method, and will not be repeated here.

[0088] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned link parameter optimization method embodiments.

[0089] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above-mentioned link parameter optimization method embodiments when running.

[0090] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0091] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above-mentioned link parameter optimization method embodiments are implemented.

[0092] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned link parameter optimization method embodiments are implemented.

[0093] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0094] The above is a detailed introduction to the link parameter optimization method, device, equipment and storage medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A link parameter optimization method, characterized in that: Applied to a server, the server includes at least one signal processing component group and at least one slot group, the signal processing component group includes at least one signal processing component, the slot group includes at least one slot, the signal processing component is installed in the slot in the slot group corresponding to the signal processing component group to which it belongs, the firmware of the signal processing component stores link parameter mapping information corresponding to the signal processing component group to which it belongs, the link parameter mapping information is used to characterize the mapping relationship between the slot information of the slot in the slot group to which it corresponds and the recommended link parameter value, the recommended link parameter value being a link parameter value that meets the link signal requirements and is obtained in advance through a link signal test, wherein the method includes: When the server is powered on, the signal processing component loads the firmware stored therein to obtain the link parameter mapping information; The signal processing component determines the slot information of the slot in which the signal processing component is installed; The signal processing component searches for the link parameter recommended value mapped by the slot information of the slot where the signal processing component is installed based on the link parameter mapping information stored therein, and performs link parameter configuration based on the found link parameter recommended value.

2. The method according to claim 1, characterized in that The slot is provided with a slot information generating component. When the signal processing component is installed in the slot, it is connected to the slot information generating component. Different slot generating components output different slot information. The signal processing component determines the slot information of the slot in which it is installed, including: The signal processing component receives the slot information output by the slot information generating component to which it is connected.

3. The method according to claim 2, characterized in that The slot information generating component includes a plurality of resistor units, and the plurality of level signals output by the plurality of resistor units are used to represent the slot information.

4. The method according to claim 1, wherein The server further includes a programmable logic component, the programmable logic component includes a plurality of independent storage spaces, and the slot information of different slots is stored in different independent storage spaces. The signal processing component determines the slot information of the slot in which it is installed, including: When the signal processing component operates in the host mode, the slot information of the slot in which the signal processing component is installed is read from the corresponding independent storage space.

5. The method according to claim 4, characterized in that The server further includes a control component and a storage component, and before the signal processing component determines the slot information of the slot in which the signal processing component is installed, further includes: When the control component operates in host mode, the configuration information of the slot is read from the storage component and sent to the programmable logic component for storage, wherein the configuration information includes the recommended values of the link parameters, and the configuration information of different slots is stored in different independent storage spaces.

6. The method according to claim 1, characterized in that The performing link parameter configuration based on the found link parameter recommended value includes: The signal processing component determines its model, and searches for a link parameter recommended value corresponding to the model of the signal processing component from the found link parameter recommended values as a link parameter target value; The signal processing component performs link parameter configuration based on the link parameter target value.

7. The method according to any one of claims 1 to 6, characterized in that The at least one signal processing component group includes at least one of the following: a graphics processor group, a retimer group, an expander group, and a central processing unit group; The recommended link parameter values include at least one of the following: a recommended transmission parameter value, a recommended equalizer parameter value, a recommended signal amplitude value, and a recommended reflection characteristic value, wherein the recommended transmission parameter value is determined based on an eye diagram of the receiving end, the recommended equalizer parameter value is determined based on compensation of the signal by the transmitting end, the recommended signal amplitude value is determined based on the eye diagram of the receiving end, and the recommended reflection characteristic value is determined based on the number of bit errors at the receiving end; The slot group corresponding to the graphics processor group is a graphics processing slot group, which includes multiple graphics processing slots. A connector is also provided on the graphics processing slot, and the graphics processor is installed on the graphics processing slot through the connector in the form of an open accelerator module.

8. A link parameter optimization device, characterized in that: Applied to a server, the server includes at least one signal processing component group and at least one slot group, the signal processing component group includes at least one signal processing component, the slot group includes at least one slot, the signal processing component is installed in the slot in the slot group corresponding to the signal processing component group to which it belongs, the firmware of the signal processing component stores link parameter mapping information corresponding to the signal processing component group to which it belongs, the link parameter mapping information is used to characterize the mapping relationship between the slot information of the slot in the slot group to which it corresponds and the recommended link parameter value, the recommended link parameter value being a link parameter value that meets the link signal requirements and is obtained in advance through a link signal test, wherein the method includes: a loading module, configured to cause the signal processing component to load the firmware stored therein to obtain the link parameter mapping information when the server is powered on; a determination module, configured for the signal processing component to determine the slot information of the slot in which the signal processing component is installed; A configuration module is used for the signal processing component to search for the link parameter recommended value mapped by the slot information of the slot where the signal processing component is installed based on the link parameter mapping information stored therein, and to configure the link parameters based on the found link parameter recommended value.

9. An electronic device, characterized in that: include: A processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the processor performs the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

Images