Control circuit board, control method, program product, electronic device and storage medium

Abstract

The present application discloses a control circuit board, a control method, a computer program product, an electronic device and a computer-readable storage medium, and relates to the field of data communication technology. The control circuit board includes a retiming chip, and the retiming chip is used to connect the OAM module and the switching node. When the retiming chip is configured in the signal retiming mode, the retiming chip is used to transparently transmit the communication signal of at least one channel in at least one link of the OAM module to the switching node; when the retiming chip is configured in the signal adaptation mode, the retiming chip is used to merge the communication signals of at least two channels in at least one link of the OAM module and transmit them to the switching node. In this way, the technical problem that the same computing node can only be compatible with one OAM module design is solved, and the retiming chip can be configured in different modes for different OAM modules to achieve the technical effect of compatibility with multiple different OAM module designs in one set of control circuit boards.

Description

Technical Field

[0001] The present application relates to the field of data communication technology, and in particular to a control circuit board, a control method, a computer program product, an electronic device, and a computer-readable storage medium. Background Art

[0002] Artificial Intelligence (AI) servers, as one of the core infrastructure components of AI technology, play a vital role in promoting its development and application expansion. With the continuous advancement of technology and the widespread expansion of its applications, the AI ​​server market is expected to continue to grow and embrace even broader development prospects. However, current AI servers have compatibility limitations at the compute node level; a single compute node is only compatible with one Open Application Model (OAM) module design. Summary of the Invention

[0003] The present application provides a control circuit board, a control method, a computer program product, an electronic device, and a computer-readable storage medium to at least solve the problem in the related art that the same computing node can only be compatible with one OAM module design.

[0004] The present application provides a control circuit board, which includes a retiming chip, and the retiming chip is used to connect the OAM module and the switching node;

[0005] When the retiming chip is configured in signal retiming mode, the retiming chip is used to transparently transmit the communication signal of at least one channel within at least one link of the OAM module to the switching node; when the retiming chip is configured in signal adaptation mode, the retiming chip is used to merge the communication signals of at least two channels within at least one link of the OAM module and transmit them to the switching node.

[0006] The present application also provides a control method, which is applied to the above-mentioned control circuit board. The control method includes:

[0007] Get the model of the OAM module;

[0008] Configure the retiming chip to signal retiming mode or signal adaptation mode according to the OAM module model.

[0009] The present application also provides a computer program product, which is applied to the above-mentioned control circuit board. The computer program product includes:

[0010] Get module, used to get the model of OAM module;

[0011] The configuration module is used to configure the retiming chip to the signal retiming mode or signal adaptation mode according to the model of the OAM module.

[0012] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of the above-mentioned control method when executing the computer program.

[0013] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned control method are implemented.

[0014] Through this application, when the retiming chip is configured in signal retiming mode, it transparently transmits the communication signal of at least one channel within at least one link of the OAM module to the switching node. When the retiming chip is configured in signal adaptation mode, it combines the communication signals of at least two channels within at least one link of the OAM module and transmits them to the switching node. This solves the current technical problem of a single computing node being compatible with only one OAM module design. The retiming chip can be configured in different modes for different OAM modules, achieving the technical effect of compatibility with multiple different OAM module designs within a single control circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0016] Figure 1 A schematic diagram of the working principle of a control circuit board provided in an embodiment of the present application;

[0017] Figure 2 A schematic diagram of the working mode of a retiming chip for a first type of OAM module provided in an embodiment of the present application;

[0018] Figure 3 A schematic diagram of the working mode of a retiming chip for a first type of OAM module provided in an embodiment of the present application;

[0019] Figure 4 A schematic diagram of the working mode of a retiming chip for a second type of OAM module provided in an embodiment of the present application;

[0020] Figure 5 A schematic diagram of the working mode of a retiming chip for a second type of OAM module provided in an embodiment of the present application;

[0021] Figure 6A two-dimensional diagram of a first connector provided in an embodiment of the present application;

[0022] Figure 7 A schematic diagram of the interconnection relationship between a computing node and a switching node provided in an embodiment of the present application;

[0023] Figure 8 A schematic diagram of the interconnection topology of an OAM module, a retiming chip, and a first connector provided in an embodiment of the present application;

[0024] Figure 9 A flow chart of a control method provided in an embodiment of the present application;

[0025] Figure 10 A schematic diagram of a computer program product provided in accordance with an embodiment of the present invention;

[0026] Figure 11 A schematic diagram of a module of an electronic device provided in an embodiment of the present application;

[0027] Figure 12 A schematic diagram of a computer-readable storage medium provided in accordance with an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0029] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0030] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0031] Artificial Intelligence (AI) servers, hardware devices designed specifically to accelerate the execution of AI algorithms and models, integrate high-performance computing chips, large-capacity storage, high-speed network connections, and optimized software support, offering high scalability, reliability, and stability. Leveraging key technologies such as heterogeneous computing, distributed computing frameworks, and deep learning frameworks, AI servers demonstrate strong application potential in a variety of fields, including deep learning, healthcare, finance, and security. As a core infrastructure component of AI technology, AI servers play a vital role in promoting the development of AI technology and expanding its applications. With continuous technological advancements and the widespread expansion of applications, the AI ​​server market will continue to grow and embrace even broader development prospects. The emergence of more deep learning applications, such as ChatGPT4, will further drive demand for AI hardware in data centers.

[0032] The Open Air Interface (OAI) platform, an open-source software-defined radio (SDR) platform, is a standards effort that aims to advance robust and scalable AI acceleration hardware designs. In these designs, time-division multiplexed (TDM), point-to-point (P2P) serial communication technology (Serializer / Deserializer, SerDes) speeds reaching 100Gbps are crucial for enabling generative AI.

[0033] The Open Application Model (OAM) in the OAI system can perform AI processing on the same rack, or in some cases across multiple racks through a horizontal expansion interface to allow multiple graphics processing units (GPUs) to connect to each other and exchange large amounts of training data to complete complex artificial intelligence and machine learning tasks.

[0034] However, current AI rack-mount servers are typically only compatible with one OAM module design. Within a single compute node, OAMs are interconnected via SerDes, which then transmits the SerDes signals to the switch node to enable communication between all compute nodes in the rack.

[0035] The current solution suffers from design differences between OAM modules from different manufacturers. For example, the A series SerDes signal has six lanes per link, each with an output rate of 112 Gbps, while the B series has eight lanes per link, each with an output rate of 56 Gbps. This requires the development of multiple printed circuit board assemblies (PCBAs) to accommodate different OAM modules, consuming significant manpower and resources.

[0036] In view of this, embodiments of the present application provide a control circuit board, a control method, a computer program product, an electronic device, and a computer-readable storage medium, so as to enable the same computing node to be compatible with multiple OAM module designs.

[0037] See also Figure 1 The control circuit board 100 of the embodiment of the present application includes a retiming chip 10. The retiming chip 10 is used to connect the OAM module 210 and the switching node 300. When the retiming chip 10 is configured in the signal retiming mode, the retiming chip 10 is used to transparently transmit the communication signal of at least one channel within at least one link of the OAM module 210 to the switching node 300; when the retiming chip 10 is configured in the signal adaptation mode, the retiming chip 10 is used to combine the communication signals of at least two channels within at least one link of the OAM module 210 and transmit them to the switching node 300.

[0038] In the control circuit board 100 of the embodiment of the present application, when the retiming chip 10 is configured in signal retiming mode, the retiming chip 10 is used to transparently transmit the communication signal of at least one channel within at least one link of the OAM module 210 to the switching node 300. When the retiming chip 10 is configured in signal adaptation mode, the retiming chip 10 is used to combine the communication signals of at least two channels within at least one link of the OAM module 210 and transmit them to the switching node 300. In this way, the retiming chip 10 can be configured in different modes for different OAM modules 210, thereby achieving compatibility with multiple different OAM module 210 designs within a single control circuit board 100.

[0039] Specifically, the retiming chip 10 may be a physical layer retiming (PHY Retimer) chip. Figure 2 and Figure 3 The host side of the retiming chip 10 is used to connect to the OAM module 210, and the line side of the retiming chip 10 is used to connect to the switching node 300 to transmit the communication signal of the OAM module 210 to the switching node 300. The communication signal can be a SerDes signal.

[0040] The retiming chip 10 can be configured in a signal retiming mode (PHY Retimer Mode) and a signal adaptation mode (Gearbox Mode).

[0041] When the retiming chip 10 is configured in signal retiming mode, it transparently transmits the communication signal of at least one channel within at least one link of the OAM module 210 to the switching node 300. Transparent transmission means that the retiming chip 10 does not modify or process the content, format, or protocol of the communication signal when transmitting it. Instead, it regenerates and forwards the signal at the physical layer, allowing the communication signal to pass directly through the retiming chip 10. In this case, the output rate of the communication signal remains unchanged.

[0042] When the retiming chip 10 is configured in signal adaptation mode, it combines the communication signals of at least two channels within at least one link of the OAM module 210 and transmits them to the switching node 300. Combined transmission refers to the retiming chip 10 combining the communication signals during transmission. By combining the communication signals of at least two channels for transmission, the output rate of the communication signals can be increased.

[0043] In an embodiment of the present application, the retiming chip 10 can be configured in different modes for different OAM modules 210 to achieve compatibility with multiple different OAM module 210 designs within a set of control circuit boards 100. Taking the aforementioned A-series and B-series products as examples, since the signal output rate of each channel of the A-series products is 112Gbps, and the signal output rate of each channel of the B-series products is 56Gbps, and the communication rate of 112Gbps needs to be unified between the computing node 200 and the switching node 300. Therefore, for the B-series products, the retiming chip 10 can be configured in signal adaptation mode to merge and transmit the communication signals of the two channels to achieve output rate conversion of the communication signals (e.g., 56Gbps → 112Gbps). For the A-series products, the retiming chip 10 only needs to be configured in signal retiming mode to maintain the signal output rate at 112Gbps. In this way, the output rate of the communication signal transmitted to the switching node 300 can be unified to 112 Gbps, that is, the compatibility of the A series products and the B series products is achieved, and the universalization of the computing node 200 is realized.

[0044] This embodiment of the present application enables the design of a universal OAM circuit board for OAM products designed in accordance with the OAM 2.0 specification. For server manufacturers, this solution eliminates the need to design matching hardware circuits for different OAM products, saving manpower and resources. For customers, they can flexibly configure different OAM configurations within the same product suite.

[0045] In some embodiments, when the retiming chip 10 is configured in the signal adaptation mode, the retiming chip 10 is further configured to cross-transmit the communication signal of at least one channel within at least one link of the OAM module 210 to the switching node 300 .

[0046] Specifically, cross transmission refers to the re-timing chip 10 reconfiguring the transmission channel when transmitting the communication signal, rather than directly mapping the original host side channel port to the corresponding original line side channel port. Figure 3 For example, the communication signal GPU0_S1_Lane12 is cross-transmitted from the host side channel port Lane4 to the line side channel port Lane2, rather than from the host side channel port Lane4 to the line side channel port Lane4, so as to achieve channel compatibility and channel optimization.

[0047] See also Figures 2 to 5 In some embodiments, the model of the OAM module 210 includes a first model and a second model. When the model of the OAM module 210 is the first model, the retiming chip 10 is configured in the signal retiming mode (eg Figure 2 ) or signal adaptation mode (as shown in Figure 3 When the model of the OAM module 210 is the second model, the retiming chip 10 is configured as a signal adaptation mode (such as Figure 4 and Figure 5 shown).

[0048] Specifically, each OAM module 210 may include multiple links, and each link may include multiple lanes. The definitions of links and lanes are introduced below.

[0049] A link is a physical connection unit in high-speed serial communications, representing a set of logically associated signal channels used to transmit data between devices. It contains multiple lanes and may also include control signals (such as clock and synchronization signals).

[0050] A lane is the smallest transmission unit in a link. It is an independent bidirectional or unidirectional data channel responsible for transmitting high-speed serial data streams. Each lane operates independently and transmits data using differential signaling (such as PAM4 encoding).

[0051] For example, a link is like a highway, which consists of multiple lanes. Each lane is like a lane on the highway, carrying vehicles, that is, transmitting signals.

[0052] For different models of OAM modules 210 , the number of Lanes included in each Link may be different, and the output rate of each Lane may also be different.

[0053] In some embodiments, the number of channels included in at least one link of the first type of OAM module 210 is smaller than the number of channels included in at least one link of the second type of OAM module 210; and / or the signal output rate of at least one channel in at least one link of the first type of OAM module 210 is greater than the signal output rate of at least one channel in at least one link of the second type of OAM module 210.

[0054] Taking the aforementioned A-series and B-series products as examples, the A-series products are the first model OAM module 210, and the B-series products are the second model OAM module 210. The first model OAM module 210 includes 8 links, each of which includes 6 lanes, and the signal output rate of each lane is 112 Gbps. The second model OAM module 210 includes 8 links, each of which includes 8 lanes, and the signal output rate of each lane is 56 Gbps.

[0055] Thus, the first model OAM module 210 achieves high bandwidth through a higher output rate (e.g., 112 Gbps) and a smaller number of channels (e.g., 6), making it suitable for high-performance computing scenarios. The second model OAM module 210, with a lower output rate (e.g., 56 Gbps) and a larger number of channels (e.g., 8), is more compliant with signal integrity and cost control. Furthermore, by being compatible with multiple models of OAM modules 210, OAM modules 210 can be flexibly selected to meet diverse needs.

[0056] When the OAM module 210 is of the first model, the retiming chip 10 is configured in signal retiming mode or signal adaptation mode. For the first model OAM module 210, the retiming chip 10 is configured in signal retiming mode to achieve transparent signal transmission. The retiming chip 10 is configured in signal adaptation mode to perform channel cross-processing on the signal to achieve channel optimization.

[0057] When the OAM module 210 is of the second model, the retiming chip 10 is configured in signal adaptation mode. For the second model OAM module 210, the retiming chip 10 is configured in signal adaptation mode to perform signal merging and channel crossover processing on the signal to achieve output rate conversion and channel optimization for the communication signal.

[0058] In this way, compatibility of various OAM modules 210 in terms of channels and output rates can be achieved.

[0059] See also Figures 2 to 5In some embodiments, the retiming chip 10 includes a plurality of retiming units 11 , each of which is configured to be in either a signal retiming mode or a signal adaptation mode.

[0060] In this way, each retiming unit 11 in the retiming chip 10 can be configured in a mode independently. By dynamically adjusting the mode of each retiming unit 11 , the flexibility and scalability of the system are improved.

[0061] It can be understood that if the entire retiming chip 10 is configured in a unified mode, when the retiming chip 10 is used to transmit communication signals of the first type of OAM module 210 and the second type of OAM module 210 at the same time, it can only be uniformly configured as the signal retiming mode or the signal adaptation mode, and it is impossible to achieve, for example: for the first type of OAM module 210, the retiming chip 10 is configured in the signal retiming mode; at the same time, for the second type of OAM module 210, the retiming chip 10 is configured in the signal adaptation mode, etc.

[0062] by Figures 2 to 5 For example, Figure 2 and Figure 3 Together they form a retiming chip 10, Figure 4 and Figure 5 Together they form a retiming chip 10. A retiming chip 10 includes four retiming units 11. For ease of distinction, they are respectively recorded as a first retiming unit 111, a second retiming unit 112, a third retiming unit 113, and a fourth retiming unit 114. The first retiming unit 111, the second retiming unit 112, the third retiming unit 113, and the fourth retiming unit 114 can each be independently configured to be either a signal retiming mode or a signal adaptation mode. For example, when the model of the OAM module 210 is the first model, the first retiming unit 111 can be configured to be in the signal retiming mode (e.g., Figure 2 As shown), the third retiming unit 113 can be configured as a signal adaptation mode (as shown Figure 3 When the model of the OAM module 210 is the second model, the second retiming unit 112 and the fourth retiming unit 114 can be configured as a signal adaptation mode (such as Figure 4 and Figure 5 shown).

[0063] See also Figures 2 to 5In some examples, the retiming chip 10 includes a host side and a line side. Each retiming unit 11 includes multiple host side channel ports 115 and multiple line side channel ports 116. For example, the first retiming unit 111, the second retiming unit 112, the third retiming unit 113, and the fourth retiming unit 114 each include eight host side channel ports 115 and eight line side channel ports 116.

[0064] The eight host-side channel ports 115 and the eight line-side channel ports 116 of the first retiming unit 111 are Lane0 to Lane7 on the host side and line side, respectively, for inputting and outputting communication signals GPU0_S1_Lane0 to GPU0_S1_Lane3 and GPU0_S1_Lane8 to GPU0_S1_Lane11 of the OAM module 210 .

[0065] The eight host-side channel ports 115 and the eight line-side channel ports 116 of the second retiming unit 112 are Lane 8 to Lane 15 on the host side and Lane 15 on the line side, respectively used to input and output communication signals GPU1_S1_Lane0 to GPU1_S1_Lane3 and GPU1_S1_Lane8 to GPU1_S1_Lane11 of the OAM module 210 .

[0066] The eight host-side channel ports 115 and the eight line-side channel ports 116 of the third retiming unit 113 are Lane0 to Lane7 on the host side and line side, respectively, for inputting and outputting communication signals GPU0_S1_Lane4 to GPU0_S1_Lane7 and GPU0_S1_Lane12 to GPU0_S1_Lane15 of the OAM module 210 .

[0067] The eight host-side channel ports 115 and the eight line-side channel ports 116 of the fourth retiming unit 114 are Lane 8 to Lane 15 on the host side and Lane 15 on the line side, respectively used to input and output communication signals GPU1_S1_Lane4 to GPU1_S1_Lane7 and GPU1_S1_Lane12 to GPU1_S1_Lane15 of the OAM module 210.

[0068] Here, "GPU0" and "GPU1" represent two OAM modules 210, respectively. The first retiming unit 111 and the third retiming unit 113 both correspond to the communication signals of GPU0, while the second retiming unit 112 and the fourth retiming unit 114 both correspond to the communication signals of GPU1. In other examples, depending on resource configuration, the retiming chip 10 may include only the first retiming unit 111 and the third retiming unit 113, or only the second retiming unit 112 and the fourth retiming unit 114, without limitation herein.

[0069] Figure 2 GPU0_S1_Lane0-GPU0_S1_Lane3 and Figure 3 GPU0_S1_Lane4-GPU0_S1_Lane5 together constitute the communication signals of the six lanes included in a link of an OAM module 210 of the first model. Figure 4 GPU0_S1_Lane0-GPU0_S1_Lane3 and Figure 5 GPU0_S1_Lane4 to GPU0_S1_Lane7 together constitute the communication signals of 8 lanes included in a link of an OAM module 210 of the second model.

[0070] Figure 2 GPU0_S1_Lane8-GPU0_S1_Lane11 and Figure 3 GPU0_S1_Lane12-GPU0_S1_Lane13 together constitute the communication signals of the six lanes included in another link of an OAM module 210 of the first model. Figure 4 GPU0_S1_Lane8-GPU0_S1_Lane11 and Figure 5 GPU0_S1_Lane12 to GPU0_S1_Lane15 in the OAM module 210 together constitute the communication signals of 8 lanes included in another link of the OAM module 210 of the second model.

[0071] Figure 2 GPU1_S1_Lane0-GPU1_S1_Lane3 and Figure 3 GPU1_S1_Lane4-GPU1_S1_Lane5 in the GPU1_S1_Lane4-GPU1_S1_Lane5 together constitute the communication signals of the six lanes included in a link of another OAM module 210 of the first model. Figure 4 GPU1_S1_Lane0-GPU1_S1_Lane3 and Figure 5GPU1_S1_Lane4 to GPU1_S1_Lane7 in the GPU1_S1_Lane4 to GPU1_S1_Lane7 together constitute the communication signals of 8 lanes included in a link of another OAM module 210 of the second model.

[0072] Figure 2 GPU1_S1_Lane8-GPU1_S1_Lane11 and Figure 3 GPU1_S1_Lane12-GPU1_S1_Lane13 in the GPU1_S1_Lane12 together constitute the communication signals of the six lanes included in another Link of another OAM module 210 of the first model. Figure 4 GPU1_S1_Lane8-GPU1_S1_Lane11 and Figure 5 GPU1_S1_Lane12 to GPU1_S1_Lane15 in the GPU1_S1_Lane12 together constitute the communication signals of 8 lanes included in another Link of another OAM module 210 of the second model.

[0073] See also Figure 2 In some embodiments, the at least one retiming unit 11 includes L host-side channel ports 115 and L line-side channel ports 116. When the OAM module 210 is of the first model, the at least one retiming unit 11 is configured in signal retiming mode. The at least one retiming unit 11 is configured to transparently transmit communication signals of channels 1 to L among M channels within at least one link of the OAM module 210 to the switching node 300 through the L host-side channel ports 115 and the L line-side channel ports 116, where M>L.

[0074] In the embodiment of the present application, the at least one retiming unit 11 includes, but is not limited to, the aforementioned first retiming unit 111 and / or second retiming unit 112. Taking the example of the at least one retiming unit 11 including the first retiming unit 111, when the OAM module 210 is of the first model, the first retiming unit 111 is configured in signal retiming mode. Assuming L=4 and M=6, the communication signals of Lanes 1 to 4 of the six lanes within a link of the OAM module 210 are transparently transmitted to the switching node 300 via the four host-side channel ports Lane 0 to Lane 3 and the four line-side channel ports Lane 0 to Lane 3.

[0075] Specifically, the communication signals GPU0_S1_Lane0-GPU0_S1_Lane3 of Lanes 1 through 4 of the six lanes within a link of an OAM module 210 of the first model are transparently transmitted to the switching node 300 via the four host-side channel interfaces Lane0 through Lane3 and the four line-side channel interfaces Lane0 through Lane3 of the first retiming unit 111. At this point, the first retiming unit 111 maintains the original lane-to-lane mapping relationship.

[0076] Since a unified 112 Gbps communication rate is required between the computing node 200 and the switching node 300, and the signal output rate of each channel of the first-type OAM module 210 already meets 112 Gbps, for the first-type OAM module 210, it is only necessary to configure the first retiming unit 111 to the signal retiming mode to maintain the signal output rate at 112 Gbps. In this way, the control circuit board 100 is compatible with the first-type OAM module 210.

[0077] See also Figure 4 In some embodiments, the at least one retiming unit 11 includes L host-side channel ports 115 and L line-side channel ports 116. When the OAM module 210 is of the second model, the at least one retiming unit 11 is configured in signal adaptation mode. The at least one retiming unit 11 is configured to combine communication signals of channels 1 to L among N channels within at least one link of the OAM module 210 and transmit them to the switching node 300 via the L host-side channel ports 115 and L / 2 line-side channel ports 116, where N>L.

[0078] In the embodiment of the present application, at least one retiming unit 11 includes, but is not limited to, the aforementioned first retiming unit 111 and / or second retiming unit 112. Taking the example of at least one retiming unit 11 including the first retiming unit 111, when the OAM module 210 is of the second model, the first retiming unit 111 is configured in signal adaptation mode. Assuming L=4 and N=8, the communication signals of Lanes 1 to 4 of the eight lanes within a link of the OAM module 210 are combined and transmitted to the switching node 300 via the four host-side channel ports Lane0 to Lane3 and the two line-side channel ports Lane0 to Lane1.

[0079] Specifically, the communication signals GPU0_S1_Lane0-GPU0_S1_Lane3 of Lanes 1 through 4 of the eight lanes within a link of an OAM module 210 of the second model are combined and transmitted to the switching node 300 via the four host-side channel interfaces Lanes 0 through Lane 3 and the two line-side channel interfaces Lanes 0 through Lane 1 of the first retiming unit 111. At this point, the first retiming unit 111 combines the two lanes into one, essentially merging two 56 Gbps SerDes signals into one 112 Gbps SerDes signal, achieving rate conversion of the communication signals (e.g., 56 Gbps to 112 Gbps).

[0080] Because the communication rate between the computing node 200 and the switching node 300 must be unified at 112 Gbps, and the signal output rate of each channel of the second-type OAM module 210 is 56 Gbps, the first retiming unit 111 of the second-type OAM module 210 needs to be configured in signal adaptation mode to convert the signal output rate to 112 Gbps. In this way, the control circuit board 100 can adapt to the second-type OAM module 210.

[0081] See also Figure 3 In some embodiments, at least one retiming unit 11 includes a first sub-retiming unit 11a and a second sub-retiming unit 11b. Each of the first sub-retiming unit 11a and the second sub-retiming unit 11b includes L host-side channel ports 115 and L line-side channel ports 116. When the OAM module 210 is of the first model, the at least one retiming unit 11 is configured in a signal adaptation mode. The at least one retiming unit 11 is configured to cross-transmit communication signals of the (L+1)th to Mth channels of the M channels within at least two links of the OAM module 210 to the switching node 300 through the (M+1)th host-side channel ports 115 in the first sub-retiming unit 11a, the (M+1)th host-side channel ports 115 in the second sub-retiming unit 11b, and the 2 (M+1)th line-side channel ports 116 in the first sub-retiming unit 11a, where M>L.

[0082] In this embodiment of the present application, at least one retiming unit 11 includes, but is not limited to, the aforementioned third retiming unit 113 and / or fourth retiming unit 114. Taking the example of at least one retiming unit 11 including the third retiming unit 113, when the OAM module 210 is of the first model, the third retiming unit 113 is configured in signal adaptation mode. Assuming L = 4 and M = 6, then ML = 2, and 2(ML) = 4. Communication signals from Lanes 5 to 6 of the six lanes within one link of the OAM module 210 and communication signals from Lanes 5 to 6 of the six lanes within another link are cross-transmitted to the switching node 300 via four host-side channel ports Lanes 0 to Lane 1 and Lanes 4 to Lane 5, and four line-side channel ports Lanes 0 to Lane 3.

[0083] Specifically, the communication signals GPU0_S1_Lane4-GPU0_S1_Lane5 of the two lanes included in a link of a first-type OAM module 210, and the communication signals GPU1_S1_Lane4-GPU1_S1_Lane5 of the two lanes included in another link of a first-type OAM module 210, are cross-transmitted to the switching node 300 via the two host-side channel interfaces Lane0-Lane1 of the first sub-retiming unit 11a, the two host-side channel interfaces Lane4-Lane5 of the second sub-retiming unit 11b, and the four line-side channel interfaces Lane0-Lane3 of the first sub-retiming unit 11a. At this time, the third retiming unit 113 maintains the lane-to-lane mapping relationship but performs lane crossover.

[0084] Unlike the second-type OAM module 210, which includes eight lanes per link, the first-type OAM module 210 includes six lanes per link. To achieve hardware compatibility, the two host-side ports, Lanes 4 and 5, of the second sub-retiming unit 11b were originally mapped to the two line-side ports, Lanes 4 and 5, of the second sub-retiming unit 11b. Instead, they are mapped to the two line-side ports, Lanes 2 and 3, of the first sub-retiming unit 11a. This allows communication signals to be outputted through the four line-side ports, Lanes 0 through Lane 3, of the first sub-retiming unit 11a, ensuring hardware compatibility with the second-type OAM module 210.

[0085] See also Figure 5In some embodiments, at least one retiming unit 11 includes a first sub-retiming unit 11a and a second sub-retiming unit 11b. The first sub-retiming unit 11a and the second sub-retiming unit 11b each include L host-side channel ports 115 and L line-side channel ports 116. When the OAM module 210 is of the second model, the at least one retiming unit 11 is configured in a signal adaptation mode. The at least one retiming unit 11 is configured to cross-transmit communication signals of the (L+1)th to Nth channels among the N channels within at least two links of the OAM module 210 to the switching node 300 through (NL) host-side channel ports 115 in the first sub-retiming unit 11a, (NL) host-side channel ports 115 in the second sub-retiming unit 11b, and (NL) line-side channel ports 116 in the first sub-retiming unit 11a, where N>L.

[0086] In the embodiment of the present application, at least one retiming unit 11 includes but is not limited to the aforementioned third retiming unit 113 and / or fourth retiming unit 114. Taking the at least one retiming unit 11 including the third retiming unit 113 as an example, when the model of the OAM module 210 is the second model, the third retiming unit 113 is configured in signal adaptation mode. Assuming L=4 and N=8, then NL=4. The communication signals of Lanes 5 to 8 among the 8 Lanes in a Link of the OAM module 210 are cross-transmitted to the switching node 300 through the 4 host-side channel ports Lane0~Lane3, the communication signals Lane4~Lane7 of Lanes 5 to 8 among the 8 Lanes in another Link, and the 4 line-side channel ports Lane0~Lane3.

[0087] Specifically, the communication signals GPU0_S1_Lane4-GPU0_S1_Lane7 of the four lanes included in a link of a second-type OAM module 210, and the communication signals GPU1_S1_Lane4-GPU1_S1_Lane7 of the four lanes included in another link of a second-type OAM module 210, are cross-transmitted to the switching node 300 via the four host-side channel ports Lane0-Lane3 of the first sub-retiming unit 11a, the four host-side channel ports Lane4-Lane7 of the second sub-retiming unit 11b, and the four line-side channel ports Lane0-Lane3 of the first sub-retiming unit 11a. At this point, the third retiming unit 113 merges the two lanes into one, achieving rate conversion of the communication signals (e.g., from 56 Gbps to 112 Gbps) and performing channel crossover.

[0088] Since each link of the second-type OAM module 210 includes 8 lanes, the communication signals can be concentrated on the output of the four line-side channel ports Lane0 to Lane3 of the first sub-retiming unit 11a through signal merging and channel crossing, saving hardware resources.

[0089] As described above, to meet the 112 Gbps communication rate requirement between the computing node 200 and the switching node 300, the retiming chip 10 is configured in signal retiming mode or signal adaptation mode according to the model of the OAM module 210 to achieve 112 Gbps SerDes signal output and centralized SerDes signal output, making it compatible with multiple OAM modules 210.

[0090] See also Figure 3 and Figure 5 In some embodiments, the first sub-retiming unit 11 a and the second sub-retiming unit 11 b are respectively used to transmit communication signals of different links of the OAM module 210 .

[0091] For example, the first sub-retiming unit 11a and the second sub-retiming unit 11b are respectively used to transmit communication signals of different links of the first model OAM module 210; or, the first sub-retiming unit 11a and the second sub-retiming unit 11b are respectively used to transmit communication signals of different links of the second model OAM module 210.

[0092] In this way, through the first sub-retiming unit 11a and the second sub-retiming unit 11b, a single retiming unit 11 can support the communication signals of different links of the OAM module 210, fully utilize the resources of the retiming unit 11, and realize the centralized output of communication signals through the above-mentioned scheme.

[0093] See also Figure 1 In some embodiments, the control circuit board 100 further includes at least one first connector 20 and at least one second connector 30. The retiming chip 10 is connected to the at least one first connector 20, and the at least one first connector 20 is connected to the at least one second connector 30. The at least one second connector 30 is used to connect to the switching node 300.

[0094] Specifically, the first connector 20 serves as the connector on the OAM module 210 side, and the second connector 30 serves as the connector on the switching node 300 side. The connection relationship between the OAM module 210, the retiming chip 10, the first connector 20, the second connector 30, and the switching node 300 is as follows: the OAM module 210 is connected to the retiming chip 10, the retiming chip 10 is connected to the first connector 20, the first connector 20 is connected to the second connector 30, and the second connector 30 is connected to the switching node 300. By designing at least one first connector 20 and at least one second connector 30, the connection between the OAM module 210 and the switching node 300 can be conveniently implemented. Furthermore, the number of first connectors 20 and second connectors 30 can be flexibly designed based on actual conditions, thereby improving the scalability of the system.

[0095] Please combine Figures 2 to 5 In some embodiments, the retiming chip 10 includes a plurality of retiming units 11. At least one retiming unit 11 is divided into a first sub-retiming unit 11a and a second sub-retiming unit 11b. The first sub-retiming unit 11a and the second sub-retiming unit 11b each include a plurality of host-side channel ports 115 and a plurality of line-side channel ports 116. The plurality of line-side channel ports 116 of the second sub-retiming unit 11b are connected to the same first connector 20.

[0096] In the embodiment of the present application, the at least one retiming unit 11 includes but is not limited to the aforementioned first retiming unit 111 and / or the second retiming unit 112 . Taking at least one retiming unit 11 including a first retiming unit 111 and a second retiming unit 112 as an example, the line-side channel ports Lane0~Lane3 of the first sub-retiming unit 11a of the first retiming unit 111 and the line-side channel ports Lane8~Lane11 of the first sub-retiming unit 11a of the second retiming unit 112 are shared by the first model OAM module 210 and the second model OAM module 210; while the line-side channel ports Lane4~Lane7 of the second sub-retiming unit 11b of the first retiming unit 111 and the line-side channel ports Lane12~Lane15 of the second sub-retiming unit 11b of the second retiming unit 112 are used solely by the first model OAM module 210. Therefore, the line-side channel ports Lane4~Lane7 and Lane12~Lane15 of the second sub-retiming unit 11b of the first retiming unit 111 and the second retiming unit 112 can be connected to a separate same first connector 20 to save costs. For example, in some cases, when the model of the OAM module 210 is fixed to the second model, the first connector 20 may not be used, that is, the number of first connectors 20 may be reduced, thereby saving costs.

[0097] The following describes, with reference to specific examples, how to implement a common PCBA design for different OAM modules 210 , and how to define and set the transmission path and connector pins between the computing node 200 and the switching node 300 .

[0098] from Figures 2 to 5 It can be seen that after retiming chip 10, the number of SerDes signals is: a SerDes signal of an A series product has a total of 6 (number of lanes) * 8 (number of links) * 2 (TX / RX) = 96 differential pairs, and a SerDes signal of a B series product has a total of 8 (number of lanes) * 8 (number of links) * 2 (TX / RX) / 2 (Gearbox Mode) = 64 differential pairs.

[0099] See also Figure 6 , the first connector 20 and the second connector 30 can use 8*8 high-density connectors. The two-dimensional diagram of the high-density connector is as follows Figure 6 As shown, the high-speed line section is arranged in 8 rows and 8 columns, with each column capable of transmitting 4 transmit signals (TX) and 4 receive signals (RX). The 8x8 high-density connector integrates 64 contact points within a relatively small footprint. This high-density design allows for more signal transmission channels within a limited space, significantly reducing the board area occupied by the connector compared to traditional low-density connectors. Furthermore, the TX and RX configuration enables simultaneous bidirectional data transmission, improving data transmission efficiency and bandwidth.

[0100] Taking a single computing node 200 including two OAM modules 210 as an example, each OAM module 210 has a maximum of 96 differential pairs. The first connector 20 needs to support a maximum of 96*2=192 differential pairs. Therefore, 192 / (8*8)=3 high-density connectors are selected (the B series products only need 2 high-density connectors) to meet the requirements.

[0101] Taking the A series products as an example, the entire cabinet can usually support up to 12 switching nodes 300. To ensure that each OAM module 210 can interconnect with each switching node 300, each OAM module 210 needs to have 96 / 12 = 8 differential pairs (i.e., 4 lanes) connected to the corresponding switching node 300. Therefore, based on 8*8 / 8 differential pairs, a maximum of 8 computing nodes 200 can be supported. The interconnection relationship between the 8 computing nodes 200 (represented as GPU+CPU Node) and the 12 switching nodes 300 (represented as SwitchNode) is as follows: Figure 7 As shown, each point (such as A1) corresponds to Figure 6 8 rows and 2 columns (a computing node 200 is connected to 8 differential pairs of an OAM, and 2 OAMs are 16 differential pairs, that is, Figure 6 8 rows and 2 columns in the ). And so on from left to right, Figure 7 Each row in represents a high-density connector. For example, A1, B1, C1, and D1 correspond to one high-density connector; A2, B2, C2, and D2 correspond to another high-density connector.

[0102] The interconnection relationship between compute node 200 and switch node 300 is that every point in the high-density connector corresponding to compute node 200 is interconnected with every point in the high-density connector corresponding to switch node 300. For example, A1 in the high-density connector corresponding to compute node 200 is interconnected with A1 in the high-density connector corresponding to switch node 300, A2 in the high-density connector corresponding to compute node 200 is interconnected with A2 in the high-density connector corresponding to switch node 300, A3 in the high-density connector corresponding to compute node 200 is interconnected with A3 in the high-density connector corresponding to switch node 300, and so on. Thus, each compute node 200 requires three first connectors 20 (the first one is A1, B1, C1, and D1; the second one is E1, F1, G1, and H1; and the third one is I1, J1, K1, and L1). Each switch node 300 requires two second connectors 30 (the first one is A1, A2, A3, and A4; the second one is A5, A6, A7, and A8).

[0103] The feasibility of this solution is theoretically explained above. The pin definition of the first connector 20 is described below as an example.

[0104] The SerDes interconnection topology of the entire system is as follows Figure 8 As shown, OAM0 is one OAM module 210, and OAM1 is another OAM module 210. S1L, S2, S3, S4, S5, S6, and S7 represent eight links of a single OAM module 210, respectively.

[0105] along Figure 8At the position of the middle dotted line L1, the corresponding signals are: S1_lane0-3, S2_lane0-3, S1_lane4-7, S2_lane4-7, S1_lane4-7, S2_lane4-7, S3_lane0-3, S4_lane0-3, S3_lane4-7, S4_lane4-7, S3_lane4-7, S4_lane4-7, S5_lane0-3, S6_lane0-3, S5_lane4-7, S6_lane4-7 ane4-7, S5_lane4-7, S6_lane4-7, S1_lane8-11, S7_lane0-3, S1_lane0-3, S2_lane0-3, S3_lane0-3, S4_lane0- 3. S1_lane12-15, S7_lane4-7, S5_lane0-3, S6_lane0-3, S1_lane8-11, S7_lane0-3, S1_lane12-15, S7_lane4-7.

[0106] PHY Retimer0~7 represent 8 retimer chips 10 respectively. Figure 8 At the position of the middle dotted line L2, the corresponding channel openings are: CH0-CH3, CH8-CH11, CH0-CH3, CH8-CH11, CH0-CH3, CH8-CH11, CH0-CH3, CH8-CH11, CH0-CH3, CH8-CH11, CH0-CH3, CH8-CH11, CH4-CH7, CH12-CH15, CH0-CH3, CH8-CH11, CH4-CH7, CH12-CH15, CH0-CH3, CH4-CH7, CH8-CH11, CH12-CH15, CH4-CH7, CH12-CH15.

[0107] Combined with the above Figures 2 to 5 The line-side channel ports Lanes 0 to 3 and Lanes 8 to Lane 11 of the retiming chip 10 are connected to the first two 8*8 high-density connectors. These lines are shared by the first and second OAM modules 210. The line-side channel ports Lanes 4 to Lane 7 and Lanes 12 to Lane 15 are used by the first OAM module 210 and are connected to the third 8*8 high-density connector. The pin definitions of the first connector 20 are as follows: Figure 8 The lines in the diagram are connected from left to right to Figure 6 Columns 1-8 in . For example, Figure 8The order is: CH0-CH3 connected to the first column, CH8-CH11 connected to the second column and so on. At this time, taking the first high-density connector of the first model OAM module 210 solution as an example, the corresponding Figure 7 The interconnection relationship can realize the connection between S1_lane4-5 and S2_lane4-5 of OAM0 and OAM1 Figure 7 In the first switching node 300, S1_lane6-7 and S2_lane6-7 are connected to Figure 7 The pins are defined in the second switching node 300. Similarly, this pin definition allows interconnection between a single OAM module 210 and twelve switching nodes 300. Similarly, for the second OAM module 210, the third high-density connector does not participate in signal transmission in actual applications. Only the first two high-density connectors are required to achieve 112Gbps SerDes signal transmission.

[0108] When multiple computing nodes 200 and switching nodes 300 are placed in the entire cabinet at the same time, each computing node 200 can be connected to the switching node 300 through a cable in the above manner to achieve OAM interconnection between each computing node 200 in the entire cabinet.

[0109] In summary, after the PCB is designed according to the system interconnection topology and the pin definition of the high-density connector in the embodiment of the present application, the firmware (Firmware, FW) of the retiming chip 10 can be remotely upgraded through the baseboard management controller (Baseboard Management Controller, BMC) to achieve compatibility with a common PCB board of multiple OAM products and realize the universality of the hardware circuit.

[0110] See also Figure 1 and Figure 9 The control method of the embodiment of the present application is applied to the control circuit board 100 of any of the above embodiments. The control method includes:

[0111] S10: Obtain the model of the OAM module 210;

[0112] S20 : ​​Configuring the retiming chip 10 to a signal retiming mode or a signal adaptation mode according to the model of the OAM module 210 .

[0113] In the control method of the embodiment of the present application, when the retiming chip 10 is configured in signal retiming mode, the retiming chip 10 is used to transparently transmit the communication signal of at least one channel within at least one link of the OAM module 210 to the switching node 300. When the retiming chip 10 is configured in signal adaptation mode, the retiming chip 10 is used to combine the communication signals of at least two channels within at least one link of the OAM module 210 and transmit them to the switching node 300. The retiming chip 10 can be configured in different modes for different OAM modules 210, thereby achieving compatibility with multiple different OAM module 210 designs within a single control circuit board 100.

[0114] Specifically, the BMC firmware code can be pre-configured with configuration firmware for the retiming chip 10 for both the A-series and B-series products. During system startup, the BMC accesses the OAM module 210 via the Inter-Integrated Circuit (I2C) interface to identify the model of the OAM module 210. Based on the identified model, the BMC automatically configures the signal transmission mode of the retiming chip 10. For example, the retiming chip 10 may be configured to operate in signal retiming mode or signal adaptation mode.

[0115] Furthermore, if a computing node 200 requires a different model of OAM module 210, the existing OAM module 210 can be replaced with the required model. Upon detecting the change of the OAM module 210 model, the BMC automatically reconfigures the firmware of the retiming chip 10 to adapt to the new OAM module 210 configuration.

[0116] For the description of the features in the embodiment corresponding to the control method, please refer to the relevant description of the embodiment corresponding to the control circuit board 100, which will not be repeated here.

[0117] Through the description of the implementation of the aforementioned control circuit board 100, technicians in this field can clearly understand that the method according to the above embodiment can be implemented with the help of software plus the necessary general hardware platform, and of course it can also be implemented through hardware, but in many cases the former is a better implementation method.

[0118] See also Figure 1 and Figure 10 Embodiments of the present application further provide a computer program product 400. The computer program product 400 is applied to the control circuit board 100 of any of the above embodiments. The computer program product 400 includes an acquisition module 410 and a configuration module 420. The acquisition module 410 is configured to acquire the model of the OAM module 210. The configuration module 420 is configured to configure the retiming chip 10 to a signal retiming mode or a signal adaptation mode based on the model of the OAM module 210.

[0119] For descriptions of features in the embodiments corresponding to the computer program product 400 , reference can be made to the relevant descriptions of the embodiments corresponding to the control circuit board 100 and the control method, which will not be repeated here.

[0120] See also Figure 11 An embodiment of the present application further provides an electronic device 500, comprising a memory 510 and a processor 520, wherein the memory 510 stores a computer program, and the processor 520 is configured to run the computer program to execute the steps in any one of the above control method embodiments.

[0121] See also Figure 12 An embodiment of the present application further provides a computer-readable storage medium 600, in which a computer program 610 is stored, wherein the computer program 610 is configured to execute the steps of any of the above control method embodiments when running.

[0122] In an exemplary embodiment, the computer-readable storage medium 600 may include, but is not limited to, various media that can store the computer program 610, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0123] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above control method embodiments are implemented.

[0124] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above control method embodiments are implemented.

[0125] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0126] The above describes in detail a control circuit board 100, a control method, a computer program product 400, an electronic device 500, and a computer-readable storage medium 600 provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A control circuit board, characterized in that: The control circuit board includes a retiming chip, which is used to connect the OAM module and the switching node; When the retiming chip is configured in a signal retiming mode, the retiming chip is used to transparently transmit a communication signal of at least one channel within at least one link of the OAM module to the switching node; When the retiming chip is configured in the signal adaptation mode, the retiming chip is used to combine and transmit communication signals of at least two channels in at least one link of the OAM module to the switching node; The retiming chip includes a plurality of retiming units, each of the retiming units being configured to be in any one of the signal retiming mode or the signal adaptation mode; At least one of the retiming units includes L host-side channel ports and L line-side channel ports; When at least one of the retiming units is configured in the signal retiming mode, the at least one retiming unit is configured to transparently transmit communication signals of channels 1 to L among the M channels in at least one link of the OAM module to the switching node through the L host-side channel ports and the L line-side channel ports, where M>L; When at least one of the retiming units is configured in the signal adaptation mode, at least one of the retiming units is used to combine and transmit the communication signals of the 1st to Lth channels among the N channels within at least one link of the OAM module to the switching node through L host-side channel ports and L / 2 line-side channel ports, where N>L.

2. The control circuit board according to claim 1, characterized in that: When the retiming chip is configured in the signal adaptation mode, the retiming chip is further configured to cross-transmit the communication signal of at least one channel in at least one link of the OAM module to the switching node.

3. The control circuit board according to claim 1, characterized in that: At least one of the retiming units includes a first sub-retiming unit and a second sub-retiming unit, wherein the first sub-retiming unit and the second sub-retiming unit each include L host-side channel ports and L line-side channel ports; When at least one of the retiming units is configured in the signal adaptation mode, at least one of the retiming units is used to cross-transmit the communication signals of the (L+1)th to Mth channels among the M channels in at least two links of the OAM module through the (ML) host-side channel ports in the first sub-retiming unit, the (ML) host-side channel ports in the second sub-retiming unit, and the 2 (ML) line-side channel ports in the first sub-retiming unit to the switching node.

4. The control circuit board according to claim 1, characterized in that: At least one of the retiming units includes a first sub-retiming unit and a second sub-retiming unit, wherein the first sub-retiming unit and the second sub-retiming unit each include L host-side channel ports and L line-side channel ports; When at least one of the retiming units is configured in the signal adaptation mode, at least one of the retiming units is used to cross-transmit the communication signals of the (L+1)th to Nth channels among the N channels within at least two links of the OAM module through the (NL)th host-side channel ports in the first sub-retiming unit, the (NL)th host-side channel ports in the second sub-retiming unit, and the (NL)th line-side channel ports in the first sub-retiming unit to the switching node.

5. The control circuit board according to claim 1, characterized in that: The control circuit board also includes at least one first connector and at least one second connector, the retiming chip is connected to at least one first connector, at least one first connector is connected to at least one second connector, and at least one second connector is used to connect to the switching node.

6. The control circuit board according to claim 5, characterized in that: At least one of the retiming units includes a first sub-retiming unit and a second sub-retiming unit, wherein the first sub-retiming unit and the second sub-retiming unit each include a plurality of host-side channel ports and a plurality of line-side channel ports; The plurality of line-side channel ports of the second sub-retiming unit are connected to the same first connector.

7. A control method, characterized in that: Applied to the control circuit board according to any one of claims 1 to 6, the control method comprises: Obtain the model of the OAM module; The retiming chip is configured to the signal retiming mode or the signal adaptation mode according to the model of the OAM module.

8. The control method according to claim 7, characterized in that: The configuring the retiming chip to the signal retiming mode or the signal adaptation mode according to the model of the OAM module includes: When the model of the OAM module is the first model, configuring the retiming chip to the signal retiming mode or the signal adaptation mode; When the model of the OAM module is the second model, the retiming chip is configured to be in the signal adaptation mode.

9. The control method according to claim 8, characterized in that: The number of channels included in at least one link of the OAM module of the first model is smaller than the number of channels included in at least one link of the OAM module of the second model; and / or The signal output rate of at least one channel in at least one link of the OAM module of the first model is greater than the signal output rate of at least one channel in at least one link of the OAM module of the second model.

10. A computer program product, characterized in that Applied to the control circuit board according to any one of claims 1 to 6, the computer program product comprising: An acquisition module, used to obtain the model of the OAM module; A configuration module is used to configure the retiming chip to the signal retiming mode or the signal adaptation mode according to the model of the OAM module.

11. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the control method according to any one of claims 7 to 9 when executing the computer program.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the control method according to any one of claims 7 to 9.

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