Vector value predictor implementation method, processor and electronic equipment

Abstract

The invention discloses a vector value predictor implementation method, a processor and electronic equipment. The method comprises the following steps: configuring table item numerical field bit width of a vector value cache table of a vector value predictor; when instruction fetching is carried out in an instruction fetching stage of a processor, aiming at an instruction generating a vectorization result, a vector value predictor generates a label through hash according to an instruction address and a branch history of a geometric history length, and carries out matching and arbitration with a VTAGE table; a vector is predicted in the vector value cache table, whether a saturation counter in a table item obtained through arbitration exceeds a threshold value or not is used as a final prediction effective signal, and the final prediction effective signal is directly written into a target vector register of the instruction in the renaming stage; and after the vector instruction is executed, updating the VTAGE table and the vector value cache table. The invention aims to solve the problem that a traditional value predictor in a high-performance processor can only predict a scalar instruction and is difficult to predict a vector instruction, so that the traditional value predictor cannot perform value prediction optimization for a vector program.

Description

Technical Field

[0001] The present invention relates to the technical field of microprocessor design, and in particular to a vector value predictor implementation method, a processor and an electronic device. Background Art

[0002] In modern high-performance processor designs, the processor's value predictor is a key technology for improving instruction-level parallelism and processor performance. Its core concept is to predict the result value of instructions and execute subsequent instructions in advance, thereby reducing pipeline stalls caused by data dependencies. Value predictors typically store historical instruction values and use this information to predict the likely future value of instructions.

[0003] The typical workflow of a value predictor consists of three phases: prediction, speculative execution, and verification and recovery. When an instruction enters the pipeline, the predictor generates a predicted value based on historical values and contextual information (such as the instruction address). The processor then uses the predicted value to continue executing subsequent instructions that depend on that result, bypassing the delay of waiting for the actual calculation result. After the actual result of the instruction is calculated, the correctness of the predicted value is verified. If the prediction is correct, the speculative execution result is retained to improve performance. If the prediction is incorrect, the pipeline state must be restored and execution must be re-executed.

[0004] Existing value predictors are mainly divided into two categories: context-based predictors and calculation-based predictors. A context-based predictor predicts one of the values under the same context (for example, the same instruction address, branch history, path history, etc.), which enables it to predict some repeated numerical sequences. A calculation-based value predictor calculates the previous value using a function to obtain the predicted value. Currently, the most common calculation-based value predictor is the stride predictor, which obtains a new predicted value by adding a stride value to the previous value, and mainly predicts instructions with stride characteristics in the program. However, the above technology is mainly designed for scalar instructions (such as integer or floating-point operations), and its limitations become increasingly prominent when it comes to vectorized instructions (such as SIMD / vector instructions) that are widely used on modern processors.

[0005] Although existing technologies have attempted to improve the accuracy of scalar value prediction by improving prediction algorithms or increasing the depth of historical records, their core designs are still limited by the bit width and processing logic of scalar values and cannot be directly migrated to vector instruction scenarios. For example, the prediction table entries of traditional value predictors usually only store a single scalar value (such as a 32-bit integer or a 64-bit floating-point number), while vector instructions require the simultaneous prediction of a complete vector value containing multiple elements (such as 4 64-bit elements). If the scalar value predictor architecture is simply used, a separate prediction table entry must be allocated for each vector element, which will cause the prediction table capacity requirement to increase exponentially with the vector length. Therefore, in the field of high-performance processors, there is an urgent need for a value predictor for vector instructions that can efficiently capture the characteristics of vector data and output vector prediction results, thereby improving the instruction-level parallelism of vectorized computing. Summary of the Invention

[0006] Technical problem to be solved by the present invention: In response to the above-mentioned problems in the prior art, a vector value predictor implementation method, a processor and an electronic device are provided. The present invention aims to solve the problem that traditional value predictors in high-performance processors can only make predictions for scalar instructions, but are difficult to make predictions for vector instructions, and thus cannot perform value prediction optimization for vector programs.

[0007] In order to solve the above technical problems, the technical solution adopted by the present invention is: A method for implementing a vector value predictor comprises the following steps: Configuring the bit width of the entry value field of the vector value cache table of the vector value predictor to be the same as the bit width of the target vector instruction set; When the processor performs instruction fetching during the instruction fetching phase, the instruction type of the fetched instruction is identified. If the instruction type of the instruction is an instruction that generates a vectorized result, the vector value predictor generates a label by hashing according to the instruction address and the branch history of the geometric history length and matches it with the table entry in the VTAGE table. The table entry of the VTAGE table includes a label, a saturation counter and a pointer. The table entry matching the label is involved in arbitration and the table entry with the longest history length is selected. If the address pointed to by the pointer in the table entry obtained by arbitration is in the three-way set-associated vector value cache table, the corresponding vector in the vector value cache table will be used as the final prediction vector, and whether the saturation counter in the table entry obtained by arbitration exceeds the threshold is used as the final prediction validity signal. If the prediction validity signal is true, the prediction vector will flow with the instruction. After the instruction passes the renaming phase, the predicted valid prediction vector will be written into the destination vector register of the instruction and the register will be marked as available, thereby enabling predictive execution of subsequent vector instructions with dependencies on the instruction. When the vector instruction is executed, the result of the instruction execution is sent to the vector value predictor to update the VTAGE table and the vector value cache table.

[0008] Optionally, the table entry numerical domain bit width of the vector value cache table of the configuration vector value predictor includes: identifying the target vector instruction set currently used, if the target vector instruction set is a 128-bit vector instruction set, then the table entry numerical domain bit width of the configuration vector value cache table is 128 bits; if the target vector instruction set is a 256-bit vector instruction set, then the table entry numerical domain bit width of the configuration vector value cache table is 256 bits; if the target vector instruction set is a 512-bit vector instruction set, then the table entry numerical domain bit width of the configuration vector value cache table is 512 bits.

[0009] Optionally, the updating of the VTAGE table and the vector value cache table includes: judging whether the prediction is accurate based on the result of the instruction execution; if the prediction result is correct, increasing the value of the saturation counter in the corresponding table entry in the VTAGE table until saturation; if the prediction result is wrong, resetting the corresponding table entry content, and trying to allocate a new table entry in a VTAGE table with a longer historical length, writing the correct vector into the vector value cache table, and setting the pointer in the table entry to the hash value of the correct vector.

[0010] Optionally, when allocating a new table entry in the VTAGE table with a longer history length, the saturation counter value in the allocated new table entry is reset to the minimum value.

[0011] Optionally, it also includes a recovery mechanism that triggers the pipeline when the prediction result is wrong.

[0012] In addition, the present invention also provides a processor, including an instruction fetch unit, a decoding unit, a renaming unit, an out-of-order execution engine, a commit unit and a value predictor, wherein the instruction fetch unit, the decoding unit, the renaming unit, the out-of-order execution engine and the commit unit are connected in sequence, and the value predictor is respectively connected to the instruction fetch unit, the renaming unit and the commit unit, and the value predictor is a vector value predictor obtained by the vector value predictor implementation method.

[0013] In addition, the present invention also provides an electronic device, comprising a microprocessor and a memory connected to each other, wherein the microprocessor is provided with a vector value predictor obtained by the vector value predictor implementation method.

[0014] Compared with the prior art, the present invention can mainly achieve the following beneficial effects: 1. The present invention directly stores complete vector values by expanding the prediction table entry bit width, thereby reducing the number of table entries required and lowering the vector value prediction overhead. 2. The present invention supports configuring the table entry bit width, thereby improving the processor's adaptability to diversified vector calculations. 3. The design logic of the present invention is simple, and the prediction principle of this value predictor is basically the same as that of the traditional value predictor, so the modified logic design is relatively simple. In view of the fact that the traditional value predictor cannot directly perform value prediction for vector instructions, the present invention, based on the existing value predictor, stores the vector numerical information in the value predictor by expanding the numerical bit width, thereby enabling the value predictor to directly output the prediction vector, which is used to break the data dependency between vector instructions and improve the instruction-level parallelism of the vector processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Schematic diagram of the working principle of the vector value predictor in an embodiment of the present invention.

[0016] Figure 2 A pipeline architecture diagram of a vector value predictor deployed in an embodiment of the present invention. DETAILED DESCRIPTION

[0017] Based on the existing value predictor architecture, the present invention proposes a method for implementing a value predictor for vector instructions. By expanding the numerical bit width of prediction table entries, this method directly supports the prediction of vectorized results. Based on the EVTAGE (Enhanced VTAGE) value predictor as its foundational framework, the present invention adapts and optimizes instructions that generate vectorized results (such as SIMD instructions). The core design focuses on expanding the vectorized bit width of the VTAGE table to achieve efficient utilization of hardware resources. To facilitate a better understanding of the technical solutions of the present invention by those skilled in the art, the technical solutions of the present invention will be further described below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0018] like Figure 1 As shown, the vector value predictor implementation method of this embodiment includes the following steps: S1, configure the bit width of the entry value field of the vector value cache table of the vector value predictor to be the same as the bit width of the target vector instruction set; S2, when performing instruction fetching in the processor instruction fetch phase, the instruction type of the instruction to be fetched is identified. If the instruction type of the instruction is an instruction that generates a vectorized result, the vector value predictor generates a label by hashing according to the instruction address and the branch history of the geometric history length and matches it with the table entry in the VTAGE table. The table entry of the VTAGE table includes a label, a saturation counter and a pointer. The table entry matching the label is involved in arbitration and the table entry with the longest history length is selected. If the address pointed to by the pointer in the table entry obtained by arbitration is in the three-way group-associated vector value cache table, the corresponding vector in the vector value cache table will be used as the final prediction vector, and whether the saturation counter in the table entry obtained by arbitration exceeds the threshold is used as the final prediction valid signal. If the prediction valid signal is true, the prediction vector will flow with the instruction. After the instruction passes the renaming phase, the predicted valid prediction vector will be written into the destination vector register of the instruction and the register will be marked as available, thereby enabling the predictive execution of the vector instructions with subsequent dependencies of the instruction. S3, when the vector instruction is executed, the result of the instruction execution is sent to the vector value predictor to update the VTAGE table and the vector value cache table.

[0019] In traditional value predictors, three-way set-associative VTABLE value cache entries typically store single scalar values (such as 32-bit integers or 64-bit floating-point numbers). To accommodate the output characteristics of vector instructions, the present invention expands the numerical bit width of the VTABLE to strictly align with the vector register bit width of the processor. For example, in a processor that supports 256-bit SIMD instructions, the numerical domain of the VTAGE table entries is expanded to 256 bits, directly storing a complete vector result consisting of four 64-bit elements, rather than allocating a separate entry for each element. By covering the complete vector value with a single entry, the hardware resource overhead is optimized from the traditional solution where it grows linearly with the number of vector elements to a fixed bit width. Taking a four-element vector as an example, the traditional design requires four independent table entries, while the present embodiment only requires one extended bit width table entry, significantly reducing the prediction table capacity requirement. In step S1 of this embodiment, configuring the table value field bit width of the vector value cache table of the vector value predictor includes: identifying the target vector instruction set currently in use, if the target vector instruction set is a 128-bit vector instruction set, configuring the table value field bit width of the vector value cache table entry to be 128 bits; if the target vector instruction set is a 256-bit vector instruction set, configuring the table value field bit width of the vector value cache table entry to be 256 bits; if the target vector instruction set is a 512-bit vector instruction set, configuring the table value field bit width of the vector value cache table entry to be 512 bits. For example, for the 128-bit NEON instruction set, the table value field is configured to be 128 bits; for the 512-bit AVX-512 instruction set, it is extended to 512 bits. This design ensures compatibility with multi-vector architectures and supports configuration that can flexibly adapt to the bit width requirements of different vector instruction sets.

[0020] Step S2 is the prediction operation step. During the prediction operation, when the processor identifies a vector instruction (such as a NEON 128-bit SIMD instruction) during the instruction fetch phase, the instruction address and the branch history of the geometric history length are hashed to generate indexes and tags for different VTAGE tables. A VTAGE table entry primarily contains three pieces of information: a tag, a saturation counter, and a pointer. The VTAGE table entry that matches the tag participates in arbitration, with the entry with the longest history length used as the basis for subsequent operations. When the saturation counter in the entry exceeds a preset threshold, the pointer in the entry is used to index into a three-way set-associative vector value table. If the address pointed to by the pointer is within the three-way set-associative vector value table, the vector in the vector value table is used as the final prediction vector, and whether the saturation counter exceeds the threshold serves as the final prediction valid signal. If the address pointed to by the pointer is not within the three-way set-associative vector value table, the prediction valid signal is false. The predicted valid prediction vector will flow with the instruction. After the instruction passes the renaming stage, the predicted valid prediction vector will be written into the destination vector register of the instruction and the register will be marked as available. In this way, subsequent vector instructions with dependencies can be executed predictively.

[0021] Step S3 is an update operation. After the vector instruction is executed, the result of the instruction execution is sent to the vector value predictor to update the VTAGE table and the vector value table. If the prediction result is correct, the value of the saturation counter is incremented until saturation is reached. If the prediction result is incorrect, the corresponding table entry content is reset, and an attempt is made to allocate a new table entry in a VTAGE table with a longer history. The saturation counter value of the new table entry is reset to the minimum value, the correct vector is written to the vector value cache table, and the pointer portion of the table entry is set to the hash value of the correct vector. In addition, an incorrect prediction will trigger the pipeline recovery mechanism, which is consistent with traditional implementation methods. In step S3 of this embodiment, updating the VTAGE table and the vector value cache table includes: determining whether the prediction is accurate based on the result of the instruction execution. If the prediction result is correct, the value of the saturation counter in the corresponding table entry in the VTAGE table is incremented until saturation is reached; if the prediction result is incorrect, the corresponding table entry content is reset, and an attempt is made to allocate a new table entry in a VTAGE table with a longer history. The correct vector is written to the vector value cache table, and the pointer portion of the table entry is set to the hash value of the correct vector. In this embodiment, when a new entry is allocated in a longer history length VTAGE table, the saturation counter value in the allocated new entry is reset to the minimum value. In addition, this embodiment also includes a recovery mechanism that triggers the pipeline when the prediction result is wrong, which is consistent with traditional implementation methods.

[0022] like Figure 1The following figure shows the structure of the vector value predictor. The prediction and update operations of this component are illustrated by taking a 128-bit NEON vector program as an example. The pipeline architecture of the vector value predictor is deployed as shown in the figure. Figure 2 As shown. Through the above steps S1 to S3, the method of this embodiment can achieve value prediction for NEON vector instructions by expanding the data bit width of E-VTAGE when encountering NEON vector instructions. Subsequent instructions with dependencies can then be executed predictively, improving the instruction-level parallelism of the processor. It can be seen that the vector value predictor in this embodiment uses the EVTAGE predictor as the basic framework and optimizes storage efficiency through hash value compression technology. During the prediction stage, the hash value of the instruction result is temporarily stored in the table entry of the VTAGE table. Only when the confidence reaches a high threshold, it is converted into a pointer to the vector value cache table to obtain the complete vector value. This mechanism retains the original E-VTAGE storage advantages while seamlessly cooperating with the vectorized vector value cache table: hash compression reduces the storage pressure of the scalar prediction table, while the extended bit width value cache table provides complete storage and fast access to vector results. Through the above-mentioned vectorized bit width expansion design, this embodiment improves the adaptability of the value predictor to vector instructions without introducing complex prediction logic, providing an effective solution for high-parallel vectorized value prediction in high-performance processors. In view of the fact that traditional value predictors are unable to directly predict values for vector instructions, the present invention is based on the original value predictor and, on its basis, stores the vector numerical information in the value predictor by expanding the numerical bit width, so that the value predictor can directly output the predicted vector, which is used to break the data dependency between vector instructions and improve the instruction-level parallelism of the vector processor.

[0023] In addition, this embodiment also provides a processor, including an instruction fetch unit, a decoding unit, a renaming unit, an out-of-order execution engine, a commit unit and a value predictor. The instruction fetch unit, decoding unit, renaming unit, out-of-order execution (OoO) engine and commit unit are connected in sequence. The value predictor is respectively connected to the instruction fetch unit, renaming unit and commit unit. The value predictor is a vector value predictor obtained by the vector value predictor implementation method.

[0024] In addition, this embodiment also provides an electronic device, including a microprocessor and a memory connected to each other, wherein the microprocessor implements the vector value predictor obtained by the vector value predictor implementation method.

[0025] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A method for implementing a vector value predictor, characterized in that: The steps include: Configuring the bit width of the entry value field of the vector value cache table of the vector value predictor to be the same as the bit width of the target vector instruction set; When the processor performs instruction fetching during the instruction fetching phase, the instruction type of the fetched instruction is identified. If the instruction type of the instruction is an instruction that generates a vectorized result, the vector value predictor generates a label by hashing according to the instruction address and the branch history of the geometric history length and matches it with the table entry in the VTAGE table. The table entry of the VTAGE table includes a label, a saturation counter and a pointer. The table entry matching the label is involved in arbitration and the table entry with the longest history length is selected. If the address pointed to by the pointer in the table entry obtained by arbitration is in the three-way set-associated vector value cache table, the corresponding vector in the vector value cache table will be used as the final prediction vector, and whether the saturation counter in the table entry obtained by arbitration exceeds the threshold is used as the final prediction validity signal. If the prediction validity signal is true, the prediction vector will flow with the instruction. After the instruction passes the renaming phase, the predicted valid prediction vector will be written into the destination vector register of the instruction and the register will be marked as available, thereby enabling predictive execution of subsequent vector instructions with dependencies on the instruction. When the vector instruction is executed, the result of the instruction execution is sent to the vector value predictor to update the VTAGE table and the vector value cache table.

2. The method for implementing a vector value predictor according to claim 1, wherein: The bit width of the numerical domain of the table entries of the vector value cache table of the configuration vector value predictor includes: identifying the target vector instruction set currently used, if the target vector instruction set is a 128-bit vector instruction set, then the bit width of the numerical domain of the table entries of the configuration vector value cache table is 128 bits; if the target vector instruction set is a 256-bit vector instruction set, then the bit width of the numerical domain of the table entries of the configuration vector value cache table is 256 bits; if the target vector instruction set is a 512-bit vector instruction set, then the bit width of the numerical domain of the table entries of the configuration vector value cache table is 512 bits.

3. The method for implementing a vector value predictor according to claim 1, wherein: The updating of the VTAGE table and the vector value cache table includes: judging whether the prediction is accurate based on the result of the instruction execution; if the prediction result is correct, increasing the value of the saturation counter in the corresponding table entry in the VTAGE table until saturation; if the prediction result is wrong, resetting the corresponding table entry content, and trying to allocate a new table entry in a VTAGE table with a longer historical length, writing the correct vector into the vector value cache table, and setting the pointer in the table entry to the hash value of the correct vector.

4. The method for implementing a vector value predictor according to claim 3, wherein: When a new table entry is allocated in a VTAGE table with a longer history length, the saturation counter value in the allocated new table entry is reset to the minimum value.

5. The method for implementing a vector value predictor according to claim 4, wherein: It also includes a recovery mechanism that triggers the pipeline when the prediction result is wrong.

6. A processor comprising an instruction fetch unit, a decode unit, a rename unit, an out-of-order execution engine, a commit unit, and a value predictor, wherein the instruction fetch unit, the decode unit, the rename unit, the out-of-order execution engine, and the commit unit are sequentially connected, and the value predictor is connected to the instruction fetch unit, the rename unit, and the commit unit, respectively, wherein: The value predictor is a vector value predictor obtained by the vector value predictor implementation method according to any one of claims 1 to 5.

7. An electronic device comprising a microprocessor and a memory connected to each other, characterized in that: The microprocessor is a vector value predictor obtained by the vector value predictor implementation method described in any one of claims 1 to 5.

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