Single event upset fault injection simulation evaluation system for MicroBlaze soft core

Abstract

The invention relates to the technical field of SOPC simulation verification, in particular to a single event upset fault injection simulation evaluation system, which comprises a binary file fault injection unit for performing static fault injection on a binary file during compiling, an instruction sending fault injection unit for performing dynamic fault injection on an instruction stream during running, and a single event upset fault injection unit for performing single event upset fault injection after injection. Positioning a physical storage address of the target instruction or data through the mapping relation, and executing a flipping operation on a specified bit; the BRAM simulation unit loads a binary file or dynamically modifies a runtime instruction stream, and the MicroBlaze soft core simulation unit executes an instruction and outputs simulation data in real time; the fault monitoring unit records simulation data in real time, forms monitoring data and sends the monitoring data to the fault comparison unit, the fault comparison unit compares normal and fault monitoring data, and the fault evaluation unit analyzes a fault propagation path and a key function failure probability based on a mapping relation between a source code and an instruction. The fault can be accurately and quickly injected into the soft core, and the influence on the function of the soft core can be evaluated.

Description

Technical Field

[0001] The present invention relates to the technical field of SOPC simulation verification, and in particular to a single-particle upset fault injection simulation evaluation system, method, device and storage medium for a MicroBlaze soft core. Background Art

[0002] The MicroBlaze soft core is an on-chip processor implemented using FPGA logic resources, offering advantages such as high flexibility, low power consumption, and fast response time. However, because its underlying architecture relies on FPGA hardware resources, it is still susceptible to high-energy particles in space radiation environments, causing single-event upsets (SEEs), which can lead to soft core malfunctions and even program loss of control.

[0003] Currently, single-event upset faults in MicroBlaze soft cores are generally injected through radiation testing. However, this method is costly and time-consuming to test, the results are somewhat random, and it is difficult to locate the fault and assess the impact of a single fault.

[0004] Therefore, this paper proposes a single-event upset fault injection simulation and evaluation system and method for MicroBlaze soft cores. By establishing a dual-mode fault injection module, a simulation run module, and a fault impact assessment module, this system accurately injects single-event upset faults into the soft core, assesses the impact of the faults on the soft core's functionality, and verifies the effectiveness of the soft core's radiation hardening measures. This method, which requires no specific hardware platform, simplifies fault injection and is highly targeted, helping to improve the reliability and stability of MicroBlaze soft core designs. Summary of the Invention

[0005] The purpose of the present invention is to address the shortcomings of the prior art and provide a single event upset fault injection simulation evaluation system for MicroBlaze soft cores, including: A dual-mode fault injection module includes a binary file fault injection unit and an instruction transmission fault injection unit. The binary file fault injection unit supports static fault injection into binary files during compilation, while the instruction transmission fault injection unit supports dynamic fault injection into instruction streams during runtime. After fault injection, the module locates the physical storage address of the target instruction or data by parsing the mapping relationship between source code and machine code, and performs a flip operation on the specified bit according to the preset fault type. A simulation operation module includes a BRAM block memory simulation unit and a MicroBlaze soft core simulation unit. The BRAM block memory simulation unit is used to load the binary file containing the fault or dynamically modify the runtime instruction stream. The MicroBlaze soft core simulation unit executes instructions and outputs the program counter pointer, instruction stream and register status in real time. The fault impact assessment module includes a fault monitoring unit, a fault comparison unit and a fault assessment unit. The fault monitoring unit records data including instruction stream, PC trace, register status and response time data during the operation of the soft core in real time, generates monitoring data based on the recorded data and sends it to the fault comparison unit. The fault comparison unit compares normal and fault monitoring data through timing alignment. The fault assessment unit analyzes the fault propagation path and the probability of failure of key functions based on the mapping relationship between source code and instructions.

[0006] Preferably, the binary file fault injection unit includes: During the compilation phase, the machine code in the binary file is analyzed and processed, and the location of the fault injection is selected based on the correspondence between the source code and the machine code in combination with the instruction set format. The number of bits to be flipped is determined based on the preset fault type requirements, and either a single bit flip is performed on the opcode field, or continuous multi-bit flips are performed on the immediate field.

[0007] Preferably, the instruction sending fault injection unit includes: During runtime, the instruction stream sent by the BRAM block memory emulation unit to the soft core is intercepted, and dynamic fault injection is performed according to preset fault trigger conditions. By parsing the mapping relationship between source code and machine code, the physical storage address of the target instruction or data is located, and a flip operation is performed on the specified bit according to the preset fault model.

[0008] Preferably, the MicroBlaze soft core simulation unit includes: The MicroBlaze soft core simulation unit is used to receive instructions and data sent by the BRAM block memory simulation unit according to the address. At the same time, during the operation process, the program counter pointer and instruction information are recorded in chronological order and sent to the fault monitoring unit.

[0009] Preferably, the fault comparison unit includes: The normal monitoring data and the fault monitoring data stream after fault injection are divided into time windows according to clock cycles, and the differences in program counter sequence, instruction stream and register value are compared within the window. If the difference within N consecutive windows exceeds the preset threshold, the comparison data will be sent to the fault assessment unit.

[0010] Preferably, the fault assessment unit includes: The fault assessment unit receives the comparison data with differences, tracks the subsequent execution path of the faulty instruction based on the instruction addresses that are reversed in the source code and the comparison data, marks the affected registers and memory areas, and calculates the functional failure severity score caused by the fault in combination with the list of safety-critical functions to evaluate the impact of the fault injection on the actual function of the soft core.

[0011] Based on the same concept, the present invention also provides a single event upset fault injection simulation evaluation method for a MicroBlaze soft core, comprising the following steps: S1: Choose between static injection at compile time or dynamic injection at runtime. If you choose injection at compile time, the debug information of the binary file is parsed, the correspondence between the source code and the machine code is located, and the fault injection location is selected based on the instruction set format. The target bit is flipped according to the preset fault type. If you choose injection at runtime, the specified bit of the instruction or data is dynamically modified according to the preset fault type during the instruction stream transmission; S2: executing a simulation process containing a fault, recording data including a program counter pointer, an instruction stream, and a register state outputted by the software during verification according to clock cycles, and generating detection data based on the recorded data; S3: Compare the fault monitoring data with the real-time monitoring data, determine the difference type based on the correspondence between the source code and the instructions in the comparison data, and assess the risk of key function failure based on the difference type.

[0012] Preferably, in step S3, determining the difference type based on the correspondence between the source code and the instructions in the comparison data includes: When a semantic change of an instruction due to flipping is identified based on the correspondence between the source code and the instructions in the comparison data, it is determined that there is an instruction-level difference; When an unexpected change in register or memory value is detected based on the correspondence between the source code and the instructions in the comparison data, it is judged as a data-level difference type and traced back to the source fault instruction; Among them, when the number of interruptions or output errors of a safety-critical function exceeds the limit, it is considered a function-level difference type and a fault impact report is generated.

[0013] Based on the same concept, the present invention also provides a computer device, including a memory and a processor, wherein the memory stores computer-readable instructions. When the computer-readable instructions are executed by the processor, the processor executes a module of a single-particle upset fault injection simulation evaluation system for a MicroBlaze soft core as described in any one of the embodiments.

[0014] Based on the same concept, the present invention also provides a storage medium storing computer-readable instructions. When the computer-readable instructions are executed by one or more processors, the one or more processors execute the module of the single-particle upset fault injection simulation evaluation system for the MicroBlaze soft core as described in any one of the embodiments.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The present invention implements binary file fault injection and instruction transmission fault injection through a dual-mode fault injection module. During compilation or runtime, single event upset faults can be injected into the soft core at the bit level, improving the accuracy and efficiency of fault injection. The present invention uses a single event upset fault injection simulation evaluation system to simulate the single event upset fault that may be generated by the MicroBlaze soft core in space radiation, and evaluates the impact of the fault on the soft core function. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Various other advantages and benefits will become apparent to those skilled in the art by reading the following detailed description of the preferred embodiment.The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the invention.

[0017] Figure 1 This is a structural diagram of the single event upset fault injection simulation evaluation system for the MicroBlaze soft core of the present invention; Figure 2 This is a flow chart of the single event upset fault injection simulation evaluation method for the MicroBlaze soft core of the present invention. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Obviously, the embodiments described are part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of this application.

[0019] Those skilled in the art will understand that, unless otherwise specified, the singular forms "a," "an," and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present invention refers to the presence of the stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0020] First embodiment See also Figure 1 As shown, the embodiment provides a single event upset fault injection simulation evaluation system for the MicroBlaze soft core. The system does not require specific hardware equipment, takes a short time, and reduces the cost of fault injection. The dual-mode fault injection module includes a binary file fault injection unit 1 and an instruction sending fault injection unit 2. The binary file fault injection unit 1 is used to support static fault injection into binary files during compilation, and the instruction sending fault injection unit 2 supports dynamic fault injection into instruction streams during runtime. After fault injection, the physical storage address of the target instruction or data is located by parsing the mapping relationship between source code and machine code, and a flip operation is performed on the specified bit according to the preset fault type.

[0021] Preferably, the binary file fault injection unit 1 includes: During the compilation phase, the machine code in the binary file is analyzed and processed. The fault injection location is selected based on the correspondence between the source code and the machine code combined with the instruction set format. The number of bits to flip is determined based on the preset fault type requirements. Either a single bit flip is performed on the opcode field, or continuous multi-bit flips are performed on the immediate field to accurately inject single-event inversion faults.

[0022] Furthermore, the instruction set format is parsed according to the instruction set specification of the target processor. In this embodiment, the instruction format of the ARM instruction set generally includes fields such as an opcode (Opcode), a register number, and an immediate value. The position and length of each field in the instruction are clearly defined. In a 32-bit ARM instruction, the opcode may occupy the first 4 bits, and the register number occupies the next 3 bits. Based on the fault injection requirements, the target source code line or code block is determined, and the corresponding machine code and its physical storage address are found using the mapping relationship. According to the instruction set format, each field in the machine code is analyzed to determine the location of the fault injection. For example, if the opcode field is to be fault injected, the bit where the opcode is located is located. Based on the requirements of the preset fault type, multiple preset fault types are determined, such as single-bit flip and multi-bit continuous flip. The number of bits to be flipped is further determined. For example, a single-bit flip only requires flipping one bit, while multi-bit continuous flip requires specifying a continuous bit range. The binary file containing the machine code is read, and the flip operation is performed at the specified location according to the determined number of bits. For example, to flip the 5th bit, the value of the bit is inverted (0 becomes 1, 1 becomes 0), and the modified machine code is written back to the binary file to complete the fault injection.

[0023] Preferably, the instruction sending fault injection unit 2 includes: During runtime, the instruction stream sent by the BRAM block memory simulation unit 3 to the soft core is intercepted, and dynamic fault injection is performed according to the preset fault trigger conditions. By parsing the mapping relationship between the source code and the machine code, the physical storage address of the target instruction or data is located, and the flip operation is performed on the specified bit according to the preset fault model.

[0024] The instruction sending fault injection unit includes a source code-machine code mapping table for storing the mapping relationship between source code line numbers and corresponding machine code addresses and contents, a fault triggering condition table for recording conditions for triggering fault injection, such as specific instruction codes, timestamps, etc., and a fault model table for defining different fault types and corresponding bit flipping rules.

[0025] When the BRAM block memory emulation unit 3 sends an instruction to the soft core, it intercepts the instruction stream and determines whether the current instruction meets the fault injection condition based on the fault trigger condition table. If the condition is met, the physical address of the target instruction or data is located through the source code-machine code mapping table, and the specified bit is flipped according to the fault model table.

[0026] The simulation operation module includes a BRAM block memory simulation unit 3 and a MicroBlaze soft core simulation unit. The BRAM block memory simulation unit 3 is used to load a binary file containing a fault or dynamically modify the runtime instruction stream. The MicroBlaze soft core simulation unit 4 executes instructions and outputs the program counter pointer, instruction stream and register status in real time. Specifically, in this embodiment, during the simulation operation, the BRAM block memory simulation unit 3 loads the binary file and sends the instructions and data required for the soft core operation to the MicroBlaze soft core simulation unit according to the address.

[0027] Furthermore, the BRAM block memory emulation unit uses a list or dictionary to simulate BRAM to store instructions and data, a dictionary to store the register state of the MicroBlaze soft core, and an integer variable to track the address of the currently executed instruction (i.e., the program counter).

[0028] The BRAM block memory emulation unit loads the binary file containing the fault into the BRAM. The MicroBlaze soft core reads instructions from the BRAM, executes the instructions, and updates the program counter and register status. After each instruction is executed, the program counter, instruction stream, and register status are output.

[0029] Preferably, the MicroBlaze soft core simulation unit 4 includes: The MicroBlaze soft core simulation unit 4 is used to receive instructions and data sent by the BRAM block memory simulation unit 3 according to the address, realize the simulation operation of the soft core, and at the same time, during the operation, record the program counter pointer (i.e., PC pointer) and instruction information in chronological order and send them to the fault monitoring unit 5.

[0030] The fault impact assessment module includes a fault monitoring unit 5, a fault comparison unit 6 and a fault assessment unit 7. The fault monitoring unit 5 records the instruction flow, PC trace, register status and response time data of the soft core in real time, and generates monitoring data based on the recorded data and sends it to the fault comparison unit 6. The fault comparison unit 6 compares the normal and fault monitoring data through timing alignment. The fault assessment unit 7 analyzes the fault propagation path and the failure probability of key functions based on the mapping relationship between source code and instructions. Specifically, in this embodiment, the fault assessment unit 7 has a high degree of freedom and versatility, and can record the simulation operation of the soft core in real time and evaluate the impact of the fault on the soft core function.

[0031] Preferably, the fault comparison unit 6 includes: The normal monitoring data and the fault monitoring data stream after fault injection are divided into time windows according to clock cycles, and the differences in program counter sequence, instruction stream and register value are compared within the window. If the difference within N consecutive windows exceeds the preset threshold, the comparison data will be sent to the fault assessment unit.

[0032] Preferably, the fault assessment unit includes: The fault assessment unit receives the comparison data with differences, traces the subsequent execution path of the faulty instruction based on the instruction addresses that are reversed in the source code and the comparison data, marks the affected registers and memory areas, and calculates the functional failure severity score caused by the fault in combination with the list of safety-critical functions to evaluate the impact of the fault injection on the actual function of the soft core.

[0033] Second embodiment See also Figure 2 As shown, this embodiment provides a single event upset fault injection simulation evaluation method for a MicroBlaze soft core, which is used to execute the system in the first embodiment. The method can accurately and quickly inject a single event upset fault into the soft core, evaluate the impact of the fault on the soft core function, and verify the effectiveness of the soft core anti-radiation hardening technology, including the following steps: S1: Select static injection at compile time or dynamic injection at runtime. If injection at compile time is selected, the debugging information of the binary file is parsed, the correspondence between the source code and the machine code is located, and the position of the fault injection is selected in combination with the instruction set format. The target bit is flipped according to the preset fault type. If injection at runtime is selected, during the transmission of the instruction stream, the specified bit of the instruction or data is dynamically modified according to the preset fault type. Specifically, in this embodiment, static injection at compile time parses the debugging information of the mem binary file. The debugging information usually contains the correspondence between the source code line number and the machine code address. With this information, the correspondence between the source code and the machine code can be accurately located. Combined with the instruction set format of the target processor, such as the position and length of the opcode and operand, the appropriate position of the fault injection is determined. According to the preset fault type, such as single-bit flip, multi-bit flip, etc., the target bit is flipped. During dynamic injection at runtime, the instruction stream is intercepted during its transmission from the memory to the processor for execution. According to the preset fault type, the specified bit in the instruction or data is dynamically modified at runtime. S2: Execute the faulty simulation process, record data including the program counter pointer, instruction stream, and register status output by the soft core in real time according to clock cycles, and generate test data based on the recorded data. Specifically, in this embodiment, the PC pointer output by the soft core, which indicates the address of the currently executed instruction, is recorded in real time according to clock cycles. The currently executed instruction stream and the status of each register are recorded, and the recorded data are organized into a unified test data format for subsequent analysis. S3: Compare the fault monitoring data with the real-time monitoring data, determine the difference type based on the correspondence between the source code and the instructions in the comparison data, and evaluate the risk of critical function failure based on the difference type. Specifically, in this embodiment, the monitoring data after fault injection is carefully compared with the real-time monitoring data under normal circumstances. Based on the correspondence between the source code and the instructions in the comparison data, determine whether the difference is a change in the instruction execution order, an error in the instruction content, or an abnormal register state. Based on different difference types, evaluate the risk level of critical function failure. For example, if the difference appears in the execution instruction of a safety-critical function, then the risk of critical function failure may be high.

[0034] Preferably, in step S3, determining the difference type based on the correspondence between the source code and the instructions in the comparison data includes: When a change in instruction semantics due to a flip is detected based on the correspondence between the source code and the instructions in the comparison data, such as an incorrect jump instruction target address, it is determined that there is an instruction-level difference; When an unexpected change in register or memory value is detected based on the correspondence between the source code and the instructions in the comparison data, it is judged as a data-level difference type and traced back to the source fault instruction; Among them, when the number of interruptions or output errors of the safety-critical function is counted to exceed the limited number, it is a function-level difference type, and a fault impact report is generated. Specifically, in this embodiment, the fault impact report includes a brief description of the time when the fault occurred, the type of injected fault and other basic information, lists the number and specific circumstances of instruction-level differences, data-level differences and function-level differences, analyzes the interruption and output error conditions of the safety-critical function in detail, evaluates the degree of impact on the overall function of the system, and sorts out the propagation path of the fault in the system based on the source fault instructions and data changes. For different types of differences, corresponding repair suggestions and improvement measures are proposed, such as modifying the code, adjusting the fault injection strategy, etc.

[0035] Third embodiment In some embodiments of the present application, a computer device is also provided, including a memory and a processor, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the processor executes a module of a fully digital closed-loop simulation verification system based on a MicroBlaze soft-core Bayer image processing FPGA as described in any one of the first embodiments.

[0036] The present invention also provides a storage medium storing computer-readable instructions. When the computer-readable instructions are executed by one or more processors, the one or more processors execute the module of the fully digital closed-loop simulation verification system based on the MicroBlaze soft-core Bayer image processing FPGA as described in any one of the first embodiments.

[0037] It can be understood that, for the aforementioned all-digital closed-loop simulation verification system based on MicroBlaze soft-core Bayer image processing FPGA, if it is implemented in the form of software function modules and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer server, or a network device, etc.) to perform all or part of the steps of the various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program code.

[0038] Computer-readable storage media may include a data signal propagated in baseband or as part of a carrier wave, which carries readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The readable storage medium may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination thereof.

[0039] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiment. All technical solutions based on the concept of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A single event upset fault injection simulation evaluation system for MicroBlaze soft core, characterized by: include: A dual-mode fault injection module includes a binary file fault injection unit and an instruction transmission fault injection unit. The binary file fault injection unit supports static fault injection into binary files during compilation, while the instruction transmission fault injection unit supports dynamic fault injection into instruction streams during runtime. After fault injection, the module locates the physical storage address of the target instruction or data by parsing the mapping relationship between source code and machine code, and performs a flip operation on the specified bit according to the preset fault type. A simulation operation module includes a BRAM block memory simulation unit and a MicroBlaze soft core simulation unit. The BRAM block memory simulation unit is used to load the binary file containing the fault or dynamically modify the runtime instruction stream. The MicroBlaze soft core simulation unit executes instructions and outputs the program counter pointer, instruction stream and register status in real time. The fault impact assessment module includes a fault monitoring unit, a fault comparison unit and a fault assessment unit. The fault monitoring unit records data including instruction stream, PC trace, register status and response time data during the operation of the soft core in real time, generates monitoring data based on the recorded data and sends it to the fault comparison unit. The fault comparison unit compares normal and fault monitoring data through timing alignment. The fault assessment unit analyzes the fault propagation path and the probability of failure of key functions based on the mapping relationship between source code and instructions.

2. The single event upset fault injection simulation evaluation system for MicroBlaze soft core according to claim 1, characterized in that: The binary file fault injection unit includes: During the compilation phase, the machine code in the binary file is analyzed and processed, and the location of the fault injection is selected based on the correspondence between the source code and the machine code in combination with the instruction set format. The number of bits to be flipped is determined based on the preset fault type requirements, and either a single bit flip is performed on the opcode field, or continuous multi-bit flips are performed on the immediate field.

3. The single event upset fault injection simulation evaluation system for MicroBlaze soft core according to claim 2, characterized in that: The instruction sending fault injection unit includes: During runtime, the instruction stream sent by the BRAM block memory emulation unit to the soft core is intercepted, and dynamic fault injection is performed according to preset fault trigger conditions. By parsing the mapping relationship between source code and machine code, the physical storage address of the target instruction or data is located, and a flip operation is performed on the specified bit according to the preset fault model.

4. The single event upset fault injection simulation evaluation system for MicroBlaze soft core according to claim 3, characterized in that: The MicroBlaze soft core simulation unit includes: The MicroBlaze soft core simulation unit is used to receive instructions and data sent by the BRAM block memory simulation unit according to the address. At the same time, during the operation process, the program counter pointer and instruction information are recorded in chronological order and sent to the fault monitoring unit.

5. The single event upset fault injection simulation evaluation system for MicroBlaze soft core according to claim 4, characterized in that: The fault comparison unit includes: The normal monitoring data and the fault monitoring data stream after fault injection are divided into time windows according to clock cycles, and the differences in the program counter sequence, instruction stream and register value are compared within the window. If the difference within N consecutive windows exceeds a preset threshold, the comparison data will be sent to the fault assessment unit.

6. The single event upset fault injection simulation evaluation system for MicroBlaze soft core according to claim 5, characterized in that: The fault assessment unit comprises: The fault assessment unit receives the comparison data with differences, tracks the subsequent execution path of the faulty instruction based on the instruction addresses that are reversed in the source code and the comparison data, marks the affected registers and memory areas, and calculates the functional failure severity score caused by the fault in combination with the list of safety-critical functions to evaluate the impact of the fault injection on the actual function of the soft core.

7. A single event upset fault injection simulation evaluation method for MicroBlaze soft core, characterized in that: The following steps are involved: S1: Choose between static injection at compile time or dynamic injection at runtime. If you choose injection at compile time, the debug information of the binary file is parsed, the correspondence between the source code and the machine code is located, and the fault injection location is selected based on the instruction set format. The target bit is flipped according to the preset fault type. If you choose injection at runtime, the specified bit of the instruction or data is dynamically modified according to the preset fault type during the instruction stream transmission; S2: executing a simulation process containing a fault, recording data including a program counter pointer, an instruction stream, and a register state outputted by the software during verification according to clock cycles, and generating detection data based on the recorded data; S3: Compare the fault monitoring data with the real-time monitoring data, determine the difference type based on the correspondence between the source code and the instructions in the comparison data, and assess the risk of key function failure based on the difference type.

8. The single event upset fault injection simulation evaluation method for the MicroBlaze soft core according to claim 7, wherein in step S3, the difference type is determined based on the correspondence between the source code and the instructions in the comparison data, including: When a semantic change of an instruction due to flipping is identified based on the correspondence between the source code and the instructions in the comparison data, it is determined that there is an instruction-level difference; When an unexpected change in register or memory value is detected based on the correspondence between the source code and the instructions in the comparison data, it is judged as a data-level difference type and traced back to the source fault instruction; Among them, when the number of interruptions or output errors of a safety-critical function exceeds the limit, it is considered a function-level difference type and a fault impact report is generated.

9. A computer device, characterized in that: The system comprises a memory and a processor, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the processor executes a module of a single-particle upset fault injection simulation evaluation system for a MicroBlaze soft core according to any one of claims 1 to 6.

10. A storage medium storing computer-readable instructions, characterized in that: When the computer-readable instructions are executed by one or more processors, the one or more processors are caused to execute the module of the single event upset fault injection simulation evaluation system for MicroBlaze soft core according to any one of claims 1 to 6.

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