Method for determining layout parameters and semiconductor device

Abstract

The application discloses a layout parameter determination method and a semiconductor device, and belongs to the technical field of semiconductor design and production. The layout parameter determination method comprises the following steps: acquiring the total quantity data of inverters in each ring oscillator and the quantity data of an object inverter; acquiring measured time data, which is the measured delay time of the ring oscillator; acquiring first relational data describing the correlation between the quantity data and the delay time according to the total quantity data, the quantity data and the measured time data; adjusting the layout parameter of the object inverter, and calculating the delay time of the ring oscillator by using a simulation model; acquiring second relational data describing the correlation between the quantity data and the delay time; and comparing the first relational data and the second relational data to determine the layout parameter of the object inverter. The layout parameter determination method and the semiconductor device provided by the application can accurately set the layout parameter of the ring oscillator.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor design and production, and particularly relates to a layout parameter determination method for determining layout parameters according to delay time of a ring oscillator and a semiconductor device. BACKGROUND

[0002] When designing a circuit, a semiconductor integrated circuit device provided with MOS transistors needs to be simulated. For example, when a ring oscillator is formed on a wafer, it is necessary to verify whether the measured delay time of the ring oscillator matches the simulated delay time.

[0003] When simulation is performed using a simulation program with integrated circuit emphasis (SPICE), layout parameters are set in the SPICE. If a simulation model can accurately reproduce the characteristics of MOS transistors, the design efficiency of a semiconductor integrated circuit device can be improved.

[0004] However, when a deviation is found between the measured delay time of the ring oscillator and the simulated delay time, it is difficult to set correct layout parameters, and thus it is difficult to accurately obtain the layout parameters of the ring oscillator. SUMMARY

[0005] The present application aims to provide a layout parameter determination method and a semiconductor device, which can solve the problem that it is difficult to set correct layout parameters and thus accurately obtain the layout parameters of a ring oscillator.

[0006] To solve the above technical problem, the present application is implemented by the following technical scheme:

[0007] The present application provides a layout parameter determination method, which comprises at least the following steps:

[0008] Obtaining total quantity data and quantity data, wherein the total quantity data comprises the number of inverters included in each ring oscillator, each ring oscillator comprises an odd number of inverters, and the inverters are reference inverters or target inverters, the reference inverters and the target inverters have different layout parameters, and the quantity data is the number of target inverters in each ring oscillator;

[0009] Obtaining measured time data, wherein the measured time data is the measured delay time of the ring oscillator;

[0010] According to the total quantity data, the quantity data, and the measured time data, obtaining first relationship data describing the correlation between the quantity data and the measured delay time of the ring oscillator;

[0011] constructing a simulation model of the ring oscillator, adjusting a layout parameter of the subject inverter, and calculating a delay time of the ring oscillator using the simulation model;

[0012] obtaining second relational data describing a relationship between the quantity data and the delay time of the ring oscillator calculated using the simulation model;

[0013] comparing the first relational data and the second relational data to determine the layout parameter of the subject inverter.

[0014] In an embodiment of the present application, the layout parameter includes a distance between a gate electrode and a diffusion layer.

[0015] In an embodiment of the present application, the reference inverter and the subject inverter are identical in layout parameters except for the distance between the gate electrode and the diffusion layer.

[0016] In an embodiment of the present application, the relationship described by the first relational data and the second relational data is a slope of a linear function, and the linear function is plotted in a two-dimensional coordinate system, in which a vertical coordinate is the measured or calculated delay time, and a horizontal coordinate is related to the quantity of the subject inverter.

[0017] In an embodiment of the present application, when the slopes of the first relational data and the second relational data are identical, the layout parameter is determined from the model data.

[0018] In an embodiment of the present application, when the slopes of the first relational data and the second relational data are not identical, an increment or decrement of the layout parameter is set, and the delay time of the ring oscillator is calculated according to the updated layout parameter.

[0019] The present application also provides a method for determining a layout parameter, which comprises at least the following steps:

[0020] obtaining total quantity data, which includes quantities of inverters included in a first ring oscillator and a second ring oscillator, each of the ring oscillators including an odd number of the inverters, and the inverters being reference inverters or subject inverters, the reference inverters and the subject inverters having different layout parameters;

[0021] obtaining first quantity data, which is the quantity of the subject inverters in the first ring oscillator, and the first ring oscillator including at least one reference inverter;

[0022] Acquire second numerical data, where the second numerical data is the number of the target inverters in the second ring oscillator, the second ring oscillator includes at least one target inverter, and the number of the target inverters in the second ring oscillator is different from the number of the target inverters in the first ring oscillator;

[0023] Acquire first time data, where the first time data is a measured delay time of the first ring oscillator;

[0024] Acquire second time data, where the second time data is a measured delay time of the second ring oscillator;

[0025] acquiring first relational data describing a correlation between the number data and the measured delay time of the ring oscillator based on the total number data, the first number data, the second number data, the first time data, and the second time data;

[0026] constructing a simulation model of the first ring oscillator and a simulation model of the second ring oscillator, adjusting layout parameters of the target inverter, and calculating a delay time of the ring oscillator using the simulation model;

[0027] acquiring second relational data describing a correlation between the number data and a delay time of the ring oscillator calculated by the simulation model;

[0028] The first relational data and the second relational data are compared to determine the layout parameters of the target inverter.

[0029] In one embodiment of the present invention, the first ring oscillator only includes the reference inverter.

[0030] In one embodiment of the present invention, the second ring oscillator only includes the object inverter.

[0031] The present invention also includes a semiconductor device comprising:

[0032] The semiconductor device is obtained using the above-mentioned layout parameter determination method, wherein the semiconductor device is provided with the first ring oscillator and the second ring oscillator;

[0033] The first ring oscillator includes an odd number of inverters, and the inverters are reference inverters or object inverters, and the reference inverters and the object inverters have different layout parameters;

[0034] The second ring oscillator includes an odd number of inverters, and the inverters are reference inverters or target inverters. The number of the target inverters in the second ring oscillator is different from the number of the target inverters in the first ring oscillator.

[0035] In summary, the layout parameter determination method and semiconductor device provided by the present invention have the unexpected effect of obtaining first relational data describing the correlation between the number data and the measured delay time of the ring oscillator, and second relational data describing the correlation between the number data and the delay time of the ring oscillator calculated using a simulation model, and comparing the first relational data with the second relational data. If the slopes of the first and second relational data differ, the layout parameters are adjusted and the delay time of the ring oscillator is recalculated until the slopes of the first and second relational data are the same. The layout parameters obtained when the first and second relational data are the same are the desired, precise layout parameters. Furthermore, the correct layout parameters can be used to separate the capacitance and resistance components of a MOS transistor.

[0036] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 FIG. 4 is a circuit block diagram showing the structure of a ring oscillator (first ring oscillator) according to an embodiment of the present invention.

[0039] Figure 2 FIG. 4 is a circuit block diagram showing the structure of a ring oscillator (second ring oscillator) according to an embodiment of the present invention.

[0040] Figure 3 FIG4 is a circuit block diagram of the structure of a ring oscillator (third ring oscillator) according to an embodiment of the present invention.

[0041] Figure 4 FIG. 4 is a layout diagram of a reference inverter and a target inverter in one embodiment of the present invention.

[0042] Figure 5 FIG. 4 is a structural block diagram of a circuit simulation system in one embodiment of the present invention.

[0043] Figure 6 FIG. 1 is a flowchart of the operation of the circuit simulation system according to an embodiment of the present invention.

[0044] Figure 7 FIG. 4 is a diagram showing the relationship between the delay time and the number of target inverters in one embodiment of the present invention.

[0045] Description of labels:

[0046] 11. Ring oscillator; 11a. First ring oscillator; 11b. Second ring oscillator; 11c. Third ring oscillator; 12. Inverter; 12a. Reference inverter; 12b. Target inverter; 61. Circuit simulation system; 62. Model construction unit; 63. Input device; 64. Total quantity data; 65. Number data; 65. Number data; 66. Display screen device; 67. Model data; 68. First relationship generation unit; 71. Measured time data; 72. First relationship data; 73. Second relationship generation unit; 74. SPICE; 75. Prediction time data; 76. Second relationship data; 78. Parameter determination unit; 79. Layout parameter data; 81. Adjustment data; 82. Operation processing unit. DETAILED DESCRIPTION

[0047] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0048] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0049] In the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" and the like indicate positions or locations based on those shown in the accompanying drawings. These terms are intended solely to facilitate the description of the present application and simplify the description, and are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present application. Furthermore, the terms "first" and "second" are used solely for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0050] See also Figures 1 to 3 As shown, in one embodiment of the present invention, a ring oscillator 11 includes multiple inverters 12 connected in a ring shape. Each inverter 12 receives the output of the preceding inverter 12, and the total number of inverters 12 in the ring oscillator 11 is set to an odd number. The final inverter 12 logically negates the output of the initial inverter 12, causing the ring oscillator 11 to oscillate.

[0051] See also Figures 1 to 3 As shown, in one embodiment of the present invention, any one inverter 12 in the ring oscillator 11 can be a reference inverter 12a or an object inverter 12b, and the layout parameters of the reference inverter 12a and the object inverter 12b are different. Figure 1 In the embodiment, the ring oscillator 11 only includes the reference inverter 12a. Figure 1 The ring oscillator 11 shown is defined as a "first ring oscillator 11a". Figure 2 In the embodiment, the ring oscillator 11 includes a reference inverter 12a and an object inverter 12b. Figure 2 The ring oscillator 11 shown is defined as a "second ring oscillator 11b". Figure 3 In the embodiment, the ring oscillator 11 only includes the object inverter 12b. Figure 3 The ring oscillator 11 shown is defined as a “third ring oscillator 11 c ”.

[0052] See also Figure 4 As shown, in one embodiment of the present invention, in the reference inverter 12a, the pMOS transistor is defined as a first pMOS transistor 13, the nMOS transistor is defined as a first nMOS transistor 14, and the drain of the first pMOS transistor 13 and the drain of the first nMOS transistor 14 are connected in series.

[0053] For details, please refer to Figure 4 As shown, in one embodiment of the present invention, in a reference inverter 12a, a first pMOS transistor 13 is provided in an N-well region (not shown) of a wafer 15 and includes a first pMOS active region 16 partitioned by a device isolation region (not shown). A first gate electrode 17 intersects the first pMOS active region 16 via a gate insulating film (not shown). A p-type first reference diffusion layer 18 provided in the first pMOS active region 16 serves as the source of the first pMOS transistor 13, and the source of the first pMOS transistor 13 is connected to a first VDD line 19 via a contact. A p-type second reference diffusion layer 21 provided in the first pMOS active region 16 serves as the drain of the first pMOS transistor 13, and the drain of the first pMOS transistor 13 is connected to a first output line 22 via a contact.

[0054] See also Figure 4As shown, in one embodiment of the present application, in the reference inverter 12a, the first nMOS transistor 14 is provided on a P-well region (not shown) of the wafer 15, and includes a first nMOS active region 24 divided by a device isolation region (not shown). The first nMOS transistor 14 shares the first gate electrode 17 with the first pMOS transistor 13, and the first gate electrode 17 crosses the first nMOS active region 24 through a gate insulating film (not shown). An n-type third reference diffusion layer 25 provided in the first nMOS active region 24 is a source of the first nMOS transistor 14, and the source of the first nMOS transistor 14 is connected to the first GND wiring 27 via a contact. An n-type fourth reference diffusion layer 28 provided in the first nMOS active region 24 is a drain of the first nMOS transistor 14, and the drain of the first nMOS transistor 14 is connected to the first output wiring 22 via a contact.

[0055] Referring to Figure 4 As shown, in one embodiment of the present application, the input wiring of each inverter 12 (i.e. the output wiring of the inverter 12 of the previous stage) is connected to the gate electrode via a contact, and the output wiring is the input wiring of the inverter 12 of the next stage. For example, the first input wiring 29 of the inverter 12 is connected to the first gate electrode 17 via a contact, and the first output wiring 22 is the input wiring of the inverter 12 of the next stage.

[0056] Referring to Figure 4 As shown, in one embodiment of the present application, in the reference inverter 12a, the first gate electrode 17 of the first pMOS transistor 13 and the first reference diffusion layer 18 have a first reference distance SA1, and the first gate electrode 17 and the second reference diffusion layer 21 have a second reference distance SB1. Similarly, the first gate electrode 17 of the first nMOS transistor 14 and the third reference diffusion layer 25 have the first reference distance SA1, and the first gate electrode 17 and the fourth reference diffusion layer 28 have the second reference distance SB1. The first gate electrode 17 and the first reference diffusion layer 18 have the first reference distance SA1, and the first gate electrode 17 and the third reference diffusion layer 25 have the first reference distance SA1. The first gate electrode 17 and the second reference diffusion layer 21 have the second reference distance SB1, and the first gate electrode 17 and the fourth reference diffusion layer 28 have the second reference distance SB1.

[0057] Referring to Figure 4As shown, in one embodiment of the present invention, the spacing between the first gate electrodes 17 of adjacent reference inverters 12a is set to a first gate distance D1. A dummy active area 31 is provided between the first pMOS active area 16 and the first nMOS active area 24 of adjacent reference inverters 12a. The first dummy active area 31 is divided by a device isolation region (not shown). The distance between the boundary of the first dummy active area 31 and the boundaries of the first reference diffusion layer 18, the second reference diffusion layer 21, the third reference diffusion layer 25, and the fourth reference diffusion layer 28 is set to a first dummy distance C1.

[0058] See also Figure 4 As shown, in one embodiment of the present invention, in the target inverter 12b, the pMOS transistor is defined as a second pMOS transistor 33, the nMOS transistor is defined as a second nMOS transistor 34, and the drain of the second pMOS transistor 33 and the drain of the second nMOS transistor 34 are connected in series.

[0059] For details, please refer to Figure 4 As shown, in one embodiment of the present invention, in the target inverter 12b, a second pMOS transistor 33 is provided in an N-well region (not shown) of the wafer 15 and includes a second pMOS active region 36 partitioned by a device isolation region (not shown). A second gate electrode 37 intersects the second pMOS active region 36 via a gate insulating film (not shown). A p-type first target diffusion layer 38 provided in the second pMOS active region 36 serves as the source of the second pMOS transistor 33, and the source of the second pMOS transistor 33 is connected to a second VDD line 39 via a contact. A p-type second target diffusion layer 41 provided in the second pMOS active region 36 serves as the drain of the second pMOS transistor 33, and the drain of the second pMOS transistor 33 is connected to a second output line 42 via a contact.

[0060] See also Figure 4As shown, in one embodiment of the present invention, in the target inverter 12b, the second nMOS transistor 34 is provided in a P-well region (not shown) of the wafer 15 and includes a second nMOS active region 44 partitioned by a device isolation region (not shown). A second gate electrode 37 intersects the second nMOS active region 44 via a gate insulating film (not shown). An n-type third target diffusion layer 45 provided in the second nMOS active region 44 serves as the source of the second nMOS transistor 34, and the source of the second nMOS transistor 34 is connected to a second GND line 47 via a contact. An n-type fourth target diffusion layer 48 provided in the second nMOS active region 44 serves as the drain of the second nMOS transistor 34, and the drain of the second nMOS transistor 34 is connected to a second output line 42 via a contact.

[0061] See also Figure 4 As shown, in one embodiment of the present invention, the input wiring of each inverter 12 (i.e., the output wiring of the preceding inverter 12) is connected to the gate electrode via a contact, and the output wiring serves as the input wiring of the succeeding inverter 12. For example, the second input wiring 49 of the inverter 12 is connected to the second gate electrode 37 via a contact, and the second output wiring 42 serves as the input wiring of the succeeding inverter 12.

[0062] See also Figure 4 As shown, in one embodiment of the present invention, in the target inverter 12 b, the first target distance SA2 between the second gate electrode 37 of the second pMOS transistor 33 and the first target diffusion layer 38 is equal to the second target distance SB2 between the second gate electrode 37 and the second target diffusion layer 41. Similarly, the first target distance SA2 between the second gate electrode 37 of the second nMOS transistor 34 and the third target diffusion layer 45 is equal to the second target distance SB2 between the second gate electrode 37 and the fourth target diffusion layer 48. The first target distance SA2 between the second gate electrode 37 and the first target diffusion layer 38 is equal to the first target distance SA2 between the second gate electrode 37 and the third target diffusion layer 45. The second target distance SB2 between the second gate electrode 37 and the second target diffusion layer 41 is equal to the second target distance SB2 between the second gate electrode 37 and the fourth target diffusion layer 48. The first object distance SA2 and the second object distance SB2 are set smaller than the first reference distance SA1 and the second reference distance SB1 , that is, the first object distance SA2 is smaller than the first reference distance SA1 , and the second object distance SB2 is smaller than the second reference distance SB1 .

[0063] See also Figure 4In an embodiment of the present application, the interval between the first gate electrode 17 of the adjacent target inverter 12b and the second gate electrode 37 of the adjacent target inverter 12b is defined as the third gate distance D3. Between the adjacent reference inverter 12a and the target inverter 12b, and between the first pMOS active region 16 of the adjacent reference inverter 12a and the second pMOS active region 36 of the target inverter 12b, and between the first nMOS active region 24 of the adjacent reference inverter 12a and the second nMOS active region 44 of the target inverter 12b, a third virtual active region 52 is provided. The third virtual active region 52 is divided by an element separation region (not shown). The interval between the boundary of the third virtual active region 52 and the boundary of the first target diffusion layer 38, the boundary of the second reference diffusion layer 21, the boundary of the third target diffusion layer 45, and the boundary of the fourth reference diffusion layer 28 is defined as the third virtual distance C3.

[0064] Referring to Figure 4 In an embodiment of the present application, the interval between the first gate electrode 17 of the adjacent reference inverter 12a and the second gate electrode 37 of the target inverter 12b is defined as the third gate distance D3. Between the adjacent reference inverter 12a and the target inverter 12b, and between the first pMOS active region 16 of the adjacent reference inverter 12a and the second pMOS active region 36 of the target inverter 12b, and between the first nMOS active region 24 of the adjacent reference inverter 12a and the second nMOS active region 44 of the target inverter 12b, a third virtual active region 52 is provided. The third virtual active region 52 is divided by an element separation region (not shown). The interval between the boundary of the third virtual active region 52 and the boundary of the first target diffusion layer 38, the boundary of the second reference diffusion layer 21, the boundary of the third target diffusion layer 45, and the boundary of the fourth reference diffusion layer 28 is defined as the third virtual distance C3.

[0065] Referring to Figure 5 In an embodiment of the present application, the width of the first virtual active region 31, the second virtual active region 51, and the third virtual active region 52 can be adjusted to achieve a layout in which the first gate distance D1, the second gate distance D2, and the third gate distance D3 are equal, and the first virtual distance C1, the second virtual distance C2, and the third virtual distance C3 are equal, while changing the first reference distance SA1, the second reference distance SB1, the first target distance SA2, and the second target distance SB2.

[0066] Referring to Figure 5As shown, the present invention provides a circuit simulation system 61. The circuit simulation system 61 includes a model building unit 62 that can build a simulation model for each ring oscillator 11. When building the simulation model, the model building unit 62 obtains the total number of inverters 12 included in the ring oscillator 11 and the number of target inverters 12b included in each ring oscillator 11. The total number of inverters 12 in all ring oscillators 11 (including the first ring oscillator 11a, the second ring oscillator 11b, and the third ring oscillator 11c) can be obtained. The number of target inverters 12b in a ring oscillator 11 can be "0" (zero), or all of the ring oscillators 11 can be target inverters 12b. Total number data 64 specifying the total number of inverters 12 in the ring oscillators 11 and number data 65 specifying the number of target inverters 12b in each ring oscillator 11 can be input to the model building unit 62 from an input device 63. The input device 63 is, for example, a keyboard. When inputting data, a user interface guiding the operation of the input device 63 can be displayed on the display device 66.

[0067] See also Figure 5As shown, in one embodiment of the present invention, the model construction unit 62 generates model data 67. Model data 67 describes a simulation model for each ring oscillator 11. The simulation model parameters are determined, for example, based on a SPICE model. These parameters include layout parameters of the MOS transistors that comprise the ring oscillator 11. Specifically, the layout parameters include distances SA and SB between gate electrodes and diffusion layer boundaries, specifically including a first reference distance SA1, a second reference distance SB1, a first target distance SA2, and a second target distance SB2 between the first gate electrode 17 and the second gate electrode 37 and the diffusion layers: the first reference diffusion layer 18, the second reference diffusion layer 21, the third reference diffusion layer 25, the fourth reference diffusion layer 28, the first target diffusion layer 38, the second target diffusion layer 41, the third target diffusion layer 45, and the fourth target diffusion layer 48. The layout parameters also include distances between inverters 12, specifically including a first gate distance D1, a second gate distance D2, and a third gate distance D3. Layout parameters also include the distances between the boundaries of the active area and the boundaries of the diffusion layer. Specifically, they include the first virtual distance C1, the second virtual distance C2, and the third virtual distance C3 between the boundaries of the first, second, and third dummy active areas 31, 51, and 52 and the boundaries of the first, second, third, and fourth reference diffusion layers 18, 21, 25, 28, first target diffusion layer 38, second target diffusion layer 41, third target diffusion layer 45, and fourth target diffusion layer 48. For example, in the SPICE model BSIM4 (Berkeley Short-Channel IGFET Model 4), the distances SA and SB between the gate electrode and the diffusion layer boundaries are used as stress effect parameters. As MOS transistors become increasingly miniaturized, the stress effects of shallow trench isolation (STI), which isolates the elements within the channel, increase. Stress directed toward the channel can cause changes in mobility, and changes in mobility can alter the characteristics of the MOS transistor. Therefore, the dimensions of the distances SA and SB significantly impact the design of semiconductor integrated circuit devices.

[0068] See also Figure 5As shown, in one embodiment of the present invention, the circuit simulation system 61 further includes a first relationship generating unit 68, which is capable of obtaining a first correlation between the measured delay time of the ring oscillator 11 and the number of target inverters 12b. When obtaining the correlation, the first relationship generating unit 68 obtains the total number of inverters 12 included in the ring oscillator 11, the number of target inverters 12b included in each ring oscillator 11, and the measured delay time of each ring oscillator 11. Specifically, in addition to the aforementioned total number data 64 and number data 65, the first relationship generating unit 68 also receives measured time data 71 that specifies the measured delay time of each ring oscillator 11. The measured time data 71 can be input via the input device 63. When the measured time data 71 is input to the first relationship generating unit 68, a user interface guiding the operation of the input device 63 can be displayed on the display device 66.

[0069] See also Figure 5 As shown, in one embodiment of the present invention, the first relationship generating unit 68 generates first relationship data 72. The first relationship data 72 describes a first correlation between the measured delay time of the ring oscillator 11 and the ratio of the number of target inverters 12b included in each ring oscillator 11 to the total number of inverters 12 included in the ring oscillator 11. When describing the first correlation, in a two-dimensional coordinate system, the two coordinate axes of the two-dimensional coordinate system represent the number of target inverters 12b included in each ring oscillator 11 and the measured delay time of the ring oscillator 11, respectively. The first correlation described in the first relationship data 72 is the slope of a linear function in the two-dimensional coordinate system.

[0070] See also Figure 5 As shown, in one embodiment of the present invention, the circuit simulation system 61 further includes a second relationship generation unit 73. The second relationship generation unit 73 can obtain a second correlation between the delay time of the ring oscillator 11 calculated based on the simulation model and the number of target inverters 12b. The second relationship generation unit 73 calculates the delay time of the ring oscillator 11 based on the simulation model of the ring oscillator 11 and performs simulation using, for example, SPICE 74. Specifically, the second relationship generation unit 73 generates predicted time data 75, which contains the delay time of the ring oscillator 11 calculated based on the simulation model.

[0071] See also Figure 5As shown, in one embodiment of the present invention, the second relationship generating unit 73 generates second relationship data 76. The second relationship data 76 describes a second correlation between the delay time of the ring oscillator 11 calculated based on the simulation model and the number of target inverters 12b included in each ring oscillator 11. When describing the correlation, similar to the first relationship data 72, in a two-dimensional coordinate system, the two coordinate axes of the two-dimensional coordinate system represent the number of target inverters 12b included in each ring oscillator 11 and the delay time of the ring oscillator 11 calculated based on the simulation model, respectively. The second correlation described in the second relationship data 76 is the slope of a linear function in the two-dimensional coordinate system.

[0072] See also Figure 5 As shown, in one embodiment of the present invention, circuit simulation system 61 further includes a parameter determination unit 78. Parameter determination unit 78 can compare a first correlation determined by the measured delay time of ring oscillator 11 with a second correlation determined by the delay time of ring oscillator 11 calculated based on the simulation model. During the comparison, parameter determination unit 78 obtains first relationship data 72 and second relationship data 76. If parameter determination unit 78 determines that the first and second correlations are identical, it determines the layout parameters. The identity of the first and second correlations is determined based on whether the slopes of the linear functions are identical. Parameter determination unit 78 then obtains layout parameters from model data 67 and outputs layout parameter data 79. Layout parameter data 79 describes the determined layout parameters.

[0073] See also Figure 5 As shown, in one embodiment of the present invention, when the first correlation and the second correlation are not identical, parameter determination unit 78 generates adjustment data 81. Adjustment data 81 describes the increase or decrease value of the layout parameter. When adjusting the layout parameter, parameter determination unit 78 converges the identity of the first correlation and the second correlation.

[0074] See also Figure 6 As shown, in one embodiment of the present invention, the model construction unit 62, the first relationship generation unit 68, the second relationship generation unit 73, the parameter determination unit 78, and the SPICE 74 can be implemented by a processing unit 82. When implementing the model construction unit 62, the first relationship generation unit 68, the second relationship generation unit 73, the parameter determination unit 78, and the SPICE 74, the processing unit 82 retrieves the software program from, for example, a large-capacity storage device. The processing unit 82 executes the software program while storing the software program and data in a temporary storage device. The processing unit 82 is, for example, provided in a computer device.

[0075] See also Figure 6As shown, the present application also uses a circuit simulation system 61 to implement a method for determining layout parameters, and the method for determining layout parameters mainly includes steps S1 to S6.

[0076] See also Figure 6 As shown, in one embodiment of the present invention, in step S1, the model construction unit 62 constructs simulation models of the first ring oscillator 11a, the second ring oscillator 11b, and the third ring oscillator 11c. When constructing the simulation models, the model construction unit 62 obtains total quantity data 64 and number data 65 from an input device 63. The total quantity data 64 includes the total number of inverters 12 in each ring oscillator 11 (including the first ring oscillator 11a, the second ring oscillator 11b, and the third ring oscillator 11c). The number data 65 includes first, second, and third number data. The first number data is the number of target inverters 12b included in the first ring oscillator 11a, the second number data is the number of target inverters 12b included in the second ring oscillator 11b, and the third number data is the number of target inverters 12 included in the third ring oscillator 11c.

[0077] A simulation model was constructed for each inverter 12 based on the SPICE model. Based on the SPICE model, a first reference distance SA1 was set between the first gate electrode 17 and the boundary between the first reference diffusion layer 18 and the third reference diffusion layer 25; a second reference distance SB1 was set between the first gate electrode 17 and the second reference diffusion layer 21 and the fourth reference diffusion layer 28; a first target distance SA2 was set between the second gate electrode 37 and the boundary between the first target diffusion layer 38 and the third target diffusion layer 45; and a second target distance SB2 was set between the second gate electrode 37 and the second target diffusion layer 41 and the fourth target diffusion layer 48. The distances between the preceding and succeeding inverters 12 (i.e., inverter 12a and inverter 12b) were equal. Specifically, the first gate distance D1, the second gate distance D2, and the third gate distance D3 were equal. A first virtual distance C1 between the boundary of the first virtual active region 31 and the boundary of the second reference diffusion layer 21, the fourth reference diffusion layer 28, the first reference diffusion layer 18, and the third reference diffusion layer 25, a second virtual distance C2 between the boundary of the second virtual active region 51 and the boundary of the second target diffusion layer 41, the fourth target diffusion layer 48, the first target diffusion layer 38, and the third target diffusion layer 45, and a third virtual distance C3 between the boundary of the third virtual active region 52 and the boundary of the second reference diffusion layer 21, the fourth reference diffusion layer 28, the first target diffusion layer 38, and the third target diffusion layer 45 are equal.

[0078] See also Figure 7As shown, in one embodiment of the present invention, in step S2, the first relationship generating unit 68 obtains the first correlation between the measured delay time of the ring oscillator 11 and the number of the target inverters 12b. When determining the first correlation, the first relationship generating unit 68 obtains not only the total quantity data 64 and the number data 65, but also the measured time data 71. The measured time data 71 includes first time data, second time data and third time data. The first time data is the delay time measured by the first ring oscillator 11a, the second time data is the delay time measured by the second ring oscillator 11b, and the third time data is the delay time measured by the third ring oscillator 11c. The first relationship generating unit 68 determines the first correlation between the number of the target inverters 12b and the measured delay time of the ring oscillator 11 based on the total quantity 64, the number data 65 and the measured time data 71. The first relationship data 72 is generated in the first relationship generating unit 68. As shown Figure 6 As shown, in the first relational data 72 , the slope mreal of the linear function is determined in the two-dimensional coordinate system.

[0079] See also Figure 6 As shown, in one embodiment of the present invention, in step S3, the second relationship generation unit 73 calculates the delay time of the first ring oscillator 11a, the delay time of the second ring oscillator 11b, and the delay time of the third ring oscillator 11c based on simulation. When calculating the delay time, the second relationship generation unit 73 obtains model data 67. Model data 67 includes simulation models of the first ring oscillator 11a, the second ring oscillator 11b, and the third ring oscillator 11c. The second relationship generation unit 73 generates predicted time data 75. The predicted time data 75 includes first, second, and third predicted time data. The first predicted time data represents the delay time of the first ring oscillator 11a, the second predicted time data represents the delay time of the second ring oscillator 11b, and the third predicted time data represents the delay time of the third ring oscillator 11c.

[0080] See also Figure 7 As shown, in one embodiment of the present invention, in step S4, the second relationship generation unit 73 obtains the second correlation between the delay time of the ring oscillator 11 calculated according to the simulation model and the number of the target inverters 12b. When determining the second correlation, the second relationship generation unit 73 obtains the predicted time data 75 in addition to the total quantity data 64 and the number data 65. The second relationship generation unit 73 obtains the second correlation between the number of the target inverters 12b and the delay time of the ring oscillator 11 calculated according to the simulation model based on the total quantity 64, the number data 65 and the predicted time data 75. The second relationship generation unit 73 generates the second relationship data 76.Figure 6 As shown, in the second relational data 76, the slope mcal of the linear function is determined in the two-dimensional coordinate system.

[0081] See also Figure 6 As shown, in one embodiment of the present invention, in step S5, parameter determination unit 78 compares slope mreal and slope mcal. During the comparison, parameter determination unit 78 obtains first relationship data 72 and second relationship data 76. If slope mreal and slope mcal match, in step S6, parameter determination unit 78 determines layout parameters from model data 67. This determines the layout parameters for target inverter 12b. The delay time of ring oscillator 11 is related to the number of target inverters 12b. When the first correlation determined based on the measured delay time of ring oscillator 11 and the second correlation determined based on the delay time of ring oscillator 11 calculated by the simulation model are identical, a simulation model is constructed that accurately reflects the characteristics of the MOS transistor.

[0082] See also Figure 6 As shown, in one embodiment of the present invention, if the slope mreal and the slope mcal do not match in step S5, the parameter determination unit 78 sets the increase or decrease value of the layout parameter in step S7 to generate adjustment data 81. Adjustment data 81 is supplied to the second relationship generation unit 73. The second relationship generation unit 73 recalculates the delay time in step S3. When calculating the delay time, the layout parameters of the target inverter 12b are modified in the simulation models of the first ring oscillator 11a, the second ring oscillator 11b, and the third ring oscillator 11c. The layout parameters are adjusted according to the increase or decrease values ​​determined in the adjustment data 81. Furthermore, the delay time changes in accordance with the change in the layout parameters, causing the second relationship generation unit 73 to update the predicted time data 75.

[0083] See also Figure 7 As shown, in one embodiment of the present invention, in step S4, the second correlation generating unit 73 determines the second correlation again. In addition to obtaining the total quantity data 64 and the number data 65, the second correlation generating unit 73 also obtains the updated predicted time data 75. The second correlation generating unit 73 generates the second correlation data 76. ​ As shown, in the second relational data 76, the slope mcal of the linear function is determined in the two-dimensional coordinate system. The layout parameters are repeatedly adjusted until the slope of the second relational data 76 matches the slope of the first relational data 72. This converges the slope of the second relational data 76 to that of the first relational data 72, eliminating any deviation in the layout parameters. The capacitance and resistance components are then determined based on the differences in the slices of the linear function.

[0084] The embodiments of the present invention disclosed above are intended only to illustrate the present invention. They do not describe all details in detail, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the content of this specification. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better understand and utilize the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for determining layout parameters, characterized in that: At least the following steps are included: Acquiring total quantity data and number data, the total quantity data including the number of inverters included in each ring oscillator, each ring oscillator including an odd number of the inverters, and the inverters being reference inverters or target inverters, the reference inverter and the target inverter having different layout parameters, and the number data being the number of the target inverters in each ring oscillator; Acquiring measured time data, where the measured time data is the measured delay time of the ring oscillator; acquiring, based on the total quantity data, the number data, and the measured time data, first relational data describing a correlation between the number data and the measured delay time of the ring oscillator; constructing a simulation model of the ring oscillator, adjusting layout parameters of the target inverter, and calculating a delay time of the ring oscillator using the simulation model; acquiring second relational data describing a correlation between the number data and a delay time of the ring oscillator calculated by the simulation model; comparing the first relational data and the second relational data to determine the layout parameters of the target inverter; The layout parameter includes a distance between a gate electrode and a diffusion layer, and the reference inverter and the target inverter have the same layout parameters except for the distance between the gate electrode and the diffusion layer.

2. The method for determining layout parameters according to claim 1, wherein: The correlation described by the first relational data and the second relational data is the slope of a linear function, and the linear function is set in a two-dimensional coordinate system, the vertical axis is the measured or calculated delay time, and the horizontal axis is related to the number of the target inverters.

3. The method for determining layout parameters according to claim 1, wherein: When the slopes of the first relational data and the second relational data are consistent, the layout parameters are determined from the simulation model data.

4. The method for determining layout parameters according to claim 1, wherein: When the slopes of the first relational data and the second relational data are inconsistent, an increase or decrease value of the layout parameter is set, and the delay time of the ring oscillator is calculated according to the updated layout parameter.

5. A method for determining layout parameters, characterized in that: At least the following steps are included: Acquiring all quantity data, where the all quantity data includes the number of inverters included in the first ring oscillator and the second ring oscillator, each of the ring oscillators includes an odd number of the inverters, and the inverters are reference inverters or target inverters, and the reference inverters and the target inverters have different layout parameters; Acquire first numerical data, where the first numerical data is the number of the target inverters in the first ring oscillator, and the first ring oscillator includes at least one reference inverter; Acquire second numerical data, where the second numerical data is the number of the target inverters in the second ring oscillator, the second ring oscillator includes at least one target inverter, and the number of the target inverters in the second ring oscillator is different from the number of the target inverters in the first ring oscillator; Acquire first time data, where the first time data is a measured delay time of the first ring oscillator; Acquire second time data, where the second time data is a measured delay time of the second ring oscillator; acquiring first relational data describing a correlation between the number data and the measured delay time of the ring oscillator based on the total number data, the first number data, the second number data, the first time data, and the second time data; constructing a simulation model of the first ring oscillator and a simulation model of the second ring oscillator, adjusting layout parameters of the target inverter, and calculating a delay time of the ring oscillator using the simulation model; acquiring second relational data describing a correlation between the number data and a delay time of the ring oscillator calculated by the simulation model; comparing the first relational data and the second relational data to determine the layout parameters of the target inverter; The layout parameter includes a distance between a gate electrode and a diffusion layer, and the reference inverter and the target inverter have the same layout parameters except for the distance between the gate electrode and the diffusion layer.

6. The method for determining layout parameters according to claim 5, wherein: The first ring oscillator includes only the reference inverter.

7. The method for determining layout parameters according to claim 5, wherein: The second ring oscillator includes only the object inverter.

8. A semiconductor device, characterized in that: include: The semiconductor device is obtained using the method for determining the layout parameters according to any one of claims 5 to 7, wherein the semiconductor device is provided with the first ring oscillator and the second ring oscillator; The first ring oscillator includes an odd number of inverters, and the inverters are reference inverters or object inverters, and the reference inverters and the object inverters have different layout parameters; The second ring oscillator includes an odd number of inverters, and the inverters are reference inverters or target inverters. The number of the target inverters in the second ring oscillator is different from the number of the target inverters in the first ring oscillator.

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