Mask pattern edge compensation and correction method and system, medium and computer equipment

Abstract

The invention relates to the technical field of semiconductor manufacturing, and particularly provides a mask pattern edge compensation and correction method, which comprises the following steps of: constructing a training data set; training the deep learning model based on the training data set; obtaining a target mask plate design graph, and determining an open circuit position coordinate set of the target mask plate design graph based on optical proximity effect correction simulation of a historical defect database and / or a photoetching imaging model; respectively inputting the target mask design graph, the open circuit position coordinate set of the target mask design graph, photoetching machine model parameters and optical model physical constraint parameters into an open circuit analysis model, and outputting an open circuit probability distribution graph and a graph edge correction rule of the target mask design graph; and inputting the target mask design graph, the open circuit probability distribution graph and the graph edge correction rule into a photoetching imaging model to generate a corrected mask design graph. According to the method, the limitation of traditional correction is broken through, the mask correction precision is remarkably improved, and the circuit breaking risk in chip production is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a mask pattern edge compensation correction method, system, medium and computer equipment. Background Art

[0002] With the rapid development of ultra-large-scale integrated circuits (ULSI), integrated circuit manufacturing processes have become increasingly complex and sophisticated. Photolithography is the driving force behind the development of integrated circuit manufacturing processes and is also one of the most complex technologies. Compared to other individual manufacturing technologies, improvements in photolithography have been of significant significance to the development of integrated circuits. Before the photolithography process begins, the design pattern must first be copied onto a mask using specialized equipment. Then, a photolithography machine copies the pattern structure on the mask onto the silicon wafer used to produce the chip. However, as the design size continues to shrink, approaching or even smaller than the wavelength of light used in the photolithography process, the diffraction and interference effects of light become increasingly pronounced, causing the actual photolithographic pattern to be severely distorted relative to the pattern on the mask. Ultimately, the actual pattern formed on the silicon wafer after photolithography differs from the designed pattern. This phenomenon is known as the optical proximity effect (OPE).

[0003] Under the influence of the optical proximity effect (OPE), the diffraction effect during the lithography process can cause the edges of the design pattern to be blurred or the line ends to be shortened, indirectly causing a pinch in the design pattern; a pinch in the design pattern can lead to functional failure in the final produced chip. To this end, Optical Proximity Correction (OPC) is usually introduced to adjust the edge shape of the mask pattern through OPC to solve the pinch problem. However, insufficient OPC can cause the pinch problem to persist. Alternatively, the correction algorithm during OPC generates error accumulation. For example, when relying on an empirical rule library, if the mutual influence between adjacent patterns is not fully anticipated, the corrected line width may gradually deviate from the target value due to insufficient or excessive proximity effect compensation, forming a potential pinch area.

[0004] Based on this, the present invention provides a mask pattern edge compensation correction method, system, medium and computer equipment to solve the above problems. Summary of the Invention

[0005] In order to overcome the deficiencies of the prior art, the present invention provides a mask pattern edge compensation correction method, system, medium and computer equipment to solve the problems in the prior art.

[0006] One embodiment of the present invention provides a method for compensating and correcting a mask pattern edge, comprising the steps of:

[0007] Constructing a training data set, the training data set comprising multiple sets of historical mask design patterns and corresponding disconnection position coordinate sets, lithography machine model parameters matching each set of the historical masks, and physical constraint parameters of an optical model;

[0008] Training a deep learning model based on the training data set to obtain a trained circuit breaker analysis model;

[0009] Obtaining a target mask design pattern, and determining a set of break position coordinates of the target mask design pattern edges that may cause breaks after silicon wafer exposure based on a historical defect database and / or optical proximity effect correction simulation using a lithography imaging model;

[0010] The target mask design pattern and its corresponding disconnection position coordinate set, the corresponding lithography machine model parameters, and the corresponding optical model physical constraint parameters are respectively input into the trained disconnection analysis model, and the disconnection probability distribution map of the target mask design pattern after silicon wafer exposure and the corresponding pattern edge correction rules are output;

[0011] The target mask design pattern, the disconnection probability distribution diagram and the pattern edge correction rule are input into the photolithography imaging model to generate a corrected mask design pattern.

[0012] By adopting this approach, a deep learning model is trained by constructing a multi-dimensional training dataset that integrates historical mask design patterns, lithography machine parameters, and optical physical constraints. This enables the deep learning model to predict the risk of open circuits in mask patterns during lithography and automatically generate correction solutions. Dynamically generating quantitative correction rules in conjunction with the lithography imaging model overcomes the inherent flaw of traditional OPC, which relies on manual rule iteration. Using the lithography imaging model to simulate and verify the correction results effectively addresses issues such as pattern deformation and line width deviation caused by light wave diffraction, preventing error propagation. This method overcomes the limitations of traditional manual correction, significantly improving mask correction accuracy and reducing the risk of open circuits in chip production.

[0013] In one embodiment, the historical defect database includes optical proximity effect correction parameters of a plurality of mask design patterns and position data of breaks at pattern edges of a plurality of mask design patterns during optical proximity effect correction.

[0014] By adopting the above scheme, the optical proximity effect correction parameters of several historical mask design patterns and the position data of the breaks at the pattern edges of several mask design patterns during the optical proximity effect correction can provide a reference for the target mask design pattern during compensation and correction, making it easier to find which position is most likely to cause a break during compensation and correction, so as to make targeted corrections to that position.

[0015] In one embodiment, the step of obtaining a target mask design pattern and determining a set of break position coordinates of the target mask design pattern that may cause a break at the pattern edge after silicon wafer exposure based on a historical defect database and / or an optical proximity effect correction simulation of a lithography imaging model specifically includes:

[0016] Acquiring a target mask design pattern and an optical proximity effect correction parameter of the target mask design pattern;

[0017] Matching the acquired optical proximity effect correction parameters of the target mask design pattern with the optical proximity effect correction parameters of several mask design patterns in a historical defect database;

[0018] Based on the matching results, the disconnection positions of several mask design patterns having matching values greater than a preset threshold value that appear during silicon wafer exposure are obtained;

[0019] The break positions of all the obtained mask design patterns that appear during silicon wafer exposure are integrated to obtain a break position coordinate set, and the obtained break position coordinate set is used as the break position coordinate set of the target mask design pattern that may cause breakage after silicon wafer exposure.

[0020] By adopting the above scheme, the target mask design pattern and its optical proximity effect correction parameters are matched with the optical proximity effect correction parameters of several mask design patterns in the historical defect database, and one or more historical mask design patterns with matching values exceeding a certain value are found, and the disconnection positions of all the historical mask design patterns found during silicon wafer exposure are integrated. The integrated result is a disconnection position coordinate set, and all positions in the disconnection position coordinate set are positions where the target mask design pattern may cause disconnection during exposure, thereby realizing the disconnection risk prediction of the mask pattern during lithography.

[0021] In one embodiment, after the step of matching the acquired optical proximity effect correction parameters of the target mask design pattern with the optical proximity effect correction parameters of a plurality of mask design patterns in the historical defect database, the method further includes:

[0022] Based on the matching result, if the matching value is less than a preset threshold, the obtained optical proximity effect correction parameters of the target mask design pattern are input into the lithography imaging model to perform an optical proximity effect correction simulation;

[0023] Based on the simulation results, several break locations where breakage may occur at the edge of the target mask design pattern after silicon wafer exposure are obtained, and the obtained several break locations are used as a break location coordinate set.

[0024] By adopting the above scheme, when the matching value is less than a certain value, an optical proximity effect correction simulation is performed on the target mask design pattern to simulate several break positions where the target mask design pattern may produce a break at the edge of the pattern after silicon wafer exposure. The simulated positions are then used as a set of break position coordinates to avoid the situation where there is no mask design pattern matching the target mask design pattern in the historical defect database, thereby making it impossible to predict the break risk of the mask pattern during lithography.

[0025] In one embodiment, the step of inputting the target mask design pattern, the disconnection probability distribution map, and the pattern edge correction rule into the lithography imaging model to generate a corrected mask design pattern specifically includes:

[0026] Based on the disconnection probability distribution map, the target mask design pattern is divided into a high disconnection risk area, a low disconnection risk area, and a low disconnection risk area;

[0027] Generating a staged correction pattern based on the pattern edge correction rules in descending order of risk level; wherein, upon completion of each stage correction, simulating the light intensity gradient distribution of the current correction pattern through a lithography imaging model; if the error between the current correction pattern and the adjacent area exceeds a preset threshold, stopping the correction of the next stage and retroactively adjusting the correction rules of the current stage until the error between the current correction pattern and the adjacent area is within the preset threshold;

[0028] When all stage corrections are completed, the corrected mask design pattern is generated and output.

[0029] By adopting this solution, the target mask design pattern is divided into high, medium, and low disconnection risk areas. Corrections are then performed in stages, from high to low risk. Through a risk-grading and phased correction strategy, high disconnection risk areas are prioritized, and error diffusion in adjacent areas is verified in real time. A lithography imaging model is used to dynamically simulate the corrected intensity gradient distribution. When an error exceeding the limit is detected in an adjacent area, subsequent corrections are immediately stopped and the current rules are retroactively adjusted to ensure the stability of the local correction and compatibility with the global process window. This effectively solves the error accumulation problem caused by traditional single global corrections. Through a closed-loop iterative mechanism of "correction-verification-backtracking," secondary defects caused by overcorrection in high disconnection risk areas are avoided, while resource waste caused by premature adjustments in low-risk areas is prevented, significantly improving mask correction efficiency.

[0030] In one embodiment, the step of generating the phased correction graphics based on the graphic edge correction rules in descending order of risk level further includes the following steps:

[0031] a) identifying, based on the disconnection probability distribution map, a high disconnection risk region and an adjacent region of the high disconnection risk region in the disconnection probability distribution map of the target mask design pattern;

[0032] b) performing offset correction on the edge of the high disconnection risk area according to the graphic edge correction rule;

[0033] c) simulating the light intensity distribution in the adjacent areas of the corrected high short circuit risk area using a photolithography imaging model;

[0034] d) If the line width error of the adjacent areas exceeds a preset threshold, the offset in the correction rule is dynamically adjusted, and steps b) to c) are repeated until the cumulative error of all adjacent areas is less than the tolerance range.

[0035] By adopting the above scheme, based on the division of high, medium, and low short-circuit risk areas, the high-short-circuit risk area and its adjacent areas are precisely located, and offset correction is prioritized for the edges of the high-short-circuit risk area. The light intensity distribution and line width errors in the adjacent areas are verified in real time using the lithography imaging model. When an error exceeding the limit is detected, the offset in the correction rule is dynamically adjusted and iterative correction is performed until the cumulative error in the adjacent areas converges to a safe tolerance range. Through the collaborative mechanism of "local priority correction-global error suppression", this scheme avoids the overcompensation problem caused by global synchronous correction in traditional methods, and effectively suppresses the error chain diffusion caused by the optical proximity effect through dynamic offset calibration.

[0036] In one embodiment, after the step of inputting the target mask design pattern, the disconnection probability distribution map, and the pattern edge correction rule into the lithography imaging model to generate a corrected mask design pattern, the following step is further included:

[0037] Reverse engineering the modified mask design pattern based on a lithography imaging model, minimizing the disconnection probability and line width error after silicon wafer exposure through an optimization algorithm, and generating an optimal pattern of the target mask;

[0038] The optimal graph is used as an optimization training set to optimize the circuit breaker analysis model.

[0039] By adopting the above solution, the accuracy and adaptability of correction are improved through a closed-loop self-optimization mechanism, and optical distortion is accurately compensated through the inverse solution of the lithography imaging model, which directly reduces the risk of circuit breakage and line width error after silicon wafer exposure. At the same time, the optimized graphics are used as training data to optimize the circuit breakage analysis model, thereby improving the circuit breakage risk prediction ability of the circuit breakage analysis model.

[0040] The present application also relates to a mask pattern edge compensation correction system, comprising:

[0041] A data acquisition module is used to construct a training data set, wherein the training data set includes multiple sets of historical mask design patterns and corresponding disconnection position coordinate sets, lithography machine model parameters matching each set of the historical masks, and physical constraint parameters of the optical model;

[0042] A model training module, configured to train a deep learning model based on the training data set to obtain a trained circuit breaker analysis model;

[0043] A disconnect pre-analysis module is used to obtain a target mask design pattern and, based on a historical defect database and / or optical proximity effect correction simulation of a lithography imaging model, determine a set of disconnect location coordinates where disconnects may occur at the pattern edge of the target mask design pattern after silicon wafer exposure.

[0044] The correction parameter analysis module is used to input the target mask design pattern and its corresponding disconnection position coordinate set, the corresponding lithography machine model parameters, and the corresponding optical model physical constraint parameters into the trained disconnection analysis model, and output the disconnection probability distribution map of the target mask design pattern after silicon wafer exposure and the corresponding pattern edge correction rules;

[0045] The compensation correction module is used to input the target mask design pattern, the disconnection probability distribution map and the pattern edge correction rule into the photolithography imaging model to generate a corrected mask design pattern.

[0046] By adopting this approach, a deep learning model is trained by constructing a multi-dimensional training dataset that integrates historical mask design patterns, lithography machine parameters, and optical physical constraints. This enables the deep learning model to predict the risk of open circuits in mask patterns during lithography and automatically generate correction solutions. Dynamically generating quantitative correction rules in conjunction with the lithography imaging model overcomes the inherent flaw of traditional OPC, which relies on manual rule iteration. Using the lithography imaging model to simulate and verify the correction results effectively addresses issues such as pattern deformation and line width deviation caused by light wave diffraction, preventing error propagation. This method overcomes the limitations of traditional manual correction, significantly improving mask correction accuracy and reducing the risk of open circuits in chip production.

[0047] The present application also relates to a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the above-mentioned mask pattern edge compensation correction method are implemented.

[0048] The present application also relates to a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the above-mentioned mask pattern edge compensation correction method are implemented.

[0049] The mask pattern edge compensation correction method, system, medium, and computer device provided in the above embodiments have the following beneficial effects:

[0050] 1. By constructing a multi-dimensional training dataset that integrates historical mask design patterns, lithography machine parameters, and optical physical constraints, a deep learning model is trained. This enables the deep learning model to predict the risk of open circuits in mask patterns during lithography and automatically generate correction solutions. Dynamically generating quantitative correction rules in conjunction with a lithography imaging model overcomes the inherent flaw of traditional OPC, which relies on manual rule iteration. Using the lithography imaging model to simulate and verify the correction results effectively addresses issues such as pattern deformation and line width deviation caused by light wave diffraction, preventing error propagation. This method overcomes the limitations of traditional manual correction, significantly improving mask correction accuracy and reducing the risk of open circuits in chip production.

[0051] 2. By matching the target mask design pattern and its optical proximity effect correction parameters with the optical proximity effect correction parameters of several mask design patterns in the historical defect database, one or more historical mask design patterns whose matching values exceed a certain value are found, and the break positions of all the historical mask design patterns found when the silicon wafer is exposed are integrated. The integration is a break position coordinate set. All positions in the break position coordinate set are positions where the target mask design pattern may break during exposure, thereby realizing the break risk prediction of the mask pattern during lithography.

[0052] 3. By dividing the target mask design into high, medium, and low disconnection risk areas, corrections are then performed in stages, from high to low risk. Through a risk-grading and phased correction strategy, high disconnection risk areas are prioritized, and error diffusion in adjacent areas is verified in real time. A lithography imaging model is used to dynamically simulate the corrected intensity gradient distribution. When an error exceeding the limit is detected in an adjacent area, subsequent corrections are immediately stopped and the current rules are retroactively adjusted to ensure the stability of the local correction and compatibility with the global process window. This effectively solves the error accumulation problem caused by traditional single global corrections. Through a closed-loop iterative mechanism of "correction-verification-backtracking," secondary defects caused by overcorrection in high disconnection risk areas are avoided, while resource waste caused by premature adjustments in low-risk areas is prevented, significantly improving mask correction efficiency.

[0053] 4. Based on the division of high, medium, and low short-circuit risk areas, the high short-circuit risk area and its adjacent areas are precisely located, and offset correction is prioritized for the edges of the high short-circuit risk area. The light intensity distribution and line width errors of the adjacent areas are verified in real time using the lithography imaging model. When an error exceeding the limit is detected, the offset in the correction rule is dynamically adjusted and iterative correction is performed until the cumulative error of the adjacent areas converges to a safe tolerance range. Through the collaborative mechanism of "local priority correction-global error suppression", this solution avoids the overcompensation problem caused by global synchronous correction in traditional methods, and effectively suppresses the error chain diffusion caused by the optical proximity effect through dynamic offset calibration. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0055] Figure 1 A flowchart of a mask pattern edge compensation correction method provided by an embodiment of the present invention;

[0056] Figure 2 A flowchart for implementing step S50 of a mask pattern edge compensation correction method provided by an embodiment of the present invention;

[0057] Figure 3 A flowchart for implementing step S51 of a mask pattern edge compensation correction method provided by an embodiment of the present invention;

[0058] Figure 4Schematic diagram of the probability of a break occurring at the edge of a target mask design pattern in an embodiment of the present invention;

[0059] Figure 5 A block diagram of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0060] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0061] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0062] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or suggesting their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features limited to "first" and "second" may explicitly or implicitly include at least one of such features. In addition, if "and / or" or "and / or" appears in the full text, its meaning includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, solution B, or solutions that satisfy both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0063] Reference Figure 1 One embodiment of the present invention provides a method for compensating and correcting a mask pattern edge, comprising the steps of:

[0064] S10, constructing a training data set, wherein the training data set includes multiple sets of historical mask design patterns and corresponding disconnection position coordinate sets, lithography machine model parameters matching each set of the historical masks, and physical constraint parameters of the optical model;

[0065] S20. Training a deep learning model based on the training data set to obtain a trained circuit breaker analysis model;

[0066] S30, obtaining a target mask design pattern, and determining a set of break position coordinates of the target mask design pattern that may cause a break at the pattern edge after silicon wafer exposure based on a historical defect database and / or an optical proximity effect correction simulation of a lithography imaging model;

[0067] S40, inputting the target mask design pattern and its corresponding disconnection position coordinate set, the corresponding lithography machine model parameters, and the corresponding optical model physical constraint parameters into the trained disconnection analysis model, and outputting a disconnection probability distribution map of the target mask design pattern after silicon wafer exposure and a corresponding pattern edge correction rule;

[0068] S50 , inputting the target mask design pattern, the disconnection probability distribution map, and the pattern edge correction rule into a photolithography imaging model to generate a corrected mask design pattern.

[0069] In this embodiment, as described in steps S10-S20 above, the multiple sets of historical mask designs in the constructed training dataset are pre-collected data / parameters corresponding to several similar / approximate mask designs, as well as data / parameters corresponding to several masks with the same / similar / approximate manufacturing processes. The corresponding break position coordinate set is formed by sorting the break locations in each of the multiple sets of historical mask designs that resulted in breaks during silicon wafer exposure. These break locations are integrated into coordinate positions to form a break position coordinate set. The lithography machine model parameters matching each set of historical masks, i.e., the lithography machine selected for exposure of the corresponding mask, and the physical constraint parameters of the optical model matching each set of historical masks, i.e., the parameters for correcting optical proximity effects for the corresponding mask designs. The collected data is pre-processed (e.g., data cleaning, missing value processing, data normalization, etc.) and then integrated into a training dataset for subsequent training of the deep learning model. The deep learning model uses any one of the convolutional neural network (CNN), recurrent neural network (RNN), and generative adversarial network (GAN). By utilizing the training data set, the deep learning model learns the mapping relationship between the mask design graphics, lithography machine parameters and physical constraint parameters of the optical model to the disconnection position coordinates and graphic edge adjustment parameters from the training data set, so as to obtain a trained disconnection analysis model, which is used to predict the disconnection risk of the mask graphics during lithography, and thus output the corresponding correction plan.

[0070] In this embodiment, as described in step S30 above, the target reticle design pattern is the reticle design pattern that requires optical proximity correction. The historical defect database is constructed by compiling and analyzing the locations of breaks that occurred during wafer exposure for several pre-collected reticle designs that are similar or similar in design, as well as the correction parameters used when performing optical proximity correction. The acquired target reticle design pattern is matched with the reticle designs in the historical defect database using a similarity algorithm. Optical proximity correction (OPC) simulation using a lithography imaging model is also performed simultaneously, or only using optical proximity correction simulation using a lithography imaging model (to generate a simulated pattern to identify all possible locations where breaks may occur) to determine the coordinate set of possible break locations on the target reticle design pattern edge after wafer exposure.

[0071] For optical proximity effect correction simulation of the lithography imaging model, computer-aided software tools for OPC (OPC software) known in the art can be used to simulate exposure of the target mask design pattern. Such software may have preset simulation exposure rules, which can be modified by those skilled in the art. This application does not limit the specific simulation exposure rules.

[0072] In this embodiment, as described in step S40 above, the acquired target mask design pattern is input into the disconnection analysis model. At the same time, the corresponding disconnection position coordinate set, the corresponding lithography machine model parameters, and the corresponding optical model physical constraint parameters are respectively input into the trained disconnection analysis model. The trained disconnection analysis model outputs the disconnection probability distribution diagram of the target mask design pattern after silicon wafer exposure and the corresponding pattern edge correction rules based on the "mapping relationship between mask design pattern, lithography machine parameters and physical constraint parameters of the optical model to disconnection position coordinates and pattern edge adjustment parameters" learned in the training phase. Figure 4 As shown, it is a schematic diagram of the probability of a break occurring at the edge of the target mask design pattern.

[0073] For example, the disconnection analysis model uses a convolutional neural network;

[0074] 1. Input includes the following data:

[0075] Target mask design graphics (2D / 3D graphic data, such as GDSII format), the set of break position coordinates generated in step S30 (a set of break position coordinate points that may cause a break), lithography machine model parameters (such as numerical aperture NA, illumination mode, light source wavelength, etc.); optical model physical constraint parameters (such as the frequency domain coefficients of the Hopkins diffraction equation, resist model parameters).

[0076] 2. Output mechanism:

[0077] (1) Generation of circuit breaker probability distribution diagram.

[0078] Feature extraction: Use convolutional neural networks (CNNs) to extract the spatial features of the design graphics (such as line width, spacing, corner shape, etc.) and generate high-dimensional feature maps.

[0079] Coordinate attention mechanism: Encode the coordinates of the disconnection location in step S30 as spatial attention weights (e.g., through a graph neural network or a coordinate encoding layer) to enhance the model's attention to areas with high disconnection risk.

[0080] Probability prediction: The feature map is mapped to the disconnection probability value (0-1) of each pixel through the classification layer (such as the activation function), forming a probability distribution in the form of a heat map.

[0081] (2) Generation of graphic edge correction rules.

[0082] Physical constraint fusion: The lithography machine parameters (such as NA) and optical model parameters (such as Hopkins equation coefficients) are input into the fully connected layer to generate a physical feature vector, which is then fused with the graphic features.

[0083] Regression network: The regression layer predicts the offset (Δx, Δy) of each edge point or the insertion rule (such as position, width) of the sub-resolution auxiliary pattern (SRAF).

[0084] Rule encoding: Revision rules can be represented as structured data.

[0085] Example output: If the model detects that an edge is prone to breakage due to insufficient photoresist coverage, it may generate a rule: "Edge L1 is offset outward by 1.5nm." If the spacing between adjacent patterns is too small, it may insert an SRAF to improve the light intensity distribution.

[0086] In this embodiment, as described in step S50 above, the target mask design pattern, the disconnection probability distribution map, and the pattern edge correction rules are input into the lithography imaging model. The lithography imaging model corrects the target mask design pattern based on the disconnection probability distribution map and the pattern edge correction rules output by the disconnection analysis model, and generates a corrected mask design pattern.

[0087] In one embodiment, the historical defect database in step S30 includes optical proximity effect correction parameters for a number of mask design patterns, as well as location data of breaks at the edges of a number of mask design patterns during optical proximity effect correction. Furthermore, step S30 specifically includes the following steps:

[0088] S31, obtaining a target mask design pattern and an optical proximity effect correction parameter of the target mask design pattern;

[0089] S32, matching the obtained optical proximity effect correction parameters of the target mask design pattern with the optical proximity effect correction parameters of several mask design patterns in the historical defect database;

[0090] S33A, based on the matching results, obtaining the disconnection locations of several mask design patterns having matching values greater than a preset threshold value when the silicon wafer is exposed;

[0091] S34A. Integrate the break positions of all the obtained mask design patterns that appear when the silicon wafer is exposed to obtain a break position coordinate set, and use the obtained break position coordinate set as the break position coordinate set of the target mask design pattern that may cause breakage after the silicon wafer is exposed.

[0092] After step S32, the method further includes:

[0093] S33B, based on the matching result, if the matching value is less than a preset threshold, inputting the obtained optical proximity effect correction parameters of the target mask design pattern into the lithography imaging model to perform an optical proximity effect correction simulation;

[0094] S34B. Based on the simulation results, several break positions where the target mask design pattern may break at the pattern edge after silicon wafer exposure are obtained, and the obtained several break positions are used as a break position coordinate set.

[0095] In this embodiment, the purpose of acquiring a target reticle design pattern is to obtain optical proximity correction parameters for the target reticle design pattern to be corrected. The obtained optical proximity correction parameters for the target reticle design pattern are then matched with the optical proximity correction parameters of several reticle designs in a historical defect database using a similarity algorithm (e.g., cosine similarity). Assuming a preset threshold of 80%, based on the matching results, if there are 10 historical reticle designs with a matching value greater than 80% with the target reticle design pattern, the locations of breaks that appear in these 10 reticle designs during silicon wafer exposure are extracted and integrated to obtain a set of break location coordinates. This set of break location coordinates represents the set of break location coordinates that may occur in the target reticle design pattern after silicon wafer exposure. Based on the matching results, there is no historical mask design pattern with a matching value greater than 80% with the target mask design pattern. At this time, the target mask design pattern is corrected and simulated using the optical proximity correction effect of the lithography imaging model to obtain an exposure simulation pattern of the target mask design pattern to determine the break position where the target mask design pattern may cause a break at the edge of the pattern after silicon wafer exposure. The break position is converted into a coordinate position and integrated into a break position coordinate set for subsequent use as input data for a break analysis model to output a break probability distribution map.

[0096] Reference Figure 2 In one embodiment, step S50 specifically includes:

[0097] S51, dividing the target mask design pattern into a high-disconnection risk area, a low-disconnection risk area, and a low-disconnection risk area based on the disconnection probability distribution map;

[0098] S52, generating a staged correction pattern based on the pattern edge correction rules in descending order of risk level; wherein, upon completion of each stage correction, simulating the light intensity gradient distribution of the current correction pattern using a lithography imaging model; if the error between the current correction pattern and the adjacent area exceeds a preset threshold, stopping the next stage correction and retroactively adjusting the correction rules of the current stage until the error between the current correction pattern and the adjacent area falls within the preset threshold;

[0099] S53. When all stage corrections are completed, generate and output the corrected mask design pattern.

[0100] In this embodiment, based on the disconnection probability distribution map output by the disconnection analysis model, the target mask design pattern is then divided into a high disconnection risk area, a disconnection risk area, and a low disconnection risk area, such as Figure 4 As shown, it is assumed that areas with a risk probability below 50% are classified as low-disconnection risk areas, areas with a risk probability between 50% and 80% are classified as medium-disconnection risk areas, and areas with a risk probability greater than 80% are classified as high-disconnection risk areas. OPC software, based on a lithography imaging model, then corrects the target mask design pattern in stages, based on pattern edge correction rules, from high to low risk levels. The corrected pattern is then generated in stages. By prioritizing high-disconnection risk areas, error diffusion caused by simultaneous global corrections can be avoided.

[0101] Among them, in the correction process according to the risk level (in stages), only when the current stage correction is qualified will the next stage of correction be entered; for example, the correction is now aimed at the high short circuit risk area. When the correction is completed, the correction for the short circuit risk area will not be entered first. The light intensity gradient distribution of the current correction pattern is simulated by the lithography imaging model, and the qualification of the current stage correction is judged according to the simulation results. Because error diffusion may occur in the correction process, the purpose is to avoid error diffusion, resulting in error accumulation, and thus forming a new potential short circuit area; if the error between the current correction pattern and the adjacent area exceeds the preset threshold, it is determined that the conditions for entering the next stage are not met, and the current stage is traced back to continue adjustment until the error between the current correction pattern and the adjacent area is within the preset threshold range, and then the next stage of correction is entered.

[0102] The preset thresholds for the error may be: the line width error does not exceed ±5% of the target line width, and the light intensity gradient change rate is less than 10% / nm.

[0103] The adjustment rule for backtracking may be: adjusting the edge offset in the opposite direction according to the error direction, and reducing or increasing the insertion density of the sub-resolution auxiliary pattern (SRAF).

[0104] Only when the corrections at each stage are qualified, the corrected mask design graphics are generated and output.

[0105] Reference Figure 3 In one embodiment, step S52 further includes the following steps:

[0106] a) identifying, based on the disconnection probability distribution map, a high disconnection risk region and an adjacent region of the high disconnection risk region in the disconnection probability distribution map of the target mask design pattern;

[0107] b) performing offset correction on the edge of the high disconnection risk area according to the graphic edge correction rule;

[0108] c) simulating the light intensity distribution in the adjacent areas of the corrected high short circuit risk area using a photolithography imaging model;

[0109] d) If the line width error of the adjacent areas exceeds a preset threshold, the offset in the correction rule is dynamically adjusted, and steps b) to c) are repeated until the cumulative error of all adjacent areas is less than the tolerance range.

[0110] In this embodiment, based on the disconnection probability distribution map output by the disconnection analysis model, the target mask design pattern is divided into a high disconnection risk area, a low disconnection risk area, and a low disconnection risk area. The high disconnection risk area and the adjacent areas of the high disconnection risk area are identified. Regarding the delineation of the adjacent areas, the following steps are performed: with the high-risk area as the center, a certain range is expanded outward (for example, twice the resolution of the lithography machine, such as 6nm at a 3nm node) to ensure that the range of influence of the optical proximity effect is covered. When the high disconnection risk area is corrected according to the pattern edge correction rules output by the disconnection analysis model, the light intensity distribution of the adjacent areas of the corrected high disconnection risk area is simulated through the lithography imaging model to avoid new lithography distortion caused by local correction. For example, "during the correction, the line edges of the high-risk area are expanded by 2nm to increase the line width, which may cause the spacing between adjacent areas to decrease, causing new disconnection risks." When it is detected that the line width error of adjacent areas exceeds a preset threshold, the offset in the correction rule is dynamically adjusted according to the light intensity distribution results simulated by the lithography imaging model, and then steps b) to c) are repeated until the cumulative error of all adjacent areas converges to a safe tolerance range, thereby suppressing the error chain diffusion caused by the optical proximity effect.

[0111] S52, generating a staged correction pattern based on the pattern edge correction rules in descending order of risk level; wherein, upon completion of each stage correction, simulating the light intensity gradient distribution of the current correction pattern using a lithography imaging model; if the error between the current correction pattern and the adjacent area exceeds a preset threshold, stopping the next stage correction and retroactively adjusting the correction rules of the current stage until the error between the current correction pattern and the adjacent area falls within the preset threshold;

[0112] As needed, further, in step S52, the error between the current corrected pattern and the adjacent area includes an edge placement error (EPE) (edge placement error = actual edge position - target edge position, used to reflect the degree of edge offset after lithography), and meets the following conditions:

[0113] S521. Calculate the edge placement error between the actual position of each graphic edge and the target position for all high-disconnection risk areas and their adjacent areas that have been corrected, as well as the target area and its adjacent areas in the current correction phase;

[0114] S522: If the absolute value of the edge placement error exceeds a first preset threshold (e.g., ±3 nm) or the gradient change rate of the edge placement error values of adjacent regions is greater than a second preset threshold (e.g., 5% / nm), it is determined that the error exceeds the limit. For example, if the absolute value of the edge placement error exceeds ±3 nm or the gradient change rate of the edge placement error values of adjacent regions is greater than 5% / nm, it is determined that the error exceeds the limit.

[0115] S523 , adjusting the edge offset in the correction rule so that the corrected edge placement error value satisfies a first preset threshold and the gradient change rate satisfies a second preset threshold.

[0116] In this embodiment, step S521 not only detects the error in the current operating area, but also tracks the stability of the historical correction area to avoid secondary defects in other areas caused by local corrections. In step S522, the gradient change rate threshold is used to identify drastic fluctuations in the light intensity distribution (such as edge mutations caused by the proximity effect of lithography) to block the error diffusion chain in advance. Through the overall dual-threshold dynamic detection and closed-loop adjustment mechanism, the edge placement error (EPE) and light intensity gradient changes in the correction area and adjacent areas can be accurately monitored. When the absolute value of the EPE or the gradient change rate exceeds the limit, the offset is dynamically adjusted in the opposite direction until the error converges, effectively blocking the error diffusion chain and improving line width uniformity.

[0117] In one embodiment, after step S50, the following steps are further included:

[0118] S60, performing reverse engineering on the modified mask design pattern based on a lithography imaging model, minimizing the disconnection probability and line width error after silicon wafer exposure through an optimization algorithm, and generating an optimal pattern of the target mask;

[0119] S70: Optimize the circuit breaker analysis model by using the optimal graph as an optimization training set.

[0120] In this embodiment, the accuracy and adaptability of the correction are improved through a closed-loop self-optimization mechanism, and the optical distortion is accurately compensated through the inverse solution of the lithography imaging model, which directly reduces the risk of circuit failure and line width error after silicon wafer exposure. At the same time, the optimized graphics are used as training data to optimize the circuit failure analysis model, thereby improving the circuit failure risk prediction capability of the circuit failure analysis model.

[0121] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0122] In one embodiment, a mask pattern edge compensation and correction system is provided, which corresponds to the mask pattern edge compensation and correction method in the above embodiment. The mask pattern edge compensation and correction system includes:

[0123] A data acquisition module is used to construct a training data set, wherein the training data set includes multiple sets of historical mask design patterns and corresponding disconnection position coordinate sets, lithography machine model parameters matching each set of the historical masks, and physical constraint parameters of the optical model;

[0124] A model training module, configured to train a deep learning model based on the training data set to obtain a trained circuit breaker analysis model;

[0125] A disconnect pre-analysis module is used to obtain a target mask design pattern and, based on a historical defect database and / or optical proximity effect correction simulation of a lithography imaging model, determine a set of disconnect location coordinates where disconnects may occur at the pattern edge of the target mask design pattern after silicon wafer exposure.

[0126] The correction parameter analysis module is used to input the target mask design pattern and its corresponding disconnection position coordinate set, the corresponding lithography machine model parameters, and the corresponding optical model physical constraint parameters into the trained disconnection analysis model, and output the disconnection probability distribution map of the target mask design pattern after silicon wafer exposure and the corresponding pattern edge correction rules;

[0127] The compensation correction module is used to input the target mask design pattern, the disconnection probability distribution map and the pattern edge correction rule into the photolithography imaging model to generate a corrected mask design pattern.

[0128] The specific definitions of a mask pattern edge compensation and correction system can be found in the definitions of a mask pattern edge compensation and correction method described above and will not be further elaborated here. Each module in the aforementioned mask pattern edge compensation and correction system can be implemented in whole or in part through software, hardware, or a combination thereof. Each of these modules can be embedded in or independent of a processor in a computer device in hardware form, or stored in a computer device memory in software form, allowing the processor to call and execute the corresponding operations of each module.

[0129] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 5 As shown. The computer device includes a processor, memory, network interface, and database connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store mask design graphic data, data processing, data analysis, etc. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a mask graphic edge compensation correction method is implemented.

[0130] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, a method for compensating and correcting a mask pattern edge is implemented.

[0131] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, a method for compensating and correcting a mask pattern edge is implemented.

[0132] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0133] Those skilled in the art will clearly understand that for the sake of convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0134] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A mask pattern edge compensation correction method, characterized in that: Including steps: Constructing a training data set, the training data set comprising multiple sets of historical mask design patterns and corresponding disconnection position coordinate sets, lithography machine model parameters matching each set of the historical masks, and physical constraint parameters of an optical model; Training a deep learning model based on the training data set to obtain a trained circuit breaker analysis model; Obtaining a target mask design pattern, and determining a set of break position coordinates of the target mask design pattern edges that may cause breaks after silicon wafer exposure based on a historical defect database and / or optical proximity effect correction simulation using a lithography imaging model; The target mask design pattern and its corresponding disconnection position coordinate set, the corresponding lithography machine model parameters, and the corresponding optical model physical constraint parameters are respectively input into the trained disconnection analysis model, and the disconnection probability distribution map of the target mask design pattern after silicon wafer exposure and the corresponding pattern edge correction rules are output; The target mask design pattern, the disconnection probability distribution diagram and the pattern edge correction rule are input into the photolithography imaging model to generate a corrected mask design pattern.

2. The mask pattern edge compensation correction method according to claim 1, wherein: The historical defect database includes optical proximity effect correction parameters of a plurality of mask design patterns and position data of disconnections at pattern edges of a plurality of mask design patterns during optical proximity effect correction.

3. The mask pattern edge compensation correction method according to claim 2, characterized in that: The step of obtaining a target mask design pattern and determining a set of break position coordinates of the target mask design pattern where a break may occur at the pattern edge after silicon wafer exposure based on an optical proximity effect correction simulation of a historical defect database and / or a lithography imaging model specifically includes: Acquiring a target mask design pattern and an optical proximity effect correction parameter of the target mask design pattern; Matching the acquired optical proximity effect correction parameters of the target mask design pattern with the optical proximity effect correction parameters of several mask design patterns in a historical defect database; Based on the matching results, the disconnection positions of several mask design patterns having matching values greater than a preset threshold value that appear during silicon wafer exposure are obtained; The break positions of all the obtained mask design patterns that appear during silicon wafer exposure are integrated to obtain a break position coordinate set, and the obtained break position coordinate set is used as the break position coordinate set of the target mask design pattern that may cause breakage after silicon wafer exposure.

4. The mask pattern edge compensation correction method according to claim 3, wherein: After the step of matching the acquired optical proximity effect correction parameters of the target mask design pattern with the optical proximity effect correction parameters of a plurality of mask design patterns in the historical defect database, the method further includes: Based on the matching result, if the matching value is less than a preset threshold, the obtained optical proximity effect correction parameters of the target mask design pattern are input into the lithography imaging model to perform an optical proximity effect correction simulation; Based on the simulation results, several break locations where breakage may occur at the edge of the target mask design pattern after silicon wafer exposure are obtained, and the obtained several break locations are used as a break location coordinate set.

5. The mask pattern edge compensation correction method according to claim 1, wherein: The step of inputting the target mask design pattern, the disconnection probability distribution map, and the pattern edge correction rule into the lithography imaging model to generate a corrected mask design pattern specifically includes: Based on the disconnection probability distribution map, the target mask design pattern is divided into a high disconnection risk area, a low disconnection risk area, and a low disconnection risk area; Generating a staged correction pattern based on the pattern edge correction rules in descending order of risk level; wherein, upon completion of each stage correction, simulating the light intensity gradient distribution of the current correction pattern through a lithography imaging model; if the error between the current correction pattern and the adjacent area exceeds a preset threshold, stopping the correction of the next stage and retroactively adjusting the correction rules of the current stage until the error between the current correction pattern and the adjacent area is within the preset threshold; When all stage corrections are completed, the corrected mask design pattern is generated and output.

6. The mask pattern edge compensation correction method according to claim 5, characterized in that: The step of generating a phased correction graphic based on the graphic edge correction rule in descending order of risk level further includes the following steps: a) identifying, based on the disconnection probability distribution map, a high disconnection risk region and an adjacent region of the high disconnection risk region in the disconnection probability distribution map of the target mask design pattern; b) performing offset correction on the edge of the high disconnection risk area according to the graphic edge correction rule; c) simulating the light intensity distribution in the adjacent areas of the corrected high short circuit risk area using a photolithography imaging model; d) If the line width error of the adjacent areas exceeds a preset threshold, the offset in the correction rule is dynamically adjusted, and steps b) to c) are repeated until the cumulative error of all adjacent areas is less than the tolerance range.

7. The mask pattern edge compensation correction method according to claim 1, wherein: After the step of inputting the target mask design pattern, the disconnection probability distribution map and the pattern edge correction rule into the lithography imaging model to generate a corrected mask design pattern, the following step is also included: Reverse engineering the modified mask design pattern based on a lithography imaging model, minimizing the disconnection probability and line width error after silicon wafer exposure through an optimization algorithm, and generating an optimal pattern of the target mask; The optimal graph is used as an optimization training set to optimize the circuit breaker analysis model.

8. A mask pattern edge compensation and correction system, used to implement the steps of a mask pattern edge compensation and correction method according to any one of claims 1 to 7, characterized in that: include: A data acquisition module is used to construct a training data set, wherein the training data set includes multiple sets of historical mask design patterns and corresponding disconnection position coordinate sets, lithography machine model parameters matching each set of the historical masks, and physical constraint parameters of the optical model; A model training module, configured to train a deep learning model based on the training data set to obtain a trained circuit breaker analysis model; A disconnect pre-analysis module is used to obtain a target mask design pattern and, based on a historical defect database and / or optical proximity effect correction simulation of a lithography imaging model, determine a set of disconnect location coordinates where disconnects may occur at the pattern edge of the target mask design pattern after silicon wafer exposure. The correction parameter analysis module is used to input the target mask design pattern and its corresponding disconnection position coordinate set, the corresponding lithography machine model parameters, and the corresponding optical model physical constraint parameters into the trained disconnection analysis model, and output the disconnection probability distribution map of the target mask design pattern after silicon wafer exposure and the corresponding pattern edge correction rules; The compensation correction module is used to input the target mask design pattern, the disconnection probability distribution map and the pattern edge correction rule into the photolithography imaging model to generate a corrected mask design pattern.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the mask pattern edge compensation and correction method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the mask pattern edge compensation and correction method according to any one of claims 1 to 7 are implemented.

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