Real-time circuit board defect detection method and system based on improved YOLOv5 model

Abstract

The invention discloses a real-time circuit board defect detection method and system based on an improved YOLOv5 model. The method comprises the following steps: acquiring a data set; training the improved YOLOv5 model by using the data set; the improved YOLOv5 model is based on the YOLOv5 model, and a lightweight SE-ENv2 backbone network is used for replacing an original backbone network, so that the calculation complexity is reduced, and feature information of more small-size defects is reserved; replacing an original neck network with a GC-Neck neck network to improve the context modeling capability of the model; replacing an original head network with a TECODE detection head to learn and fuse multi-scale defect features; pruning is carried out on the trained YOLOv5 model; and inputting a circuit board image obtained in real time into the pruned YOLOv5 model to obtain a defect detection result. According to the invention, defects of the circuit board can be accurately detected in real time.

Description

Technical Field

[0001] The present invention relates to the fields of deep learning and computer vision technology, and industrial circuit board detection technology, and in particular to a real-time circuit board defect detection method, system, terminal device, and computer-readable storage medium based on an improved YOLOv5 model. Background Art

[0002] With the rapid development of integrated circuit and semiconductor technologies, circuit boards have become essential components and carriers for electronic devices and equipment. The integrity of these boards plays a crucial role in the overall quality and stability of these electronic devices. Defective circuit boards not only negatively impact the performance of electronic devices and the user experience, but also pose safety risks such as short circuits and fires during use.

[0003] Traditional methods for detecting PCB defects rely primarily on manual inspection. However, due to the small size of PCB defects and their high similarity to the background, manual inspection is inefficient and can easily cause visual fatigue for workers. Automated optical inspection (AOI) has since emerged. While this method offers high detection accuracy, the high equipment costs further increase factory production costs. Image processing-based methods, such as image pattern recognition and wavelet transform, offer lower costs and higher detection accuracy, and have gradually become the preferred choice for many factories. However, these methods lack robustness and are susceptible to extraneous noise. Machine learning-based defect detection methods, such as support vector machines and random forests, require manual image feature extraction. Detection effectiveness is heavily dependent on classifier performance, and detection speed needs to be improved. Therefore, achieving real-time and accurate PCB defect detection has become a pressing technical challenge.

[0004] In recent years, deep learning-based defect detection methods have been continuously proposed. These methods can automatically learn low-level and high-level image feature information and achieve good detection results. The YOLOv5 model is one of the most popular detection models. It mainly consists of an input terminal, a backbone feature extraction network, a neck feature fusion network, and an output terminal. The YOLOv5 model has been applied in various industrial scenarios, demonstrating its stability. However, the YOLOv5 model has a large number of parameters and computational complexity, and its detection performance for small objects needs further improvement. Summary of the Invention

[0005] In order to solve the technical problems in the above-mentioned prior art, the present invention provides a real-time circuit board defect detection method, system, terminal device and computer-readable storage medium based on the improved YOLOv5 model. By improving the YOLOv5 model, the improved YOLOv5 model has the advantages of lightweight, high detection accuracy, high detection efficiency, etc., which improves the detection performance of small targets; at the same time, the pruning algorithm in the model compression method is combined to reduce the complexity of the model and improve the detection speed; thereby, circuit board defects can be detected in real time and accurately.

[0006] The first object of the present invention is to provide a real-time circuit board defect detection method based on an improved YOLOv5 model.

[0007] The second object of the present invention is to provide a real-time circuit board defect detection system based on an improved YOLOv5 model.

[0008] The third object of the present invention is to provide a terminal device.

[0009] A fourth object of the present invention is to provide a computer-readable storage medium.

[0010] The first object of the present invention can be achieved by adopting the following technical solutions: A real-time circuit board defect detection method based on an improved YOLOv5 model, the method comprising: Obtain a data set; the data set includes multiple images containing circuit board defects and label files annotating corresponding defect types; The dataset was used to train an improved YOLOv5 model. The improved YOLOv5 model is based on the YOLOv5 model and replaces the original backbone network with a lightweight SE-ENv2 backbone network to reduce computational complexity and retain more feature information of small-sized defects. The GC-Neck network replaces the original neck network to improve the model's context modeling capabilities. The TECODE detection head replaces the original head network to learn and fuse multi-scale defect features. Prune the trained YOLOv5 model; The real-time circuit board image is input into the pruned YOLOv5 model to obtain the defect detection results.

[0011] Furthermore, suppose the input image size is H×W×3, where H and W represent the height and width of the image respectively. The process of extracting features from the lightweight SE-ENv2 backbone network is as follows: Perform a 3×3 conventional convolution operation on the input image to obtain a feature map of size H×W×16; then pass it through the SPDConv downsampling module to obtain a feature map of size H / 2×W / 2×16; then pass it through the Fused-MBConv module for feature extraction, and the size of the feature map remains unchanged; then pass it through the Fused-MBConv-SPD downsampling module to obtain a feature map of size H / 4×W / 4×24; then pass it through the Fused-MBConv for feature extraction, and the size of the feature map remains unchanged, and the obtained feature map is used as the first feature map; then pass it through the Fused-MBConv-SPD downsampling module to obtain a feature map of size H / 8×W / 8×32; then pass it through the Fus ed-MBConv performs feature extraction, and the size of the obtained feature map remains unchanged, and the obtained feature map is used as the second feature map; then it is down-sampled by the MBConv-SE module to obtain a feature map of size H / 16×W / 16×64; then it is down-sampled by the MBConv-ELA module to obtain a feature map of size H / 32×W / 32×80, and the obtained feature map is used as the third feature map; then it is down-sampled by the MBConv-SE module to obtain a feature map of size H / 32×W / 32×80, and the feature map size is changed to 20×20×80; finally, it is extracted by the MBConv-ELA module and the SPPF module in sequence, and the size of the obtained feature map remains unchanged, and the obtained feature map is used as the final feature map; The Fused-MBConv-SPD downsampling module replaces the 3×3 conventional convolution with a stride of 2 in the Fused-MBConv module in the EfficientNetv2 model with the SPDConv downsampling module. The MBConv-SE module replaces the 3×3 regular convolution with a stride of 2 in the MBConv module in the EfficientNetv2 model with the SPDConv downsampling module, and uses the ELA attention module to replace the SE module. The MBConv-ELA module replaces the SE attention mechanism in the MBConv module in the EfficientNetv2 model with the ELA attention module.

[0012] Furthermore, the process of sampling and splicing the feature maps extracted by the lightweight SE-ENv2 backbone network by the GC-Neck network is as follows: The final feature map is passed through the GSConv module to adjust the number of channels, and then upsampled to improve the feature map resolution; the upsampled feature map is spliced with the third feature map; the spliced feature map is passed through the C3-GC module for feature fusion and extraction, and then passed through the GSConv module in sequence to adjust the number of channels and upsample to increase the feature map size, and then spliced with the second feature map, and then the spliced feature map is passed through the C3-GC module to obtain the learned feature map.

[0013] Furthermore, the C3-GC module performs the following processing on the spliced feature map: The spliced feature maps are subjected to a 1×1 regular convolution operation to adjust the number of channels; then they are subjected to a 1×1 regular convolution operation and a GC-Bottleneck module in parallel; the parallel output feature maps are then spliced and then subjected to a 1×1 regular convolution operation for feature fusion and extraction.

[0014] Furthermore, the learned feature map, the first feature map, and the third feature map are used as inputs to the TECODE detection head.

[0015] Furthermore, the LAMP pruning algorithm is used to prune the trained YOLOv5 model, including: First, calculate the LAMP score corresponding to the feature weight of each layer; Then, based on the LAMP score, the feature weights corresponding to the low LAMP score are pruned according to the set compression ratio.

[0016] Furthermore, before using the dataset to train the improved YOLOv5 model, confirm whether the label file is in TXT format; if not, convert it to TXT format.

[0017] The second object of the present invention can be achieved by adopting the following technical solutions: A real-time circuit board defect detection system based on an improved YOLOv5 model, the system comprising: An acquisition module is used to acquire a data set; the data set includes multiple images containing circuit board defects and label files annotating corresponding defect types; A training module is used to train an improved YOLOv5 model using a dataset. The improved YOLOv5 model is based on the YOLOv5 model and replaces the original backbone network with a lightweight SE-ENv2 backbone network to reduce computational complexity and retain more feature information of small-sized defects. The original neck network is replaced with a GC-Neck network to improve the model's context modeling capabilities. The original head network is replaced with a TECODE detection head to learn and fuse multi-scale defect features. Pruning module, used to prune the trained YOLOv5 model; The detection module is used to input the real-time circuit board image into the pruned YOLOv5 model to obtain defect detection results.

[0018] The third object of the present invention can be achieved by adopting the following technical solutions: A terminal device includes a processor and a memory for storing a program executable by the processor. When the processor executes the program stored in the memory, the above-mentioned real-time circuit board defect detection method based on the improved YOLOv5 model is implemented.

[0019] The fourth object of the present invention can be achieved by adopting the following technical solutions: A computer-readable storage medium stores a program, which, when executed by a processor, implements the above-mentioned real-time circuit board defect detection method based on the improved YOLOv5 model.

[0020] The present invention has the following beneficial effects compared to the prior art: (1) This paper improves the YOLOv5 model by designing the SE-ENv2 backbone network to retain more small defect feature information during the downsampling process; by designing the C3-GC neck network, the model's context modeling capability is improved; by introducing the TECODE detection head, multi-scale defect features are learned and integrated; the improved model has higher detection accuracy for small-scale circuit board defects.

[0021] (2) The present invention is based on the improved YOLOv5 model and further combines the LAMP pruning algorithm to prune the weights that have little impact on the model detection effect according to the set compression ratio. The pruned model has lower computational complexity and faster detection speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0023] Figure 1 This is a schematic diagram of the real-time circuit board defect detection process based on the improved YOLOv5 model in Example 1 of the present invention.

[0024] Figure 2 Graphs of samples of each category of the dataset used in Example 1 of the present invention.

[0025] Figure 3This is a structural diagram of the improved YOLOv5 model according to Example 1 of the present invention.

[0026] Figure 4 This is a structural diagram of the SPDConv and ELA modules of Example 1 of the present invention.

[0027] Figure 5 This is a structural diagram of the Fused-MBConv-SPD module of Example 1 of the present invention.

[0028] Figure 6 This is a structural diagram of the MBConv-SE module according to Example 1 of the present invention.

[0029] Figure 7 This is a structural diagram of the MBConv-ELA module of Example 1 of the present invention.

[0030] Figure 8 Schematic diagram of the GSConv, CAA and C3-GC modules of Example 1 of the present invention.

[0031] Figure 9 This is a structural diagram of the TSCODE decoupling detection head of Example 1 of the present invention.

[0032] Figure 10 This is a structural block diagram of a real-time circuit board defect detection system based on an improved YOLOv5 model according to Example 2 of the present invention.

[0033] Figure 11 This is a structural block diagram of the terminal device of embodiment 3 of the present invention. DETAILED DESCRIPTION

[0034] To make the purpose, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention. It should be understood that the specific embodiments described are only used to explain this application and are not used to limit this application.

[0035] Example 1: like Figure 1 As shown, this embodiment provides a real-time circuit board defect detection method based on an improved YOLOv5 model, including the following steps: S101. Obtain a data set.

[0036] The dataset used in this example is the HRIPCB dataset released by Peking University. Some image samples can be found in Figure 2,The dataset contains 1386 defective images with 6 defect types (leak hole, rat bite, open circuit, short circuit, stray, and stray copper).

[0037] S102: Convert the label files in the dataset.

[0038] The XML format label file is converted into a TXT format label file corresponding to the YOLOv5 model, and finally divided into training set, validation set and test set in a ratio of 8:1:1.

[0039] S103. Improve the YOLOv5 model.

[0040] The improved YOLOv5 model can be referenced Figure 3 , the specific improvements are as follows: (1) Based on the EfficientNetv2 network, a lightweight backbone network SE-ENv2 is designed to replace the original backbone network.

[0041] The schematic diagram of the backbone network SE-ENv2 can be found at Figure 3 The input image of size 640×640×3 (height×width×channel) undergoes 3×3 conventional convolution to become a feature map of size 640×640×16; then it passes through the SPDConv downsampling module, and the feature map size becomes 320×320×16; then it passes through the Fused-MBConv for feature extraction, and the feature map size remains unchanged; then it passes through the Fused-MBConv-SPD downsampling module, and the feature map size becomes 160×160×24; then it passes through the Fused-MBConv for feature extraction, and the feature map size remains unchanged; then it passes through the Fused-MB Conv-SPD downsampling module, the feature map size becomes 80×80×32; then Fused-MBConv is used for feature extraction, and the feature map size remains unchanged; then downsampling is completed by the MBConv-SE module, and the feature map size becomes 40×40×64; then feature extraction is performed by MBConv-ELA, and the feature map size remains unchanged; then downsampling is completed again by the MBConv-SE module, and the feature map size becomes 20×20×80; finally, feature extraction is performed by the MBConv-ELA module and the SPPF module in sequence, and the feature map size remains unchanged.

[0042] The schematic diagram of the SPDConv downsampling module can be found in Figure 4First, by extracting features at intervals, the feature information is converted from the spatial dimension to the channel dimension. The feature map is halved and the number of channels is quadrupled. Then, the number of output channels is adjusted through convolution to reduce computational complexity. In this embodiment, the number of output channels is adjusted to be consistent with the number of input channels. The SPDConv downsampling module can retain more feature information of small-sized defects while completing feature map downsampling.

[0043] The schematic diagram of the Fused-MBConv-SPD downsampling module can be found in Figure 5 , the 3×3 regular convolution with a stride of 2 in the original EfficientNetv2 module Fused-MBConv is replaced with the SPDConv downsampling module to retain more small target feature information.

[0044] The schematic diagram of the MBConv-SE module can be found in Figure 6 The 3×3 regular convolution with a stride of 2 in the original EfficientNetv2 module MBConv is replaced with the SPDConv downsampling module, and the ELA attention module is used to replace the original SE module.

[0045] The schematic diagram of the ELA module can be found in Figure 4 It mainly consists of parallel skip connections and two feature extraction branches. The first feature extraction branch consists of the serial X-direction average pooling, 1×1 convolution, group normalization and Sigmoid activation function. The second feature extraction branch consists of the serial Y-direction average pooling, 1×1 convolution, group normalization and Sigmoid activation function. The feature information of the three branches is multiplied to obtain the final output. The ELA module can simultaneously focus on the feature information at the channel level and the spatial level.

[0046] The MBConv-ELA module works as follows Figure 7 As shown, only the SE attention mechanism in the MBConv module is replaced by the ELA module.

[0047] The SE-ENv2 backbone network designed in this embodiment has the advantages of being lighter and more efficient in extracting small target features compared to the original backbone network.

[0048] (2) Design the GC-Neck network.

[0049] like Figure 3As shown in the figure, GC-Neck mainly consists of a C3-GC module, GSConv, an upsampling module, and a splicing module. In the GC-Neck neck network, the input is the 20×20×80 feature map extracted by the backbone network. GSConv adjusts the number of channels, and then the upsampling module increases the resolution of the feature map. It is then spliced with the 40×40×64 feature map from the backbone network. The spliced feature map is then fused and extracted by the C3-GC module. GSConv adjusts the number of channels again, and the upsampling module increases the size of the feature map. It is then spliced with the 80×80×32 feature map from the backbone network. The C3-GC module then performs feature learning, and the learned features are finally fed into the detection head.

[0050] The schematic diagram of the C3-GC module can be found in Figure 8 , the input features are first adjusted by 1×1 convolution for the number of channels, then passed through the 1×1 convolution branch and the GC-Bottleneck branch in parallel, and the learned features are spliced, and then feature fusion is performed through 1×1 convolution.

[0051] The schematic diagram of the GC-Bottleneck module can be found at Figure 8 , the input feature map passes through the GSConv and CAA attention mechanism modules in parallel, then the learned feature information is multiplied, and finally feature learning and fusion are performed through GSConv.

[0052] The principle diagram of GSConv can be found in Figure 8. The input feature map first undergoes conventional convolution, followed by a depthwise convolution operation on the resulting features. The resulting feature maps are then concatenated, and finally, feature information is exchanged through a channel shuffling module. GSConv has a smaller computational footprint than conventional convolution, reducing redundant model operations and lowering model complexity.

[0053] The principle diagram of CAA attention mechanism can be referred to Figure 7 The input feature map first passes through a pooling module and a 1×1 convolution, then undergoes two large-kernel strip convolutions to enhance the model's contextual awareness, and finally undergoes feature fusion through a 1×1 convolution. The CAA attention mechanism improves the model's contextual modeling capabilities while incurring minimal computational overhead.

[0054] (3) Introduce TSCODE decoupling detection head.

[0055] The schematic diagram of TSCODE decoupling detection head can be referred to Figure 9It is mainly divided into the classification branch (SCE branch) and the regression branch (DPE branch). The overall input consists of the feature map of size 80×80×64 (medium size) finally extracted by GC-Neck, and the feature maps of size 160×160×24 (large size) and 40×40×64 (small size) in the backbone network.

[0056] The input of the classification branch consists of large-scale and small-scale feature maps. The large-scale feature map is first down-sampled by a 3×3 regular convolution with a stride of 2; then it is spliced with the small-scale feature map, and then the number of channels is adjusted and features are fused through a 1×1 convolution; finally, a 3×3 convolution is used for feature learning and a 1×1 convolution is used to adjust the number of channels to predict the defect category.

[0057] The input to the regression branch consists of large-, medium-, and small-scale feature maps. The medium-sized feature map is first added to the large-sized feature map through an upsampling module. The resulting feature map is downsampled through a 3×3 regular convolution with a stride of 2 and added to the medium-sized feature map. The small-sized feature map is also passed through an upsampling module and then added to the medium-sized feature map. Finally, two 3×3 regular convolutions with a stride of 1 are used for feature extraction. The number of channels is then adjusted through two 1×1 convolutions to predict the confidence, location, and size of the defect, respectively.

[0058] In this embodiment, the TSCODE decoupling detection head can learn features at different levels and improve the model's detection accuracy for circuit board defects.

[0059] S104. Train the improved YOLOv5 model.

[0060] In this embodiment, the number of training rounds is set to 300, the batch size is 32, the image input size is 640×640 pixels, the optimizer used is stochastic gradient descent, and the learning rate is set to 0.01.

[0061] S105. Prune the trained YOLOv5 model.

[0062] Combined with the model pruning algorithm, the trained model is compressed to further improve the real-time performance of the model.

[0063] This example uses the LAMP pruning algorithm. The LAMP pruning algorithm first calculates the LAMP score corresponding to each layer of feature weights. Then, based on the LAMP score, it prunes feature weights with low LAMP scores according to a set compression ratio (1.25 is used in this example). The LAMP score of the u-th index of the feature weight tensor W is defined as follows:

[0064] S106. Perform defect detection using the pruned model.

[0065] Use the pruned model to perform defect detection on the input circuit board image and obtain the detection results.

[0066] Those skilled in the art will appreciate that all or part of the steps in the method for implementing the above embodiments may be completed by instructing related hardware through a program, and the corresponding program may be stored in a computer-readable storage medium.

[0067] It should be noted that although the method operations of the above embodiments are described in a particular order in the accompanying drawings, this does not require or imply that the operations must be performed in this particular order, or that all of the illustrated operations must be performed to achieve the desired results. Rather, the depicted steps may be performed in a different order. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into a single step, and / or a single step may be broken down into multiple steps.

[0068] Example 2: like Figure 10 As shown, this embodiment provides a real-time circuit board defect detection system based on an improved YOLOv5 model, which includes an acquisition module 1001, a training module 1002, a pruning module 1003, and a detection module 1004, wherein: The acquisition module 1001 is used to acquire a data set; the data set includes multiple images containing circuit board defects and label files annotating corresponding defect types; Training module 1002 is used to train an improved YOLOv5 model using a data set. The improved YOLOv5 model is based on the YOLOv5 model and replaces the original backbone network with a lightweight SE-ENv2 backbone network to reduce computational complexity and retain more feature information of small-sized defects. The original neck network is replaced with a GC-Neck network to improve the model's context modeling capabilities. The original head network is replaced with a TECODE detection head to learn and fuse multi-scale defect features. Pruning module 1003, used to prune the trained YOLOv5 model; The detection module 1004 is used to input the circuit board image acquired in real time into the pruned YOLOv5 model to obtain defect detection results.

[0069] The specific implementation of each module in this embodiment can be found in the above-mentioned embodiment 1, and will not be described one by one here; it should be noted that the system provided in this embodiment is only illustrated by the division of the above-mentioned functional modules. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure can be divided into different functional modules to complete all or part of the functions described above.

[0070] Example 3: This embodiment provides a terminal device, which can be a computer, such as Figure 11 As shown, it includes a processor 1102, a memory, an input device 1103, a display 1104, and a network interface 1105 connected via a system bus 1101. The processor is used to provide computing and control capabilities. The memory includes a non-volatile storage medium 1106 and an internal memory 1107. The non-volatile storage medium 1106 stores an operating system, a computer program, and a database. The internal memory 1107 provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. When the processor 1102 executes the computer program stored in the memory, the real-time circuit board defect detection method based on the improved YOLOv5 model of the above-mentioned embodiment 1 is implemented as follows: Obtain a data set; the data set includes multiple images containing circuit board defects and label files annotating corresponding defect types; The dataset was used to train an improved YOLOv5 model. The improved YOLOv5 model is based on the YOLOv5 model and replaces the original backbone network with a lightweight SE-ENv2 backbone network to reduce computational complexity and retain more feature information of small-sized defects. The GC-Neck network replaces the original neck network to improve the model's context modeling capabilities. The TECODE detection head replaces the original head network to learn and fuse multi-scale defect features. Prune the trained YOLOv5 model; The real-time circuit board image is input into the pruned YOLOv5 model to obtain the defect detection results.

[0071] Example 4: This embodiment provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the real-time circuit board defect detection method based on the improved YOLOv5 model of the above-mentioned embodiment 1 is implemented as follows: Obtain a data set; the data set includes multiple images containing circuit board defects and label files annotating corresponding defect types; The dataset was used to train an improved YOLOv5 model. The improved YOLOv5 model is based on the YOLOv5 model and replaces the original backbone network with a lightweight SE-ENv2 backbone network to reduce computational complexity and retain more feature information of small-sized defects. The GC-Neck network replaces the original neck network to improve the model's context modeling capabilities. The TECODE detection head replaces the original head network to learn and fuse multi-scale defect features. Prune the trained YOLOv5 model; The real-time circuit board image is input into the pruned YOLOv5 model to obtain the defect detection results.

[0072] It should be noted that the computer-readable storage medium of this embodiment may be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0073] The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes based on the technical solution and inventive concept of the present invention within the scope disclosed by the present invention, which falls within the scope of protection of the present invention.

Claims

1. A real-time circuit board defect detection method based on an improved YOLOv5 model, characterized in that: The method comprises: Obtain a data set; the data set includes multiple images containing circuit board defects and label files annotating corresponding defect types; The dataset was used to train an improved YOLOv5 model. The improved YOLOv5 model is based on the YOLOv5 model and replaces the original backbone network with a lightweight SE-ENv2 backbone network to reduce computational complexity and retain more feature information of small-sized defects. The GC-Neck network replaces the original neck network to improve the model's context modeling capabilities. The TECODE detection head replaces the original head network to learn and fuse multi-scale defect features. Prune the trained YOLOv5 model; The real-time circuit board image is input into the pruned YOLOv5 model to obtain the defect detection results.

2. The real-time circuit board defect detection method according to claim 1, characterized in that: Assume the input image size is H×W×3, where H and W represent the height and width of the image respectively. The process of extracting features from the lightweight SE-ENv2 backbone network is as follows: Perform a 3×3 conventional convolution operation on the input image to obtain a feature map of size H×W×16; then pass it through the SPDConv downsampling module to obtain a feature map of size H / 2×W / 2×16; then pass it through the Fused-MBConv module for feature extraction, and the size of the feature map remains unchanged; then pass it through the Fused-MBConv-SPD downsampling module to obtain a feature map of size H / 4×W / 4×24; then pass it through the Fused-MBConv for feature extraction, and the size of the feature map remains unchanged, and the obtained feature map is used as the first feature map; then pass it through the Fused-MBConv-SPD downsampling module to obtain a feature map of size H / 8×W / 8×32; then pass it through the Fus ed-MBConv performs feature extraction, and the size of the obtained feature map remains unchanged, and the obtained feature map is used as the second feature map; then it is down-sampled by the MBConv-SE module to obtain a feature map of size H / 16×W / 16×64; then it is down-sampled by the MBConv-ELA module to obtain a feature map of size H / 32×W / 32×80, and the obtained feature map is used as the third feature map; then it is down-sampled by the MBConv-SE module to obtain a feature map of size H / 32×W / 32×80, and the feature map size is changed to 20×20×80; finally, it is extracted by the MBConv-ELA module and the SPPF module in sequence, and the size of the obtained feature map remains unchanged, and the obtained feature map is used as the final feature map; The Fused-MBConv-SPD downsampling module replaces the 3×3 conventional convolution with a stride of 2 in the Fused-MBConv module in the EfficientNetv2 model with the SPDConv downsampling module. The MBConv-SE module replaces the 3×3 regular convolution with a stride of 2 in the MBConv module in the EfficientNetv2 model with the SPDConv downsampling module, and uses the ELA attention module to replace the SE module. The MBConv-ELA module replaces the SE attention mechanism in the MBConv module in the EfficientNetv2 model with the ELA attention module.

3. The real-time circuit board defect detection method according to claim 2, characterized in that: The process of sampling and splicing the feature maps extracted by the lightweight SE-ENv2 backbone network by the GC-Neck network is as follows: The final feature map is passed through the GSConv module to adjust the number of channels, and then upsampled to improve the feature map resolution; the upsampled feature map is spliced with the third feature map; The spliced feature map is passed through the C3-GC module for feature fusion and extraction, and then passed through the GSConv module in sequence to adjust the number of channels and upsample to increase the feature map size, and then spliced with the second feature map. The spliced feature map is then passed through the C3-GC module to obtain the learned feature map.

4. The real-time circuit board defect detection method according to claim 3, characterized in that: The C3-GC module processes the concatenated feature maps as follows: The spliced feature maps are subjected to a 1×1 regular convolution operation to adjust the number of channels; then they are subjected to a 1×1 regular convolution operation and a GC-Bottleneck module in parallel; the parallel output feature maps are then spliced and then subjected to a 1×1 regular convolution operation for feature fusion and extraction.

5. The real-time circuit board defect detection method according to claim 3, characterized in that: The learned feature map, the first feature map, and the third feature map are used as the input of the TECODE detection head.

6. The real-time circuit board defect detection method according to any one of claims 1 to 5, characterized in that: The trained YOLOv5 model is pruned using the LAMP pruning algorithm, including: First, calculate the LAMP score corresponding to the feature weight of each layer; Then, based on the LAMP score, the feature weights corresponding to the low LAMP score are pruned according to the set compression ratio.

7. The real-time circuit board defect detection method according to any one of claims 1 to 5, characterized in that: Before using the dataset to train the improved YOLOv5 model, confirm whether the label file is in TXT format; if not, convert it to TXT format.

8. A real-time circuit board defect detection system based on an improved YOLOv5 model, characterized in that: The system comprises: An acquisition module is used to acquire a data set; the data set includes multiple images containing circuit board defects and label files annotating corresponding defect types; A training module is used to train an improved YOLOv5 model using a dataset. The improved YOLOv5 model is based on the YOLOv5 model and replaces the original backbone network with a lightweight SE-ENv2 backbone network to reduce computational complexity and retain more feature information of small-sized defects. The original neck network is replaced with a GC-Neck network to improve the model's context modeling capabilities. The original head network is replaced with a TECODE detection head to learn and fuse multi-scale defect features. Pruning module, used to prune the trained YOLOv5 model; The detection module is used to input the real-time circuit board image into the pruned YOLOv5 model to obtain defect detection results.

9. A terminal device comprising a processor and a memory for storing a program executable by the processor, characterized in that: When the processor executes the program stored in the memory, the real-time circuit board defect detection method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the real-time circuit board defect detection method according to any one of claims 1 to 7 is implemented.

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