Chip defect lightweight detection method, system and equipment based on dynamic distillation and depth separable convolution, and medium

Abstract

The invention relates to a chip defect lightweight detection method, system and device based on dynamic distillation and depth separable convolution, and a medium, and the method comprises the steps: constructing a multi-scale temperature distillation frame, taking a feature pyramid output by a teacher model as a reference, and adjusting the knowledge migration granularity between the teacher model and a student model; a deformable feature alignment module is introduced, geometric deformation feature offset between the teacher model and the student model is corrected through learnable offset parameters, and a target feature channel is screened; reconstructing a backbone network of the student model by embedding depth separable convolution, and performing iterative pruning compression by using channel importance evaluation results of each convolution layer to generate a lightweight inference model; and inputting the preprocessed chip image into the lightweight reasoning model, and outputting a detection result. Through deep fusion of knowledge migration dynamic adjustment, feature deformation adaptive correction and hardware sensing compression, a defect detection solution which is high in precision, low in delay and easy to deploy is provided.

Description

Technical Field

[0001] The present invention relates to the field of chip detection technology, and in particular to a lightweight chip defect detection method, system, equipment and medium based on dynamic distillation and deep separable convolution. Background Art

[0002] Due to the rapid iteration requirements of semiconductor manufacturing processes, chip defect detection technology faces the following technical bottlenecks: Traditional manual visual inspection and machine vision algorithms have insufficient efficiency and consistency in identifying micron-level defects. While deep learning-based detection technology has advantages in accuracy, its high computing power requirements are in sharp conflict with edge device compatibility. Specifically, the existing technology system has the following three core flaws:

[0003] First, in the field of knowledge distillation technology, the fixed temperature parameter distillation mechanism used by traditional methods is difficult to adapt to the multi-scale characteristics of chip defects. Since chip surface defects have cross-scale distribution characteristics ranging from macro scratches (>1mm) to micro oxidation points (<0.05mm), fixed temperature parameters will lead to the dual problems of over-smoothing tiny defect features in the high-temperature stage and sensitivity to background noise in the low-temperature stage during the feature distillation process. In addition, the feature alignment method based on the L2 norm does not take into account the non-rigid deformation caused by the packaging process. Its rigid feature matching mechanism will significantly increase the feature matching error in the presence of spatial geometric offset, which directly leads to an increase in the false detection rate of deformation defects such as solder joint offset.

[0004] Secondly, existing solutions for lightweight network design suffer from insufficient hardware adaptability. While depthwise separable convolution technology can effectively reduce the number of model parameters, its fixed-structure backbone network still suffers from channel redundancy in chip defect scenarios due to the lack of a dynamic pruning mechanism. This issue generates unnecessary computational load when the model is deployed on edge devices, making inference latency difficult to meet the real-time requirements of production lines, thereby limiting the practical application value of the detection system.

[0005] Finally, the existing technology system suffers from the systematic flaw of a single optimization strategy. Because the two key technologies, knowledge distillation and convolutional structure optimization, mostly use isolated optimization models, they fail to establish a joint optimization framework tailored to chip defect characteristics, making it difficult to achieve an effective balance between model accuracy and operational efficiency. This flaw is particularly pronounced in low-contrast detection scenarios for microcrack defects (<0.1mm). Traditional solutions are unable to maintain high-dimensional feature resolution while ensuring model lightweighting, severely restricting the overall performance improvement of the detection system. Summary of the Invention

[0006] (1) Technical issues to be resolved

[0007] In view of the above-mentioned shortcomings and deficiencies of the prior art, the present invention provides a lightweight chip defect detection method, system, equipment and medium based on dynamic distillation and deep separable convolution, which solves the technical problem that the existing chip defect detection technology cannot coordinately optimize the detection accuracy and hardware efficiency due to the fixed temperature parameters of knowledge distillation, the lack of deformation adaptability of feature alignment and the redundancy of model channels.

[0008] (2) Technical solution

[0009] In order to achieve the above objectives, the main technical solutions adopted by the present invention include:

[0010] In a first aspect, an embodiment of the present invention provides a lightweight chip defect detection method using dynamic distillation and depthwise separable convolution, comprising:

[0011] A multi-scale temperature distillation framework is constructed, consisting of a teacher model and a student model based on YOLOv11. Using the feature pyramid output by the teacher model as a benchmark, the framework adjusts the granularity of knowledge transfer between the teacher and student models by configuring exponentially decaying temperature parameters for features at different scales, thereby achieving progressive feature transfer.

[0012] During the feature migration process, a deformable feature alignment module is introduced to dynamically correct the geometric deformation feature offset between the teacher model and the student model through a learnable offset parameter. Target feature channels carrying chip defect characterization information are then selected from the features output by the deformable feature alignment module.

[0013] The backbone network of the student model is reconstructed by embedding depthwise separable convolutions, replacing convolution operations with channel-by-channel convolutions and point-by-point convolutions. The gradient-magnitude-based channel importance evaluation results of each convolutional layer are used for iterative pruning and compression to generate a lightweight inference model.

[0014] The preprocessed chip image is input into the lightweight inference model, and the target feature channel is used for cross-scale fusion, feature decoding and post-processing, and the detection results including defect type, location coordinates and confidence score are output.

[0015] Optionally, a multi-scale temperature distillation framework consisting of a YOLOv11-based teacher model and a student model is constructed. Taking the feature pyramid output by the teacher model as a benchmark, the framework adjusts the granularity of knowledge transfer between the teacher model and the student model by configuring exponentially decaying differential temperature parameters for features at different scales to achieve progressive feature transfer. This includes:

[0016] Build a multi-scale temperature distillation framework consisting of a teacher model and a student model based on YOLOv11;

[0017] Extract the feature tensors of the P3-P5 levels in the feature pyramid from the teacher model and configure the following independent temperature parameters for each scale feature:

[0018] For the characteristic tensor of the P3 layer, the initial temperature value is set to the first preset high temperature threshold, and the temperature parameter is dynamically adjusted according to the exponential decay law;

[0019] For the characteristic tensor of the P5 layer, the initial temperature value is set to the second preset high temperature threshold and lower than the first preset high temperature threshold, and the temperature parameter is adjusted according to the exponential law with a decay rate lower than that of the P3 layer;

[0020] For the characteristic tensor of the P4 layer, the initial temperature value is set to the third preset high temperature threshold and between the first preset high temperature threshold and the second preset high temperature threshold, and the temperature parameter is adjusted according to the exponential law with a decay rate between the P3 and P5 layers;

[0021] Construct a multi-scale dynamic temperature loss function and fuse the cross-scale knowledge transfer losses of P3, P4, and P5 levels through weighted summation;

[0022] The exponential decay process of the temperature parameters at the P3-P5 levels is synchronously controlled with the model parameter update to achieve a gradual transition from coarse-grained feature migration to fine-grained feature migration.

[0023] Optionally, a deformable feature alignment module is introduced during the feature migration process to dynamically correct the geometric deformation feature offset between the teacher model and the student model using a learnable offset parameter. Target feature channels carrying chip defect characterization information are selected from the features output by the deformable feature alignment module. These channels include:

[0024] Embed a deformable feature alignment module in the feature transfer path between the teacher model and the student model;

[0025] The original feature map output by the teacher model is used as the deformation correction benchmark. The learnable offset parameters in the deformable feature alignment module are used to determine the spatial geometric compensation amount of the original feature map output by the student model relative to the feature map output by the teacher model, thereby generating a deformation-compensated feature map.

[0026] The deformation compensation feature map is fused with the original feature map output by the teacher model channel by channel to obtain a cross-model semantic enhancement feature map;

[0027] Perform global average pooling of the channel dimension on the cross-model semantic enhancement feature map to generate a channel description vector, and calculate the attention weight value of each channel through the fully connected layer and Sigmoid activation function;

[0028] The channel screening threshold is adjusted according to the current defect size distribution data obtained, and the feature channels with attention weight values higher than the dynamic threshold are selected as the target channels carrying chip defect characterization information.

[0029] Optionally, when the proportion of microcrack defects in a statistical period exceeds a preset ratio threshold, the channel screening threshold is lowered to a first preset interval, the hidden layer capacity of the fully connected layer is expanded, and the offset parameter learning rate of the deformable feature alignment module is simultaneously increased to a first learning rate range;

[0030] When the proportion of solder joint deformation defects in a statistical period exceeds a preset ratio threshold, the channel screening threshold is raised to a second preset interval, the hidden layer capacity of the fully connected layer is compressed, and the offset parameter learning rate of the deformable feature alignment module is simultaneously reduced to a second learning rate range;

[0031] When the proportion of microcrack defects and weld deformation defects does not exceed the preset ratio threshold, a weighted fusion strategy is used to calculate the channel screening threshold based on the weights of the proportions of microcracks and deformation defects;

[0032] The first preset interval is the lower limit interval of the channel screening threshold, the upper limit value of the first preset interval does not exceed the lower limit value of the second preset interval, and the minimum value of the first learning rate range is higher than the maximum value of the second learning rate range.

[0033] Optionally, the backbone network of the student model is reconstructed by embedding depthwise separable convolution, replacing the convolution operation with channel-by-channel convolution and point-by-point convolution, and iteratively pruning and compressing the channel importance evaluation results of each convolution layer based on the gradient amplitude to generate a lightweight inference model including:

[0034] Replace the convolutional layers of the student model with depth-wise separable convolutional modules to reconstruct the backbone network of the student model;

[0035] The importance of each convolutional layer channel is dynamically evaluated based on the back-propagation gradient amplitude. Redundant channels with importance scores lower than the preset pruning threshold are iteratively pruned according to the preset pruning threshold. A sparse feature extraction network is constructed based on the retained channels.

[0036] After each pruning operation, the convolution kernel parameters of the retained channels are recalibrated, and the model detection accuracy is restored through constrained fine-tuning;

[0037] Perform hardware adaptation optimization on the pruned student model to generate a lightweight inference model that can be deployed on edge computing devices;

[0038] Among them, the depthwise separable convolution module includes a channel-by-channel convolution layer and a point-by-point convolution layer connected in series. The channel-by-channel convolution layer independently performs spatial feature extraction on each channel of the input feature, and the point-by-point convolution layer linearly combines the cross-channel features.

[0039] Optionally, hardware adaptation optimization includes:

[0040] Perform mixed-precision quantization on models deployed on embedded GPUs, converting 32-bit floating-point parameters to 8-bit fixed-point format while retaining 16-bit floating-point accuracy for at least 5% of weight perturbation-sensitive channels.

[0041] Perform layer fusion optimization on the model deployed on the FPGA, merge adjacent channel-by-channel convolution layers and point-by-point convolution layers into a composite operator, and generate a static bitstream file with a configurable logic block resource occupancy rate of ≤65%.

[0042] Optionally, the preprocessed chip image is input into a lightweight inference model, and cross-scale fusion, feature decoding, and post-processing are performed using the target feature channel. The output includes the following detection results: defect type, location coordinates, and confidence score:

[0043] The pre-processed chip image is input into the lightweight inference model, and the target feature channel is used for cross-scale fusion to generate a multi-scale fusion feature map;

[0044] Multi-task decoding is performed on the multi-scale fusion feature map. The classification branch and regression branch respectively output the decoding results containing the probability distribution of defect categories and bounding box coordinates. The regression branch introduces a deformation resistance coefficient to correct the positioning error of solder joint offset.

[0045] Dynamic post-processing optimization is performed on the decoding results. A hierarchical non-maximum suppression strategy is used to distinguish and process redundant detection frames for microcracks and solder joint deformation defects, and a temperature scaling calibration method is used to adjust the confidence score.

[0046] The output includes structured detection result data including defect type, location coordinates and confidence score.

[0047] In a second aspect, an embodiment of the present invention provides a lightweight chip defect detection system using dynamic distillation and depthwise separable convolution, including:

[0048] The model transfer module is used to build a multi-scale temperature distillation framework consisting of a teacher model and a student model based on YOLOv11. Based on the feature pyramid output by the teacher model, the module adjusts the granularity of knowledge transfer between the teacher and student models by configuring exponentially decaying differentiated temperature parameters for features at different scales, thereby achieving progressive feature transfer.

[0049] The offset adjustment and channel screening module is used to introduce the deformable feature alignment module during the feature migration process. It dynamically corrects the geometric deformation feature offset between the teacher model and the student model through learnable offset parameters, and selects the target feature channels that carry chip defect characterization information from the features output by the deformable feature alignment module.

[0050] The model lightweight processing module is used to reconstruct the backbone network of the student model by embedding depthwise separable convolution, replacing the convolution operation with channel-by-channel convolution and point-by-point convolution. It also uses the gradient magnitude-based channel importance evaluation results of each convolution layer to perform iterative pruning and compression to generate a lightweight inference model.

[0051] The defect detection module is used to input the preprocessed chip image into the lightweight inference model, use the target feature channel for cross-scale fusion, feature decoding and post-processing, and output the detection results including defect type, location coordinates and confidence score.

[0052] In the third aspect, an embodiment of the present invention provides a lightweight chip defect detection device using dynamic distillation and depthwise separable convolution, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the lightweight chip defect detection method using dynamic distillation and depthwise separable convolution as described above.

[0053] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium having computer-executable instructions stored thereon. When the executable instructions are executed by a processor, the lightweight chip defect detection method of dynamic distillation and depth-separable convolution as described above is implemented.

[0054] (3) Beneficial effects

[0055] The beneficial effects of the present invention are: the present invention realizes the coordinated optimization of detection accuracy and hardware efficiency in the field of chip defect detection, effectively overcoming key bottlenecks in traditional technologies such as knowledge distillation parameter solidification, insufficient feature alignment deformation adaptability and serious model redundancy.

[0056] First, by constructing a multi-scale dynamic temperature distillation framework, different temperature parameters are set for different levels of the feature pyramid and exponential decay control is implemented, so that the knowledge transfer process can adaptively adjust the granularity. In the early stage of training, the background noise interference is suppressed by softening the probability distribution through high temperature. In the later stage of training, the detailed features of microscopic defects are accurately transmitted with the help of low-temperature sharpening operations, which significantly improves the student model's ability to learn the multi-level feature expression of the teacher model.

[0057] Secondly, in order to solve the problem of feature offset caused by geometric deformation, an innovative dynamic correction mechanism of the deformable feature alignment module is introduced. The key spatial information of the teacher features is captured through learnable deformation parameters, and the expression of defect-sensitive channels is enhanced by combining the channel attention screening strategy, so that the model's detection robustness to complex defects such as solder joint offset and tensile deformation is significantly enhanced.

[0058] Furthermore, in terms of model lightweight design, through the coordinated optimization of depthwise separable convolution reconstruction and dynamic channel pruning, precise control of computing load is achieved while retaining high-dimensional semantic features. This not only eliminates the loss of detailed features caused by capacity limitations of traditional lightweight models, but also effectively adapts to the computing power constraints of edge devices, forming an efficient inference architecture that takes into account both detection accuracy and real-time performance.

[0059] Through the deep integration of dynamic adjustment of knowledge migration, adaptive correction of feature deformation and hardware perception compression, the present invention provides a high-precision, low-latency and easy-to-deploy defect detection solution for industrial quality inspection scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 A schematic flow chart of a method provided in an embodiment of the present invention;

[0061] Figure 2 A schematic diagram of a specific flow chart of step S1 of the method provided in an embodiment of the present invention;

[0062] Figure 3 A schematic diagram of a specific flow chart of step S2 of the method provided in an embodiment of the present invention;

[0063] Figure 4 A schematic diagram of a specific flow chart of step S3 of the method provided in an embodiment of the present invention;

[0064] Figure 5 A schematic diagram of a specific flow chart of step S4 of the method provided in an embodiment of the present invention;

[0065] Figure 6 This is a diagram showing the packaged chip detection results of the method provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0066] In order to better explain the present invention and facilitate understanding, the present invention is described in detail below through specific implementation methods in conjunction with the accompanying drawings.

[0067] like Figure 1As shown, an embodiment of the present invention proposes a lightweight chip defect detection method using dynamic distillation and depthwise separable convolution, including: constructing a multi-scale temperature distillation framework including a teacher model and a student model based on YOLOv11, taking the feature pyramid output by the teacher model as a benchmark, configuring differential temperature parameters with exponential decay for features of different scales, and adjusting the knowledge transfer granularity between the teacher model and the student model to achieve progressive feature migration; introducing a deformable feature alignment module in the feature migration process, dynamically correcting the geometric deformation feature offset between the teacher model and the student model through a learnable offset parameter, and screening target feature channels carrying chip defect characterization information from the features output by the deformable feature alignment module; reconstructing the backbone network of the student model by embedding depthwise separable convolution, replacing the convolution operation with channel-by-channel convolution and point-by-point convolution, and iteratively pruning and compressing using the channel importance evaluation results of each convolution layer based on gradient amplitude to generate a lightweight inference model; inputting the preprocessed chip image into the lightweight inference model, using the target feature channel for cross-scale fusion, feature decoding and post-processing, and outputting a detection result including defect type, location coordinates and confidence score.

[0068] The present invention achieves the coordinated optimization of detection accuracy and hardware efficiency in the field of chip defect detection, effectively overcoming key bottlenecks in traditional technologies such as knowledge distillation parameter solidification, insufficient adaptability of feature alignment deformation, and serious model redundancy.

[0069] First, by constructing a multi-scale dynamic temperature distillation framework, different temperature parameters are set for different levels of the feature pyramid and exponential decay control is implemented, so that the knowledge transfer process can adaptively adjust the granularity. In the early stage of training, the background noise interference is suppressed by softening the probability distribution through high temperature. In the later stage of training, the detailed features of microscopic defects are accurately transmitted with the help of low-temperature sharpening operations, which significantly improves the student model's ability to learn the multi-level feature expression of the teacher model.

[0070] Secondly, in order to solve the problem of feature offset caused by geometric deformation, an innovative dynamic correction mechanism of the deformable feature alignment module is introduced. The key spatial information of the teacher features is captured through learnable deformation parameters, and the expression of defect-sensitive channels is enhanced by combining the channel attention screening strategy, so that the model's detection robustness to complex defects such as solder joint offset and tensile deformation is significantly enhanced.

[0071] Furthermore, in terms of model lightweight design, through the coordinated optimization of depthwise separable convolution reconstruction and dynamic channel pruning, precise control of computing load is achieved while retaining high-dimensional semantic features. This not only eliminates the loss of detailed features caused by capacity limitations of traditional lightweight models, but also effectively adapts to the computing power constraints of edge devices, forming an efficient inference architecture that takes into account both detection accuracy and real-time performance.

[0072] Through the deep integration of dynamic adjustment of knowledge migration, adaptive correction of feature deformation and hardware perception compression, the present invention provides a high-precision, low-latency and easy-to-deploy defect detection solution for industrial quality inspection scenarios.

[0073] To better understand the above technical solutions, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a clearer and more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0074] Specifically, an embodiment of the present invention provides a lightweight chip defect detection method using dynamic distillation and depthwise separable convolution, which includes:

[0075] S1. Construct a multi-scale temperature distillation framework that includes a teacher model and a student model based on YOLOv11. Taking the feature pyramid output by the teacher model as the benchmark, the knowledge transfer granularity between the teacher model and the student model is adjusted by configuring differential temperature parameters with exponential decay for features of different scales to achieve progressive feature transfer.

[0076] Further, if Figure 2 As shown, step S1 includes:

[0077] S11. Build a multi-scale temperature distillation framework that includes a teacher model and a student model based on YOLOv11.

[0078] S12. Extract the feature tensors of the P3-P5 levels in the feature pyramid extracted by the teacher model and configure the following independent temperature parameters for each scale feature:

[0079] For the feature tensor of the P3 layer, the initial temperature value is set as the first preset high temperature threshold, and the temperature parameter is dynamically adjusted according to the exponential decay law, so that the background noise is suppressed by softening the probability distribution at high temperature in the early stage of training, and the microcrack detail features are focused by sharpening the probability distribution at low temperature in the later stage of training.

[0080] For the characteristic tensor of the P5 layer, the initial temperature value is set to the second preset high temperature threshold and lower than the first preset high temperature threshold, and the temperature parameters are adjusted according to the exponential law with a decay rate lower than that of the P3 layer, so that the knowledge transfer process prioritizes stabilizing the expression of macro-defect features.

[0081] For the characteristic tensor of the P4 layer, the initial temperature value is set to the third preset high temperature threshold and between the first preset high temperature threshold and the second preset high temperature threshold. The temperature parameters are adjusted according to the exponential law with a decay rate between the P3 and P5 layers to balance the characteristic migration stability of microscopic details and macroscopic structures.

[0082] In a specific embodiment, the P3 level is dedicated to capturing the fine geometric features of microscopic defects, including the linear topological structure of microcracks, the local texture anomalies of solder joints, and the edge fracture characteristics of oxidation points; the P3 level retains the high-resolution feature map of the input image at a 1 / 8 downsampling scale, and the actual defect size range corresponding to a single pixel is 0.05 to 0.2 mm; the maximum initial temperature value is set to the first preset high temperature threshold τ init (P3) =10±0.5, according to the exponential decay law τ s =τ init ·e {-kt} Dynamically adjust the temperature parameters (attenuation coefficient k (P3) =0.035±0.003), so that the probability distribution is softened by high temperature (τ>5) in the early stage of training to suppress background noise, and the low temperature (τ final =3±0.3) sharpens the distribution and focuses on details, achieving a migration transition from noise suppression to detail focusing.

[0083] The P4 layer dominates the cross-layer feature fusion of medium-scale defects, including contrast anomalies in local oxidation areas, regional morphological distortion of small-area deformations, and multi-scale correlation features of transitional defects. The P4 layer corresponds to a medium-resolution feature map with a downsampling scale of 1 / 16, and the single-pixel coverage defect size range is 0.2 to 0.8 mm. Its initial temperature value is between P3 and P5, which is τ init (P4) =8±0.5, decay rate k=0.028±0.003, and its parameter decay law satisfies τ init (P3) >τ init (P4) >τ init (P5) And k (P3) >k (P4) >k (P5) , balancing the stability of micro- and macro-feature migration.

[0084] The P5 level is used to extract global semantic features of macro defects, including continuous edge features of large-area scratches, overall shape distortion of package offsets, and cross-region contrast anomalies. The P5 level corresponds to a low-resolution feature map with a downsampling scale of 1 / 32, and the single-pixel coverage defect size range is 0.8 to 2.0 mm; its set minimum initial temperature value is τ init (P5) =6±0.5, using the slowest decay rate (k (P5) =0.022±0.003), maintaining the continuous stability of macroscopic feature migration.

[0085] S13. Construct a multi-scale dynamic temperature loss function, and fuse the cross-scale knowledge transfer losses of the P3, P4, and P5 levels through weighted summation. The square value of the temperature parameter of each level is used as the loss weight coefficient of the corresponding level. The multi-scale dynamic temperature loss function is:

[0086]

[0087] Where s∈{3,4,5} is the feature pyramid level index, corresponding to layers P3 to P5, Ts and Ss are the feature tensors of the teacher and student at scale s respectively; τ s is the exponential decay temperature parameter differentiated by level, satisfying τ s =τ init ·e {-kt} ;D KL is the KL divergence, which measures the difference in the distribution of teacher and student characteristics, and σ(·) is the Softmax function, which is used to generate the probability distribution.

[0088] S14. Synchronously control the exponential decay process of the temperature parameters at the P3-P5 level and the model parameter update to achieve a gradual transition from coarse-grained feature migration to fine-grained feature migration.

[0089] S2. In the feature migration process, a deformable feature alignment module is introduced to dynamically correct the geometric deformation feature offset between the teacher model and the student model through the learnable offset parameter, and the target feature channel carrying chip defect characterization information is screened from the features output by the deformable feature alignment module.

[0090] Further, if Figure 3 As shown, step S2 includes:

[0091] S21. Embed a deformable feature alignment module (DFAM) in the feature migration path of the teacher model and the student model. The module consists of a deformable convolution and a channel attention unit, and performs the following operations: align =DeformConv(F tea ,Δp)+SE(F stu ), where F tea is the original feature map output by the teacher model, Δp is the learnable offset parameter, and the key position offset pattern in the teacher feature space is learned through back propagation, F stu is the original feature map output by the student model, SE(·) is the channel attention unit, and the important channels of the student features are screened through the compression-excitation mechanism.

[0092] S22. Using the original feature map output by the teacher model as the deformation correction benchmark, the spatial geometric compensation of the original feature map output by the student model relative to the feature map output by the teacher model is determined by the learnable offset parameter in the deformable feature alignment module to generate a deformation compensation feature map. The offset parameter Δp learns the non-rigid deformation relationship between the teacher feature and the student feature (such as solder joint offset, package warpage), and generates a deformation compensation feature map DeformConv(F tea ,Δp).

[0093] S23. Add and fuse the deformation compensation feature map with the original feature map output by the teacher model channel by channel to obtain a cross-model semantic enhancement feature map.

[0094] The deformation-compensated teacher feature map and the student feature map are cross-model fused with the channel-attention-weighted features: Falign = DeformConv(F tea ,Δp)+γ·SE(F stu ), where γ = 0.6 is the fusion coefficient, which balances the semantic integrity of the teacher supervision signal and the student features.

[0095] S24. Perform global average pooling in the channel dimension on the cross-model semantic enhancement feature map to generate a channel description vector, and calculate the attention weight value of each channel through the fully connected layer and Sigmoid activation function.

[0096] S25. Adjust the channel screening threshold according to the current defect size distribution data obtained, and select feature channels with attention weight values higher than the dynamic threshold as target channels carrying chip defect characterization information.

[0097] Furthermore, when the proportion of microcrack defects in a statistical period exceeds a preset ratio threshold, the channel screening threshold is lowered to a first preset interval, and the hidden layer capacity of the fully connected layer is expanded, and the offset parameter learning rate of the deformable feature alignment module is simultaneously increased to a first learning rate range; when the proportion of weld deformation defects in a statistical period exceeds a preset ratio threshold, the channel screening threshold is raised to a second preset interval, and the hidden layer capacity of the fully connected layer is compressed, and the offset parameter learning rate of the deformable feature alignment module is simultaneously reduced to a second learning rate range; when the defect distribution does not meet any dominant type standard, a weighted fusion strategy is used to calculate the channel screening threshold based on the weight of the proportion of microcracks and deformation defects; wherein, the first preset interval is the lower limit interval of the channel screening threshold, and the upper limit value of the first preset interval does not exceed the lower limit value of the second preset interval, and the minimum value of the first learning rate range is higher than the maximum value of the second learning rate range.

[0098] It should be understood that crack defects refer to linear or branch-like topological structural defects formed on the surface or inside the chip. Their characteristic size is smaller than the tolerance threshold allowed by the chip packaging process, and they appear as high-frequency texture anomalies and local contrast mutations in the characteristic image. Their maximum linear width is less than 0.1mm.

[0099] Solder joint deformation defects: These are regional geometric distortion defects caused by abnormal soldering processes. These defects have a larger characteristic size than microcracks and a continuous edge morphology. In the feature map, these defects manifest as abnormal semantic associations and shape consistency across channels. The spatial offset of the solder joint area relative to the designed position is greater than 0.5 mm, or the deformed area exceeds 25% of the standard pad area.

[0100] Specifically, when the proportion of microcracks smaller than 0.1 mm in the defect size distribution data exceeds the preset ratio threshold, the channel screening threshold is adjusted to the first dynamic threshold range (0.12-0.18), and the hidden nodes of the fully connected layer are increased to the first preset number (≥128 nodes) to enhance the capture capability of the high-frequency detail channel, and the offset learning rate of the deformable feature alignment module is increased to the first learning rate range (3e-4-5e-4); when the proportion of weld deformation defects larger than 0.5 mm exceeds the preset ratio threshold, the channel screening threshold is adjusted to the second dynamic threshold range (0.22-0.28), and the hidden nodes of the fully connected layer are reduced to the second preset number (≤64 nodes) to focus on the structural deformation channel screening, and the offset learning rate of the deformable feature alignment module is reduced to the second learning rate range (1e-4-2e-4) to suppress over-correction of macro features; when the proportion of both types of defects does not reach the preset ratio threshold, the weighted average method is used to calculate the mixed threshold, and the weighted average method is used to calculate the channel screening threshold.

[0101] S3. Reconstruct the backbone network of the student model by embedding depthwise separable convolution, replace the convolution operation with channel-by-channel convolution and point-by-point convolution, and use the gradient amplitude-based channel importance evaluation results of each convolution layer to iteratively prune and compress to generate a lightweight inference model.

[0102] Further, if Figure 4 As shown, step S3 includes:

[0103] S31. Replace the convolutional layer of the student model with a depthwise separable convolutional module to reconstruct the backbone network of the student model; wherein the depthwise separable convolutional module includes a channel-by-channel convolutional layer and a point-by-point convolutional layer connected in series, the channel-by-channel convolutional layer independently performs spatial feature extraction on each channel of the input feature, and the point-by-point convolutional layer linearly combines the cross-channel features.

[0104] Replace the regular convolutional layers of the YOLOv11 student model with depthwise separable convolutional modules. Each module consists of a series of channel-wise convolution (Depthwise Conv) and pointwise convolution (Pointwise Conv):

[0105] Channel-by-channel convolution layer: Spatial feature extraction is performed independently on each channel of the input feature map X, using a k×k convolution kernel (k=3). The number of output channels remains the same as the input. The calculation process is:

[0106]

[0107] Point-by-point convolution layer: Cross-channel feature fusion is achieved through 1×1 convolution, and the channel dimension is expanded to the target output dimension. The calculation process is:

[0108] Pointwise(X)=Conv 1×1 (X);

[0109] Obviously, the number of parameters of a standard 3×3 convolution is 9C in C out , the number of depth-separable convolution parameters is 9C in +C in C out , the compression ratio is up to 8.9 times (when the output channel number C out 》Number of input channels C in hour)

[0110] S32 dynamically evaluates the importance of each convolutional layer channel based on backpropagation gradient amplitude, where the importance score is positively correlated with the gradient norm of the channel weight tensor. Redundant channels with importance scores below the preset pruning threshold are iteratively pruned, and a sparse feature extraction network is constructed based on the retained channels. By evaluating channel importance based on gradient amplitude and dynamically removing redundant channels, the model size can be compressed to 5.2MB. Support for TensorRT static acceleration makes it more advantageous in hardware deployment and meets the requirements of practical applications for small model size and fast execution.

[0111] The importance of each convolutional layer channel is evaluated based on the back-propagation gradient magnitude, and the importance score is calculated as:

[0112]

[0113] Where W c Represents the weight tensor of the c-th channel, L detect For the target detection loss function, we set a pruning threshold of β = 0.15 and dynamically pruned channels with importance scores below the threshold, retaining key feature channels to form a sparse network. After pruning, the model's parameters were reduced to 17.6% of the original model.

[0114] S33. After each pruning operation, recalibrate the convolution kernel parameters of the retained channels and restore the model detection accuracy through constrained fine-tuning. Apply L2 norm constraint (λ = 1e-4) to the convolution kernel of the retained channels and perform fine-tuning through constrained backpropagation:

[0115] W pruned ←W pruned -η(▽L+λ·sign(W pruned ));

[0116] Where W pruned is the weight parameter retained after pruning, η is the learning rate, ▽L is the gradient of the loss function with respect to the weight, sign(W) is the weight sign function, and the number of fine-tuning rounds is 5 to 8 to recover the accuracy loss caused by pruning.

[0117] S34. Perform hardware adaptation optimization on the pruned student model to generate a lightweight inference model that can be deployed on edge computing devices.

[0118] Specifically, hardware adaptation optimization includes the following situations: performing mixed precision quantization on the model deployed on the embedded GPU, converting the 32-bit floating-point parameters into 8-bit fixed-point format, and simultaneously retaining the 16-bit floating-point precision of at least 5% of the weight perturbation-sensitive channels, where the weight perturbation-sensitive channels are screened out by slightly perturbing the weights and observing the output changes, that is, the output mean square error ΔMSE ≥ the set threshold; performing layer fusion optimization on the model deployed on the FPGA, merging adjacent channel-by-channel convolution layers and point-by-point convolution layers into a composite operator, and generating a static bitstream file with a configurable logic block resource occupancy rate of ≤65%.

[0119] S4. Input the pre-processed chip image into the lightweight inference model, use the target feature channel for cross-scale fusion, feature decoding and post-processing, and output the detection results including defect type, location coordinates and confidence score

[0120] Furthermore, if Figure 5 As shown, step S4 includes:

[0121] S41. Input the preprocessed chip image into the lightweight inference model, use the target feature channel for cross-scale fusion, and generate a multi-scale fusion feature map.

[0122] Before model training, it is essential to pre-process the chip data. We use advanced data enhancement techniques to expand and complicate the original chip dataset to improve the generalization ability of the model. Specific techniques include image rotation, flipping, scaling, and adjustment of brightness and contrast. These operations can simulate actual application scenarios in different environments, increase data diversity, and enable the model to maintain good performance in the face of various complex situations. Next, the chip data is normalized to ensure that the distribution of input data tends to be consistent, which helps accelerate model convergence and improve training results. At the same time, professional annotation tools are used to accurately annotate the chip data to ensure that the model can accurately understand and learn the location and attributes of each target, providing effective supervision signals for subsequent training.

[0123] S42. Perform multi-task decoding on the multi-scale fusion feature map, and output the decoding results including the probability distribution of defect categories and bounding box coordinates through the classification branch and the regression branch respectively. The regression branch introduces a deformation resistance coefficient to correct the positioning error of the solder joint offset.

[0124] S43. Dynamic post-processing optimization is performed on the decoding results. The redundant detection frames for microcracks and solder joint deformation defects are distinguished by a hierarchical non-maximum suppression strategy, and the confidence score is adjusted using a temperature scaling calibration method.

[0125] S44. Output structured detection result data including defect type, location coordinates, confidence score and deformation energy level.

[0126] In one specific embodiment, a preprocessed chip image is fed into the lightweight inference model, and cross-scale feature fusion is performed using the target feature channels selected by the deformable feature alignment module: a) a first fusion weight is applied to the high-resolution micro-defect features of the P3 layer, dynamically calculated based on the proportion of microcrack channels in the current batch; b) a second fusion weight is applied to the low-resolution macro-defect features of the P5 layer, positively correlated with the confidence of the solder joint deformation channel; c) the P4 layer features, weighted by channel attention, serve as a transition bridge for cross-scale fusion, connecting the P3 and P5 layer feature maps. Next, multi-task decoding is performed on the fused cross-scale feature maps: the classification branch outputs a probability distribution of defect categories, employing a label smoothing strategy to suppress false detections of oxidation defects; the regression branch outputs normalized bounding box coordinates, which are combined with the deformation resistance coefficient to correct for positioning errors caused by solder joint offset.

[0127] Then, the decoded original detection results are dynamically post-processed and optimized: a) Hierarchical non-maximum suppression (NMS) is performed: an IOU threshold of 0.35±0.02 and Gaussian weighted confidence fusion are used for microcrack defects; an IOU threshold of 0.55±0.02 is used for solder joint deformation defects and combined with deformation energy constraints; b) The confidence score is adjusted using the temperature scaling calibration method, and the calibration temperature T=1.5±0.1 is set to match the edge device deployment requirements. Finally, the structured detection result data is output, including: defect type code and corresponding confidence score, normalized values of the bounding box center coordinates (x, y) and width and height (w, h), and defect size estimation (unit: μm) and deformation energy level identification. Reference Figure 6 , it can be seen that the packaged chip detection results show a confidence level of 0.8, indicating that the model is highly confident that there is deformation anomaly in this area.

[0128] Additionally, an embodiment of the present invention provides a lightweight chip defect detection system using dynamic distillation and depthwise separable convolution, including:

[0129] The model transfer module is used to build a multi-scale temperature distillation framework that includes a teacher model and a student model based on YOLOv11. Based on the feature pyramid output by the teacher model, it adjusts the granularity of knowledge transfer between the teacher model and the student model by configuring differential temperature parameters with exponential decay for features at different scales to achieve progressive feature transfer.

[0130] The offset adjustment and channel screening module is used to introduce a deformable feature alignment module during the feature migration process, dynamically correct the geometric deformation feature offset between the teacher model and the student model through learnable offset parameters, and screen the target feature channels carrying chip defect characterization information from the features output by the deformable feature alignment module.

[0131] The model lightweight processing module is used to reconstruct the backbone network of the student model by embedding depthwise separable convolution, replacing the convolution operation with channel-by-channel convolution and point-by-point convolution, and using the gradient amplitude-based channel importance evaluation results of each convolution layer to iteratively prune and compress to generate a lightweight inference model.

[0132] The defect detection module is used to input the preprocessed chip image into the lightweight inference model, use the target feature channel for cross-scale fusion, feature decoding and post-processing, and output the detection results including defect type, location coordinates and confidence score.

[0133] In addition, an embodiment of the present invention provides a lightweight chip defect detection device using dynamic distillation and deep separable convolution, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the lightweight chip defect detection method using dynamic distillation and deep separable convolution as described above.

[0134] Furthermore, an embodiment of the present invention provides a computer-readable storage medium, which stores computer-executable instructions. When the executable instructions are executed by a processor, the lightweight chip defect detection method using dynamic distillation and depth-separable convolution as described above is implemented.

[0135] Since the systems / devices described in the above embodiments of the present invention are systems / devices used to implement the methods of the above embodiments of the present invention, those skilled in the art will be able to understand the specific structures and variations of these systems / devices based on the methods described in the above embodiments of the present invention, and thus will not be described in detail here. All systems / devices used in the methods of the above embodiments of the present invention are within the scope of protection of the present invention.

[0136] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0137] The present invention is described with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions.

[0138] It should be noted that, in the claims, any reference signs placed between brackets shall not be construed as limiting the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claims. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The invention may be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In claims enumerating several means, several of these means may be embodied by one and the same hardware. The use of the words first, second, third etc. is for convenience only and does not indicate any order. These words may be understood as part of the component name.

[0139] In addition, it should be noted that, in the description of this specification, the description of the terms "one embodiment", "some embodiments", "embodiment", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

[0140] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments after learning the basic creative concept. Therefore, the claims should be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0141] Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if such modifications and variations fall within the scope of the claims and their equivalents, the present invention shall also include such modifications and variations.

Claims

1. A lightweight chip defect detection method based on dynamic distillation and depthwise separable convolution, characterized by: include: A multi-scale temperature distillation framework is constructed, consisting of a teacher model and a student model based on YOLOv11. Using the feature pyramid output by the teacher model as a benchmark, the framework adjusts the granularity of knowledge transfer between the teacher and student models by configuring exponentially decaying temperature parameters for features at different scales, thereby achieving progressive feature transfer. During the feature migration process, a deformable feature alignment module is introduced to dynamically correct the geometric deformation feature offset between the teacher model and the student model through a learnable offset parameter. Target feature channels carrying chip defect characterization information are then selected from the features output by the deformable feature alignment module. The backbone network of the student model is reconstructed by embedding depthwise separable convolutions, replacing convolution operations with channel-by-channel convolutions and point-by-point convolutions. The gradient-magnitude-based channel importance evaluation results of each convolutional layer are used for iterative pruning and compression to generate a lightweight inference model. The preprocessed chip image is input into the lightweight inference model, and the target feature channel is used for cross-scale fusion, feature decoding and post-processing, and the detection results including defect type, location coordinates and confidence score are output.

2. The lightweight chip defect detection method using dynamic distillation and depthwise separable convolution as claimed in claim 1 is characterized in that: A multi-scale temperature distillation framework is constructed, which includes a teacher model and a student model based on YOLOv11. Taking the feature pyramid output by the teacher model as the benchmark, the framework adjusts the granularity of knowledge transfer between the teacher model and the student model by configuring differential temperature parameters with exponential decay for features at different scales, thereby achieving progressive feature transfer. This includes: Build a multi-scale temperature distillation framework consisting of a teacher model and a student model based on YOLOv11; Extract the feature tensors of the P3-P5 levels in the feature pyramid from the teacher model and configure the following independent temperature parameters for each scale feature: For the characteristic tensor of the P3 layer, the initial temperature value is set to the first preset high temperature threshold, and the temperature parameter is dynamically adjusted according to the exponential decay law; For the characteristic tensor of the P5 layer, the initial temperature value is set to the second preset high temperature threshold and lower than the first preset high temperature threshold, and the temperature parameter is adjusted according to the exponential law with a decay rate lower than that of the P3 layer; For the characteristic tensor of the P4 layer, the initial temperature value is set to the third preset high temperature threshold and between the first preset high temperature threshold and the second preset high temperature threshold, and the temperature parameter is adjusted according to the exponential law with a decay rate between the P3 and P5 layers; Construct a multi-scale dynamic temperature loss function and fuse the cross-scale knowledge transfer losses of P3, P4, and P5 levels through weighted summation; The exponential decay process of the temperature parameters at the P3-P5 levels is synchronously controlled with the model parameter update to achieve a gradual transition from coarse-grained feature migration to fine-grained feature migration.

3. The lightweight chip defect detection method using dynamic distillation and depthwise separable convolution as claimed in claim 1, characterized in that: During the feature migration process, a deformable feature alignment module is introduced to dynamically correct the geometric deformation feature offset between the teacher model and the student model through learnable offset parameters. Target feature channels carrying chip defect characterization information are selected from the features output by the deformable feature alignment module. These channels include: Embed a deformable feature alignment module in the feature transfer path between the teacher model and the student model; The original feature map output by the teacher model is used as the deformation correction benchmark. The learnable offset parameters in the deformable feature alignment module are used to determine the spatial geometric compensation amount of the original feature map output by the student model relative to the feature map output by the teacher model, thereby generating a deformation-compensated feature map. The deformation compensation feature map is fused with the original feature map output by the teacher model channel by channel to obtain a cross-model semantic enhancement feature map; Perform global average pooling of the channel dimension on the cross-model semantic enhancement feature map to generate a channel description vector, and calculate the attention weight value of each channel through the fully connected layer and Sigmoid activation function; The channel screening threshold is adjusted according to the current defect size distribution data obtained, and the feature channels with attention weight values higher than the dynamic threshold are selected as the target channels carrying chip defect characterization information.

4. The lightweight chip defect detection method using dynamic distillation and depthwise separable convolution as claimed in claim 3 is characterized in that: When the proportion of microcrack defects in the statistical period exceeds the preset ratio threshold, the channel screening threshold is lowered to the first preset range, the hidden layer capacity of the fully connected layer is expanded, and the offset parameter learning rate of the deformable feature alignment module is simultaneously increased to the first learning rate range; When the proportion of solder joint deformation defects in a statistical period exceeds a preset ratio threshold, the channel screening threshold is raised to a second preset interval, the hidden layer capacity of the fully connected layer is compressed, and the offset parameter learning rate of the deformable feature alignment module is simultaneously reduced to a second learning rate range; When the proportion of microcrack defects and weld deformation defects does not exceed the preset ratio threshold, a weighted fusion strategy is used to calculate the channel screening threshold based on the weights of the proportions of microcracks and deformation defects; The first preset interval is the lower limit interval of the channel screening threshold, the upper limit value of the first preset interval does not exceed the lower limit value of the second preset interval, and the minimum value of the first learning rate range is higher than the maximum value of the second learning rate range.

5. The lightweight chip defect detection method using dynamic distillation and depthwise separable convolution as claimed in claim 1, characterized in that: The backbone network of the student model is reconstructed by embedding depthwise separable convolutions, replacing convolution operations with channel-by-channel and point-by-point convolutions. Iterative pruning and compression are performed using the gradient magnitude-based channel importance evaluation results of each convolutional layer to generate a lightweight inference model. Replace the convolutional layers of the student model with depth-wise separable convolutional modules to reconstruct the backbone network of the student model; The importance of each convolutional layer channel is dynamically evaluated based on the back-propagation gradient amplitude. Redundant channels with importance scores lower than the preset pruning threshold are iteratively pruned according to the preset pruning threshold. A sparse feature extraction network is constructed based on the retained channels. After each pruning operation, the convolution kernel parameters of the retained channels are recalibrated, and the model detection accuracy is restored through constrained fine-tuning; Perform hardware adaptation optimization on the pruned student model to generate a lightweight inference model that can be deployed on edge computing devices; Among them, the depthwise separable convolution module includes a channel-by-channel convolution layer and a point-by-point convolution layer connected in series. The channel-by-channel convolution layer independently performs spatial feature extraction on each channel of the input feature, and the point-by-point convolution layer linearly combines the cross-channel features.

6. The lightweight chip defect detection method using dynamic distillation and depthwise separable convolution as claimed in claim 5, characterized in that: Hardware adaptation optimization includes: Perform mixed-precision quantization on models deployed on embedded GPUs, converting 32-bit floating-point parameters to 8-bit fixed-point format while retaining 16-bit floating-point accuracy for at least 5% of weight perturbation-sensitive channels. Perform layer fusion optimization on the model deployed on the FPGA, merge adjacent channel-by-channel convolution layers and point-by-point convolution layers into a composite operator, and generate a static bitstream file with a configurable logic block resource occupancy rate of ≤65%.

7. The lightweight chip defect detection method using dynamic distillation and depthwise separable convolution as claimed in claim 1, characterized in that: The pre-processed chip image is input into the lightweight inference model, and the target feature channel is used for cross-scale fusion, feature decoding, and post-processing. The output includes the following detection results: defect type, location coordinates, and confidence score: The pre-processed chip image is input into the lightweight inference model, and the target feature channel is used for cross-scale fusion to generate a multi-scale fusion feature map; Multi-task decoding is performed on the multi-scale fusion feature map. The classification branch and regression branch respectively output the decoding results containing the probability distribution of defect categories and bounding box coordinates. The regression branch introduces a deformation resistance coefficient to correct the positioning error of solder joint offset. Dynamic post-processing optimization is performed on the decoding results. A hierarchical non-maximum suppression strategy is used to distinguish and process redundant detection frames for microcracks and solder joint deformation defects, and a temperature scaling calibration method is used to adjust the confidence score. The output includes structured detection result data including defect type, location coordinates and confidence score.

8. A lightweight chip defect detection system based on dynamic distillation and depth-separable convolution, characterized by: include: The model transfer module is used to build a multi-scale temperature distillation framework consisting of a teacher model and a student model based on YOLOv11. Based on the feature pyramid output by the teacher model, the module adjusts the granularity of knowledge transfer between the teacher and student models by configuring exponentially decaying differentiated temperature parameters for features at different scales, thereby achieving progressive feature transfer. The offset adjustment and channel screening module is used to introduce the deformable feature alignment module during the feature migration process. It dynamically corrects the geometric deformation feature offset between the teacher model and the student model through learnable offset parameters, and selects the target feature channels that carry chip defect characterization information from the features output by the deformable feature alignment module. The model lightweight processing module is used to reconstruct the backbone network of the student model by embedding depthwise separable convolution, replacing the convolution operation with channel-by-channel convolution and point-by-point convolution. It also uses the gradient magnitude-based channel importance evaluation results of each convolution layer to perform iterative pruning and compression to generate a lightweight inference model. The defect detection module is used to input the preprocessed chip image into the lightweight inference model, use the target feature channel for cross-scale fusion, feature decoding and post-processing, and output the detection results including defect type, location coordinates and confidence score.

9. A lightweight chip defect detection device using dynamic distillation and deep separable convolution, characterized by: include: at least one processor; and a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by at least one processor, and the instructions are executed by at least one processor so that the at least one processor can execute the lightweight chip defect detection method of dynamic distillation and deep separable convolution as described in any one of claims 1 to 7.

10. A computer-readable storage medium having computer-executable instructions stored thereon, characterized in that: When the executable instructions are executed by the processor, the lightweight chip defect detection method using dynamic distillation and depthwise separable convolution as described in any one of claims 1 to 7 is implemented.

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