Driving circuit, driving method, driving module and display device

Abstract

The invention provides a driving circuit, a driving method, a driving module and a display device. The driving circuit comprises a driving output end, N input circuits, N input control circuits, a first node control circuit and an output circuit, and N is an integer greater than 1; n is a positive integer smaller than or equal to N; the nth input circuit writes an input signal into the first node under the control of the potential of the nth input control node; the nth input control circuit controls the potential of the nth input control node according to the nth input control voltage under the control of the driving signal; the first node control circuit controls the potential of the first node; the output circuit controls the driving output end to provide a driving signal under the control of the potential of the first node.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a driving circuit, a driving method, a driving module and a display device. Background Art

[0002] In the related art, in order to save costs, the gate-on-array (GOA) circuit (a gate driver circuit provided on the array substrate) is often used in the TFT-LCD (thin-film transistor-liquid crystal display) manufacturing process instead of an external printed circuit board. However, during use, the TFT devices in the GOA circuit may be mischarged due to noise interference. Summary of the Invention

[0003] The main purpose of the present invention is to provide a driving circuit, a driving method, a driving module and a display device to solve the problem that TFT devices in existing GOA circuits may be mischarged due to noise interference.

[0004] In one aspect, an embodiment of the present invention provides a driving circuit, comprising a driving output terminal, N input circuits, N input control circuits, a first node control circuit, and an output circuit, where N is an integer greater than 1; n is a positive integer less than or equal to N;

[0005] The nth input circuit is electrically connected to the first node, the input terminal, and the nth input control node, respectively, and is configured to write the input signal provided by the input terminal into the first node under the control of the potential of the nth input control node;

[0006] an nth input control circuit electrically connected to the driving output terminal, the nth input control node, and the nth input control voltage terminal, respectively, for controlling the potential of the nth input control node according to an nth input control voltage provided by the nth input control voltage terminal under the control of a driving signal provided by the driving output terminal;

[0007] The first node control circuit is electrically connected to the first node and is used to control the potential of the first node;

[0008] The output circuit is electrically connected to the first node and the driving output end respectively, and is used to control the driving output end to provide a driving signal under the control of the potential of the first node.

[0009] Optionally, the nth input circuit includes an nth first transistor;

[0010] The gate of the nth first transistor is electrically connected to the nth input control node, the first electrode of the nth first transistor is electrically connected to the input end, and the second electrode of the nth first transistor is electrically connected to the first node.

[0011] Optionally, the nth input control circuit includes an nth second transistor and an nth third transistor;

[0012] The gate of the nth second transistor and the first electrode of the nth second transistor are electrically connected to the nth input control voltage terminal, and the second electrode of the nth second transistor is electrically connected to the nth input control node;

[0013] The gate of the nth third transistor is electrically connected to the driving output terminal, the first electrode of the nth third transistor is electrically connected to the nth input control node, and the second electrode of the nth third transistor is electrically connected to the first voltage terminal.

[0014] Optionally, a channel width-to-length ratio of the nth third transistor is greater than a channel width-to-length ratio of the nth second transistor.

[0015] Optionally, a ratio of a channel width-to-length ratio of the nth third transistor to a channel width-to-length ratio of the nth second transistor is greater than or equal to 1.5 and less than or equal to 3.5.

[0016] Optionally, the first node control circuit is further electrically connected to the reset terminal, the second node, and the second voltage terminal, respectively, and is configured to control the connection or disconnection between the first node and the second voltage terminal under the control of a reset signal provided by the reset terminal, and to control the connection or disconnection between the first node and the second voltage terminal under the control of the potential of the second node;

[0017] The output circuit is also electrically connected to the output clock signal terminal, and is configured to provide the output clock signal provided by the output clock signal terminal to the driving output terminal under the control of the potential of the first node.

[0018] Optionally, the driving circuit further includes a second node control circuit and an output reset circuit;

[0019] The second node control circuit is electrically connected to the first node and the second node respectively, and is used to control the potential of the second node under the control of the potential of the first node;

[0020] The output reset circuit is electrically connected to the second node, the driving output terminal and the third voltage terminal respectively, and is used to control the connection or disconnection between the driving output terminal and the third voltage terminal under the control of the potential of the second node.

[0021] Optionally, the second node control circuit includes a first second node control circuit and a second second node control circuit;

[0022] The first second node control circuit is electrically connected to the first control voltage terminal, the first node, the first second node, and the fourth voltage terminal, respectively, and is configured to control the potential of the first second node according to a first control voltage provided by the first control voltage terminal under the control of the potential of the first node;

[0023] The second second-node control circuit is electrically connected to the second control voltage terminal, the first node, the second second node, and the fourth voltage terminal, respectively, and is configured to control the potential of the second second node according to a second control voltage provided by the second control voltage terminal under the control of the potential of the first node;

[0024] The output reset circuit is electrically connected to the first second node, the second second node, the drive output terminal and the third voltage terminal, respectively, and is used to control the connection or disconnection between the drive output terminal and the third voltage terminal under the control of the potential of the first second node, and to control the connection or disconnection between the drive output terminal and the third voltage terminal under the control of the potential of the second second node.

[0025] Optionally, N is equal to 2;

[0026] The first input control voltage terminal is a first control voltage terminal, and the second input control voltage terminal is a second control voltage terminal.

[0027] Optionally, the first second-node control circuit includes a first fourth transistor and a first fifth transistor, and the second second-node control circuit includes a second fourth transistor and a second fifth transistor;

[0028] The gate of the first fourth transistor and the first electrode of the first fourth transistor are electrically connected to the first control voltage terminal, and the second electrode of the first fourth transistor is electrically connected to the first second node;

[0029] The gate of the first fifth transistor is electrically connected to the first node, the first electrode of the first fifth transistor is electrically connected to the first second node, and the second electrode of the first fifth transistor is electrically connected to the fourth voltage terminal;

[0030] The gate of the second fourth transistor and the first electrode of the second fourth transistor are electrically connected to the second control voltage terminal, and the second electrode of the second fourth transistor is electrically connected to the second second node;

[0031] The gate of the second fifth transistor is electrically connected to the first node, the first electrode of the second fifth transistor is electrically connected to the second second node, and the second electrode of the second fifth transistor is electrically connected to the fourth voltage terminal.

[0032] Optionally, the nth input control circuit includes an nth second transistor and an nth third transistor;

[0033] The channel width-to-length ratio of each second transistor is greater than the channel width-to-length ratio of each fourth transistor, and the channel width-to-length ratio of each third transistor is greater than the channel width-to-length ratio of each fifth transistor.

[0034] Optionally, a ratio of a channel width-to-length ratio of each of the second transistors to a channel width-to-length ratio of each of the fourth transistors is greater than or equal to 20 and less than or equal to 70;

[0035] A ratio of a channel width-to-length ratio of each third transistor to a channel width-to-length ratio of each fifth transistor is greater than or equal to 1.2 and less than or equal to 4.

[0036] In a second aspect, an embodiment of the present invention provides a driving method, which is applied to the above-mentioned driving circuit, wherein a display cycle includes an output phase; the driving method includes:

[0037] In the output stage, the driving output terminal provides a valid driving signal, the nth input control circuit controls the potential of the nth input control node to be an invalid potential, and the nth input circuit controls the input terminal to be disconnected from the first node under the control of the potential of the nth input control node.

[0038] The driving method according to at least one embodiment of the present invention further includes:

[0039] In a time period other than the output phase included in the display cycle, when the driving output terminal provides an invalid driving signal, the nth input control circuit controls the potential of the nth input control node to be a valid potential, and the nth input circuit controls the input terminal to be connected to the first node under the control of the potential of the nth input control node.

[0040] In a third aspect, an embodiment of the present invention provides a driving module, comprising a plurality of stages of the above-mentioned driving circuits; the driving circuits include an input terminal and a reset terminal;

[0041] The input terminal of the m-th driving circuit is electrically connected to the driving output terminal of the ma-th driving circuit, and the reset terminal of the m-th driving circuit is electrically connected to the driving output terminal of the m+a-th driving circuit;

[0042] m is a positive integer, and a is a positive integer.

[0043] In a fourth aspect, an embodiment of the present invention provides a display device, characterized in that it includes the above-mentioned driving circuit.

[0044] At least one embodiment of the present invention uses at least two input circuits and at least two input control circuits, wherein the input circuit is electrically connected to the input end, and the input end can be electrically connected to the previous a-level driver output end to achieve noise reduction of the first node, so that the transistor in the driver circuit will not be mischarged due to noise interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0046] Figure 2 is a structural diagram of a three-stage driving circuit included in the driving module according to at least one embodiment of the present invention;

[0047] Figure 3 is a structural diagram of a driving circuit according to at least one embodiment of the present invention;

[0048] Figure 4 is a circuit diagram of a driving circuit according to at least one embodiment of the present invention;

[0049] Figure 5 is a circuit diagram of a three-stage driving circuit included in the driving module according to at least one embodiment of the present invention;

[0050] Figure 6 yes Figure 5 The working timing diagram of at least one embodiment is shown. DETAILED DESCRIPTION

[0051] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0052] The transistors used in all embodiments of the present invention may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0053] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0054] The driving circuit according to the embodiment of the present invention includes a driving output terminal, N input circuits, N input control circuits, a first node control circuit, and an output circuit, where N is an integer greater than 1; n is a positive integer less than or equal to N;

[0055] The nth input circuit is electrically connected to the first node, the input terminal, and the nth input control node, respectively, and is configured to write the input signal provided by the input terminal into the first node under the control of the potential of the nth input control node;

[0056] an nth input control circuit electrically connected to the driving output terminal, the nth input control node, and the nth input control voltage terminal, respectively, for controlling the potential of the nth input control node according to an nth input control voltage provided by the nth input control voltage terminal under the control of a driving signal provided by the driving output terminal;

[0057] The first node control circuit is electrically connected to the first node and is used to control the potential of the first node;

[0058] The output circuit is electrically connected to the first node and the driving output end respectively, and is used to control the driving output end to provide a driving signal under the control of the potential of the first node.

[0059] In the related art, in order to save costs, the gate-on-array (GOA) circuit (a gate driver circuit provided on the array substrate) is often used in the TFT-LCD (thin-film transistor-liquid crystal display) manufacturing process instead of an external printed circuit board. However, during use, the TFT devices in the GOA circuit may be mischarged due to noise interference.

[0060] Based on the above problems, at least one embodiment of the present invention adopts at least two input circuits and at least two input control circuits, wherein the input circuit is electrically connected to the input end, and the input end can be electrically connected to the previous a-level driver output end to achieve noise reduction of the first node, so that the transistors in the driver circuit will not be mischarged due to noise interference; and when the driver circuit described in at least one embodiment of the present invention is working, the N input circuits can work alternately and the N input control circuits can work alternately, thereby reducing the stress effect of the transistors included in the input circuit and the transistors included in the input control circuit.

[0061] like Figure 1 As shown, the driving circuit according to at least one embodiment of the present invention includes a driving output terminal GT, a first input circuit 11, a second input circuit 12, a first input control circuit 21, a second input control circuit 22, a first node control circuit 31 and an output circuit 32;

[0062] The first input circuit 11 is electrically connected to the first node PU, the input terminal SI and the first input control node PDD respectively, and is used to write the input signal provided by the input terminal SI into the first node PU under the control of the potential of the first input control node PDD;

[0063] The second input circuit 12 is electrically connected to the first node PU, the input terminal SI, and the second input control node PDD', respectively, and is configured to write the input signal provided by the input terminal SI into the first node PU under the control of the potential of the second input control node PDD';

[0064] The first input control circuit 21 is electrically connected to the driving output terminal GT, the first input control node PDD, and the first input control voltage terminal VI1, respectively, and is configured to control the potential of the first input control node PDD according to the first input control voltage provided by the first input control voltage terminal VI1 under the control of the driving signal provided by the driving output terminal GT;

[0065] The second input control circuit 22 is electrically connected to the driving output terminal GT, the second input control node PDD′, and the second input control voltage terminal VI2, respectively, and is configured to control the potential of the second input control node PDD′ according to the second input control voltage provided by the second input control voltage terminal VI2 under the control of the driving signal provided by the driving output terminal GT;

[0066] The first node control circuit 31 is electrically connected to the first node PU and is used to control the potential of the first node PU;

[0067] The output circuit 32 is electrically connected to the first node PU and the driving output terminal GT respectively, and is configured to control the driving output terminal GT to provide a driving signal under the control of the potential of the first node PU.

[0068] In the present invention Figure 1 In at least one embodiment of the driving circuit shown, the first input circuit 11, the second input circuit 12, the first input control circuit 21 and the second input control circuit 22 are used as starting units to implement the noise reduction function for the first node PU.

[0069] Optionally, the nth input circuit includes an nth first transistor;

[0070] The gate of the nth first transistor is electrically connected to the nth input control node, the first electrode of the nth first transistor is electrically connected to the input end, and the second electrode of the nth first transistor is electrically connected to the first node.

[0071] Optionally, the nth input control circuit includes an nth second transistor and an nth third transistor;

[0072] The gate of the nth second transistor and the first electrode of the nth second transistor are electrically connected to the nth input control voltage terminal, and the second electrode of the nth second transistor is electrically connected to the nth input control node;

[0073] The gate of the nth third transistor is electrically connected to the driving output terminal, the first electrode of the nth third transistor is electrically connected to the nth input control node, and the second electrode of the nth third transistor is electrically connected to the first voltage terminal.

[0074] Optionally, the first voltage terminal may be a low voltage terminal.

[0075] like Figure 2 As shown, the M-1-th stage driving circuit includes a first input circuit, a second input circuit, a first input control circuit, a second input control circuit and a first driving unit 201;

[0076] The first input circuit includes a first first transistor M11, the second input circuit includes a second first transistor M21, the first input control circuit includes a first second transistor M12 and a first third transistor M13, and the second input control circuit includes a second second transistor M22 and a second third transistor M23;

[0077] The gate of M11 is electrically connected to the first input control node PDDM-1 of the M-1th stage, the source of M11 is electrically connected to the driving output terminal GTM-2 of the M-2th stage, and the drain of M11 is electrically connected to the first node PUM-1 of the M-1th stage;

[0078] The gate of M21 is electrically connected to the second input control node PDDM-1′ of the M-1th stage, the source of M21 is electrically connected to the driving output terminal GTM-2 of the M-2th stage, and the drain of M21 is electrically connected to the first node PUM-1 of the M-1th stage;

[0079] The gate of M12 and the source of M12 are both electrically connected to the first control voltage terminal VDD1, and the drain of M12 is electrically connected to the first input control node PDDM-1 of the M-1th stage;

[0080] The gate of M13 is electrically connected to the M-1-th stage driving output terminal GTM-1, the source of M13 is electrically connected to the M-1-th stage first input control node PDDM-1, and the drain of M13 is electrically connected to the low voltage terminal Vss;

[0081] The gate of M22 and the source of M22 are both electrically connected to the second control voltage terminal VDD2, and the drain of M22 is electrically connected to the second input control node PDDM-1' of the M-1th stage;

[0082] The gate of M23 is electrically connected to the M-1 stage driving output terminal GTM-1, the source of M23 is electrically connected to the M-1 stage second input control node PDDM-1', and the drain of M23 is electrically connected to the low voltage terminal Vss;

[0083] The first driving unit 201 is electrically connected to the M-1th first node PUM-1, the first clock signal line CLK, the M-th level driving output terminal GTM, and the M-1th level driving output terminal GTM-1, respectively, and is configured to control the M-1th level driving output terminal GTM-1 to output the M-1th level driving signal under the control of the potential of the M-1th first node PUM-1 and according to the first clock signal provided by the first clock signal line CLK, and reset the M-1th level driving signal under the control of the M-th level driving signal provided by the M-th level driving output terminal GTM;

[0084] The M-th stage driving circuit includes a third input circuit, a fourth input circuit, a third input control circuit, a fourth input control circuit and a second driving unit 202;

[0085] The third input circuit includes a third first transistor M31, the fourth input circuit includes a fourth first transistor M41, the third input control circuit includes a third second transistor M32 and a third third transistor M33, and the fourth input control circuit includes a fourth second transistor M42 and a fourth third transistor M43;

[0086] The gate of M31 is electrically connected to the first input control node PDDM of the Mth stage, the source of M31 is electrically connected to the driving output terminal GTM-1 of the M-1th stage, and the drain of M31 is electrically connected to the first node PUM of the Mth stage;

[0087] The gate of M41 is electrically connected to the second input control node PDDM' of the Mth stage, the source of M41 is electrically connected to the driving output terminal GTM-1 of the M-1th stage, and the drain of M41 is electrically connected to the first node PUM of the Mth stage;

[0088] The gate of M32 and the source of M32 are both electrically connected to the first control voltage terminal VDD1, and the drain of M32 is electrically connected to the first input control node PDDM of the Mth stage;

[0089] The gate of M33 is electrically connected to the M-th stage driving output terminal GTM, the source of M33 is electrically connected to the M-th stage first input control node PDDM, and the drain of M33 is electrically connected to the low voltage terminal Vss;

[0090] The gate of M42 and the source of M42 are both electrically connected to the second control voltage terminal VDD2, and the drain of M42 is electrically connected to the second input control node PDDM' of the Mth stage;

[0091] The gate of M43 is electrically connected to the M-th stage driving output terminal GTM, the source of M43 is electrically connected to the M-th stage second input control node PDDM', and the drain of M43 is electrically connected to the low voltage terminal Vss;

[0092] The second driving unit 202 is electrically connected to the M-th first node PUM, the second clock signal line CLKB, the M+1-th level driving output terminal GTM+1, and the M-th level driving output terminal GTM, respectively, and is configured to control the M-th level driving output terminal GTM to output the M-th level driving signal according to the second clock signal provided by the second clock signal line CLKB under the control of the potential of the M-th first node PUM, and reset the M-th level driving signal under the control of the M+1-th level driving signal provided by the M+1-th level driving output terminal GTM+1;

[0093] The M+1th stage driving circuit includes a fifth input circuit, a sixth input circuit, a fifth input control circuit, a sixth input control circuit and a third driving unit 203;

[0094] The fifth input circuit includes a fifth first transistor M51, the sixth input circuit includes a sixth first transistor M61, the fifth input control circuit includes a fifth second transistor M52 and a fifth third transistor M53, and the sixth input control circuit includes a sixth second transistor M62 and a sixth third transistor M63;

[0095] The gate of M51 is electrically connected to the first input control node PDDM+1 of the M+1th stage, the source of M51 is electrically connected to the driving output terminal GTM of the Mth stage, and the drain of M51 is electrically connected to the first node PUM+1 of the M+1th stage;

[0096] The gate of M61 is electrically connected to the second input control node PDDM+1′ of the M+1th stage, the source of M61 is electrically connected to the driving output terminal GTM of the Mth stage, and the drain of M61 is electrically connected to the first node PUM+1 of the M+1th stage;

[0097] The gate of M52 and the source of M52 are both electrically connected to the first control voltage terminal VDD1, and the drain of M52 is electrically connected to the first input control node PDDM+1 of the M+1th stage;

[0098] The gate of M53 is electrically connected to the M+1-th stage driving output terminal GTM+1, the source of M53 is electrically connected to the M+1-th stage first input control node PDDM+1, and the drain of M53 is electrically connected to the low voltage terminal Vss;

[0099] The gate of M62 and the source of M62 are both electrically connected to the second control voltage terminal VDD2, and the drain of M62 is electrically connected to the second input control node PDDM+1′ of the M+1th stage;

[0100] The gate of M63 is electrically connected to the M+1-th stage driving output terminal GTM+1, the source of M63 is electrically connected to the M+1-th stage second input control node PDDM+1′, and the drain of M63 is electrically connected to the low voltage terminal Vss;

[0101] The third driving unit 203 is respectively connected to the M+1 first node PUM+1, the first clock signal line CLK, the M+2 stage driving output terminal ( Figure 2 The M+1st-level driving output terminal GTM+1 is electrically connected to the M+1th-level driving output terminal GTM+1, and is used for controlling the M+1th-level driving output terminal GTM+1 to output the M+1th-level driving signal according to the first clock signal provided by the first clock signal line CLK under the control of the potential of the M+1th first node PUM+1, and resetting the M+1th-level driving signal under the control of the M+2th-level driving signal provided by the M+2-level driving output terminal.

[0102] Figure 2 In at least one embodiment shown, during operation, VDD1 and VDD2 alternately output high voltage signals every predetermined time. The predetermined time may be, for example, 2 seconds or 3 seconds.

[0103] Figure 2 In at least one embodiment shown in FIG. 1 , when VDD1 outputs a high voltage signal and VDD2 outputs a low voltage signal,

[0104] When GTM-1 starts to output a high voltage signal, GTM outputs a low voltage signal, M32 opens, M33 closes, the potential of PDDM is high, M31 opens, the high voltage signal output by GTM-1 is written to PUM, and the potential of PUM changes from low to high.

[0105] When the GTM starts to output a high voltage signal, the potential of the M-1th level drive signal output by GTM-1 changes from high to low, M32 and M33 are both turned on, and the potential of PDDM is low; M31 is turned off. Therefore, although GTM-1 outputs a low voltage signal at this time, since M31 is turned off, the low voltage signal output by GTM-1 will not be written to PUM, that is, the potential of PUM remains high. This ensures that the potential of PUM remains high when the GTM outputs a high voltage signal, ensuring normal output of GTM;

[0106] When GTM-1 and GTM output low-voltage signals, M32 is turned on, M33 is turned off, the potential of PDDM is high, M31 is turned on, and the PUM and GTM-1 are connected. Since GTM-1 outputs a low-voltage signal, the potential of the PUM is pulled to a low level, achieving noise reduction for the PUM.

[0107] In at least one embodiment of the present invention, each row driving unit has a noise reduction function to reduce the noise of the first node of the row. At least one embodiment of the present invention increases the noise reduction efficiency of the first node by adding a first input circuit, a second input circuit, a first input control circuit, and a second input control circuit, while realizing the function of a starting unit.

[0108] In at least one embodiment of the present invention, a channel width-to-length ratio of the nth third transistor is greater than a channel width-to-length ratio of the nth second transistor.

[0109] Optionally, a ratio of a channel width-to-length ratio of the nth third transistor to a channel width-to-length ratio of the nth second transistor is greater than or equal to 1.5 and less than or equal to 3.5.

[0110] In at least one embodiment of the present invention, the first node control circuit is further electrically connected to the reset terminal, the second node, and the second voltage terminal, respectively, and is configured to control the connection or disconnection between the first node and the second voltage terminal under the control of a reset signal provided by the reset terminal, and to control the connection or disconnection between the first node and the second voltage terminal under the control of a potential of the second node;

[0111] The output circuit is also electrically connected to the output clock signal terminal, and is configured to provide the output clock signal provided by the output clock signal terminal to the driving output terminal under the control of the potential of the first node.

[0112] In a specific implementation, the first node control circuit can control the connection or disconnection between the first node and the second voltage terminal under the control of the reset signal and the potential of the second node, and the output circuit provides the output clock signal to the driving output terminal under the control of the potential of the first node.

[0113] Optionally, the second voltage terminal may be a low voltage terminal.

[0114] In at least one embodiment of the present invention, the driving circuit further includes a second node control circuit and an output reset circuit;

[0115] The second node control circuit is electrically connected to the first node and the second node respectively, and is used to control the potential of the second node under the control of the potential of the first node;

[0116] The output reset circuit is electrically connected to the second node, the driving output terminal and the third voltage terminal respectively, and is used to control the connection or disconnection between the driving output terminal and the third voltage terminal under the control of the potential of the second node.

[0117] In a specific implementation, the driving circuit may further include a second node control circuit and an output reset circuit; the second node control circuit controls the potential of the second node under the control of the potential of the first node; the output reset circuit controls the connection or disconnection between the driving output terminal and the third voltage terminal under the control of the potential of the second node.

[0118] Optionally, the third voltage terminal may be a low voltage terminal.

[0119] In at least one embodiment of the present invention, the second node control circuit includes a first second node control circuit and a second second node control circuit;

[0120] The first second node control circuit is electrically connected to the first control voltage terminal, the first node, the first second node, and the fourth voltage terminal, respectively, and is configured to control the potential of the first second node according to a first control voltage provided by the first control voltage terminal under the control of the potential of the first node;

[0121] The second second-node control circuit is electrically connected to the second control voltage terminal, the first node, the second second node, and the fourth voltage terminal, respectively, and is configured to control the potential of the second second node according to a second control voltage provided by the second control voltage terminal under the control of the potential of the first node;

[0122] The output reset circuit is electrically connected to the first second node, the second second node, the drive output terminal and the third voltage terminal, respectively, and is used to control the connection or disconnection between the drive output terminal and the third voltage terminal under the control of the potential of the first second node, and to control the connection or disconnection between the drive output terminal and the third voltage terminal under the control of the potential of the second second node.

[0123] Optionally, the driving circuit further includes a driving reset circuit and an energy storage circuit;

[0124] The driving reset circuit is electrically connected to the reset terminal, the driving output terminal and the third voltage terminal respectively, and is used to control the connection or disconnection between the driving output terminal and the third voltage terminal under the control of the reset signal provided by the reset terminal;

[0125] The energy storage circuit is electrically connected to the first node and the driving output terminal respectively, and is used for storing electric energy.

[0126] like Figure 3 As shown, in Figure 1 Based on at least one embodiment of the driving circuit shown, the first input control voltage terminal is the first control voltage terminal VDD1, and the second input control voltage terminal is the second control voltage terminal VDD2;

[0127] The first node control circuit 31 is further electrically connected to the reset terminal RST, the first second node PD1, the second second node PD2, and the second voltage terminal V2, respectively, and is configured to control the connection or disconnection between the first node PU and the second voltage terminal V2 under the control of a reset signal provided by the reset terminal RST, control the connection or disconnection between the first node PU and the second voltage terminal V2 under the control of the potential of the first second node PD1, and control the connection or disconnection between the first node PU and the second voltage terminal V2 under the control of the potential of the second second node PD2;

[0128] The output circuit 32 is further electrically connected to the output clock signal terminal CK, and is configured to provide the output clock signal provided by the output clock signal terminal CK to the driving output terminal GT under the control of the potential of the first node PU;

[0129] The driving circuit of at least one embodiment of the present invention further includes a first second node control circuit 41, a second second node control circuit 42, an output reset circuit 43, a driving reset circuit 44 and an energy storage circuit 40;

[0130] The first second-node control circuit 41 is electrically connected to the first control voltage terminal VDD1, the first node PU, the first second node PD1, and the fourth voltage terminal V4, respectively, and is configured to control the potential of the first second node PD1 according to a first control voltage provided by the first control voltage terminal VDD1 under the control of the potential of the first node PU;

[0131] The second second-node control circuit 42 is electrically connected to the second control voltage terminal VDD2, the first node PU, the second second node PD2, and the fourth voltage terminal V4, respectively, and is configured to control the potential of the second second node PD2 according to a second control voltage provided by the second control voltage terminal VDD2 under the control of the potential of the first node PU;

[0132] The output reset circuit 43 is electrically connected to the first second node PD1, the second second node PD2, the driving output terminal GT, and the third voltage terminal V3, respectively, and is used to control the connection or disconnection between the driving output terminal GT and the third voltage terminal V3 under the control of the potential of the first second node PD1, and to control the connection or disconnection between the driving output terminal GT and the third voltage terminal V3 under the control of the potential of the second second node PD2;

[0133] The driving reset circuit 44 is electrically connected to the reset terminal RST, the driving output terminal GT and the third voltage terminal V3 respectively, and is used to control the connection or disconnection between the driving output terminal GT and the third voltage terminal V3 under the control of the reset provided by the reset terminal RST;

[0134] The energy storage circuit 40 is electrically connected to the first node PU and the driving output terminal GT respectively, and is used for storing electrical energy.

[0135] Optionally, the fourth voltage terminal may be a low voltage terminal.

[0136] Optionally, N is equal to 2;

[0137] The first input control voltage terminal is a first control voltage terminal, and the second input control voltage terminal is a second control voltage terminal.

[0138] In a specific implementation, the first input control voltage terminal and the first control voltage terminal may be the same voltage terminal, and the second input control voltage terminal and the second control voltage terminal may be the same voltage terminal, so as to reduce the number of voltage terminals used.

[0139] In at least one embodiment of the present invention, the first second-node control circuit includes a first fourth transistor and a first fifth transistor, and the second second-node control circuit includes a second fourth transistor and a second fifth transistor;

[0140] The gate of the first fourth transistor and the first electrode of the first fourth transistor are electrically connected to the first control voltage terminal, and the second electrode of the first fourth transistor is electrically connected to the first second node;

[0141] The gate of the first fifth transistor is electrically connected to the first node, the first electrode of the first fifth transistor is electrically connected to the first second node, and the second electrode of the first fifth transistor is electrically connected to the fourth voltage terminal;

[0142] The gate of the second fourth transistor and the first electrode of the second fourth transistor are electrically connected to the second control voltage terminal, and the second electrode of the second fourth transistor is electrically connected to the second second node;

[0143] The gate of the second fifth transistor is electrically connected to the first node, the first electrode of the second fifth transistor is electrically connected to the second second node, and the second electrode of the second fifth transistor is electrically connected to the fourth voltage terminal.

[0144] Optionally, the nth input control circuit includes an nth second transistor and an nth third transistor;

[0145] The channel width-to-length ratio of each second transistor is greater than the channel width-to-length ratio of each fourth transistor, and the channel width-to-length ratio of each third transistor is greater than the channel width-to-length ratio of each fifth transistor.

[0146] In at least one embodiment of the present invention, a ratio of a channel width-to-length ratio of each of the second transistors to a channel width-to-length ratio of each of the fourth transistors is greater than or equal to 20 and less than or equal to 70;

[0147] A ratio of a channel width-to-length ratio of each third transistor to a channel width-to-length ratio of each fifth transistor is greater than or equal to 1.2 and less than or equal to 4.

[0148] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the driving circuit shown,

[0149] The first input circuit includes a first transistor M11;

[0150] The gate of M11 is electrically connected to the first input control node PDD, the source of M11 is electrically connected to the input terminal S1, and the drain of M11 is electrically connected to the first node PU;

[0151] The second input circuit includes a second first transistor M21;

[0152] The gate of M21 is electrically connected to the second input control node PDD', the source of M21 is electrically connected to the input terminal S1, and the drain of M21 is electrically connected to the first node PU;

[0153] The first input control circuit includes a first second transistor M12 and a first third transistor M13;

[0154] The gate of M12 and the source of M12 are electrically connected to the first control voltage terminal VDD1, and the drain of M12 is electrically connected to the first input control node PDD;

[0155] The gate of M13 is electrically connected to the driving output terminal GT, the source of M13 is electrically connected to the first input control node PDD, and the drain of M13 is electrically connected to the low voltage terminal Vss;

[0156] The second input control circuit includes a second second transistor M22 and a second third transistor M23;

[0157] The gate of M22 and the source of M22 are electrically connected to the second control voltage terminal VDD2, and the drain of M22 is electrically connected to the second input control node PDD';

[0158] The gate of M23 is electrically connected to the driving output terminal GT, the source of M23 is electrically connected to the second input control node PDD', and the drain of M23 is electrically connected to the low voltage terminal Vss;

[0159] The first second-node control circuit includes a first fourth transistor M14 and a first fifth transistor M15, and the second second-node control circuit includes a second fourth transistor M24 and a second fifth transistor M25;

[0160] The gate of M14 and the source of M14 are electrically connected to the first control voltage terminal VDD1, and the drain of M14 is electrically connected to the first second node PD1;

[0161] The gate of M15 is electrically connected to the first node PU, the source of M15 is electrically connected to the first second node PD1, and the drain of M15 is electrically connected to the low voltage terminal Vss;

[0162] The gate of M24 and the source of M24 are electrically connected to the second control voltage terminal VDD2, and the drain of M24 is electrically connected to the second second node PD2;

[0163] The gate of M25 is electrically connected to the first node PU, the source of M25 is electrically connected to the second node PD2, and the drain of M25 is electrically connected to the low voltage terminal Vss;

[0164] The first node control circuit includes a sixth transistor M6, a seventh transistor M7 and an eighth transistor M8;

[0165] The gate of M6 is electrically connected to the reset terminal RST, the source of M6 is electrically connected to the first node PU, and the drain of M6 is electrically connected to the low voltage terminal Vss;

[0166] The gate of M7 is electrically connected to the first second node PD1, the source of M7 is electrically connected to the first node PU, and the drain of M7 is electrically connected to the low voltage terminal Vss;

[0167] The gate of M8 is electrically connected to the second second node PD2, the source of M8 is electrically connected to the first node PU, and the drain of M8 is electrically connected to the low voltage terminal Vss;

[0168] The output circuit includes a ninth transistor M9;

[0169] The gate of M9 is electrically connected to the first node PU, the source of M9 is electrically connected to the output clock signal terminal CK, and the drain of M9 is electrically connected to the driving output terminal GT;

[0170] The output reset circuit includes a tenth transistor M10 and an eleventh transistor T11;

[0171] The gate of M10 is electrically connected to the first second node PD1, the source of M10 is electrically connected to the driving output terminal GT, and the drain of M10 is electrically connected to the low voltage terminal Vss;

[0172] The gate of T11 is electrically connected to the second second node PD2, the source of T11 is electrically connected to the driving output terminal GT, and the drain of T11 is electrically connected to the low voltage terminal Vss;

[0173] The driving reset circuit includes a twelfth transistor T12;

[0174] The gate of T12 is electrically connected to the reset terminal RST, the source of T12 is electrically connected to the driving output terminal GT, and the drain of T12 is electrically connected to the low voltage terminal Vss;

[0175] The energy storage circuit includes a storage capacitor Cst;

[0176] A first end of Cst is electrically connected to the first node PU, and a second end of Cst is electrically connected to the driving output end.

[0177] exist Figure 4 In at least one embodiment shown, all transistors are n-type transistors.

[0178] The present invention Figure 4 In at least one embodiment shown, when GT outputs a high voltage signal, M12 and M13 are both turned on, the potential of PDD is low, M22 and M23 are both turned on, and the potential of PDD' is low. Therefore, the conduction capability of M13 needs to be stronger than that of M12, and the conduction capability of M23 needs to be stronger than that of M22.

[0179] exist Figure 4 In at least one embodiment shown, the channel width-to-length ratio of M13 is greater than that of M12, and the channel width-to-length ratio of M23 is greater than that of M22.

[0180] A ratio of a channel width-to-length ratio of M13 to a channel width-to-length ratio of M12 is greater than or equal to 1.5 and less than or equal to 3.5, and a ratio of a channel width-to-length ratio of M23 to a channel width-to-length ratio of M22 is greater than or equal to 1.5 and less than or equal to 3.5;

[0181] The channel width of M12 may be greater than or equal to 50 μm and less than or equal to 100 μm, and the channel width of M13 may be greater than or equal to 100 μm and less than or equal to 200 μm;

[0182] The channel width of M22 may be greater than or equal to 50 μm and less than or equal to 100 μm, and the channel width of M23 may be greater than or equal to 100 μm and less than or equal to 200 μm;

[0183] The channel length of M12, the channel length of M22, the channel length of M13, and the channel length of M23 may be 6 μm.

[0184] exist Figure 4 In at least one embodiment shown, the conduction capability of M15 needs to be greater than that of M14, and the conduction capability of M25 needs to be greater than that of M24; for example, the channel width-to-length ratio of M15 can be 70 / 6, and the channel width-to-length ratio of M14 can be 5 / 18;

[0185] The channel width-to-length ratio of M12 is greater than that of M14, the channel width-to-length ratio of M22 is greater than that of M24, the channel width-to-length ratio of M13 is greater than that of M15, and the channel width-to-length ratio of M23 is greater than that of M25;

[0186] The ratio of the channel width-to-length ratio of M12 to the channel width-to-length ratio of M14 may be greater than or equal to 20 and less than or equal to 70; the ratio of the channel width-to-length ratio of M22 to the channel width-to-length ratio of M24 may be greater than or equal to 20 and less than or equal to 70;

[0187] The ratio of the channel width-to-length ratio of M13 to the channel width-to-length ratio of M15 may be greater than or equal to 1.2 and less than or equal to 4; the ratio of the channel width-to-length ratio of M23 to the channel width-to-length ratio of M25 may be greater than or equal to 1.2 and less than or equal to 4.

[0188] In the present invention Figure 4 In at least one embodiment shown, M11, M21, M12, M13, M22, and M23 may serve as starting units and perform noise reduction on the PU.

[0189] In the present invention Figure 4 In at least one embodiment shown, the source of M12 is electrically connected to VDD1, the source of M22 is electrically connected to VDD2, the phase of the first control voltage provided by VDD1 is opposite to the phase of the second control voltage provided by VDD2, and when VDD1 outputs a high voltage signal, M11 and the inverter composed of M12 and M13 operate, and when VDD2 outputs a high voltage signal, M21 and the inverter composed of M22 and M23 operate, thereby reducing the stress of the transistors included in the input circuit and the stress effect of the transistors included in the input control circuit.

[0190] In the present invention Figure 4In at least one embodiment shown, M14 and M15 form a group of inverters to control M7 and M10; M24 and M25 form a group of inverters to control M8 and T11 to reduce noise on the first node and the drive output end of the row; M6 and T12, under the control of the reset signal, pull down the potential of the first node of the row and the potential of the drive output end; M9 is an output transistor, and when the potential of PU is a high voltage and CK also outputs a high voltage signal, GT outputs a high voltage signal.

[0191] like Figure 5 As shown, in Figure 2 Based on at least one embodiment shown,

[0192] The first driving unit may include a first fourth transistor M14, a first fifth transistor M15, a second fourth transistor M24, a second fifth transistor M25, a first sixth transistor M16, a first seventh transistor M17, a first eighth transistor M18, a first ninth transistor M19, a first tenth transistor M110, a first eleventh transistor M111, a first twelfth transistor M112 and a first storage capacitor Cst1;

[0193] The source of M11 is electrically connected to the M-2 stage driver output terminal GTM-2;

[0194] The gate of M14 and the source of M14 are electrically connected to the first control voltage terminal VDD1, and the drain of M14 is electrically connected to the first second node PD1-M-1 of the M-1th stage;

[0195] The gate of M15 is electrically connected to the first node PU, the source of M15 is electrically connected to the first second node PD1-M-1 of the M-1th level, and the drain of M15 is electrically connected to the low voltage terminal Vss;

[0196] The gate of M24 and the source of M24 are electrically connected to the second control voltage terminal VDD2, and the drain of M24 is electrically connected to the second second node PD2-M-1 of the M-1th stage;

[0197] The gate of M25 is electrically connected to the first node PU, the source of M25 is electrically connected to the second second node PD2-M-1 of the M-1th level, and the drain of M25 is electrically connected to the low voltage terminal Vss;

[0198] The gate of M16 is electrically connected to the M-th stage driving output terminal GTM, the source of M16 is electrically connected to the M-1-th stage first node PUM-1, and the drain of M16 is electrically connected to the low voltage terminal Vss;

[0199] The gate of M17 is electrically connected to the first second node PD1-M-1 of the M-1th stage, the source of M17 is electrically connected to the first node PUM-1 of the M-1th stage, and the drain of M17 is electrically connected to the low voltage terminal Vss;

[0200] The gate of M18 is electrically connected to the second second node PD2-M-1 of the M-1th stage, the source of M18 is electrically connected to the first node PUM-1 of the M-1th stage, and the drain of M18 is electrically connected to the low voltage terminal Vss;

[0201] The gate of M19 is electrically connected to the first node PUM-1 of the M-1 stage, the source of M19 is electrically connected to the first clock signal line CLK, and the drain of M19 is electrically connected to the driving output terminal GTM-1 of the M-1 stage;

[0202] The gate of M110 is electrically connected to the first second node PD1-M-1 of the M-1th stage, the source of M110 is electrically connected to the M-1th stage driving output terminal GTM-1, and the drain of M110 is electrically connected to the low voltage terminal Vss;

[0203] The gate of M111 is electrically connected to the second second node PD2-M-1 of the M-1th stage, the source of M111 is electrically connected to the M-1th stage driving output terminal GTM-1, and the drain of M111 is electrically connected to the low voltage terminal Vss;

[0204] The gate of M112 is electrically connected to the M-th level driving output terminal GTM, the source of M112 is electrically connected to the M-1-th level driving output terminal GTM-1, and the drain of M112 is electrically connected to the low voltage terminal Vss;

[0205] The first end of Cst1 is electrically connected to the first node PUM-1 of the M-1th stage, and the second end of Cst1 is electrically connected to the driving output terminal GTM-1 of the M-1th stage;

[0206] The second driving unit may include a third fourth transistor M34, a third fifth transistor M35, a fourth fourth transistor M44, a fourth fifth transistor M45, a second sixth transistor M26, a second seventh transistor M27, a second eighth transistor M28, a second ninth transistor M29, a second tenth transistor M210, a second eleventh transistor M211, a second twelfth transistor M212 and a second storage capacitor Cst2;

[0207] The gate of M34 and the source of M34 are electrically connected to the first control voltage terminal VDD1, and the drain of M34 is electrically connected to the first second node PD1-M of the Mth stage;

[0208] The gate of M35 is electrically connected to the first node PUM of the M-th stage, the source of M35 is electrically connected to the first second node PD1-M of the M-th stage, and the drain of M35 is electrically connected to the low voltage terminal Vss;

[0209] The gate of M44 and the source of M44 are electrically connected to the second control voltage terminal VDD2, and the drain of M44 is electrically connected to the second second node PD2-M of the Mth stage;

[0210] The gate of M45 is electrically connected to the first node PUM of the M-th stage, the source of M45 is electrically connected to the second second node PD2-M of the M-th stage, and the drain of M45 is electrically connected to the low voltage terminal Vss;

[0211] The gate of M26 is electrically connected to the M+1-th stage driving output terminal GTM+1, the source of M26 is electrically connected to the M-th stage first node PUM, and the drain of M26 is electrically connected to the low voltage terminal Vss;

[0212] The gate of M27 is electrically connected to the first second node PD1-M of the Mth stage, the source of M27 is electrically connected to the first node PUM of the Mth stage, and the drain of M27 is electrically connected to the low voltage terminal Vss;

[0213] The gate of M28 is electrically connected to the second second node PD2-M of the M-th stage, the source of M28 is electrically connected to the first node PUM of the M-th stage, and the drain of M28 is electrically connected to the low voltage terminal Vss;

[0214] The gate of M29 is electrically connected to the first node PUM of the Mth stage, the source of M29 is electrically connected to the second clock signal line CLKB, and the drain of M29 is electrically connected to the driving output terminal GTM of the Mth stage;

[0215] The gate of M210 is electrically connected to the first second node PD1-M of the Mth stage, the source of M210 is electrically connected to the Mth stage driving output terminal GTM, and the drain of M210 is electrically connected to the low voltage terminal Vss;

[0216] The gate of M211 is electrically connected to the second second node PD2-M of the Mth stage, the source of M211 is electrically connected to the Mth stage driving output terminal GTM, and the drain of M211 is electrically connected to the low voltage terminal Vss;

[0217] The gate of M212 is electrically connected to the M+1-th level driving output terminal GTM+1, the source of M212 is electrically connected to the M-th level driving output terminal GTM, and the drain of M212 is electrically connected to the low voltage terminal Vss;

[0218] The first end of Cst2 is electrically connected to the M-th stage first node PUM, and the second end of Cst2 is electrically connected to the M-th stage driving output terminal GTM;

[0219] The third driving unit may include a fifth fourth transistor M54, a fifth fifth transistor M55, a sixth fourth transistor M64, a sixth fifth transistor M65, a third sixth transistor M36, a third seventh transistor M37, a third eighth transistor M38, a third ninth transistor M39, a third tenth transistor M310, a third eleventh transistor M311, a third twelfth transistor M312 and a third storage capacitor Cst3;

[0220] The gate of M54 and the source of M54 are electrically connected to the first control voltage terminal VDD1, and the drain of M54 is electrically connected to the first second node PD1-M+1 of the M+1th stage;

[0221] The gate of M55 is electrically connected to the first node PUM+1 of the M+1th stage, the source of M55 is electrically connected to the first second node PD1-M+1 of the M+1th stage, and the drain of M55 is electrically connected to the low voltage terminal Vss;

[0222] The gate of M64 and the source of M64 are electrically connected to the second control voltage terminal VDD2, and the drain of M64 is electrically connected to the second second node PD2-M+1 of the M+1th stage;

[0223] The gate of M65 is electrically connected to the first node PUM+1 of the M+1th stage, the source of M65 is electrically connected to the second second node PD2-M+1 of the M+1th stage, and the drain of M65 is electrically connected to the low voltage terminal Vss;

[0224] The gate of M36 is electrically connected to the M+2-th stage driving output terminal GTM+2, the source of M36 is electrically connected to the M+1-th stage first node PUM+1, and the drain of M36 is electrically connected to the low voltage terminal Vss;

[0225] The gate of M37 is electrically connected to the first second node PD1-M+1 of the M+1th stage, the source of M37 is electrically connected to the first node PUM+1 of the M+1th stage, and the drain of M37 is electrically connected to the low voltage terminal Vss;

[0226] The gate of M38 is electrically connected to the second second node PD2-M+1 of the M+1th stage, the source of M38 is electrically connected to the first node PUM+1 of the M+1th stage, and the drain of M38 is electrically connected to the low voltage terminal Vss;

[0227] The gate of M39 is electrically connected to the first node PUM+1 of the M+1 stage, the source of M39 is electrically connected to the first clock signal line CLK, and the drain of M39 is electrically connected to the driving output terminal GTM+1 of the M+1 stage;

[0228] The gate of M310 is electrically connected to the first second node PD1-M+1 of the M+1th stage, the source of M310 is electrically connected to the M+1th stage driving output terminal GTM+1, and the drain of M310 is electrically connected to the low voltage terminal Vss;

[0229] The gate of M311 is electrically connected to the second second node PD2-M+1 of the M+1th stage, the source of M311 is electrically connected to the M+1th stage driving output terminal GTM+1, and the drain of M311 is electrically connected to the low voltage terminal Vss;

[0230] The gate of M312 is electrically connected to the M+2-th level driving output terminal GTM+2, the source of M312 is electrically connected to the M+1-th level driving output terminal GTM+1, and the drain of M312 is electrically connected to the low voltage terminal Vss;

[0231] A first end of Cst3 is electrically connected to the M+1-th stage first node PUM+1, and a second end of Cst3 is electrically connected to the M+1-th stage driving output terminal GTM+1.

[0232] exist Figure 5 In at least one embodiment shown, all transistors are n-type transistors.

[0233] The present invention Figure 5 In at least one embodiment shown, when VDD1 provides a high voltage signal and VDD2 provides a low voltage signal,

[0234] When GTM-2 outputs a high-voltage signal, the PUM potential is low, the GTM outputs a low-voltage signal, M32 is turned on, M33 is turned off, the PDDM potential is high, M31 is turned on, and the PUM and GTM-1 are connected. Since GTM-1 outputs a low-voltage signal at this time, noise reduction can be performed on the PUM potential. In addition, M34 is turned on, M35 is turned off, the PD1-M potential is high, and M27 is turned on, reducing noise on the PUM potential. Therefore, the PUM potential is subject to dual noise reduction effects from both the current row and the previous row.

[0235] When GTM-1 outputs a high-voltage signal, GTM outputs a low-voltage signal, M32 opens, M33 closes, the PDDM voltage reaches a high voltage, M31 opens, and the PUM and GTM-1 are connected. GTM-1 charges the PUM through its high-voltage signal. Because the PUM voltage is high, the PD1-M voltage reaches a low voltage under the action of M34 and M35, and no noise reduction is performed on the PUM voltage.

[0236] When the GTM outputs a high-voltage signal, M112 opens, GTM-1 provides a low-voltage signal, and under the action of M34 and M35, M27 and M210 close, and no noise reduction is performed on the PUM. At the same time, under the action of M32 and M33, M31 closes, thereby disconnecting GTM-1 from the PUM, ensuring that the PUM potential is high and the GTM can output normally.

[0237] When GTM+1 outputs a high-voltage signal, M26 and M212 are turned on, and the potential of the PUM and the potential of the M-th level drive signal output by the GTM are pulled low. Under the action of M34 and M35, the noise of the PUM is reduced. At the same time, under the action of M32 and M33, M34 is turned on, the PUM is connected to GTM-1, and GTM-1 outputs a low-voltage signal, synchronously reducing the noise of the PUM.

[0238] In the present invention Figure 5 In at least one embodiment shown, the potential of PDDM is given by M32 and M33, and controls M31; the potential of PDDM' is given by M42 and M43, and controls M41;

[0239] When GTM outputs a high voltage signal, the potentials of PDD and PDD' are low voltage, M31 and M41 are closed, so that the potential of PUM is not affected by the low level of GTM-1, ensuring the normal output of GTM;

[0240] When the GTM outputs a low-voltage signal and VDD1 provides a high-voltage signal, the PDDM potential is high, M31 is open, and the PUM and GTM-1 are connected. When the GTM-1 outputs a high-voltage signal, the PUM is charged; when the GTM-1 outputs a low-voltage signal, the PUM is de-noised.

[0241] When GTM outputs a low-voltage signal and VDD2 supplies a high-voltage signal, the PDDM' potential is high, M4 is open, and the PUM and GTM-1 are connected. When GTM-1 outputs a high-voltage signal, the PUM is charged. When GTM-1 outputs a low-voltage signal, the PUM is noise-reduced.

[0242] Figure 6 yes Figure 5 The working timing diagram of at least one embodiment is shown.

[0243] In at least one embodiment of the present invention, the driving output end of each level of driving circuit not only outputs a gate voltage to the corresponding row of pixel circuits, but also outputs a reset signal to the previous level of driving circuit and provides an input signal to the next level of driving circuit, thereby achieving row-by-row voltage transfer.

[0244] The potential of PDDM is given by M32, M33, M42 and M43, and controls M31 and M41. When GTM outputs a high voltage signal and VDD1 outputs a high voltage signal, the potential of PDDM is low voltage and M31 is closed. Therefore, the potential of PUM is not affected by the low level of GTM-1, ensuring the normal output of GTM.

[0245] When GTM outputs a low voltage signal and VDD1 outputs a high voltage signal, the potential of PDDM is high, M31 is open, and the PUM and GTM-1 are connected. When GTM-1 outputs a high voltage signal, the PUM is charged; when GTM-1 outputs a low voltage signal, the PUM is de-noised.

[0246] The phase of the first control voltage provided by VDD1 is opposite to the phase of the second control voltage provided by VDD2, alternating between high and low levels, thereby ensuring that only one group of M31 / M32 / M33 and M41 / M42 / M43 is working while the other group is resting. The working time of each group of transistors is 50% of the existing one, thereby improving the lifespan of each group of transistors. There is no strict requirement for the working time of VDD1 and VDD2, for example, they work alternately for 50 frames and 100 frames.

[0247] like Figure 6 As shown, the present invention Figure 5 At least one embodiment shown, when in operation, performs noise reduction for the PUM in the first stage S1 and the fourth stage S4;

[0248] In the second stage S2, the potential of PUM is precharged by the M-1th level driving signal provided by GTM-1;

[0249] In the third stage S3, the potential of PUM is bootstrapped by Cst2.

[0250] The driving method according to an embodiment of the present invention is applied to the above-mentioned driving circuit, wherein a display cycle includes an output phase; the driving method includes:

[0251] In the output stage, the driving output terminal provides a valid driving signal, the nth input control circuit controls the potential of the nth input control node to be an invalid potential, and the nth input circuit, under the control of the potential of the nth input control node, controls the input terminal and the first node to be disconnected so that the potential of the first node is not affected by the input terminal.

[0252] In at least one embodiment of the present invention, when the transistor whose gate of the pixel circuit is electrically connected to the driving output terminal is an n-type transistor, the effective driving signal is a high voltage signal;

[0253] When the transistor whose gate of the pixel circuit is electrically connected to the driving output terminal is a p-type transistor, the effective driving signal is a low voltage signal;

[0254] When the transistor included in the input circuit is an n-type transistor, the inactive potential is a high potential; when the transistor included in the input circuit is a p-type transistor, the inactive potential is a low potential.

[0255] The driving method according to at least one embodiment of the present invention further includes:

[0256] During a time period other than the output phase included in the display cycle, when the driving output terminal provides an invalid driving signal, the nth input control circuit controls the potential of the nth input control node to be a valid potential, and the nth input circuit controls the input terminal to be connected to the first node under the control of the potential of the nth input control node;

[0257] When the input terminal provides a valid voltage signal, the first node can be charged; when the input terminal provides an invalid voltage signal, the first node can be noise-reduced.

[0258] In at least one embodiment of the present invention, when the transistor included in the input circuit is an n-type transistor, the effective voltage signal is a high voltage signal, and the invalid voltage signal is a low voltage signal; when the transistor included in the input circuit is a p-type transistor, the effective voltage signal is a low voltage signal, and the invalid voltage signal is a high voltage signal.

[0259] The driving module described in the embodiment of the present invention includes multiple stages of the above-mentioned driving circuit; the driving circuit includes an input terminal and a reset terminal;

[0260] The input terminal of the m-th driving circuit is electrically connected to the driving output terminal of the ma-th driving circuit, and the reset terminal of the m-th driving circuit is electrically connected to the driving output terminal of the m+a-th driving circuit;

[0261] m is a positive integer, and a is a positive integer.

[0262] The display device according to the embodiment of the present invention includes the above-mentioned driving circuit.

[0263] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A driving circuit, characterized in that: The device comprises a driving output terminal, N input circuits, N input control circuits, a first node control circuit and an output circuit, wherein N is an integer greater than 1; and n is a positive integer less than or equal to N. The nth input circuit is electrically connected to the first node, the input terminal, and the nth input control node, respectively, and is configured to write the input signal provided by the input terminal into the first node under the control of the potential of the nth input control node; an nth input control circuit electrically connected to the driving output terminal, the nth input control node, and the nth input control voltage terminal, respectively, for controlling the potential of the nth input control node according to an nth input control voltage provided by the nth input control voltage terminal under the control of a driving signal provided by the driving output terminal; The first node control circuit is electrically connected to the first node and is used to control the potential of the first node; The output circuit is electrically connected to the first node and the driving output end respectively, and is used to control the driving output end to provide a driving signal under the control of the potential of the first node.

2. The driving circuit according to claim 1, wherein: The nth input circuit includes an nth first transistor; The gate of the nth first transistor is electrically connected to the nth input control node, the first electrode of the nth first transistor is electrically connected to the input end, and the second electrode of the nth first transistor is electrically connected to the first node.

3. The driving circuit according to claim 1, wherein: The nth input control circuit includes an nth second transistor and an nth third transistor; The gate of the nth second transistor and the first electrode of the nth second transistor are electrically connected to the nth input control voltage terminal, and the second electrode of the nth second transistor is electrically connected to the nth input control node; The gate of the nth third transistor is electrically connected to the driving output terminal, the first electrode of the nth third transistor is electrically connected to the nth input control node, and the second electrode of the nth third transistor is electrically connected to the first voltage terminal.

4. The driving circuit according to claim 3, wherein: The channel width-to-length ratio of the nth third transistor is greater than the channel width-to-length ratio of the nth second transistor.

5. The driving circuit according to claim 4, wherein: A ratio of a channel width-to-length ratio of the nth third transistor to a channel width-to-length ratio of the nth second transistor is greater than or equal to 1.5 and less than or equal to 3.

5.

6. The driving circuit according to claim 1, wherein: The first node control circuit is further electrically connected to the reset terminal, the second node, and the second voltage terminal, respectively, and is configured to control the connection or disconnection between the first node and the second voltage terminal under the control of a reset signal provided by the reset terminal, and to control the connection or disconnection between the first node and the second voltage terminal under the control of the potential of the second node; The output circuit is also electrically connected to the output clock signal terminal, and is configured to provide the output clock signal provided by the output clock signal terminal to the driving output terminal under the control of the potential of the first node.

7. The driving circuit according to any one of claims 1 to 6, wherein: The driving circuit further includes a second node control circuit and an output reset circuit; The second node control circuit is electrically connected to the first node and the second node respectively, and is used to control the potential of the second node under the control of the potential of the first node; The output reset circuit is electrically connected to the second node, the driving output terminal and the third voltage terminal respectively, and is used to control the connection or disconnection between the driving output terminal and the third voltage terminal under the control of the potential of the second node.

8. The driving circuit according to claim 7, wherein: The second node control circuit includes a first second node control circuit and a second second node control circuit; The first second node control circuit is electrically connected to the first control voltage terminal, the first node, the first second node, and the fourth voltage terminal, respectively, and is configured to control the potential of the first second node according to a first control voltage provided by the first control voltage terminal under the control of the potential of the first node; The second second-node control circuit is electrically connected to the second control voltage terminal, the first node, the second second node, and the fourth voltage terminal, respectively, and is configured to control the potential of the second second node according to a second control voltage provided by the second control voltage terminal under the control of the potential of the first node; The output reset circuit is electrically connected to the first second node, the second second node, the drive output terminal and the third voltage terminal, respectively, and is used to control the connection or disconnection between the drive output terminal and the third voltage terminal under the control of the potential of the first second node, and to control the connection or disconnection between the drive output terminal and the third voltage terminal under the control of the potential of the second second node.

9. The driving circuit according to claim 8, wherein: N is equal to 2; The first input control voltage terminal is a first control voltage terminal, and the second input control voltage terminal is a second control voltage terminal.

10. The driving circuit according to claim 8, wherein: The first second-node control circuit includes a first fourth transistor and a first fifth transistor, and the second second-node control circuit includes a second fourth transistor and a second fifth transistor; The gate of the first fourth transistor and the first electrode of the first fourth transistor are electrically connected to the first control voltage terminal, and the second electrode of the first fourth transistor is electrically connected to the first second node; The gate of the first fifth transistor is electrically connected to the first node, the first electrode of the first fifth transistor is electrically connected to the first second node, and the second electrode of the first fifth transistor is electrically connected to the fourth voltage terminal; The gate of the second fourth transistor and the first electrode of the second fourth transistor are electrically connected to the second control voltage terminal, and the second electrode of the second fourth transistor is electrically connected to the second second node; The gate of the second fifth transistor is electrically connected to the first node, the first electrode of the second fifth transistor is electrically connected to the second second node, and the second electrode of the second fifth transistor is electrically connected to the fourth voltage terminal.

11. The driving circuit according to claim 10, wherein: The nth input control circuit includes an nth second transistor and an nth third transistor; The channel width-to-length ratio of each second transistor is greater than the channel width-to-length ratio of each fourth transistor, and the channel width-to-length ratio of each third transistor is greater than the channel width-to-length ratio of each fifth transistor.

12. The driving circuit according to claim 11, wherein: a ratio of a channel width-to-length ratio of each of the second transistors to a channel width-to-length ratio of each of the fourth transistors is greater than or equal to 20 and less than or equal to 70; A ratio of a channel width-to-length ratio of each third transistor to a channel width-to-length ratio of each fifth transistor is greater than or equal to 1.2 and less than or equal to 4.

13. A driving method, applied to the driving circuit according to any one of claims 1 to 12, characterized in that: The display cycle includes an output phase; the driving method includes: In the output stage, the driving output terminal provides a valid driving signal, the nth input control circuit controls the potential of the nth input control node to be an invalid potential, and the nth input circuit controls the input terminal to be disconnected from the first node under the control of the potential of the nth input control node.

14. The driving method according to claim 13, wherein: Also includes: In a time period other than the output phase included in the display cycle, when the driving output terminal provides an invalid driving signal, the nth input control circuit controls the potential of the nth input control node to be a valid potential, and the nth input circuit controls the input terminal to be connected to the first node under the control of the potential of the nth input control node.

15. A driving module, characterized in that: A drive circuit comprising multiple stages according to any one of claims 1 to 12; the drive circuit comprising an input terminal and a reset terminal; The input terminal of the m-th driving circuit is electrically connected to the driving output terminal of the ma-th driving circuit, and the reset terminal of the m-th driving circuit is electrically connected to the driving output terminal of the m+a-th driving circuit; m is a positive integer, and a is a positive integer.

16. A display device, characterized in that: The drive circuit comprises the drive circuit according to any one of claims 1 to 12.

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