Enhanced sense amplifier architecture

Abstract

The invention relates to an enhanced sense amplifier architecture. The architecture of p-type transistors in a sense amplifier may be modified to support greater accuracy of voltage sensing operations in a memory system. The shape and / or positioning of one or more channel portions of a p-type transistor relative to one or more gate portions of the p-type transistor may increase the effective channel length of the p-type transistor, which may support increased accuracy of cell voltage sensing. In some examples, a channel portion of the p-type transistor may have a non-rectangular shape to support a relatively long electrical path between a source and a drain of the p-type transistor. In some examples, a shape of a gate portion of the p-type transistor may have a non-rectangular shape to support a relatively long path between the source and the drain.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 18 / 784,822, filed by Vimercati et al. on July 25, 2024, entitled “ENHANCED SENSE AMPLIFIER ARCHITECTURE,” and U.S. patent application No. 63 / 553,036, filed by Vimercati et al. on February 13, 2024, entitled “ENHANCED SENSE AMPLIFIER ARCHITECTURE,” each of which is assigned to its assignee and the entire contents of each of which are expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to enhanced sense amplifier architectures. Background Art

[0004] Memory devices are used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by a logic 1 or a logic 0. In some examples, a single memory cell can support more than two states, any of which can be stored by the memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to a memory cell. To access stored information, a memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell. Summary of the Invention

[0005] A memory system is described. The memory system may include: a memory cell; a digit line coupled to the memory cell; and a sense amplifier coupled to the digit line, the sense amplifier comprising: an n-type transistor; and a p-type transistor comprising: a source; a drain; a channel positioned between the source and the drain, the channel comprising a dopant material configured to facilitate carrier flow between the source and the drain, the channel comprising: a first portion coupled to the source, the first portion comprising a first edge, a second edge opposite the first edge, a third edge extending between the first edge and the second edge, and a fourth edge opposite the third edge; and a second portion coupled to the drain, the second portion comprising: comprising a fifth edge, a sixth edge opposite to the fifth edge, a seventh edge extending between the fifth edge and the sixth edge, and an eighth edge opposite to the seventh edge, wherein the fifth edge of the second portion is offset from the first edge of the first portion by a first distance, wherein the sixth edge of the second portion is offset from the second edge of the first portion by a second distance, wherein the seventh edge of the second portion is offset from the third edge of the first portion by a third distance, and wherein a portion of the fourth edge of the first portion contacts a portion of the seventh edge of the second portion; and a gate positioned above the channel and configured to control the amount of the carriers flowing through the channel.

[0006] A memory system is described. The memory system may include: a memory cell; a digit line coupled to the memory cell; and a sense amplifier coupled to the digit line, the sense amplifier comprising: an n-type transistor; and a p-type transistor comprising: a source; a drain; a channel positioned between the source and the drain, the channel comprising a doped material configured to facilitate carrier flow between the source and the drain, the channel comprising a first edge, a second edge opposite the first edge, a third edge extending between the first edge and the second edge, and a fourth edge opposite the third edge; and a gate positioned above the channel and configured to control the amount of the carriers flowing through the channel, the gate comprising: a first portion comprising a fifth edge, a gate opposite the fifth edge, a gate extending between the first edge and the second edge, and a gate extending between the first edge and the second edge. a sixth edge of the first portion, a seventh edge extending between the fifth edge and the sixth edge, and an eighth edge opposite to the seventh edge, wherein the sixth edge of the first portion is aligned with a portion of the second edge, wherein the seventh edge of the first portion is offset from the third edge by a first distance, and wherein the eighth edge of the first portion is offset from the fourth edge by a second distance; and a second portion comprising a ninth edge, a tenth edge opposite to the ninth edge, an eleventh edge extending between the ninth edge and the tenth edge, and a twelfth edge opposite to the eleventh edge, wherein the tenth edge of the second portion contacts a portion of the fifth edge of the first portion, and wherein the ninth edge of the second portion is offset from the first edge.

[0007] A memory system is described. The memory system may include: a memory cell; a digit line coupled to the memory cell; and a sense amplifier coupled to the digit line, the sense amplifier comprising: an n-type transistor; and a p-type transistor comprising: a source; a drain; a channel positioned between the source and the drain, the channel comprising a dopant material configured to facilitate carrier flow between the source and the drain, the channel comprising: a first portion coupled to the source, the first portion comprising a first edge, a second edge opposite the first edge, a third edge extending between the first edge and the second edge, and a third edge opposite the third edge. four edges; a second portion coupled to the drain, the second portion including a fifth edge, a sixth edge opposite to the fifth edge, a seventh edge extending between the fifth edge and the sixth edge, and an eighth edge opposite to the seventh edge; and a third portion including a ninth edge, a tenth edge opposite to the ninth edge, an eleventh edge extending between the ninth edge and the tenth edge, and a twelfth edge opposite to the eleventh edge, wherein the eleventh edge of the third portion extends from the third edge of the first portion in a first direction, and the twelfth edge of the third portion extends from the third edge of the first portion in the first direction. the eighth edge of the second portion extending; and a gate positioned above the channel and configured to control the amount of the carriers flowing through the channel, the gate comprising: a fourth portion including a thirteenth edge, a fourteenth edge opposite the thirteenth edge, a fifteenth edge extending between the thirteenth and fourteenth edges, and a sixteenth edge opposite the fifteenth edge, wherein the thirteenth edge of the fourth portion is offset from the first edge of the first portion by a first distance, and wherein the fifteenth edge of the fourth portion is offset from the third edge of the first portion by a second distance, and the sixteenth edge of the fourth portion is offset from the third edge of the first portion by a third distance; a fifth portion including a seventeenth edge, an eighteenth edge opposite the seventeenth edge, a nineteenth edge extending between the seventeenth and eighteenth edges, and a twentieth edge opposite the nineteenth edge; and a sixth portion including a twenty-first edge, a twenty-second edge opposite the twenty-first edge, a twenty-third edge extending between the twenty-first and twenty-second edges, and a twenty-fourth edge opposite the twenty-third edge, wherein a portion of the twenty-second edge of the sixth portion is aligned with the twelfth edge of the third portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 An example of an architecture supporting an enhanced sense amplifier architecture according to examples disclosed herein is shown.

[0009] Figure 2 Shown is an example of a circuit diagram supporting an enhanced sense amplifier architecture according to examples disclosed herein.

[0010] Figure 3 An example of a sense amplifier supporting an enhanced sense amplifier architecture according to examples disclosed herein is shown.

[0011] Figure 4A and 4B Examples of transistor structures and sense amplifier architectures supporting enhanced sense amplifier architectures according to examples disclosed herein are shown.

[0012] Figures 5 to 8 An example of a sense amplifier architecture supporting an enhanced sense amplifier architecture according to examples disclosed herein is shown. DETAILED DESCRIPTION

[0013] In some memory systems, a sense amplifier can be used to determine the state stored by a memory cell. The sense amplifier can be coupled to an access line (e.g., a bit line, a word line) coupled to the memory cell. The memory cell can transfer charge to the access line after it is coupled to the access line. The sense amplifier can amplify a low-power signal from the access line to identify a logic level (e.g., 0, 1) so that the data can be interpreted by the memory device. However, in some cases, the sense amplifier can experience degradation that causes errors in access operations at the memory device, causing read or write operations to be performed incorrectly. For example, due to differences between a first p-type transistor for manufacturing the sense amplifier and a second p-type transistor for manufacturing the sense amplifier, the p-type transistor may drift from a target voltage threshold associated with the p-type transistor, causing the p-type transistor to behave differently than expected. Such variations in the performance of the p-type transistor (e.g., at least in part due to manufacturing variations) can reduce the performance of the sense amplifier to accurately interpret data from the access line, which can lead to various inefficiencies in memory access.

[0014] According to examples described herein, the architecture of a p-type transistor in a sense amplifier can be modified to support greater accuracy in voltage sensing operations in a memory system. For example, the shape and / or positioning of one or more channel portions of the p-type transistor relative to one or more gate portions of the p-type transistor can increase the effective channel length of the p-type transistor, which can support increased accuracy in cell voltage sensing. In some examples, the channel portion (e.g., channel region, active area) of the p-type transistor can have a non-rectangular shape (e.g., a 'Z' shape) to support a relatively long path (e.g., a conductive path) between the source and drain of the p-type transistor, thereby effectively increasing the channel length (e.g., the path or distance that carriers travel in the channel portion of the transistor). In other examples, the shape of the gate portion of the p-type transistor can have a non-rectangular shape (e.g., a 'half-H' shape, a 'C' shape) to support a relatively long path between the source and drain.

[0015] In addition to being applied to the memory systems described herein, the techniques for the enhanced sense amplifier architecture can also be generally implemented to improve the performance of various electronic devices and systems, including artificial intelligence (AI) applications, augmented reality (AR) applications, virtual reality (VR) applications, and gaming. Some electronic device applications, including high-performance applications such as AI, AR, VR, and gaming, can be associated with relatively high processing requirements to meet user expectations. Thus, increasing the processing capabilities of electronic devices by reducing response time, improving power consumption, reducing complexity, increasing data throughput or access speed, reducing communication time, or increasing memory capacity or density, among other performance metrics, can improve user experience or appeal. Implementing the techniques described herein can improve the performance of electronic devices by improving the accuracy and reliability of memory access operations, which can improve response time and lead to more accurate and efficient memory access, among other benefits.

[0016] Features of the present disclosure are illustrated and described in the context of an architecture. Features of the present disclosure are further illustrated and described in the context of circuit diagrams, sense amplifiers, transistor structures, and sense amplifier architectures.

[0017] Figure 1 An example of an architecture 100 (e.g., a memory architecture) supporting an enhanced sense amplifier architecture according to examples disclosed herein is described. The architecture 100 can be implemented in a memory system or one or more components thereof (e.g., a memory device). Aspects of the architecture 100 can be referred to or implemented in a semiconductor component, such as a memory die.

[0018] Architecture 100 includes memory cells 205 that are programmable to store information. In some examples, memory cells 205 are operable to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some examples, memory cells 205 (e.g., multi-level memory cells) are operable to store more than one bit of information at a time (e.g., a logic 00, a logic 01, a logic 10, a logic 11). Memory cells 205 can be arranged in an array, such as a memory array.

[0019] In the example of architecture 100, memory cell 205 may include a storage component (e.g., capacitor 230) and a selection component 235 (e.g., a cell selection component, a transistor). Capacitor 230 may be a dielectric capacitor or a ferroelectric capacitor. A node of capacitor 230 may be coupled to a voltage source 240, which may be a cell plate reference voltage (e.g., Vpl) or a ground voltage (e.g., Vss). The charge stored by memory cell 205 (e.g., by capacitor 230) may represent a programmed state. Other memory architectures supporting the techniques described herein may implement different types or arrangements of storage components and associated circuitry (e.g., with or without selection components).

[0020] Architecture 100 can include various arrangements of access lines, such as word lines 210 and digit lines 215. Access lines can be conductive lines that are coupled to memory cells 205 and can be used to perform access operations on memory cells 205. Word lines 210 can be referred to as row lines, and digit lines 215 can be referred to as column lines or bit lines, among other nomenclature. Memory cells 205 can be located at the intersection of the access lines, and the intersection can be referred to as the address of the memory cell 205.

[0021] In some architectures, word line 210 can be coupled to the gate of select element 235 of memory cell 205 and can be operated to control select element 235 (e.g., switch, modulate the conductivity of select element 235). Digit line 215 can be operated to couple memory cell 205 to sense element 245. In some architectures, memory cell 205 (e.g., capacitor 230) can be coupled to digit line 215 during portions of an access operation. For example, word line 210 and select element 235 of memory cell 205 can be operated to couple or isolate capacitor 230 of memory cell 205 from digit line 215.

[0022] Operations such as reading and writing can be performed on memory cell 205 by activating (e.g., applying a voltage to) an access line such as word line 210 or digit line 215. Access to memory cell 205 can be controlled by row decoder 220 or column decoder 225, or a combination thereof. For example, row decoder 220 can receive a row address (e.g., from local memory controller 260) and activate word line 210 based on the received row address, and column decoder 225 can receive a column address and activate digit line 215 based on the received column address. Selecting or deselecting memory cell 205 can include activating or deactivating selection element 235 using word line 210. For example, when selection element 235 is deactivated, capacitor 230 can be isolated from digit line 215, and when selection element 235 is activated, capacitor 230 can be coupled to digit line 215.

[0023] Sense component 245 is operable to detect a state (e.g., charge) stored by capacitor 230 of memory cell 205 and determine a logic state of memory cell 205 based on the stored state. Sense component 245 may include one or more sense amplifiers to amplify or otherwise convert a signal resulting from accessing memory cell 205. Sense component 245 may compare the signal detected from memory cell 205 to a reference 250 (e.g., a reference voltage). The detected logic state of memory cell 205 may be provided as an output of sense component 245 (e.g., via input / output 255) and may be indicated to another component of a memory system implementing architecture 100.

[0024] The local memory controller 260 can control access to the memory cells 205 through various components, such as the row decoder 220, the column decoder 225, and the sensing component 245, and can be an example of or otherwise included in a local controller, a memory system controller, or both. In some examples, one or more of the row decoder 220, the column decoder 225, and the sensing component 245 can be co-located with or included in the local memory controller 260. The local memory controller 260 can be operable to receive commands or data from one or more different controllers (e.g., a host system controller, a memory system controller), translate the commands or data into information that can be used by the architecture 100, initiate or control one or more operations of the architecture 100, and communicate data from the architecture 100 to a host (e.g., a host system) based on the execution of the one or more operations.

[0025] The local memory controller 260 is operable to perform one or more access operations on one or more memory cells 205 of the architecture 100. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, the access operations may be performed or otherwise coordinated by the local memory controller 260 in response to one or more access commands (e.g., from a host system). The local memory controller 260 is operable to perform other access operations not listed here or other operations related to the operation of the architecture 100 that are not directly related to accessing the memory cells 205.

[0026] To support an access operation, the local memory controller 260 can identify a target memory cell 205 for which the access operation is to be performed. The access operation can be associated with identifying a target word line 210 and a target digit line 215 coupled to the target memory cell 205 (e.g., an address of the target memory cell 205). The local memory controller 260 can control activation of the target word line 210 and the target digit line 215 to access the target memory cell 205. During a write operation, the local memory controller 260 can control application of a signal (e.g., a write pulse, a write voltage) to the target digit line 215 to store a specific state of the memory cell 205 (e.g., the charge in the capacitor 230). The signal used as part of the write operation can include one or more voltage levels applied to the target memory cell 205 (e.g., via the target digit line 215) for one or more corresponding durations. During a read operation, the target memory cell 205 can transfer a signal (e.g., a charge, a voltage) to the sensing component 245 based on activation of the target word line 210 and the target digit line. The local memory controller 260 can activate the sensing component 245 (e.g., activate a sense amplifier of the latched sensing component 245), which can include comparing the signal transferred from the memory cell 205 with a reference (e.g., reference 250). Based on the comparison, the sensing component 245 can determine the logic state stored on the memory cell 205.

[0027] In some examples, sensing component 245 may include p-type transistors and n-type transistors that support the functionality of sensing component 245 in performing access operations. However, the p-type transistors and n-type transistors of sensing component 245 may have voltage thresholds or target voltages that vary from transistor to transistor. The lack of uniformity between the p-type transistors in sensing component 245 may result in inaccurate sensed voltages for memory access operations. According to examples described herein, the architecture of a sense amplifier within or as part of sensing component 245 may be modified to increase the effective channel length of the p-type transistors within sensing component 245, which may support increased accuracy of voltage sensing operations performed by sensing component 245.

[0028] Figure 2An example of a circuit diagram 200 supporting an enhanced sense amplifier architecture according to examples disclosed herein is shown. The circuit diagram 200 may include a sense amplifier 265-a and other sense amplifiers 265, which may be components of a sense component 245, as described in reference to FIG. Figure 1 For example, the sensing component 245 may include one or more sense amplifiers 265, including sense amplifiers 265-a to 265-M (where M is a variable). The sense amplifier 265-a may amplify the data signal from the access line, which may enable the sensing component 245 to interpret the data signal as logic (e.g., 0, 1).

[0029] In some examples, the sensing component 245 may include multiple sense amplifiers 265, each coupled to one of a plurality of access lines (e.g., bit lines). From a power perspective, the multiple sense amplifiers can be coupled to various voltage sources (e.g., V1 and V2) in a parallel configuration. In some examples, a sense amplifier 265-a can be connected in parallel with other sense amplifiers 265 (e.g., M other sense amplifiers 265), and the parallel-connected sense amplifiers 265 can share one or more common voltage sources (e.g., V1 and V2). The common voltage source can output a voltage V1 on a first voltage line of the sense amplifier 265 and a voltage V2 on a second voltage line of the sense amplifier 265. The voltages V1 and V2 can be based on the combined load of the sense amplifiers 265. For example, the voltages V1 and V2 can vary based on the cumulative electrical response of the loads (e.g., multiple sense amplifiers) coupled to the voltages V1 and V2.

[0030] The actual voltage difference (eg, dV) of the sense amplifier 265-a is th ) may differ from the average sense amplifier (e.g., due to manufacturing inconsistencies in the sense amplifiers). However, because the other sense amplifiers 265 share a voltage source with sense amplifier 265-a, dictating the values of V1 and V2, sense amplifier 265-a can adapt its functionality based on the common power supply. Thus, in some cases, an individual sense amplifier 265 may have an ideal operating voltage at a first value due to manufacturing variations, but its operating voltage may differ from the ideal operating voltage because the voltage on the common voltage source is a product of the entire electrical load. In some examples, because sense amplifier 265-a is connected in parallel with the other sense amplifiers 265, sense amplifier 265-a may also share a voltage threshold compensation (VTC) time with the other sense amplifiers 265. Sense amplifier 265-a can adapt its functionality based on the common VTC time.

[0031] The sense amplifier 265-a can be adapted to a common voltage source (eg, a common dV th), and the behavior of the sense amplifier 265-a may differ from the expected behavior of the sense amplifier 265-a (e.g., based on the difference between the ideal operating voltage and the actual operating voltage of the individual sense amplifiers). th ) different voltage values (which explains the skew of sense amplifier 265-a about the average value of sense amplifier 265), sense amplifier 265-a may operate with inefficient voltage sensing behavior. As a result, sense amplifier 265-a may amplify the data value from the digit line with a certain error, which may lead to inaccurate readings from the digit line. According to examples described herein, the architecture of p-type transistors (e.g., p-channel metal oxide semiconductor (PMOS)) can be modified to reduce the effect of variations in the common voltage source across the parallel-connected sense amplifiers 265. For example, the effective channel length of the p-type transistors in sense amplifier 265-a can be increased, which can reduce voltage sensing variations of sense amplifier 265-a, such as in situations where there is a mismatch between the common voltage source of sense amplifier 265-a and the characteristics of sense amplifier 265-a (e.g., voltage threshold), thereby resulting in improved performance.

[0032] Figure 3 An example of a sense amplifier 300 supporting an enhanced sense amplifier architecture according to examples disclosed herein is shown. The sense amplifier 300 may be an example of a component of the sensing component 245, as described with reference to FIG. Figure 1 For example, the sensing component 245 may include a sense amplifier 300, and the sense amplifier 300 may amplify the data signal from the access line, which may enable the sensing component 245 to interpret the data signal as logic (eg, 0, 1).

[0033] Sense amplifier 300 may include p-type transistor 305-a, p-type transistor 305-b, n-type transistor 310-a, and n-type transistor 310-b. N-type transistor 310 may be connected in diode mode (e.g., metal oxide semiconductor (MOS) diode mode). For example, n-type transistor 310-b may act as a diode and may take an input voltage from a digit line (e.g., DL) and connect (e.g., pass) the voltage from the digit line to the source of p-type transistor 305-b. P-type transistor 305-b may amplify the voltage from the digit line to generate an inverted digit line (e.g., DL#). The amplified voltage at the inverted digit line may be used by sensing component 245 to interpret data from the digit line into logic.

[0034] In some instances, sense amplifier 300 is inefficient at amplifying data from a digit line for a read operation at sensing element 245. The output voltage of sense amplifier 300 may be associated with a tail that prevents the data from the digit line from being accurately read and interpreted. The inefficiency of sense amplifier 300 may be caused by inconsistencies associated with n-type transistors or p-type transistors, or inconsistencies in the interaction between n-type transistors and p-type transistors.

[0035] In some cases, n-type transistors 310-a and 310-b may be associated with small inconsistencies relative to the expected performance of n-type transistor 310. Due to these inconsistencies, n-type transistor 310-b may output a voltage that is inconsistent with the voltage of the digit line, even though the n-type transistor is operating in diode mode. When the n-type transistor passes the output voltage to the source of p-type transistor 305-b, any voltage difference caused by the n-type transistor may be amplified by the amplification performed by p-type transistor 305-b on the voltage.

[0036] In some examples, in addition to the inconsistencies of n-type transistor 310, p-type transistor 305 may also be associated with various inconsistencies (e.g., variations from expected behavior). Specifically, for example, p-type transistor 305-b may have a voltage threshold difference (e.g., dV th ) operation, the voltage threshold difference may be different from the voltage threshold difference of a typical p-type transistor 305-b and may be different from the voltage threshold difference of p-type transistor 305-a. This difference in the operating voltage threshold differences of the p-type transistors 305 within sense amplifier 300 may result in a relatively large tail associated with the voltage sensing performance of sense amplifier 300.

[0037] In some cases, there may be a large spread (e.g., 0.5 uA to 15 uA) in the operating currents of p-type transistor 305 and n-type transistor 310, which may be a product of an offset corresponding to variations in p-type transistor 305 and n-type transistor 310. This large current spread may be due to p-type transistor 305 operating in a transition region between below the threshold voltage of p-type transistor 305 (e.g., below Vth) and above the voltage threshold (e.g., above Vth).

[0038] In some examples, to improve the performance of sense amplifier 300, the architecture of the channel portion and the gate portion within p-type transistor 305 can be modified. Modifying the architecture of p-type transistor 305 can improve the performance of sense amplifier 300 for cell voltage sensing, thereby increasing the range of cell voltages that can be correctly sensed (e.g., interpreted). According to examples described herein, the effective channel length of p-type transistor 305 can be increased, which can enable p-type transistor 305 to have improved sensing performance. For example, due to the enhancement-mode architecture of p-type transistors 305 of sense amplifier 300, differences in the threshold voltage difference from one p-type transistor (e.g., p-type transistor 305-a) to another p-type transistor (e.g., p-type transistor 305-b) can have a relatively small impact on the sensing performance of sense amplifier 300.

[0039] Figure 4A An example of a transistor structure 400 supporting an enhanced sense amplifier architecture according to examples disclosed herein is shown. The transistor structure 400 illustrates an example of a transistor formed at least in part from a portion of a substrate 420 (e.g., a doped portion 440 of the substrate 420) and may illustrate a characteristic arrangement of the transistor configured in a planar transistor arrangement. The substrate 420 may be a portion of a semiconductor chip, such as a silicon chip (e.g., crystalline silicon, single crystal silicon) of a memory die. For illustrative purposes, aspects of the transistor structure 400 may be described with reference to the x-, y-, and z-directions of a coordinate system 415. In some examples, the z-direction may illustrate a direction perpendicular to a surface of the substrate 420 (e.g., a surface in the xy plane, a surface on or over which other materials may be deposited), and each of the structures (illustrated by their respective cross-sections in the xz plane) may extend a distance (e.g., a length) in the y-direction.

[0040] Transistor structure 400 illustrates an example of a transistor channel that may include one or more doped portions 440 of substrate 420, electrically coupled between terminals 470-a and 470-b. In various examples, one of terminals 470-a or 470-b may be referred to as a source terminal, and the other of terminals 470-a or 470-b may be referred to as a drain terminal, where such designations or nomenclature may be based on the configuration or relative biasing of the circuit that includes transistor structure 400. A channel of a transistor (e.g., channel portion 405) may include or refer to one or more portions of a transistor structure that are operable to open or close a conductive path between a source and a drain (e.g., between terminals 470-a and 470-b) based at least in part on a voltage at a gate (e.g., a gate terminal, gate portion 410). In other words, channel portion 405 of the transistor structure may be doped in a manner to create a conductive path between terminals 470-a and 470-b in response to a voltage applied to gate portion 410. The channel portion 405 can be activated, deactivated, become conductive, or become non-conductive based at least in part on a voltage of a gate portion, such as gate portion 410. In some examples of the transistor structure 400, such as a planar transistor arrangement, the channel portion 405 formed by the one or more doped portions 440 of the substrate 420 can support a conductive path in a generally horizontal or in-plane direction, such as along the x-direction, in the xy plane, within the surface of the substrate 420, or in a direction parallel to the surface of the substrate 420.

[0041] In some examples, the gate portion 410 can be physically separated from the channel portion 405 (e.g., separated from the substrate 420, separated from one or more of the doped portions 440) by a gate insulating portion 460. Each of the terminals 470 can be in contact with or otherwise coupled (e.g., electrically, physically) to a respective doped portion 440-a, and each of the terminals 470 and the gate portion 410 can be formed of a conductive material, such as a metal or metal alloy or a polycrystalline semiconductor (e.g., polysilicon).

[0042] In some examples, transistor structure 400 can operate as an n-type or n-channel transistor. In the case of an n-type transistor, applying a relatively positive voltage above a threshold voltage to gate portion 410 (e.g., an applied voltage having a positive magnitude greater than the threshold voltage relative to the source terminal) activates channel portion 405 or otherwise enables a conductive path between terminals 470-a and 470-b (e.g., within substrate 420 along a direction generally aligned with the x-direction). In such examples, doped portion 440-a and doped portion 440-b can refer to portions having n-type doping or n-type semiconductor.

[0043] In some examples, transistor structure 400 can operate as a p-type or p-channel transistor. In the case of a p-type transistor, applying a relatively negative voltage above a threshold voltage to gate portion 410 (e.g., an applied voltage having a negative magnitude greater than the threshold voltage relative to the source terminal) activates channel portion 405 or otherwise enables a conductive path between terminals 470-a and 470-b. In such examples, doped portion 440-a and doped portion 440-b can refer to portions having p-type doping or p-type semiconductor.

[0044] In some examples, the distance that a charge carrier travels in channel portion 405 can be associated with the conductive path between terminals 470-a and 470-b. This distance can be referred to as the channel length. The channel length can be the distance that an average charge carrier travels from terminal 470-a to terminal 470-b when the transistor is activated (e.g., when gate portion 410 activates channel portion 405 to form a conductive path). In some examples, channel portion 405 can be modified to increase the channel length, which can improve the accuracy of a sensing component (e.g., sensing component 245) used to perform cell voltage sensing. For example, the threshold voltage of a p-type transistor is based at least in part on the length of the channel in the transistor. The shorter the channel length, the more susceptible the transistor's threshold voltage is to variations. The p-type transistor in a sense amplifier is configured as an amplifier. If the p-type transistor is not fully thresholded (e.g., due to variations in the threshold voltage), the amplification provided by the p-type transistor can vary, which can cause variations in the performance of the sense amplifier. To reduce the variability of the threshold voltage of a p-type transistor, techniques can be used to increase the channel length of the transistor (rather than increasing the size of the transistor). According to the examples described herein, various architectures of the channel portion 405 and the gate portion 410 can be used to extend the effective channel length for carriers to pass through the channel portion 405.

[0045] Figure 4B An example of a sense amplifier architecture 401 supporting an enhanced sense amplifier architecture according to examples disclosed herein is shown. The sense amplifier architecture 401 may illustrate an example architecture of p-type transistors 305-a and 305-b of the sense amplifier 300, as described with reference to FIG. Figure 3 described.

[0046] In some examples, as described with reference to FIG4 , the channel portion 405 of the transistor structure 400 can be divided (e.g., logically and not necessarily physically) into a channel portion 405 - a , a channel portion 405 - b , and a channel portion 405 - c . The sense amplifier architecture 401 can illustrate Figure 4A , and the channel portion 405 and the gate portion 410 may be located on different layers such that the gate portion 410 is positioned above the channel portion 405 .

[0047] As reference Figure 4A In more detail, gate portion 410 can activate channel portion 405, which, when activated, can form a conductive path between source 430 and drain 435. An example of a first channel between source 430-a and drain 435-a of a first transistor corresponding to a sense amplifier is illustrated by channel path 480. A second channel corresponding to a second transistor of the sense amplifier can also exist between source 430-a and drain 435-b, where both transistors share a common source 430-a.

[0048] A first channel portion 405-a can be coupled to the drain 435-a and can include an edge 405-a-1, an edge 405-a-2 opposite the edge 405-a-1, an edge 405-a-3 extending between the edge 405-a-1 and the edge 405-a-2, and an edge 405-a-4 opposite the edge 405-a-3. A second channel portion 405-b can be coupled to the source 430-a (e.g., a common source between two transistors) and can include an edge 405-b-1, an edge 405-b-2, an edge 405-b-3, and an edge 405-b-4 in a manner similar to, but offset from, the channel portion 405-a. For example, edge 405-b-1 may be offset from edge 405-a-1 by a first distance 445-a, and edge 405-b-2 may be offset from edge 405-a-1 by a second distance 445-b greater than the first distance. Edge 405-b-3 may be offset from edge 405-a-3 by a third distance 445-c equal to the length of edge 405-a-1. The width of channel portion 405-a may be smaller than the width of channel portion 405-b, such that a fifth distance 445-d between edges 405-a-1 and 405-a-2 may be smaller than a sixth distance 445-e between edges 405-b-1 and 405-b-2. Channel portion 405-a and channel portion 405-b may contact each other to form a continuous plane. For example, a portion of edge 405-a-4 may contact a portion of edge 405-b-3.

[0049] Gate portion 410-a, which may overlap at least a portion of channel portion 405-a and channel portion 405-b, may include edge 410-a-1, edge 410-a-2 opposite edge 410-a-1, edge 410-a-3 extending between edge 410-a-1 and edge 410-a-2, and edge 410-a-4 opposite edge 410-a-3. Edge 410-a-1 may be offset from edge 405-b-1 by a seventh distance 445-f, and edge 410-a-2 may be offset from edge 405-a-2 by an eighth distance 445-g that is different from seventh distance 445-f (e.g., in the opposite direction relative to the seventh distance). Edge 410-a-3 may be offset from edge 405-a-3, and edge 410-a-4 may be offset from edge 405-b-4.

[0050] The third channel portion may be coupled to drain 435-b and may include edge 405-c-1, edge 405-c-2 opposite edge 405-c-1, edge 405-c-3 extending between edge 405-c-1 and edge 405-c-2, and edge 405-c-4 opposite edge 405-c-3. Edge 405-c-1 may be offset from edge 405-a-1 by a ninth distance 445-h, which is different from first distance 445-a, and edge 405-c-2 may be offset from edge 405-a-1 by a tenth distance 445-i, which is different from second distance 445-b. Channel portions 405-c and 405-b may contact each other to form a continuous plane. For example, a portion of edge 405-c-4 may contact a portion of edge 405-b-3.

[0051] Gate portion 410-b, which may overlap at least a portion of channel portion 405-c and channel portion 405-b, may include edge 410-b-1, edge 410-b-2 opposite edge 410-b-1, edge 410-b-3 extending between edge 410-b-1 and edge 410-b-2, and edge 410-b-4 opposite edge 410-b-3. Edge 410-a-1 may be offset from edge 410-b-1 by an eleventh distance 445-j that is different from first distance 445-a and second distance, and edge 410-a-2 may be offset from edge 410-b-2 by the eleventh distance 445-j (e.g., gate portion 410-a and gate portion 410-b may be the same width).

[0052] Figure 4BThe shape of the channel portion 405 illustrated in FIG. 4 is designed to increase the distance that carriers will travel in the channel portion 405. For example, the source and drain are offset from each other in a first direction and the channel portion 405 has a zigzag pattern, which increases the distance that carriers will travel relative to if the channel portion were a solid rectangle (e.g., a single rectangle with no portions or offsets) or if the source and drain were aligned. For example, on average, carriers traveling through the channel portion 405 (e.g., the conductive path of the channel portion 405) may travel along a channel path 480 (e.g., a 'Z' shaped path), which may be a greater distance relative to if the channel portion were a solid rectangle or if the source and drain were aligned. This increased distance reduces the variability of the threshold voltage in the p-type transistor, which reduces performance variations in a sense amplifier that includes such a p-type transistor.

[0053] Figure 5 An example of a sense amplifier architecture 500 supporting an enhanced sense amplifier architecture according to examples disclosed herein is shown. The sense amplifier architecture 500 may illustrate an example architecture of p-type transistors 305-a and 305-b of the sense amplifier 300, as described with reference to FIG. Figure 3 The sense amplifier architecture 500 is also described in Figure 4B 4. Sense amplifier architecture 500 is an example of a variation of the described sense amplifier architecture 401. More specifically, sense amplifier architecture 500 has some edges that are more angled relative to each other than sense amplifier architecture 401, which has edges that are more perpendicular relative to each other. For example, edge 405-b-1, edge 405-a-2, edge 405-b-2, and edge 405-c-1 in sense amplifier architecture 500 can be angled relative to corresponding edges in sense amplifier architecture 401. Other edges of sense amplifier architecture 500 can be the same between sense amplifier architecture 401 and sense amplifier architecture 500, or can include similar relationships relative to edge 405 of sense amplifier architecture 401.

[0054] In the example of sense amplifier architecture 500, edge 405-a-2 can be positioned at a first angle relative to edge 405-a-1. Edge 405-b-1 can also be positioned at the first angle relative to edge 405-a-1 such that edge 405-b-1 is parallel to edge 405-a-2, or can be positioned at an angle different from the first angle. Edge 405-c-1 can be positioned at a second angle relative to edge 405-c-2. Edge 405-b-2 can also be positioned at a second angle relative to edge 405-c-2 such that edge 405-b-2 is parallel to edge 405-c-1, or can be positioned at an angle different from the second angle.

[0055] In some examples, positioning one or more edges of one or more channel portions 405 at an angle relative to other edges may result in reduced complexity or reduced cost in manufacturing the one or more channel portions 405 .

[0056] Figure 6 An example of a sense amplifier architecture 600 supporting an enhanced sense amplifier architecture according to examples disclosed herein is shown. The sense amplifier architecture 600 may illustrate an example architecture of p-type transistors 305-a and 305-b of the sense amplifier 300, as described with reference to FIG. Figure 3 described.

[0057] In some examples, gate portion 610 may be divided into gate portion 610-a, gate portion 610-b, gate portion 610-c, and gate portion 610-d. Figure 4A In more detail, gate portion 610 can activate channel portion 605, which, when activated, can form a conductive path between source 630 and drain 635. An example of a first channel between source 630-a and drain 635-a, corresponding to a first transistor of a sense amplifier, is illustrated by channel path 680. A second channel can also exist between source 630-b and drain 635-b, corresponding to a second transistor of the sense amplifier.

[0058] Channel portion 605-a may include edge 605-a-1, edge 605-a-2, edge 605-a-3, and edge 605-a-4. Gate portion 610-a, which may overlap at least a first portion of channel portion 605-a, may include edge 610-a-1, edge 610-a-2 opposite edge 610-a-1, edge 610-a-3 extending between edge 610-a-1 and edge 610-a-2, and edge 610-a-4 opposite edge 610-a-3. Edge 610-a-2 may be aligned with a portion of edge 605-a-2. Edge 610-a-3 may be offset from edge 605-a-3 by a first distance 645-a. Edge 610-a-4 may be offset from edge 605-a-4 by a second distance 645-b.

[0059] Gate portion 610-b, which may overlap at least a second portion of channel portion 605-a, distinct from the first portion of channel portion 605-a, may include edge 610-b-1, edge 610-b-2 opposite edge 610-b-1, edge 610-b-3 extending between edge 610-b-1 and edge 610-b-2, and edge 610-b-4 opposite edge 610-b-3. Gate portion 610-a and gate portion 610-b may contact each other to form a continuous plane. For example, edge 610-b-2 may contact a portion of edge 610-a-1. Edge 610-b-1 may be offset from edge 605-a-1 by a distance 645-f. Edge 610-b-3 may be offset from edge 605-a-3 by a third distance 645-c. Edge 610-b-4 may be offset from edge 605-a-4 by a fourth distance 645-d. Edge 610-a-1 may be offset from edge 605-a-1 by a fifth distance 645-e.

[0060] A second channel portion 605-b, corresponding to another p-type transistor, may include an edge 605-b-1, an edge 605-b-2, an edge 605-b-3, and an edge 605-b-4, in a manner similar to channel portion 605-b, but offset relative to channel portion 605-b. For example, edge 605-a-1 may be offset from edge 605-b-1 by a sixth distance 645-g, and edge 605-a-2 may be offset from edge 605-b-2 by a sixth distance 645-g (e.g., channel portions 605-a and 605-b may be the same width). Gate portion 610-c may include an edge 610-c-1, an edge 610-c-2, an edge 610-c-3, and an edge 610-c-4, in a manner similar to gate portion 610-a, but offset relative to gate portion 610-a. For example, edge 610-c-1 may be offset from edge 610-a-1 by a seventh distance 645-h, and edge 610-c-2 may be offset from edge 610-a-2 by a seventh distance 645-h. Gate portion 610-d may include edge 610-d-1, edge 610-d-2, edge 610-d-3, and edge 610-d-4, in a manner similar to gate portion 610-b, but offset relative to gate portion 610-b. For example, edge 610-d-1 may be offset from edge 610-b-1 by an eighth distance 645-i, and edge 610-d-2 may be offset from edge 610-b-2 by an eighth distance 645-i.

[0061] Figure 6The shape of gate portion 610 illustrated in FIG. 6 is designed to increase the distance carriers travel in channel portion 605. For example, while source 630 and drain 635 are vertically aligned and some carriers traveling through channel portion 605 may pass directly through the channel portion overlapping gate portion 610-b, other carriers may travel a greater distance along a 'C'-shaped trajectory or travel path illustrated by channel path 680 through the channel portion overlapping gate portion 610-a. Between the two travel paths, which may average out to a 'C'-shaped travel path, carriers may travel a greater distance relative to a solid rectangle (e.g., a single rectangle with no sections or offsets) of gate portion 610. This increased distance reduces the variability of the threshold voltage in p-type transistors, which reduces performance variations in sense amplifiers that include such p-type transistors.

[0062] Figure 7 An example of a sense amplifier architecture 700 supporting an enhanced sense amplifier architecture according to examples disclosed herein is shown. The sense amplifier architecture 700 may illustrate an example architecture of p-type transistors 305-a and 305-b of the sense amplifier 300, as described with reference to FIG. Figure 3 described.

[0063] In some examples, the channel portion 705 can be divided into channel portion 705-a, channel portion 705-b, channel portion 705-c, channel portion 705-d, channel portion 705-e, and channel portion 705-f, and the gate portion 710 can be divided into gate portion 710-a, gate portion 710-b, gate portion 710-c, gate portion 710-d, gate portion 710-e, and gate portion 710-f. Figure 4A In more detail, gate portion 710 can activate channel portion 705, which, when activated, can form a conductive path between source 730 and drain 735. An example of a first channel between source 730 and drain 735 of a first transistor corresponding to a sense amplifier is illustrated by channel path 780. A second channel can also exist between another source 730 and another drain 735, corresponding to a second transistor of the sense amplifier.

[0064] Channel portion 705-a may include edge 705-a-1, edge 705-a-2, edge 705-a-3, and edge 705-a-4. Channel portion 705-b may include edge 705-b-1, edge 705-b-2, edge 705-b-3, and edge 705-b-4. Channel portion 705-c may include edge 705-c-1, edge 705-c-2, edge 705-c-3, and edge 705-c-4. Edge 705-c-3 may extend from edge 705-a-3 in a first direction, and edge 705-c-4 may extend from edge 705-b-4 in a first direction.

[0065] Gate portion 710-b may include edge 710-b-1, edge 710-b-2, edge 710-b-3, and edge 710-b-4. Edge 710-b-1 may be offset from edge 705-a-1 by a first distance 745-a. Edge 710-b-3 may be offset from edge 705-a-3 by a second distance 745-b, and edge 710-b-4 may be offset from edge 705-a-3 by a third distance 745-c. Gate portion 710-c may include edge 710-c-1, edge 710-c-2, edge 710-c-3, and edge 710-c-4. Edge 710-c-1 may be offset from edge 705-b-1 by the first distance 745-a. Edge 710-c-4 may be offset from edge 705-b-4 by a second distance 745-b and edge 710-c-3 may be offset from edge 705-b-4 by a third distance 745-c.

[0066] Gate portion 710-a may include edge 710-a-1, edge 710-a-2, edge 710-a-3, and edge 710-a-4. A portion of edge 710-a-2 may be aligned with edge 705-c-2. Edge 710-b-2 may contact a first portion (e.g., a segment) of edge 705-c-1, and edge 710-c-2 may contact a second portion (e.g., a segment) of edge 705-c-1.

[0067] Edge 705-a-4 may be offset from edge 705-b-3 by a fourth distance 745-d. Gate portion 710-b and gate portion 710-c may be associated with an extension relative to gate portion 710-a to form a 'C' shaped configuration such that edge 710-b-1 is offset from edge 705-c-1 by a fifth distance 745-e and edge 710-c-1 is offset from edge 705-c-1 by a fifth distance 745-e.

[0068] Channel portions 705-d, 705-e and 705-f corresponding to another p-type transistor may include edge 705-d-1, edge 705-d-2, edge 705-d-3, edge 705-d-4, edge 705-e-1, edge 705-e-2, edge 705-e-3, edge 705-e-4, edge 705-f-1, edge 705-f-2, edge 705-f-3 and edge 705-f-4, in a manner similar to channel portions 705-a, 705-b and 705-c, respectively, but have an offset (e.g., a horizontal offset) relative to channel portions 705-a, 705-b and 705-c. For example, edge 705-c-1 may be offset from edge 705-f-1 by a sixth distance 745-f, and edge 705-c-2 may be offset from edge 705-f-2 by a sixth distance 745-f, thereby offsetting channel portion 705-c from channel portion 705-f. Similarly, channel portion 705-a may be offset from channel portion 705-d, and channel portion 705-b may be offset from channel portion 705-e.

[0069] Figure 7 The shapes of gate portion 710 and channel portion 705 illustrated in FIGURE 7 are designed to increase the distance carriers travel in channel portion 705. For example, due to the physical separation between channel portion 705-a and channel portion 705-b, there may not be a direct path between source 730 and drain 735. Instead, carriers may travel through channel portion 705-c along a 'C'-shaped trajectory or travel path illustrated by channel path 780, which may be a greater distance than carriers would travel if channel portion 705 and gate portion 710 were solid rectangles (e.g., each being a single rectangle with no sections or offsets) with a direct path (e.g., a conductive path) between the source and drain. This increased distance reduces the variability of the threshold voltage in p-type transistors, which reduces performance variations in sense amplifiers that include such p-type transistors.

[0070] Figure 8 An example of a sense amplifier architecture 800 supporting an enhanced sense amplifier architecture according to examples disclosed herein is shown. The sense amplifier architecture 800 may illustrate an example architecture of p-type transistors 305-a and 305-b of the sense amplifier 300, as described with reference to FIG. Figure 3 described.

[0071] Channel portion 805-a may be an example of channel portion 805 and may include edge 805-a-1, edge 805-a-2, edge 805-a-3, and edge 805-a-4. In some examples, gate portion 810 may be divided into gate portion 810-a, gate portion 810-b, gate portion 810-c, gate portion 810-d, gate portion 810-e, and gate portion 810-f. As shown in FIG. Figure 4A In more detail, gate portion 810 can activate channel portion 805-a, which, when activated, can form a conductive path between source 830 and drain 835. An example of a first channel between source 830 and drain 835 of a first transistor corresponding to a sense amplifier is illustrated by channel path 880. A second channel corresponding to a second transistor of the sense amplifier can also exist between source 830 and drain 835, which can be a common source between the two transistors.

[0072] Gate portion 810-a may include edge 810-a-1, edge 810-a-2, edge 810-a-3, and edge 810-a-4. Gate portion 810-b may include edge 810-b-1, edge 810-b-2, edge 810-b-3, and edge 810-b-4. Gate portion 810-c may include edge 810-c-1, edge 810-c-2, edge 810-c-3, and edge 810-c-4. Edge 810-b-3 may extend from edge 810-a-3 in a first direction, and edge 810-c-4 may extend from edge 810-a-4 in the first direction. Edge 810-b-2 may contact a first portion (e.g., a segment) of edge 810-a-1, and edge 810-c-2 may contact a second portion of edge 810-a-1 that is larger than the first portion of edge 810-a-1.

[0073] Edge 810-b-3 may be offset from edge 810-b-4 by a first distance 845-a, and edge 810-c-3 may be offset from edge 810-c-4 by a second distance 845-b that is greater than first distance 845-a. That is, gate portion 810-b may be associated with a shorter height relative to gate portion 810-c. Edge 805-a-1 may be aligned with edge 810-b-1 and edge 810-c-1 (e.g., in a vertical plane). Edge 810-a-3 may be offset from edge 805-a-3, and edge 810-a-4 may be offset from edge 805-a-4.

[0074] Gate portions 810-d, 810-e, and 810-f corresponding to another p-type transistor may include edge 810-d-1, edge 810-d-2, edge 810-d-3, edge 810-d-4, edge 810-e-1, edge 810-e-2, edge 810-e-3, edge 810-e-4, edge 810-f-1, edge 810-f-2, edge 810-f-3, and edge 810-f-4, in a manner similar to gate portions 810-a, 810-b, and 810-c, respectively, but with an offset (e.g., a horizontal offset) relative to gate portions 810-a, 810-b, and 810-c. For example, edge 810-a-1 may be offset from edge 810-d-1 by a third distance 845-c, and edge 810-a-2 may be offset from edge 810-d-2 by a third distance 845-c, thereby offsetting gate portion 810-a from gate portion 810-d. Similarly, gate portion 810-b may be offset from gate portion 810-e, and gate portion 810-c may be offset from gate portion 810-f.

[0075] Figure 8 835 are designed to increase the distance carriers travel in the channel portion 805. For example, due to the presence of additional space in the channel portion 805 overlapping the gate portion 810-c and the relatively lower positioning of the source 830 compared to the drain 835, carriers (e.g., a subset of carriers in a group of carriers passing through the channel portion 805) may travel according to an indirect path (e.g., a U-shaped path) as illustrated by the channel path 880. Because some carriers travel in an indirect path between the source and the drain, the distance traveled by the carriers may be increased relative to if the gate portion 810 is a solid rectangle (e.g., a single rectangle without portions or offsets, e.g., without the overhanging portions 810-c and / or 810-b) due to the larger conductive area in the channel portion and the relative positions of the source 830 and the drain 835. This increased distance reduces the variability of the threshold voltage in the p-type transistors, which reduces performance variations of sense amplifiers that include such p-type transistors.

[0076] It should be noted that the aspects described herein describe possible implementations, and that operations and steps may be rearranged or otherwise modified, and that other implementations are possible. Additionally, portions from two or more of the methods may be combined.

[0077] A device is described. The following provides an overview of aspects of the device described herein:

[0078] Aspect 1: A memory system comprising: a memory cell; a digit line coupled to the memory cell; and a sense amplifier coupled to the digit line, the sense amplifier comprising: an n-type transistor; and a p-type transistor comprising: a source; a drain; a channel positioned between the source and the drain, the channel comprising a dopant material configured to facilitate carrier flow between the source and the drain, the channel comprising: a first portion coupled to the source, the first portion comprising a first edge, a second edge opposite the first edge, a third edge extending between the first edge and the second edge, and a fourth edge opposite the third edge; and a second portion coupled to the drain, the first portion comprising a first edge, a second edge opposite the first edge, a third edge extending between the first edge and the second edge, and a fourth edge opposite the third edge. two portions including a fifth edge, a sixth edge opposite the fifth edge, a seventh edge extending between the fifth and sixth edges, and an eighth edge opposite the seventh edge, wherein the fifth edge of the second portion is offset from the first edge of the first portion by a first distance, wherein the sixth edge of the second portion is offset from the second edge of the first portion by a second distance, wherein the seventh edge of the second portion is offset from the third edge of the first portion by a third distance, and wherein a portion of the fourth edge of the first portion contacts a portion of the seventh edge of the second portion; and a gate positioned above the channel and configured to control the amount of the carriers flowing through the channel.

[0079] Aspect 2: The memory system according to Aspect 1, wherein the gate includes a ninth edge, a tenth edge opposite the ninth edge, an eleventh edge extending between the ninth edge and the tenth edge, and a twelfth edge opposite the eleventh edge, the ninth edge is offset from the fifth edge of the second portion by a fourth distance different from the first distance, and the tenth edge is offset from the second edge of the first portion by a fifth distance different from the second distance.

[0080] Aspect 3: The memory system according to any one of aspects 1 to 2, wherein the sense amplifier further includes: a second p-type transistor including: a second source; a second drain; a second channel positioned between the second source and the second drain, the second channel including the dopant material configured to facilitate flow of the carriers between the second source and the second drain, the second channel including: a second portion coupled to the second drain; and a third portion coupled to the second source, the third portion including a ninth edge, a tenth edge opposite the ninth edge, an eleventh edge extending between the ninth edge and the tenth edge, and a twelfth edge opposite the eleventh edge; and a second gate positioned above the second channel and configured to control a second number of the carriers flowing through the second channel.

[0081] Aspect 4: The memory system according to Aspect 3, wherein the ninth edge of the third portion is offset from the first edge of the first portion by a fourth distance different from the first distance, and the tenth edge of the third portion is offset from the second edge of the first portion by a fifth distance different from the second distance.

[0082] Aspect 5: A memory system according to any one of aspects 3 to 4, wherein the gate includes a thirteenth edge, a fourteenth edge opposite the thirteenth edge, a fifteenth edge extending between the thirteenth edge and the fourteenth edge, and a sixteenth edge opposite the fifteenth edge, wherein the second gate includes a seventeenth edge, an eighteenth edge opposite the seventeenth edge, a nineteenth edge extending between the seventeenth edge and the eighteenth edge, and a twentieth edge opposite the nineteenth edge, wherein the thirteenth edge is offset from the seventeenth edge by a fourth distance different from the first distance and the second distance, and wherein the fourteenth edge is offset from the eighteenth edge by the fourth distance.

[0083] Aspect 6: The memory system according to any one of aspects 1 to 5, wherein the second edge of the first portion is disposed at an angle relative to the first edge of the first portion.

[0084] Aspect 7: The memory system according to aspect 6, wherein the fifth edge of the second portion is disposed at the angle relative to the first edge of the first portion, and the fifth edge of the second portion is parallel to the second edge of the first portion.

[0085] A device is described. The following provides an overview of aspects of the device described herein:

[0086] Aspect 8: A memory system comprising: a memory cell; a digit line coupled to the memory cell; and a sense amplifier coupled to the digit line, the sense amplifier comprising: an n-type transistor; and a p-type transistor comprising: a source; a drain; a channel positioned between the source and the drain, the channel comprising a doped material configured to facilitate carrier flow between the source and the drain, the channel comprising a first edge, a second edge opposite the first edge, a third edge extending between the first edge and the second edge, and a fourth edge opposite the third edge; and a gate positioned above the channel and configured to control the amount of the carriers flowing through the channel, the gate comprising: a first portion comprising a fifth edge, a gate extending from the fifth edge to the gate; a sixth edge opposite to the ninth edge, a seventh edge extending between the ninth edge and the sixth edge, and an eighth edge opposite to the seventh edge, wherein the sixth edge of the first portion is aligned with a portion of the second edge, wherein the seventh edge of the first portion is offset from the third edge by a first distance, and wherein the eighth edge of the first portion is offset from the fourth edge by a second distance; and a second portion comprising a ninth edge, a tenth edge opposite to the ninth edge, an eleventh edge extending between the ninth edge and the tenth edge, and a twelfth edge opposite to the eleventh edge, wherein the tenth edge of the second portion contacts a portion of the fifth edge of the first portion, and wherein the ninth edge of the second portion is offset from the first edge.

[0087] Aspect 9: The memory system according to aspect 8, wherein the eleventh edge of the second portion is offset from the third edge by a third distance, and the twelfth edge of the second portion is offset from the fourth edge by a fourth distance.

[0088] Aspect 10: The memory system of any one of aspects 8 to 9, wherein the fifth edge of the first portion is offset from the first edge by a third distance.

[0089] Aspect 11: The memory system according to any one of aspects 8 to 10, wherein the sense amplifier further comprises: a second p-type transistor comprising: a second source; a second drain; a second channel positioned between the second source and the second drain, the second channel comprising the dopant material configured to facilitate flow of the carriers between the second source and the second drain, the second channel comprising a thirteenth edge, a fourteenth edge opposite the thirteenth edge, a fifteenth edge extending between the thirteenth edge and the fourteenth edge, and a sixteenth edge opposite the fifteenth edge; and a second gate positioned above the channel and configured to control a second amount of the carriers flowing through the second channel, the second gate comprising: a third portion comprising a seventeenth edge, an eighteenth edge opposite the seventeenth edge, an eighteenth edge extending between the seventeenth edge, and a sixth edge extending between the seventeenth edge and the fifteenth edge. a nineteenth edge extending between the seventeenth edge and the eighteenth edge and a twentieth edge opposite the nineteenth edge, wherein the seventeenth edge of the third portion is aligned with a portion of the thirteenth edge, wherein the nineteenth edge of the third portion is offset from the fifteenth edge by the first distance, and wherein the twentieth edge of the third portion is offset from the sixteenth edge by the second distance; and a fourth portion comprising a twenty-first edge, a twenty-second edge opposite the twenty-first edge, a twenty-third edge extending between the twenty-first edge and the twenty-second edge, and a twenty-fourth edge opposite the twenty-third edge, wherein the twenty-first edge of the fourth portion contacts a portion of the eighteenth edge of the third portion, and wherein the twenty-second edge of the fourth portion is offset from the fourteenth edge.

[0090] Aspect 12: The memory system of aspect 11, wherein the thirteenth edge is offset from the second edge by a third distance, and the seventeenth edge of the third portion is offset from the sixth edge of the first portion by the third distance.

[0091] A device is described. The following provides an overview of aspects of the device described herein:

[0092] Aspect 13: A memory system comprising: a memory cell; a digit line coupled to the memory cell; and a sense amplifier coupled to the digit line, the sense amplifier comprising: an n-type transistor; and a p-type transistor comprising: a source; a drain; a channel positioned between the source and the drain, the channel comprising a dopant material configured to facilitate carrier flow between the source and the drain, the channel comprising: a first portion coupled to the source, the first portion comprising a first edge, a second edge opposite the first edge, a third edge extending between the first edge and the second edge, and a second edge extending from the third edge. a fourth edge opposite to the drain; a second portion coupled to the drain, the second portion including a fifth edge, a sixth edge opposite to the fifth edge, a seventh edge extending between the fifth edge and the sixth edge, and an eighth edge opposite to the seventh edge; and a third portion including a ninth edge, a tenth edge opposite to the ninth edge, an eleventh edge extending between the ninth edge and the tenth edge, and a twelfth edge opposite to the eleventh edge, wherein the eleventh edge of the third portion extends from the third edge of the first portion in a first direction and the twelfth edge of the third portion is in the first direction and a gate positioned above the channel and configured to control the number of carriers flowing through the channel, the gate comprising: a fourth portion comprising a thirteenth edge, a fourteenth edge opposite the thirteenth edge, a fifteenth edge extending between the thirteenth edge and the fourteenth edge, and a sixteenth edge opposite the fifteenth edge, wherein the thirteenth edge of the fourth portion is offset from the first edge of the first portion by a first distance, wherein the fifteenth edge of the fourth portion is offset from the third edge of the first portion by a second distance, and the tenth edge of the fourth portion is offset from the third edge of the first portion by a second distance. a sixth portion comprising a seventeenth edge, an eighteenth edge opposite the seventeenth edge, a nineteenth edge extending between the seventeenth edge and the eighteenth edge, and a twentieth edge opposite the nineteenth edge; and a sixth portion comprising a twenty-first edge, a twenty-second edge opposite the twenty-first edge, a twenty-third edge extending between the twenty-first edge and the twenty-second edge, and a twenty-fourth edge opposite the twenty-third edge, wherein a portion of the twenty-second edge of the sixth portion is aligned with the twelfth edge of the third portion.

[0093] Aspect 14: The memory system of aspect 13, wherein the seventeenth edge of the fifth portion is offset from the fifth edge of the second portion by the first distance.

[0094] Aspect 15: The memory system of any one of aspects 13 to 14, wherein the twentieth edge of the fifth portion is offset from the eighth edge of the second portion by the second distance and the nineteenth edge of the fifth portion is offset from the eighth edge of the second portion by the third distance.

[0095] Aspect 16: The memory system of any one of aspects 13 to 15, wherein the fourteenth edge of the fourth portion contacts a first portion of the twenty-first edge of the sixth portion and the eighteenth edge of the fifth portion contacts a second portion of the twenty-first edge of the sixth portion.

[0096] Aspect 17: The memory system according to any one of aspects 13 to 16, wherein the sense amplifier further comprises: a second p-type transistor comprising: a second source; a second drain; a second channel positioned between the second source and the second drain, the second channel comprising the dopant material configured to facilitate flow of carriers between the second source and the second drain, the second channel comprising: a seventh portion coupled to the second source, the seventh portion comprising a twenty-fifth edge, a twenty-sixth edge opposite the twenty-fifth edge, a twenty-seventh edge extending between the twenty-fifth edge and the twenty-sixth edge, and a second edge opposite the twenty-seventh edge. an eighth portion coupled to the second drain, the eighth portion including a twenty-ninth edge, a thirtieth edge opposite to the twenty-ninth edge, a thirty-first edge extending between the twenty-ninth edge and the thirtieth edge, and a thirty-second edge opposite to the thirty-first edge; and a ninth portion including a thirty-third edge, a thirty-fourth edge opposite to the thirty-third edge, a thirty-fifth edge extending between the thirty-third edge and the thirty-fourth edge, and a thirty-sixth edge opposite to the thirty-fifth edge, wherein the thirty-fifth edge of the ninth portion extends from the second edge of the seventh portion in a second direction opposite to the first direction a tenth portion including a thirty-seventh edge, a thirty-eighth edge opposite to the thirty-seventh edge, a thirty-ninth edge extending between the thirty-seventh edge and the thirty-eighth edge, and a fortieth edge opposite to the thirty-ninth edge, wherein the thirty-ninth edge of the tenth portion is offset from the twenty-seventh edge of the seventh portion by the second distance and the fortieth edge of the tenth portion is offset from the twenty-seventh edge of the seventh portion by the second distance and the fortieth edge of the tenth portion is offset from the twenty-seventh edge of the seventh portion by the second distance. the third distance offset from the twenty-seventh edge of the seventh portion; an eleventh portion comprising a forty-first edge, a forty-second edge opposite the forty-first edge, a forty-third edge extending between the forty-first edge and the forty-second edge, and a forty-fourth edge opposite the forty-third edge; and a twelfth portion comprising a forty-fifth edge, a forty-sixth edge opposite the forty-fifth edge, a forty-seventh edge extending between the forty-fifth edge and the forty-sixth edge, and a forty-eighth edge opposite the forty-seventh edge, wherein a portion of the forty-fifth edge of the twelfth portion is aligned with the thirty-third edge of the ninth portion.

[0097] Aspect 18: The memory system of aspect 17, wherein the tenth edge of the third portion is offset from the thirty-third edge of the ninth portion by a fourth distance.

[0098] Aspect 19: The memory system of any one of aspects 13 to 18, wherein the fourth edge of the first portion is offset from the seventh edge of the second portion by a fourth distance.

[0099] Aspect 20: The memory system of any one of aspects 13 to 19, wherein the thirteenth edge of the fourth portion is offset from the twenty-first edge of the sixth portion by a fourth distance and the seventeenth edge of the fifth portion is offset from the twenty-first edge of the sixth portion by the fourth distance.

[0100] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a bus of signals, where the bus may have various bit widths.

[0101] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication (e.g., conductive contact, connection, coupling) with each other if there is any electrical path (e.g., conductive path) between the components that can support the flow of signals (e.g., charge, current, voltage) between the components at any time. The conductive path between components that are in electronic communication (e.g., conductive contact, connection, coupling) with each other may be an open circuit or a closed circuit, depending on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components or may be an indirect conductive path that includes an intermediate component (e.g., a switch, transistor, or other component). In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0102] The term "isolation" may refer to a relationship between components where signals are no longer able to flow between them. Components are isolated from one another if an open circuit exists between them. For example, when a switch positioned between two components is opened, the components separated by the switch are isolated from one another. When a component isolates two components, it may cause changes that prevent signals from flowing between the other components using the conductive path that previously allowed signal flow.

[0103] The term "coupled" (e.g., "electrically coupled") may refer to a condition that transitions from an open-circuit relationship between components, where signals cannot currently be communicated between the components (e.g., via conductive paths), to a closed-circuit relationship between the components, where signals can be communicated between the components (e.g., via conductive paths). When a component, such as a controller, couples other components together, the component may induce a change that allows signals to flow between the other components through conductive paths that previously did not allow signal flow.

[0104] The term "layer" or "step" can refer to an organization (e.g., a stratum or sheet) of a geometric structure (e.g., relative to a substrate). Each layer or step can have three dimensions (e.g., height, width, and depth) and can cover at least a portion of a surface. For example, a layer or step can be a three-dimensional structure in which two dimensions are larger than the third, such as a thin film. A layer or step can include different elements, components, or materials. In some examples, a layer or step can be composed of two or more sub-layers or sub-steps.

[0105] As used herein, the term "electrode" may refer to an electrical conductor and, in some examples, may serve as an electrical contact for a memory cell or other component of a memory array. An electrode may include a trace, wire, conductive line, conductive layer, or the like that provides a conductive path between components of a memory array.

[0106] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate (e.g., silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOS)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic.

[0107] The switching components (e.g., transistors) discussed herein may be field-effect transistors (FETs) and may include a source (e.g., a source terminal), a drain (e.g., a drain terminal), a channel between the source and drain, and a gate (e.g., a gate terminal). The conductivity of the channel can be controlled (e.g., modulated) by applying a voltage to the gate, which, in some examples, can cause the channel to become conductive. The switching component may be an example of an n-type FET or a p-type FET.

[0108] The description set forth herein, in conjunction with the accompanying drawings, describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0109] In the accompanying drawings, similar components or features may have the same reference label. Similar components can be distinguished by following the reference label with one or more dashes and an additional label that distinguishes the similar component. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, without regard to the additional reference labels.

[0110] The functions described herein may be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions may be stored on or transmitted over a computer-readable medium as one or more instructions (e.g., code). Due to the nature of software, the functions described herein may be implemented using software executed by a processing system, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may be physically located at various locations, including being distributed such that portions of the functions are implemented at different physical locations.

[0111] The illustrative blocks and modules described herein may be implemented or executed with one or more processors designed to perform the functions described herein, such as a DSP, an ASIC, an FPGA, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or other type of processor. A processor may also be implemented as at least one of one or more computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0112] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of ..." or "one or more of ...") indicates an inclusive list, such that a list such as at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" could be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0113] As used herein (including in the claims), the article "a" or "an" preceding a noun is open-ended and should be understood to refer to "at least one" of the noun or "one or more" of the noun. Thus, the terms "a," "at least one," "one or more," and "at least one of the one or more" are interchangeable. For example, if a claim lists "a component" that performs one or more functions, each of the individual functions may be performed by a single component or by any combination of multiple components. Thus, the term "a component" having a characteristic or performing a function may refer to "at least one of the one or more components" having a particular characteristic or performing a particular function. Subsequent reference to a component introduced with the article "a" using the term "the" or "said" may refer to any or all of the one or more components. For example, a component introduced with the article "a" may be understood to mean "one or more components," and subsequent reference to "said component" in the claims may be understood to be equivalent to referring to "at least one of the one or more components." Similarly, subsequent reference to a component introduced as "one or more components" using the term "the" or "said" may refer to any or all of the one or more components. For example, "the one or more components" mentioned later in a claim may be understood to be equivalent to referring to "at least one of the one or more components."

[0114] Computer-readable media includes both non-transitory computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media or combination of media that can be accessed by a computer. By way of example, but not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory media or combination of media that can be used to carry or store desired program code components in the form of instructions or data structures and that can be accessed by a computer or processor.

[0115] The description and drawings are provided to enable one of ordinary skill in the art to make or use the present disclosure. Various modifications of the present disclosure will be apparent to one of ordinary skill in the art, and the techniques disclosed herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory system comprising: memory unit; a digit line coupled to the memory cell; and a sense amplifier coupled to the digit line, the sense amplifier comprising: n-type transistors; and A p-type transistor comprising: source; drain; a channel positioned between the source and the drain, the channel comprising a dopant material configured to facilitate carrier flow between the source and the drain, the channel comprising: a first portion coupled to the source, the first portion including a first edge, a second edge opposite the first edge, a third edge extending between the first edge and the second edge, and a fourth edge opposite the third edge; and a second portion coupled to the drain, the second portion including a fifth edge, a sixth edge opposite the fifth edge, a seventh edge extending between the fifth edge and the sixth edge, and an eighth edge opposite the seventh edge; wherein the fifth edge of the second portion is offset from the first edge of the first portion by a first distance, wherein the sixth edge of the second portion is offset from the second edge of the first portion by a second distance, wherein the seventh edge of the second portion is offset from the third edge of the first portion by a third distance, and wherein a portion of the fourth edge of the first portion contacts a portion of the seventh edge of the second portion; and A gate is positioned above the channel and is configured to control the amount of the carriers flowing through the channel.

2. The memory system of claim 1 , wherein the gate comprises a ninth edge, a tenth edge opposite the ninth edge, an eleventh edge extending between the ninth edge and the tenth edge, and a twelfth edge opposite the eleventh edge, and Wherein the ninth edge is offset from the fifth edge of the second portion by a fourth distance different from the first distance and the tenth edge is offset from the second edge of the first portion by a fifth distance different from the second distance.

3. The memory system of claim 1 , wherein the sense amplifier further comprises: A second p-type transistor comprising: Second source; a second drain; a second channel positioned between the second source and the second drain, the second channel including the dopant material configured to facilitate carrier flow between the second source and the second drain, the second channel comprising: the second portion coupled to the second drain; and a third portion coupled to the second source, the third portion including a ninth edge, a tenth edge opposite to the ninth edge, an eleventh edge extending between the ninth edge and the tenth edge, and a twelfth edge opposite to the eleventh edge; and A second gate is positioned above the second channel and is configured to control a second amount of the carriers flowing through the second channel.

4. The memory system of claim 3 , wherein the ninth edge of the third portion is offset from the first edge of the first portion by a fourth distance different from the first distance and the tenth edge of the third portion is offset from the second edge of the first portion by a fifth distance different from the second distance.

5. The memory system of claim 3 , wherein the gate includes a thirteenth edge, a fourteenth edge opposite the thirteenth edge, a fifteenth edge extending between the thirteenth edge and the fourteenth edge, and a sixteenth edge opposite the fifteenth edge, wherein the second gate includes a seventeenth edge, an eighteenth edge opposite to the seventeenth edge, a nineteenth edge extending between the seventeenth edge and the eighteenth edge, and a twentieth edge opposite to the nineteenth edge, and The thirteenth edge is offset from the seventeenth edge by a fourth distance different from the first distance and the second distance, and the fourteenth edge is offset from the eighteenth edge by the fourth distance. 6 . The memory system of claim 1 , wherein the second edge of the first portion is disposed at an angle relative to the first edge of the first portion.

7. The memory system of claim 6, wherein the fifth edge of the second portion is disposed at the angle relative to the first edge of the first portion and the fifth edge of the second portion is parallel to the second edge of the first portion.

8. A memory system comprising: memory unit; a digit line coupled to the memory cell; and a sense amplifier coupled to the digit line, the sense amplifier comprising: n-type transistors; and A p-type transistor comprising: source; drain; a channel positioned between the source and the drain, the channel comprising a dopant material configured to facilitate carrier flow between the source and the drain, the channel comprising a first edge, a second edge opposite the first edge, a third edge extending between the first edge and the second edge, and a fourth edge opposite the third edge; and a gate positioned above the channel and configured to control the amount of the carriers flowing through the channel, the gate comprising: a first portion comprising a fifth edge, a sixth edge opposite the fifth edge, a seventh edge extending between the fifth edge and the sixth edge, and an eighth edge opposite the seventh edge, wherein the sixth edge of the first portion is aligned with a portion of the second edge, wherein the seventh edge of the first portion is offset from the third edge by a first distance, and wherein the eighth edge of the first portion is offset from the fourth edge by a second distance; and a second portion comprising a ninth edge, a tenth edge opposite the ninth edge, an eleventh edge extending between the ninth edge and the tenth edge, and a twelfth edge opposite the eleventh edge, wherein the tenth edge of the second portion contacts a portion of the fifth edge of the first portion, and wherein the ninth edge of the second portion is offset from the first edge.

9. The memory system of claim 8, wherein the eleventh edge of the second portion is offset from the third edge by a third distance and the twelfth edge of the second portion is offset from the fourth edge by a fourth distance.

10. The memory system of claim 8, wherein the fifth edge of the first portion is offset from the first edge by a third distance.

11. The memory system of claim 8, wherein the sense amplifier further comprises: A second p-type transistor comprising: Second source; a second drain; a second channel positioned between the second source and the second drain, the second channel including the dopant material configured to facilitate carrier flow between the second source and the second drain, the second channel including a thirteenth edge, a fourteenth edge opposite the thirteenth edge, a fifteenth edge extending between the thirteenth edge and the fourteenth edge, and a sixteenth edge opposite the fifteenth edge; and a second gate positioned above the channel and configured to control a second amount of the carriers flowing through the second channel, the second gate comprising: a third portion comprising a seventeenth edge, an eighteenth edge opposite the seventeenth edge, a nineteenth edge extending between the seventeenth edge and the eighteenth edge, and a twentieth edge opposite the nineteenth edge; wherein the seventeenth edge of the third portion is aligned with a portion of the thirteenth edge, wherein the nineteenth edge of the third portion is offset from the fifteenth edge by the first distance, and wherein the twentieth edge of the third portion is offset from the sixteenth edge by the second distance; and a fourth portion including a twenty-first edge, a twenty-second edge opposite the twenty-first edge, a twenty-third edge extending between the twenty-first edge and the twenty-second edge, and a twenty-fourth edge opposite the twenty-third edge, wherein the twenty-first edge of the fourth portion contacts a portion of the eighteenth edge of the third portion, and The twenty-second edge of the fourth portion is offset from the fourteenth edge.

12. The memory system of claim 11, wherein the thirteenth edge is offset from the second edge by a third distance and the seventeenth edge of the third portion is offset from the sixth edge of the first portion by the third distance.

13. A memory system comprising: memory unit; a digit line coupled to the memory cell; and a sense amplifier coupled to the digit line, the sense amplifier comprising: n-type transistors; and A p-type transistor comprising: source; drain; a channel positioned between the source and the drain, the channel comprising a dopant material configured to facilitate carrier flow between the source and the drain, the channel comprising: a first portion coupled to the source, the first portion comprising a first edge, a second edge opposite the first edge, a third edge extending between the first edge and the second edge, and a fourth edge opposite the third edge; a second portion coupled to the drain, the second portion including a fifth edge, a sixth edge opposite the fifth edge, a seventh edge extending between the fifth edge and the sixth edge, and an eighth edge opposite the seventh edge; and a third portion including a ninth edge, a tenth edge opposite the ninth edge, an eleventh edge extending between the ninth edge and the tenth edge, and a twelfth edge opposite the eleventh edge, wherein the eleventh edge of the third portion extends from the third edge of the first portion in a first direction and the twelfth edge of the third portion extends from the eighth edge of the second portion in the first direction; and a gate positioned above the channel and configured to control the amount of the carriers flowing through the channel, the gate comprising: a fourth portion comprising a thirteenth edge, a fourteenth edge opposite the thirteenth edge, a fifteenth edge extending between the thirteenth edge and the fourteenth edge, and a sixteenth edge opposite the fifteenth edge, wherein the thirteenth edge of the fourth portion is offset from the first edge of the first portion by a first distance, and wherein the fifteenth edge of the fourth portion is offset from the third edge of the first portion by a second distance and the sixteenth edge of the fourth portion is offset from the third edge of the first portion by a third distance; a fifth portion comprising a seventeenth edge, an eighteenth edge opposite the seventeenth edge, a nineteenth edge extending between the seventeenth and eighteenth edges, and a twentieth edge opposite the nineteenth edge; and a sixth portion including a twenty-first edge, a twenty-second edge opposite the twenty-first edge, a twenty-third edge extending between the twenty-first edge and the twenty-second edge, and a twenty-fourth edge opposite the twenty-third edge, A portion of the twenty-second edge of the sixth portion is aligned with the twelfth edge of the third portion.

14. The memory system of claim 13, wherein the seventeenth edge of the fifth portion is offset from the fifth edge of the second portion by the first distance.

15. The memory system of claim 13, wherein the twentieth edge of the fifth portion is offset from the eighth edge of the second portion by the second distance and the nineteenth edge of the fifth portion is offset from the eighth edge of the second portion by the third distance. 16 . The memory system of claim 13 , wherein the fourteenth edge of the fourth portion contacts a first portion of the twenty-first edge of the sixth portion and the eighteenth edge of the fifth portion contacts a second portion of the twenty-first edge of the sixth portion.

17. The memory system of claim 13, wherein the sense amplifier further comprises: A second p-type transistor comprising: Second source; a second drain; a second channel positioned between the second source and the second drain, the second channel including the dopant material configured to facilitate carrier flow between the second source and the second drain, the second channel comprising: a seventh portion coupled to the second source, the seventh portion including a twenty-fifth edge, a twenty-sixth edge opposite the twenty-fifth edge, a twenty-seventh edge extending between the twenty-fifth edge and the twenty-sixth edge, and a twenty-eighth edge opposite the twenty-seventh edge; an eighth portion coupled to the second drain, the eighth portion including a twenty-ninth edge, a thirtieth edge opposite the twenty-ninth edge, a thirty-first edge extending between the twenty-ninth edge and the thirtieth edge, and a thirty-second edge opposite the thirty-first edge; and a ninth portion comprising a thirty-third edge, a thirty-fourth edge opposite the thirty-third edge, a thirty-fifth edge extending between the thirty-third edge and the thirty-fourth edge, and a thirty-sixth edge opposite the thirty-fifth edge; wherein the thirty-fifth edge of the ninth portion extends from the twenty-seventh edge of the seventh portion in a second direction opposite to the first direction and the thirty-sixth edge of the ninth portion extends from the thirty-second edge of the eighth portion in the second direction; and a second gate positioned above the channel and configured to control a second amount of the carriers flowing through the channel, the gate comprising: a tenth portion comprising a thirty-seventh edge, a thirty-eighth edge opposite the thirty-seventh edge, a thirty-ninth edge extending between the thirty-seventh edge and the thirty-eighth edge, and a fortieth edge opposite the thirty-ninth edge; wherein the thirty-ninth edge of the tenth portion is offset from the twenty-seventh edge of the seventh portion by the second distance and the fortieth edge of the tenth portion is offset from the twenty-seventh edge of the seventh portion by the third distance; an eleventh portion comprising a forty-first edge, a forty-second edge opposite the forty-first edge, a forty-third edge extending between the forty-first edge and the forty-second edge, and a forty-fourth edge opposite the forty-third edge; and a twelfth portion comprising a forty-fifth edge, a forty-sixth edge opposite the forty-fifth edge, a forty-seventh edge extending between the forty-fifth edge and the forty-sixth edge, and a forty-eighth edge opposite the forty-seventh edge; Wherein a portion of the forty-fifth edge of the twelfth portion is aligned with the thirty-third edge of the ninth portion.

18. The memory system of claim 17, wherein the tenth edge of the third portion is offset from the thirty-third edge of the ninth portion by a fourth distance.

19. The memory system of claim 13, wherein the fourth edge of the first portion is offset from the seventh edge of the second portion by a fourth distance.

20. The memory system of claim 13, wherein the thirteenth edge of the fourth portion is offset from the twenty-first edge of the sixth portion by a fourth distance and the seventeenth edge of the fifth portion is offset from the twenty-first edge of the sixth portion by the fourth distance.

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