Storage and calculation integrated multiplier based on nonvolatile memory
By using Booth encoding and digital readout methods in nonvolatile memory, combined with Booth multiplication and decoding circuits, the problems of slow speed and high power consumption in high-precision calculations are solved, and efficient and accurate neural network calculations are achieved.
Patent Information
- Application Number
- CN202510576625.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-06
- Publication Date
- 2025-08-15
AI Technical Summary
The existing SRAM-based multiplier has problems such as slow computing speed, high power consumption and insufficient computing accuracy in high-precision computing, which is difficult to meet the needs of complex neural networks.
A memory-based integrated multiplier based on nonvolatile memory is used to store the multiplier using MRAM, and the calculation amount of part of the product is reduced through Booth encoding. Combined with the Booth multiplication decoding circuit, multiplication circuit, full adder tree and word line control circuit, digital readout and parallel calculation are realized.
It significantly improves the calculation speed and accuracy, reduces the number of calculation cycles, improves energy efficiency, and is suitable for high-precision neural network computing.
Smart Images
Figure CN120496599A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of artificial intelligence neural networks, and in particular to a storage-computation integrated multiplier based on a non-volatile memory. Background Art
[0002] With the development of artificial intelligence and IoT applications, neural networks have demonstrated remarkable performance in tasks such as classification, speech recognition, and face detection. However, traditional AI processors based on the von Neumann architecture, due to the separation of storage and computation, frequently transfer data and are limited by the "von Neumann bottleneck" or "memory wall." This leads to computational delays and high energy consumption when performing complex reasoning tasks. Integrated memory (CIM) computing is a highly competitive solution that improves energy efficiency by reducing data transfer and performing computations in parallel. CIM architectures based on non-volatile memory (NVM) are particularly attractive. Compared to SRAM-based CIM, NVM-based CIM avoids data loss due to storage volatility and significantly reduces static power consumption. Magnetoresistive random access memory (MRAM) is an ideal choice for CIM architectures due to its high energy efficiency, non-volatility, and high-speed read and write capabilities.
[0003] However, existing SRAM-based multipliers use static random access memory (SRAM) cells for data storage and perform multiplication operations by accumulating analog current or voltage. Although SRAM, composed of CMOS, has good read, write, and calculation speeds, it is inevitable that its static power consumption and power consumption during calculation are greater than those of non-volatile memory. In addition, its characterization method using analog current or voltage causes the calculation margin to continuously decrease as the calculation accuracy increases, thereby affecting the final calculation accuracy. The existing MRAM-CIM architecture is mostly used for low-precision calculations and cannot meet the high-precision reasoning requirements of complex neural networks. Therefore, it is crucial to study the application of high-precision, multi-bit multipliers in the storage and computing integrated architecture. Summary of the Invention
[0004] In view of the above problems existing in the prior art, the purpose of the present invention is to provide a storage-computation multiplier based on a non-volatile memory to solve the problems raised in the above background technology.
[0005] To achieve the above object, the present invention provides the following technical solutions:
[0006] A storage-computation integrated multiplier based on non-volatile memory includes a non-volatile memory array, a Booth multiplication decoding circuit, a multiplication circuit, a full adder tree, a word line control circuit, and a row and column decoder; the non-volatile memory array is electrically connected to the multiplication circuit, the Booth multiplication decoding circuit is electrically connected to the input end of the multiplication circuit, the word line control circuit is electrically connected to the non-volatile memory array, the row and column decoder is electrically connected to the non-volatile memory array, and the multiplication circuit is electrically connected to the full adder tree.
[0007] As a further solution of the present invention: the non-volatile memory array is composed of 16 rows and 8 columns of MRAM memory cells.
[0008] As a further solution of the present invention: each column of memory cells in the non-volatile memory array is connected to a sense amplifier SA, and each sense amplifier SA is connected to a reference circuit.
[0009] As a further solution of the present invention: the storage unit is electrically connected to the multiplication circuit via a sense amplifier SA.
[0010] As a further solution of the present invention: a bit line BL and a source line SL are provided on the memory cell; the bit line BL and the source line SL on each column of memory cells are the same.
[0011] As a further solution of the present invention: the Booth multiplication decoding circuit includes a data register and a decoder module.
[0012] As a further solution of the present invention: the data register output end and the decoder module input end are electrically connected.
[0013] As a further solution of the present invention: the output end of the decoder module in the Booth multiplication decoding circuit is connected to the input end of the multiplication circuit.
[0014] As a further solution of the present invention, the row and column decoders and word line control circuit are used to control the conduction and shutdown of the word lines and bit lines of the non-volatile memory array, and control the writing and reading of the non-volatile memory array.
[0015] As a further solution of the present invention: the function of the multiplication circuit is to perform multiplication operations based on the input data of the Booth multiplication decoding circuit and the weight data of the non-volatile memory array; the full adder tree is used to add and shift the results calculated by the multiplication circuit.
[0016] Compared with the prior art, the present invention has the following beneficial effects:
[0017] The present invention can convert corresponding multiplication inputs into four sets of operands and then convert these four sets of operands into corresponding enable signals for multiplication operations. By employing the Booth multiplication method and digital readout in a non-volatile memory array, the computational speed and accuracy are significantly improved compared to traditional non-volatile multiplication structures. The present invention utilizes MRAM to store the multiplicand and employs Booth encoding to reduce the computational complexity of partial products, thereby reducing the number of computational cycles, increasing computational parallelism, and significantly improving energy efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 The present invention is a schematic diagram of a circuit framework of a non-volatile memory-based storage and calculation integrated multiplier disclosed in an embodiment.
[0019] Figure 2 The present invention is a structural diagram of a non-volatile storage array in a non-volatile memory-based storage-computation integrated multiplier disclosed in an embodiment.
[0020] Figure 3 The present invention is a schematic diagram of an 8-bit Booth multiplication operation in a non-volatile memory-based storage and calculation integrated multiplier disclosed in an embodiment.
[0021] Figure 4 The present invention is a schematic diagram of a Booth multiplication decoding architecture in a non-volatile memory-based storage and calculation integrated multiplier disclosed in an embodiment.
[0022] Figure 5 The present invention is a structural diagram of a data register in a non-volatile memory-based storage and calculation integrated multiplier disclosed in an embodiment.
[0023] Figure 6 The present invention is a schematic diagram of the structure of a multiplication circuit in a non-volatile memory-based storage and calculation integrated multiplier disclosed in an embodiment. DETAILED DESCRIPTION
[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort shall fall within the scope of protection of the present invention.
[0025] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "provided with," "connected," and "connected" should be understood in a broad sense; for example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections via an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention in specific contexts.
[0026] This paper proposes an 8-bit, integrated memory-and-calculation multiplier based on nonvolatile memory, specifically designed to optimize multi-bit multiplication and accumulation (MAC) operations. This solution utilizes MRAM to store the multiplicand and employs Booth coding to reduce the computational complexity of partial products, thereby reducing the number of computation cycles, increasing computational parallelism, and significantly improving energy efficiency.
[0027] See also Figure 1-6 A storage-computation integrated multiplier based on non-volatile memory includes a non-volatile memory array, a Booth multiplication decoding circuit, a multiplication circuit, a full adder tree, a word line control circuit and a row and column decoder; the non-volatile memory array is electrically connected to the multiplication circuit, the Booth multiplication decoding circuit is electrically connected to the input end of the multiplication circuit, the word line control circuit is electrically connected to the non-volatile memory array, the row and column decoder is electrically connected to the non-volatile memory array, and the multiplication circuit is electrically connected to the full adder tree.
[0028] The non-volatile memory array consists of 16 rows and 8 columns of MRAM memory cells;
[0029] Each column of memory cells is connected to a sense amplifier SA, and each sense amplifier SA is connected to a reference circuit so as to read out the corresponding weight.
[0030] The memory cell is electrically connected to the multiplication circuit via the sense amplifier SA.
[0031] Traditional multiplication operations based on non-volatile memory involve connecting multiple memory cells in parallel and measuring the bitline discharge current. The resulting bitline current is then characterized to generate the calculated result. However, the in-memory multiplier circuit described in this paper utilizes a Booth multiplication decoder circuit as input to the multiplication circuit, significantly improving computational accuracy and doubling computational speed with its unique decoding circuit. The row and column decoders and wordline control circuits primarily control the conduction and blocking of the memory array's wordlines and bitlines, thereby controlling writes and reads from the memory array. The memory array consists of 16 rows and 8 columns of MRAM memory cells, capable of storing 16 8-bit data, which serve as weight multipliers in multiplication operations. These weights are typically immutable in neural network calculations and are therefore fixed after writing. Each column of memory cells is connected to a sense amplifier (SA), and each SA is also connected to a reference circuit to read the corresponding weights.
[0032] The Booth multiplication decoding circuit consists of a data register and a decoder module. The data register is used to store 16 8-bit input data. The decoder module, based on the Booth multiplication algorithm, converts the input data into a corresponding pattern and inputs it into the multiplication circuit according to specific rules for the next multiplication operation. The multiplication module performs multiplication operations based on the input data of the Booth multiplication decoding circuit and the weight data of the non-volatile memory array. The full adder tree performs operations such as addition and shifting on the results calculated by the multiplication circuit.
[0033] The data register output terminal is electrically connected to the decoder module input terminal.
[0034] The output end of the decoder module in the Booth multiplication decoding circuit is connected to the input end of the multiplication circuit.
[0035] The memory cells are provided with a bit line BL and a source line SL; the bit line BL and the source line SL on the memory cells in each column are the same.
[0036] The present invention constructs a non-volatile memory cell array, the circuit structure of which is as follows: Figure 2As shown. There is a bit line BL and source line SL on each column of an array, which are mainly used to read data. 1 bit of data is stored in it in the form of MTJ resistance state, high resistance state represents data "1" and low resistance state represents the number "0". Each storage cell stores 1 bit of weight data, and 8 columns constitute an 8-bit weight data. When performing a multiplication operation, the bit line BL on the left will first be precharged to a high potential. Secondly, the read word line transistors RWL of the corresponding row will all be turned on, and the bit line will be discharged at this time. Due to the different states of MRAM, the difference between high resistance state and low resistance state will cause the bit line discharge speed to be different, so that different data can be read. And the different weight data read out are input into the multiplication operation module for the next calculation.
[0037] The input data will be input into the multiplication calculation module through the special operation of the Booth multiplication decoding circuit. Conventional multiplication usually involves two stages: (1) multiplying the multiplier and the multiplicand to generate partial products; (2) adding the partial products in pairs to gradually reduce them into two groups until the final result is finally generated. For example, when two 8-bit data are multiplied, 8 partial products are first obtained through 8 cycles, and then the final result is obtained by adding them in pairs. This method not only has a long calculation cycle but also wastes computing resources. In order to further optimize the calculation method, the present invention adopts a Booth multiplication operation rule in this work. The Booth multiplication decoding circuit is a mature and effective method to reduce partial products to increase speed and reduce power consumption. The number of partial products reduced is related to the radix of the Booth algorithm. The larger the radix, the more partial products are reduced. Taking two 8-bit multiplications as an example, the 8-bit multiplier is first encoded into 4 operands. According to the operation principle, one operand can be generated for every 3 bits. Then, the 4 operands generated in the first step are transferred to the memory operation of the multiplicand. This step is called decoding, and partial products are generated. Finally, a series of addition operations are performed through the ripple carry adder to obtain the final result. Multiplying two 8-bit data will only produce 4 partial products, which saves half the time compared to ordinary multiplication operations. Figure 3 shown.
[0038] Table 1 Coding rules
[0039]
[0040]
[0041] Table 1 shows the truth table for the Booth algorithm. The three adjacent bits of the multiplier are defined as A, B, and C, and the encoding result is defined as Z. The multiplicand is then subjected to a specific operation based on the value of Z. When the encoding result is "0," the partial product is assigned 0. When the encoding result is "1," the partial product is the multiplicand itself. When the encoding result is "2," the partial product is twice the multiplicand. This is represented in binary by a left shift. When the encoding result is "-1," the multiplicand is inverted. The partial product is then compensated by one. When the encoding result is -2, the result must always be inverted and the partial product compensated. This also requires a bit shift.
[0042] First, let's deal with the zeroing case. The zeroing signal is applied to the enable pin of the adder tree. When "Z = 1," the enable pin is directly set to low, preventing any precharge steps in the adder and effectively disabling the adder. In the non-zero case, when Z is "-1," it indicates multiplying the multiplier by a negative number, requiring two operations: inversion and compensation. The inversion part is designed first. The SA used directly reads the weight data itself and its negative. Therefore, a signal selector easily selects the weight value or its negative. The compensation is added uniformly within the full adder tree, and the compensation data is stored in a register. When the value of Z is "2," in binary, multiplying the multiplicand by 2 is equivalent to shifting the partial product left by one bit. Therefore, its signal serves as the enable pin of the shift register. When the enable signal is high, it indicates that the value of Z is "2," shifting it left by one bit. When the value of Z is not "2", the enable terminal is low and no shifting is performed. Therefore, in this work, three signals are designed to complete my complete multiplication operation: zero signal, inverted signal and shift signal. Next, the main design structure of the three signals is introduced in detail, such as Figure 4 As shown in Table 2, each of the three operands of the input data is sequentially input into the multiplication decoding module, which correctly outputs three signals through the operation of the logic gates. The truth table of these signals is shown in Table 2.
[0043] Table 2 Signal truth table
[0044] A B C Zero Negation Displacement 0 0 0 1 0 - 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 1 1 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 1 1 -
[0045] The input data will be stored in the data register first, which uses the hardware description language to build its logical function. Its structure is as follows Figure 5As shown in the figure, its main function is to store 16 8-bit input data and input the four groups of operands of each round of data into the multiplication decoding structure in sequence. Adr[0:3] is the address input of the register; Data_In[0:7] is the input data interface of the register; CLK is the clock terminal; WEN is the write enable terminal of the register. When it is high, the register can be written; EN is the output enable terminal of the register. When it is high, the operands can be output in sequence.
[0046] The reading of weight data and the decoding of input data will be carried out simultaneously. After both are completed, they will be input into the multiplication module for partial product calculation. The main structure of the multiplication operation is as follows: Figure 6 As shown. The negation signal will be connected to the selection end of the data selector to select the weight data or negate it. The shift signal is connected to the enable end of the shift register. When the shift signal is high, the data will be shifted left by one position. The zeroing signal end will be directly connected to the enable end of the full adder tree. When the zeroing signal is high, no data will be added. In addition, compensation can be achieved through an adder, using the negation signal and the shift signal as enable signals. When the negation signal is high, the compensation operation is required and the adder starts working. According to the corresponding shift signal 0 or 1, the corresponding bit will be added by 1.
[0047] The decoding circuit and register circuit based on Booth multiplication operation in the present invention can convert the corresponding multiplication input into 4 groups of operands and convert the 4 groups of operands into corresponding enable signals for multiplication operation. The in-memory calculation multiplier structure based on non-volatile memory in the present invention adopts the Booth multiplication operation method and adopts the form of digital readout in the non-volatile memory array. This structure greatly improves the calculation speed and calculation accuracy compared with the traditional non-volatile multiplication structure. The multiplier circuit in the present invention is a structure that multiplies the enable signal converted from the operand with the weight data read out from the non-volatile memory array to obtain a partial product.
[0048] The present invention utilizes MRAM to store multiplicands and reduces the amount of calculation of partial products through Booth coding, thereby reducing the number of calculation cycles, increasing calculation parallelism, and significantly improving energy efficiency.
[0049] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-limiting. The scope of the invention is defined by the appended claims, not the foregoing description, and it is intended that all variations within the meaning and range of equivalents of the claims be encompassed within the present invention, and any reference signs in the claims should not be construed as limiting the claim to which they relate.
[0050] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.
Claims
1. A storage-computation integrated multiplier based on non-volatile memory, characterized in that: The invention comprises a non-volatile memory array, a Booth multiplication decoding circuit, a multiplication circuit, a full adder tree, a word line control circuit and a row and column decoder; the non-volatile memory array is electrically connected to the multiplication circuit, the Booth multiplication decoding circuit is electrically connected to the input end of the multiplication circuit, the word line control circuit is electrically connected to the non-volatile memory array, the row and column decoder is electrically connected to the non-volatile memory array, and the multiplication circuit is electrically connected to the full adder tree.
2. The non-volatile memory-based storage-computation integrated multiplier according to claim 1, characterized in that: The non-volatile memory array is composed of 16 rows and 8 columns of MRAM memory cells.
3. The non-volatile memory-based storage-computation integrated multiplier according to claim 2, characterized in that: Each column of memory cells in the nonvolatile memory array is connected to a sense amplifier SA, and each sense amplifier SA is connected to a reference circuit.
4. The non-volatile memory-based storage-computation integrated multiplier according to claim 3, characterized in that: The storage unit is electrically connected to the multiplication circuit via the sense amplifier SA.
5. The non-volatile memory-based storage-computation integrated multiplier according to claim 4, characterized in that: The memory cells are provided with a bit line BL and a source line SL; the bit line BL and the source line SL on the memory cells in each column are the same.
6. The non-volatile memory-based storage-computation integrated multiplier according to claim 1, characterized in that: The Booth multiplication decoding circuit includes a data register and a decoder module.
7. The non-volatile memory-based storage-computation integrated multiplier according to claim 6, characterized in that: The data register output end is electrically connected to the decoder module input end.
8. The non-volatile memory-based storage-computation integrated multiplier according to claim 7, characterized in that: The output end of the decoder module in the Booth multiplication decoding circuit is connected to the input end of the multiplication circuit.
9. The non-volatile memory-based storage-computation integrated multiplier according to claim 1, characterized in that: The row and column decoders and the word line control circuit are used to control the conduction and closing of the word lines and bit lines of the non-volatile memory array, and control the writing and reading of the non-volatile memory array.
10. The non-volatile memory-based storage-computation integrated multiplier according to claim 9, characterized in that: The function of the multiplication circuit is to perform multiplication operation based on the input data of the Booth multiplication decoding circuit and the weight data of the non-volatile memory array; the full adder tree is used to perform addition and shift operations on the results calculated by the multiplication circuit.