Memory structure, refreshing method and memory

Abstract

The invention relates to the field of semiconductor circuit design, in particular to a memory structure, a refresh method and a memory wherein the memory structure comprises: a refresh memory circuit arranged in a memory controller and used for storing a supplementary refresh address for indicating a memory cell having a defect in charge storage capability; a refresh register disposed in each of the plurality of memory blocks; wherein in the power-on process of the memory structure, the refresh memory circuit transmits a supplementary refresh address to a corresponding refresh register; and each storage block is configured to refresh the supplementary refresh address stored in the refresh register based on a full-memory-bank refresh command issued by the storage controller in the process of executing the full-memory-bank refresh command to refresh, so as to avoid negative effects caused by restoring a weak unit.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit design, and in particular to a memory structure, a refresh method, and a memory. Background Art

[0002] Memory is a storage component used to store programs and various data. Memory can be categorized as either volatile or non-volatile. Dynamic Random Access Memory (DRAM), a type of volatile memory, stores data by charging or discharging capacitors within its storage cells. This data is lost when power is removed. Non-volatile memory, on the other hand, retains stored data even when power is removed.

[0003] DRAM cell failures are inevitable during the manufacturing process, and they become more severe with process scaling. For example, the number of weak cells in DRAM is increasing. Weak cells are cells with reduced data retention time due to leakage.

[0004] Repairing weak cells is crucial to improving DRAM performance. Summary of the Invention

[0005] Embodiments of the present disclosure provide a memory structure, a refresh method, and a memory to avoid the negative impact caused by repairing weak cells.

[0006] An embodiment of the present disclosure provides a memory structure, which includes a memory controller and multiple memory blocks. The memory structure includes: a refresh storage circuit, which is arranged in the memory controller and is used to store a supplementary refresh address, where the supplementary refresh address is used to indicate a memory cell with a defective charge retention capability; a refresh register, which is arranged in each of the multiple memory blocks; wherein, during the power-on process of the memory structure, the refresh storage circuit transmits the supplementary refresh address to the corresponding refresh register; and each memory block is configured to refresh the supplementary refresh address stored in the refresh register during the process of executing the full-bank refresh command issued by the memory controller.

[0007] The supplementary refresh address is sent to the storage block. During the process of the storage block executing the full memory refresh command, the storage block also performs a refresh on the supplementary refresh address, that is, the storage block is also used to refresh each supplementary refresh address stored in the refresh register during the process of executing the full memory refresh command. Since the memory executes the full memory refresh command at a high frequency, the refresh interval between two adjacent supplementary refresh addresses is short, which can better preserve the data stored in the weak unit and avoid the negative impact of repairing the weak unit.

[0008] In some embodiments, the storage controller includes: a counting processing circuit, which is configured to count based on each refresh command to generate a refresh count value during the process of executing a full storage body refresh command for refresh; the counting processing circuit is also configured to generate and output an indication signal when the refresh count value meets a first preset value, and the indication signal is used to instruct the storage block to perform a refresh on the supplementary refresh address.

[0009] In some embodiments, the first preset value is set to be less than or equal to k, where k is set based on the capacity of the refresh register to store the supplementary refresh address.

[0010] In some embodiments, the counting processing circuit is further configured to reset the count when the refresh count value meets a second preset value; wherein the second preset value is set to an intermediate moment in the process of executing the full memory bank refresh command to perform refresh.

[0011] In some embodiments, each storage block includes: a selector, one input end for receiving a refresh address, another input end for receiving a supplementary refresh address, and a control end for receiving an indication signal; the selector is configured to output a supplementary refresh address based on an indication signal of a first level, and to output a refresh address based on an indication signal of a second level, and the refresh address is the address to be refreshed corresponding to the full storage body refresh command.

[0012] In some embodiments, the memory controller is further configured to output a refresh address masked by the indication signal.

[0013] In some embodiments, the refresh memory circuit is based on an anti-fuse memory array arrangement.

[0014] In some embodiments, the refresh storage circuit transmits the supplementary refresh address to the corresponding refresh register by broadcasting.

[0015] Another embodiment of the present disclosure also provides a refresh method, which is applied to the memory structure provided in the above embodiment, including: the storage controller transmits the set supplementary refresh address to the corresponding storage block; the storage block refreshes the supplementary refresh address during the process of executing the full storage body refresh command to refresh.

[0016] In some embodiments, a method for performing a refresh on a supplementary refresh address includes: in the process of executing a full storage body refresh command for refresh, counting based on each refresh command to generate a refresh count value; when the refresh count value meets a first preset value, generating and outputting a valid indication signal; if the indication signal is valid, performing a refresh on the supplementary refresh address; if the indication signal is invalid, not performing a refresh on the supplementary refresh address in the process of executing the full storage body refresh command for refresh.

[0017] In some embodiments, the first preset value is set to be less than or equal to k, where k is the capacity of the corresponding refresh register to store the supplementary refresh address.

[0018] In some embodiments, the method for performing a refresh on a supplementary refresh address further includes: resetting the refresh count when the refresh count meets a second preset value, the second preset value being set to an intermediate moment in the process of executing a full memory bank refresh command for refresh.

[0019] In some embodiments, the method of performing a refresh on a supplemental refresh address further includes: refreshing a refresh address covered by the supplemental refresh address.

[0020] Yet another embodiment of the present disclosure provides a memory, which is configured based on the memory structure provided in the above embodiments to avoid negative effects caused by repairing weak cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A schematic diagram of a memory structure provided in one embodiment of the present disclosure;

[0023] Figure 2 A schematic diagram illustrating the principle of a refresh control circuit according to an embodiment of the present disclosure sending a supplementary refresh address to a refresh register;

[0024] Figure 3 An embodiment of the present disclosure provides Figure 1 In the following example, a schematic diagram of the principle of refreshing the supplementary refresh address of a memory block is shown;

[0025] Figure 4An embodiment of the present disclosure provides Figure 1 In the example below, another schematic diagram of the principle of refreshing the supplementary refresh address of a memory block;

[0026] Figure 5 A schematic diagram of refreshing a supplementary refresh address during a refresh process of executing a full bank refresh command provided by an embodiment of the present disclosure;

[0027] Figure 6 A schematic diagram of refreshing a supplementary refresh address during a refresh process of executing a full bank refresh command provided by an embodiment of the present disclosure;

[0028] Figure 7 A schematic diagram of refreshing a supplementary refresh address during a refresh process of executing a full bank refresh command provided by an embodiment of the present disclosure;

[0029] Figure 8 A schematic diagram of refreshing a supplementary refresh address during a refresh process of executing a full bank refresh command provided by an embodiment of the present disclosure;

[0030] Figure 9 A flowchart of a refresh method provided in another embodiment of the present disclosure;

[0031] Figure 10 A flowchart of a specific refresh method provided in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] As we know from the background, memory cell failure is an inevitable problem during the DRAM manufacturing process, and with process scaling, the problem of memory cell failure becomes more severe. For example, the number of weak cells in DRAM is increasing. Weak cells are memory cells with reduced data retention time due to leakage.

[0033] Specifically, weak cells can be repaired using redundant addresses (redundancy WL / BL) in the memory, by increasing the overall memory refresh rate, or by merging two word lines (WL) into a single architecture. Repairing weak cells based on redundant addresses, which have a limited number of redundant addresses, can strain memory repair resources. Increasing the overall memory refresh rate increases overall memory power consumption, while merging two word lines (WL) reduces memory capacity.

[0034] It can be seen from this that the current repair methods for weak units will bring certain negative effects.

[0035] An embodiment of the present disclosure provides a memory structure to avoid the negative effects caused by repairing weak cells.

[0036] Those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments may be combined and referenced with each other as long as there is no contradiction.

[0037] The memory structure provided by this embodiment is described in detail below with reference to the accompanying drawings, as follows:

[0038] refer to Figure 1 , Figure 1 This is a schematic diagram of a memory structure provided by an embodiment of the present disclosure. The memory structure includes a memory controller 10 and multiple memory blocks 20 , and the memory structure includes: a refresh memory circuit 101 and a refresh register 102 .

[0039] Among them, the refresh storage circuit 101 is provided in the memory controller 10 and is used to store supplementary refresh addresses. The supplementary refresh addresses are used to indicate memory cells with defective charge retention capabilities. In other words, the refresh storage circuit 101 is used to store the addresses of weak cells. The refresh register 102 is provided in each of the multiple memory blocks 20. During the power-up process of the memory structure, the refresh storage circuit 101 transmits the supplementary refresh addresses to the corresponding refresh register 102. Each memory block 20 is configured to refresh the supplementary refresh addresses stored in the refresh register 102 during the execution of the full bank refresh command REFab issued by the memory controller 10.

[0040] Specifically, the supplementary refresh address stored in the refresh storage circuit 101 is obtained during the memory test phase. During the memory power-on process, the refresh storage circuit 101 transmits the stored supplementary refresh address to the refresh register 102 of the corresponding memory block 20. For example, referring to Figure 2 , Figure 2A schematic diagram illustrating the principle of a refresh control circuit issuing supplemental refresh addresses to a refresh register according to an embodiment of the present disclosure is provided. Assuming a memory structure includes 32 memory blocks, refresh register 1 is provided in memory block 1, refresh register 2 is provided in memory block 2, and refresh register 32 is provided in memory block 32. Refresh storage circuit 101 stores 2560 supplemental refresh addresses. During power-up of the memory structure, refresh storage circuit 101 issues supplemental refresh addresses 1-80 to memory block 1, and refresh register 1 is used to store supplemental refresh addresses 1-80. Refresh storage circuit 101 issues supplemental refresh addresses 80n-79-80n to memory block n, and refresh register n is used to store supplemental refresh addresses 80n-79-80n. Refresh storage circuit 101 issues supplemental refresh addresses 2481-2560 to memory block 32, and refresh register 32 is used to store supplemental refresh addresses 2481-2560.

[0041] In some embodiments, the refresh storage circuit 101 is configured based on an antifuse memory array. Specifically, based on the address of a weak memory cell obtained during the test phase, the memory device fuses the corresponding memory cell in the antifuse memory array, allowing the refresh storage circuit 101 to store the supplementary refresh address. The refresh storage circuit 101 configured with the antifuse memory array can relatively completely retain the set supplementary refresh address even if the memory structure loses power. In other embodiments, the refresh storage circuit can also store the supplementary refresh address using a register or capacitor.

[0042] In some embodiments, the refresh storage circuit 101 transmits the supplemental refresh address to the corresponding refresh register 102 via broadcast. Specifically, during the memory power-up process, the refresh storage circuit 101 transmits the stored supplemental refresh address to the refresh register 102 of the corresponding memory block 20 via broadcast to increase the speed of issuing the supplemental refresh address. In other embodiments, the refresh storage circuit can also be configured such that during the memory structure power-up process, based on a corresponding control signal, the supplemental refresh address is transmitted to the refresh register of the corresponding memory block.

[0043] The supplementary refresh address is sent to the storage block 20. During the process of the storage block 20 executing the full memory refresh command REFab, the storage block 20 also performs a refresh on the supplementary refresh address, that is, the storage block 20 is also used to refresh each supplementary refresh address stored in the refresh register 102 during the process of executing the full memory refresh command REFab. Since the memory executes the full memory refresh command REFab at a high frequency, the refresh interval between two adjacent supplementary refresh addresses is short, which can better preserve the data stored in the weak unit and avoid the negative impact of repairing the weak unit.

[0044] When the memory block 20 executes the full memory refresh command REFab, the memory block 20 performs a refresh on the supplementary refresh address. The principle is as follows: the full memory refresh command REFab is used to open a refresh window. In this refresh window, the memory block 20 performs a refresh on all addresses inside the memory block 20. In this refresh window, a plurality of sub-refresh commands are included. Each sub-refresh command is used to refresh two addresses, such as Figure 3 As shown, Figure 3 An embodiment of the present disclosure provides Figure 1 In the following example, a schematic diagram of the principle of refreshing the supplementary refresh address of a storage block is provided. Each sub-refresh command corresponds to a sub-refresh process cy. Assuming that the storage block includes N addresses, the storage block needs N / 2 sub-refresh processes cy to complete the refresh of N addresses, and the storage block also needs 40 sub-refresh processes to refresh 80 supplementary refresh addresses. The 40 sub-refresh processes are arbitrarily inserted into the process of N / 2 sub-refresh processes cy to achieve that the storage block also performs a refresh on the supplementary refresh address during the process of executing the full storage body refresh command REFab.

[0045] Since the memory block executes each sub-refresh process cy strictly in accordance with the timing, in some embodiments, reference Figure 3 , the 40 sub-refresh processes cy of the memory block refresh supplementary refresh address replace the 40 sub-refresh processes cy in the full memory bank refresh command REFab to perform the refresh of the supplementary refresh address. In some embodiments, reference Figure 4 , Figure 4 An embodiment of the present disclosure provides Figure 1 In the following example, a schematic diagram of the principle of refreshing the supplementary refresh address of another memory block is shown, where the 40 sub-refresh processes cy of the memory block refreshing the supplementary refresh address are inserted between the N / 2 sub-refresh processes cy in the full memory refresh command REFab, and then the remaining 40 sub-refresh processes cy in the full memory refresh command REFab are refreshed based on the additional tRC (Row Cycle Time) in the full memory refresh command REFab, that is, Figure 4 Where m = 40. Figure 4 For example, in some embodiments, the 40 sub-refresh processes cy of the supplementary refresh address can all be set in the tRC of the normal refresh in the full storage body refresh command REFab; or all can be set in the additional tRC in the full storage body refresh command REFab; or part can be set in the tRC of the normal refresh in the full storage body refresh command REFab, and part can be set in the additional tRC in the full storage body refresh command REFab.

[0046] It should be noted that Figure 4The m shown is at least greater than the number of sub-refresh processes required to completely refresh the supplementary refresh addresses. For example, if the number of supplementary refresh addresses stored in the refresh register is a, and each sub-refresh process is used to refresh b addresses, then m is at least greater than a / b.

[0047] In some embodiments, reference Figure 5 , Figure 5 A schematic diagram of the first method of refreshing a supplementary refresh address during a refresh of a full memory body refresh command is provided for one embodiment of the present disclosure. The storage controller 10 includes a counting processing circuit 104. The counting processing circuit 104 is configured to count based on each refresh command to generate a refresh count value during a refresh of a full memory body refresh command REFab. The counting processing circuit 104 is also configured to generate and output an indication signal when the refresh count value meets a first preset value. The indication signal is used to instruct the storage block 20 to refresh the supplementary refresh address.

[0048] Specifically, the count processing circuit 104 counts each refresh command one by one to generate a refresh count value. The refresh count value starts at 0 and is incremented by +1 based on each refresh command. When the refresh count value meets the first preset value, the supplemental refresh address is refreshed based on the refresh command. For example, when the first preset value is set to 8, 15, and 22, the supplemental refresh address is refreshed based on the 8th refresh command, the 15th refresh command, and the 22nd refresh command in the process of executing the full memory refresh command REFab to refresh the memory.

[0049] In some embodiments, reference Figure 5 and Figure 6 , Figure 6 A second schematic diagram of refreshing the supplementary refresh address during the execution of a full memory bank refresh command for refresh provided by an embodiment of the present disclosure, wherein each memory block 20 further includes a refresh control circuit 103, and the refresh control circuit 103 includes a selector 201, wherein one input end of the selector 201 is used to receive a refresh address, the other input end is used to receive a supplementary refresh address, and the control end is used to receive an indication signal. The selector 201 is configured to output a supplementary refresh address based on an indication signal of a first level, and to output a refresh address based on an indication signal of a second level, wherein the refresh address is the address to be refreshed corresponding to the full memory bank refresh command REFab. In one example, when the indication signal is at a high level, the selector 201 selects to output the supplementary refresh address, and when the indication signal is at a low level, the selector 201 selects to output the refresh address.

[0050] Based on the foregoing, it can be seen that the triggering of the indication signal depends on whether the refresh count value meets the first preset value, so that the refresh address of the supplementary refresh address is refreshed during the execution of the full memory refresh command REFab based on the first preset value configuration.

[0051] In some embodiments, reference Figure 7 , Figure 7 A third schematic diagram of refreshing the supplementary refresh address in the process of executing a full memory refresh command for refresh provided by an embodiment of the present disclosure, wherein the first preset value is set to be less than or equal to k, wherein k is a capacity setting of the supplementary refresh address stored based on the refresh register. Specifically, if the capacity of the supplementary refresh address that can be stored in the refresh register is c, each refresh command is used to refresh d addresses, and then k = c / d. Specifically, if the capacity of the supplementary refresh address that can be stored in the refresh register is 80, each refresh command is used to refresh 2 addresses, that is, 40 refresh commands are required to refresh the 80 supplementary refresh addresses stored in the refresh register, by setting k to 40, that is, in the refresh process of each full memory refresh command REFab, the refresh of the 80 supplementary refresh addresses is first performed, and then the refresh of the full memory refresh command REFab is started.

[0052] In some embodiments, reference Figure 8 , Figure 8 The fourth schematic diagram of refreshing the supplementary refresh address during the refresh process of executing a full memory refresh command is provided in an embodiment of the present disclosure. The counting processing circuit is further configured to reset when the refresh count value meets a second preset value. The second preset value is set to an intermediate moment in the process of executing a full memory refresh command. For example, if 32K addresses are refreshed during the refresh process of executing a full memory refresh command, after the refresh of 16K addresses is completed, the refresh count value is 16K / 2, that is, the second preset value is set to 8K. When the refresh count value reaches 8K, it is reset to 0 and the judgment of whether it meets the first preset value is restarted. That is, multiple refreshes of the supplementary refresh address are introduced during the refresh process of a full memory refresh command REFab to further ensure the accuracy of the data stored in the weak unit. In other embodiments, the second preset value can be configured to more values so that the supplementary refresh address is refreshed a configured number of times during the refresh process of a full memory refresh command REFab.

[0053] refer to Figure 6Because the refresh address and the supplemental refresh address are output based on the selection of selector 201, when selector 201 selects to output the supplemental refresh address, the indication signal at this time masks the refresh address. That is, the current refresh command should originally refresh the refresh address, but is currently used to refresh the supplemental refresh address. In some embodiments, the memory controller 10 is further configured to output the refresh address masked by the indication signal to prevent the refresh address from being missed during the refresh process of the full memory refresh command REFab.

[0054] For the memory structure provided in this embodiment, the supplementary refresh address is sent to the memory block 20. During the process of the memory block 20 executing the full memory refresh command REFab, the memory block 20 also performs a refresh on the supplementary refresh address, that is, the memory block 20 is also used to refresh each supplementary refresh address stored in the refresh register 102 during the process of executing the full memory refresh command REFab. Since the memory executes the full memory refresh command REFab at a high frequency, the interval between two adjacent refreshes of the supplementary refresh address is short, which can better preserve the data stored in the weak unit and avoid the negative impact of repairing the weak unit.

[0055] It should be noted that the features disclosed in the memory structures provided in the above embodiments can be arbitrarily combined without conflict to obtain new memory structure embodiments.

[0056] Another embodiment of the present disclosure provides a refresh method, which provides a way to refresh weak cells to avoid negative effects caused by repairing the weak cells.

[0057] The refresh method provided by this embodiment is described in detail below with reference to the accompanying drawings, as follows:

[0058] refer to Figure 9 , Figure 9 This is a flowchart of a refresh method provided by another embodiment of the present disclosure. The refresh method includes steps 301 to 303.

[0059] Step 301: Record the supplementary refresh address in the memory controller.

[0060] Specifically, the supplementary refresh address stored in the refresh storage circuit is obtained by the memory during the test phase.

[0061] In some embodiments, the refresh storage circuit is configured based on an antifuse storage array. Specifically, based on the address of a weak memory cell obtained during the test phase, the memory device fuses the corresponding memory cell in the antifuse storage array, allowing the refresh storage circuit 101 to store the supplementary refresh address. The refresh storage circuit configured with the antifuse storage array allows the set supplementary refresh address to be relatively intact even if the memory structure loses power. In other embodiments, the refresh storage circuit can also store the supplementary refresh address using a register or capacitor.

[0062] Step 302: The memory controller transmits the set supplementary refresh address to the corresponding memory block.

[0063] In some embodiments, the refresh storage circuit transmits the supplementary refresh address to the corresponding refresh register via broadcast. Specifically, during the memory power-up process, the refresh storage circuit transmits the stored supplementary refresh address to the refresh register of the corresponding memory block via broadcast to increase the speed of issuing the supplementary refresh address. In other embodiments, the refresh storage circuit can also be configured such that during the memory structure power-up process, based on a corresponding control signal, the supplementary refresh address is transmitted to the refresh register of the corresponding memory block.

[0064] Step 303 : While the memory block is being refreshed by executing the full memory refresh command, the memory block also refreshes the supplementary refresh address.

[0065] Specifically, the supplementary refresh address is sent to the storage block, and in the process of the storage block executing the full storage body refresh command REFab, the storage block also performs a refresh on the supplementary refresh address, that is, the storage block is also used to refresh each supplementary refresh address stored in the refresh register in the process of executing the full storage body refresh command REFab. Since the memory executes the full storage body refresh command REFab at a high frequency, the interval between two adjacent refreshes of the supplementary refresh address is short, which can better preserve the data stored in the weak unit and avoid the negative impact of repairing the weak unit.

[0066] In some embodiments, reference Figure 10 , Figure 10 This is a flowchart of a specific refresh method provided by another embodiment of the present disclosure, where step 303 includes steps 310 to 340.

[0067] Step 310: Generate / adjust a refresh count value.

[0068] Specifically, during the process of executing the full-bank refresh command to perform refresh, counting is performed based on each refresh command to generate a refresh count value.

[0069] In one example, the counting processing circuit counts one by one based on each refresh command to generate a refresh count value, where the refresh count value starts from 0 and is counted up by +1 based on each refresh command.

[0070] Step 320: Determine whether the refresh count value meets a first preset value.

[0071] Step 330 , performing a refresh on the supplementary refresh address.

[0072] Step 340: Perform a full memory refresh.

[0073] In steps 320 to 340, when the refresh count value meets the first preset value, a valid indication signal is generated and output. If the indication signal is valid, the supplemental refresh address is refreshed; if the indication signal is invalid, the full memory refresh process continues. After executing steps 330 and 340, step 310 is continued to adjust the refresh count value until the entire refresh process is completed by executing the full memory bank refresh command.

[0074] For example, when the first preset value is set to 8, 15, and 22, refreshing of the supplementary refresh address is performed based on the 8th refresh command, the 15th refresh command, and the 22nd refresh command in the process of executing the full memory refresh command REFab for refresh.

[0075] In some embodiments, the first preset value is set to be less than or equal to k, where k is set based on the capacity of the supplementary refresh addresses stored in the refresh register. Specifically, if the capacity of the supplementary refresh addresses that can be stored in the refresh register is c, each refresh command is used to refresh d addresses, then k=c / d.

[0076] Specifically, if the capacity of the supplementary refresh addresses that can be stored in the refresh register is 80, each refresh command is used to refresh 2 addresses, that is, 40 refresh commands are required to refresh the 80 supplementary refresh addresses stored in the refresh register. By setting k to 40, that is, in the refresh process of each full memory refresh command REFab, the refresh of the 80 supplementary refresh addresses is performed first, and then the refresh of the full memory refresh command REFab is started.

[0077] In some embodiments, the refresh method further comprises: determining whether the refresh count value meets a second preset value, and resetting the refresh count value when the refresh count value meets the second preset value, wherein the second preset value is set to an intermediate time during the refresh process of executing the full memory bank refresh command.

[0078] For example, if a refresh is performed on 32K addresses during the refresh process of executing a full bank refresh command, after the refresh of 16K addresses is completed, the refresh count value is 16K / 2, that is, the second preset value is set to 8K. When the refresh count reaches 8K, it is reset to 0, and the determination of whether it meets the first preset value is restarted. In other words, multiple refreshes of the supplementary refresh addresses are introduced during the refresh process of a full memory refresh command REFab to further ensure the accuracy of the data stored in the weak cells. In other embodiments, the second preset value can be configured to more values, so that the supplementary refresh addresses are refreshed a configured number of times during the refresh process of a full memory refresh command REFab.

[0079] refer to Figure 6 Because the refresh address and the supplemental refresh address are output based on the selector selection, when the selector selects to output the supplemental refresh address, the indication signal at this time masks the refresh address. That is, the current refresh command should originally refresh the refresh address, but is currently used to refresh the supplemental refresh address. In some embodiments, the refresh method further includes: during the execution of the full memory refresh process, refreshing the refresh address covered by the supplemental refresh address to prevent the refresh address from being missed during the refresh process of the full memory refresh command REFab.

[0080] It should be noted that the features disclosed in the refresh methods provided in the above embodiments can be arbitrarily combined without conflict to obtain new refresh method embodiments. In addition, this embodiment can be implemented in conjunction with the refresh control structure provided in the previous embodiment. The relevant technical details mentioned in the previous embodiment are still valid in this embodiment and will not be repeated here to reduce repetition.

[0081] Yet another embodiment of the present disclosure provides a memory, which is configured based on the memory structure provided in the above embodiments to avoid negative effects caused by repairing weak cells.

[0082] Specifically, for the memory structure provided in this embodiment, the supplementary refresh address is sent to the storage block. In the process of the storage block executing the full storage body refresh command, the storage block also performs a refresh on the supplementary refresh address, that is, the storage block is also used to refresh each supplementary refresh address stored in the refresh register in the process of executing the full storage body refresh command. Since the memory executes the full storage body refresh command at a high frequency, the interval between two adjacent refreshes of the supplementary refresh address is short, which can better preserve the data stored in the weak unit and avoid the negative impact of repairing the weak unit.

[0083] The memory device may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphics double data rate synchronous dynamic random access memory (GDDR SDRAM), double data rate type dual synchronous dynamic random access memory (DDR2 SDRAM), double data rate type triple synchronous dynamic random access memory (DDR3 SDRAM), double data rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM), thyristor random access memory (TRAM), etc.; or it may be a non-volatile memory, such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.

[0084] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A memory structure, characterized in that: The memory structure includes a memory controller and a plurality of memory blocks, and the memory structure includes: a refresh storage circuit, provided in the storage controller, for storing a supplementary refresh address, wherein the supplementary refresh address is used to indicate a storage unit having a defective charge retention capability; a refresh register, provided in each of the plurality of storage blocks; Wherein, during the power-on process of the memory structure, the refresh storage circuit transmits the supplementary refresh address to the corresponding refresh register; Each of the storage blocks is configured to, based on a full-bank refresh command issued by the storage controller, refresh the supplementary refresh address stored in the refresh register during a process of executing the full-bank refresh command for refreshing.

2. The memory structure according to claim 1, wherein: The storage controller includes: a counting processing circuit configured to, during a process of executing the full-bank refresh command to perform refresh, count based on each refresh command to generate a refresh count value; The count processing circuit is further configured to generate and output an indication signal when the refresh count value meets a first preset value, wherein the indication signal is used to instruct the memory block to perform a refresh on the supplementary refresh address.

3. The memory structure according to claim 2, wherein: The first preset value is set to be less than or equal to k, where k is set based on the capacity of the refresh register to store the supplementary refresh address.

4. The memory structure according to claim 2, wherein: The counting processing circuit is further configured to reset the count when the refresh count value meets a second preset value; wherein the second preset value is set to an intermediate moment in the process of executing the full memory bank refresh command to perform the refresh.

5. The memory structure according to any one of claims 2 to 4, characterized in that: Each of the storage blocks comprises: A selector, having one input terminal for receiving a refresh address, another input terminal for receiving the supplementary refresh address, and a control terminal for receiving the indication signal; The selector is configured to output the supplementary refresh address based on the indication signal of a first level, and output the refresh address based on the indication signal of a second level, wherein the refresh address is an address to be refreshed corresponding to the full-bank refresh command.

6. The memory structure according to claim 5, characterized in that The memory controller is further configured to output a refresh address masked by the indication signal.

7. The memory structure according to claim 1, wherein: The refresh storage circuit is arranged based on an anti-fuse storage array.

8. The memory structure according to claim 1, wherein: The refresh storage circuit transmits the supplementary refresh address to the corresponding refresh register by broadcasting.

9. A refresh method, applied to the memory structure according to any one of claims 1 to 8, characterized in that: include: The memory controller transmits the set supplementary refresh address to the corresponding memory block; The memory block refreshes the supplementary refresh address during a refresh process of executing the full bank refresh command.

10. The refreshing method according to claim 9, wherein: The method of performing a refresh on the supplementary refresh address includes: During the process of executing the full-bank refresh command to perform refresh, counting is performed based on each refresh command to generate a refresh count value; When the refresh count value meets the first preset value, a valid indication signal is generated and output; If the indication signal is valid, the supplementary refresh address is refreshed; if the indication signal is invalid, the supplementary refresh address is not refreshed during the refresh process of executing the full memory bank refresh command.

11. The refreshing method according to claim 10, wherein: The first preset value is set to be less than or equal to k, where k is the capacity of the corresponding refresh register for storing the supplementary refresh address.

12. The refreshing method according to claim 10, wherein: The method for refreshing the supplementary refresh address further includes resetting the refresh count value when the refresh count value meets a second preset value, wherein the second preset value is set to an intermediate moment in the process of executing the full memory bank refresh command to refresh.

13. The refreshing method according to claim 10, wherein: The method of performing a refresh on the supplementary refresh address further includes refreshing a refresh address covered by the supplementary refresh address.

14. A memory, characterized in that: The memory is configured based on the memory structure according to any one of claims 1 to 8.

Images