Half-bridge module packaging structure

Abstract

The invention provides a half-bridge module packaging structure which comprises a substrate and a power loop arranged on the substrate, a first end of a first pole layer is connected with a first terminal, a first end of a second pole layer is connected with a second terminal, a second end of the first pole layer is connected with a first end of an alternating current layer, and a second end of the alternating current layer is connected with a second terminal. The second end of the alternating current layer is connected with the alternating current terminal and the second end of the second pole layer at the same time; the first end of the first pole layer and the first end of the second pole layer are both located at one end of the substrate, and the second end of the alternating current layer and the second end of the second pole layer are both located at the other end of the substrate; the first pole layer and the alternating current layer form a first current path, the second pole layer is a second current path, and the current flow directions of the first current path and the second current path are opposite; the first end of the decoupling capacitor is connected with the first end of the first pole layer, and the second end of the decoupling capacitor is connected with the first end of the second pole layer. According to the invention, equivalent parasitic inductance in a high-frequency loop can be greatly reduced, and interference is avoided.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a half-bridge module packaging structure. Background Art

[0002] As global energy demand continues to grow, traditional power electronic devices experience significant energy losses during conversion and transmission. Wide-bandgap power semiconductor devices, such as SiC MOSFETs, offer low on-resistance and high switching frequency, significantly reducing switching and conduction losses, thereby improving energy efficiency. To meet the demands of high-current applications, SiC power modules often utilize multiple chips in parallel to increase current capacity. Current sharing performance is a crucial metric that cannot be ignored. Reduced current sharing performance can lead to a range of issues, including local overheating and thermal runaway, reduced efficiency and power density, accelerated device aging, and a dramatic reduction in device lifespan.

[0003] Currently, commercial silicon carbide power modules still use the packaging technology of traditional silicon IGBT modules, which causes the modules to generate large high-frequency parasitic parameters. In high-current applications, the unidirectional current flow path will make the impact of parasitic parameters more significant, resulting in uneven distribution of dynamic and static currents in parallel paths. Summary of the Invention

[0004] The present invention provides a half-bridge module packaging structure for solving the problem that the unidirectional current flow path in the above-mentioned high current application scenario will make the influence of parasitic parameters more significant, resulting in uneven distribution of dynamic and static currents in the parallel path.

[0005] The present invention provides a half-bridge module packaging structure, comprising: a substrate and a power circuit arranged on the substrate,

[0006] The power circuit includes: a first terminal, a second terminal, an AC terminal, a first pole layer, a second pole layer, an AC layer and a decoupling capacitor;

[0007] The first end of the first pole layer is connected to the first terminal, the first end of the second pole layer is connected to the second terminal, the second end of the first pole layer is connected to the first end of the AC layer, and the second end of the AC layer is connected to both the AC terminal and the second end of the second pole layer;

[0008] The first end of the first pole layer and the first end of the second pole layer are both located at one end of the substrate, and the second end of the AC layer and the second end of the second pole layer are both located at the other end of the substrate; the first pole layer and the AC layer form a first current path, and the second pole layer forms a second current path, and the currents in the first current path and the second current path flow in opposite directions;

[0009] The first end of the decoupling capacitor is connected to the first end of the first polar layer, and the second end of the decoupling capacitor is connected to the first end of the second polar layer.

[0010] Furthermore, the first terminal is located on one side of the decoupling capacitor, and the second terminal is located on the other side of the decoupling capacitor.

[0011] Furthermore, the first pole layer, the second pole layer and the AC layer are strip-shaped, the AC layer is located outside the first pole layer, the second pole layer is located outside the AC layer, and the first current path and the second current path are the same in length.

[0012] Furthermore, the power circuit also includes: a first bridge arm and a second bridge arm, the second end of the first pole layer is connected to the first end of the AC layer through the first bridge arm, the second end of the AC layer is connected to the second end of the second pole layer through the second bridge arm, the current flows in the first bridge arm and the second bridge arm are opposite, and the connection direction of the first bridge arm and the second bridge arm is perpendicular to the current direction.

[0013] Furthermore, the first bridge arm and the second bridge arm are both copper clips.

[0014] Furthermore, it includes two first pole layers, two second pole layers, two AC layers and two decoupling capacitors that are axially symmetrically distributed, the first ends of the two first pole layers are commonly connected to a first terminal, the first ends of the two second pole layers are respectively connected to two second terminals, the second ends of the two AC layers are commonly connected to the AC terminal, and the two decoupling capacitors are respectively located between the first ends of the two first pole layers and the first ends of the two second pole layers.

[0015] Furthermore, it also includes a driving circuit arranged on the substrate, the driving circuit includes a power chip and a driving terminal, the driving terminal includes a Kelvin source driving terminal and a gate driving terminal, the first bridge arm and the second bridge arm are respectively connected to the power chip, and the source driving terminal and the gate driving terminal are both connected to the power chip.

[0016] Furthermore, the driving circuit includes two driving terminals, namely a first driving terminal and a second driving terminal. The power chip of the first bridge arm is connected to the first driving terminal, and the power chip of the second bridge arm is connected to the second driving terminal.

[0017] Furthermore, it includes multiple first bridge arms and multiple second bridge arms, and the driving circuit also includes a driving copper layer and an aluminum bonding wire. Each of the first bridge arm and the second bridge arm is connected to one of the power chips. The power chips of the multiple first bridge arms are connected to the driving copper layer led out from the first driving terminal through the aluminum bonding wire, and the power chips of the multiple second bridge arms are connected to the driving copper layer led out from the second driving terminal through the aluminum bonding wire.

[0018] Furthermore, the first terminal, the second terminal and the AC terminal are all arranged perpendicular to the substrate.

[0019] It can be seen from the above technical solutions that the present invention has the following advantages: on the one hand, this embodiment constructs a first current path and a second current path with opposite current flows by optimizing the current path layout, thereby forming a reverse current flow path, and establishing a negative mutual inductance based on the principle of spatial magnetic field cancellation, thereby greatly reducing the equivalent parasitic inductance in the high-frequency circuit; on the other hand, due to the adoption of a reverse flow path layout, the distance between the first terminal and the second terminal is too close, and by arranging decoupling capacitors at the first end of the first pole layer and the first end of the second pole layer, that is, close to the first terminal and the second terminal, the inter-pole coupling capacitance can be effectively reduced, the coupling current can be reduced, and interference with the drive circuit can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 A top view of the SiC MOSFET half-bridge module packaging structure provided by an embodiment of the present invention;

[0022] Figure 2 A front view of the SiC MOSFET half-bridge module packaging structure provided by an embodiment of the present invention;

[0023] Figure 3 A left view of the SiC MOSFET half-bridge module packaging structure provided by an embodiment of the present invention;

[0024] Figure 4 A three-dimensional diagram of the SiC MOSFET half-bridge module packaging structure provided by an embodiment of the present invention;

[0025] Explanation of the accompanying drawings: 1. Substrate; 2. DBC substrate; 3. Power chip; 4. First polar layer; 5. Second polar layer; 6. AC layer; 7. First terminal; 8. Second terminal; 9. AC terminal; 10. Gate drive terminal; 11. Kelvin source drive terminal; 12. Drive copper layer; 13. Decoupling capacitor; 14. Aluminum bonding wire; 15. Copper clip. DETAILED DESCRIPTION

[0026] In order to make the purpose, features, and advantages of the present invention more obvious and easy to understand, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0027] The terms "first," "second," "third," "fourth," and so forth (if any) in the description and drawings of the present invention are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that, for example, the implementation of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, product, or apparatus.

[0028] See also Figures 1-4 , which is a high current sharing performance half-bridge module packaging structure suitable for high-voltage SiC MOSFET provided by an embodiment of the present invention.

[0029] An embodiment of the present invention provides a half-bridge module packaging structure, comprising: a substrate 1 and a power circuit arranged on the substrate 1,

[0030] The power circuit includes: a first terminal 7, a second terminal 8, an AC terminal 9, a first pole layer 4, a second pole layer 5, an AC layer 6 and a decoupling capacitor 13;

[0031] The first end of the first pole layer 4 is connected to the first terminal 7, the first end of the second pole layer 5 is connected to the second terminal 8, the second end of the first pole layer 4 is connected to the first end of the AC layer 6, the second end of the AC layer 6 is also connected to the AC terminal 9 and the second end of the second pole layer 5;

[0032] The first end of the first pole layer 4 and the first end of the second pole layer 5 are both located at one end of the substrate 1, and the second end of the AC layer 6 and the second end of the second pole layer 5 are both located at the other end of the substrate 1; the first pole layer 4 and the AC layer 6 form a first current path, and the second pole layer 5 forms a second current path. The currents in the first and second current paths flow in opposite directions.

[0033] A first end of the decoupling capacitor 13 is connected to a first end of the first electrode layer 4 , and a second end of the decoupling capacitor 13 is connected to a first end of the second electrode layer 5 .

[0034] It is understandable that, in specific implementation, on the one hand, this embodiment optimizes the current path layout to construct a first current path and a second current path with opposite current flows, thereby forming reverse current flow paths. Based on the principle of spatial magnetic field cancellation, a negative mutual inductance is established, thereby significantly reducing the equivalent parasitic inductance in the high-frequency circuit. At the same time, the magnetic fields generated by currents in opposite directions cancel each other, effectively reducing parasitic inductance and electromagnetic interference.

[0035] On the other hand, due to the adoption of a reverse flow path layout, the distance between the first terminal 7 and the second terminal 8 is too close. Specifically, the first end of the first pole layer 4, the first end of the second pole layer 5, and the first terminal 7 and the second terminal 8 are all concentrated at the same end of the substrate 1, and the distance between the power terminals is shortened, which in turn leads to an increase in the inter-pole coupling capacitance. In high-frequency working scenarios, the increase in the inter-pole coupling capacitance will cause an increase in the capacitive coupling current, causing interference to the drive circuit. To address this problem, by providing a decoupling capacitor 13 at the first end of the first pole layer 4 and the first end of the second pole layer 5, that is, close to the first terminal 7 and the second terminal 8, the inter-pole coupling capacitance can be effectively reduced, the coupling current can be reduced, and interference with the drive circuit can be avoided.

[0036] On the other hand, when SiC modules operate at high switching frequencies, they radiate high-frequency noise, such as conduction and radiated EMI, through the power circuit. Theoretically, the design of the reverse current flow path is based on the principle of spatial magnetic field cancellation, creating a negative mutual inductance that significantly reduces the equivalent parasitic inductance in the high-frequency circuit. This effectively suppresses variations in magnetic field strength around the power circuit, weakens the source of electromagnetic radiation, and reduces the amplitude of high-frequency noise. However, due to factors such as the complexity of the power circuit, component layout limitations, and uneven current distribution, complete magnetic field cancellation is difficult to achieve, and high-frequency noise still exists. To further suppress high-frequency noise, a decoupling capacitor 13 is connected in parallel directly between the starting and end points of the reverse current flow path, that is, between the positive and negative terminals. This decoupling capacitor 13 interacts with the parasitic inductance of the module's internal power circuit (stray inductance of the terminals and chip interconnects), leveraging the capacitor's low impedance at low frequencies and high impedance at high frequencies, which complements the parasitic inductance impedance, forming a second-order low-pass filter network. When the input frequency is less than the cutoff frequency (low frequency band), the filter presents low impedance, ensuring the smooth passage of low-frequency currents such as fundamental power signals; when the input frequency is greater than the cutoff frequency (high frequency band), the parasitic inductance dominates the impedance, and together with the capacitor, forms a high-impedance path, effectively attenuating high-frequency noise such as switching harmonics and ringing. In this way, the LC low-pass filter composed of the decoupling capacitor 13 and the loop inductance can filter out noise above the switching frequency of 100kHz-10MHz, significantly reducing the EMI amplitude. However, if the parasitic inductance is too high, it will seriously weaken the filtering effect of the decoupling capacitor 13, and even cause it to fail completely. The design of the reverse current flow path can just solve the problem of excessive parasitic inductance. The two work together to better improve the electromagnetic compatibility performance of the SiC module. Among them, the cutoff frequency is:

[0037]

[0038] Among them, L stray is the total parasitic inductance of the power circuit, C is the capacitance of the decoupling capacitor, f c is the cutoff frequency.

[0039] In a more specific embodiment, the first terminal 7 is located on one side of the decoupling capacitor 13 , and the second terminal 8 is located on the other side of the decoupling capacitor 13 .

[0040] It is understandable that, in specific implementation, the stacked design of power terminals in the past would result in a problem of close terminal spacing, which not only reduced the insulation gap between the terminals and reduced the insulation performance, but also blocked the heat dissipation path, increased thermal resistance, and affected long-term reliability. However, this embodiment avoids the close stacking layout of the first terminal 7 and the second terminal 8 by locating the first terminal 7 on one side of the decoupling capacitor 13 and the second terminal 8 on the other side of the decoupling capacitor 13. The first terminal 7 is located on the first side of the substrate 1, and the second terminal 8 is located on the second side of the substrate 1 perpendicular to the first side. This has significant advantages: on the one hand, it reduces the coupling capacitance between the first terminal 7 and the second terminal 8, effectively avoiding greater electromagnetic interference during high-frequency switching, and improving the current sharing performance of the module; on the other hand, this arrangement also greatly improves the insulation strength and thermal performance of the module.

[0041] In a more specific embodiment, the first pole layer 4, the second pole layer 5 and the AC layer 6 are strip-shaped, the AC layer 6 is located outside the first pole layer 4, the second pole layer 5 is located outside the AC layer 6, and the first current path is consistent with the second current path in length.

[0042] It is understandable that, in specific implementations, the strip-shaped structure constrains the current path, limits the current flow, avoids the direct use of large rectangular copper layers, reduces unnecessary copper loss, and thus reduces the module's parasitic inductance. Arranging the first pole layer 4, the AC layer 6, and the second pole layer 5 from the inside out makes the two reverse current paths straight and of equal length, forming a reverse flow loop. This further defines the magnetic field shape and area of action, promotes more complete spatial magnetic field cancellation, and significantly reduces the negative impact of parasitic inductance.

[0043] In a more specific embodiment, the power circuit also includes: a first bridge arm and a second bridge arm, the second end of the first pole layer 4 is connected to the first end of the AC layer 6 through the first bridge arm, the second end of the AC layer 6 is connected to the second end of the second pole layer 5 through the second bridge arm, the current flows in the first bridge arm and the second bridge arm are opposite, and the connection direction of the first bridge arm and the second bridge arm is perpendicular to the current direction.

[0044] It can be understood that, in a specific implementation, the first bridge arm and the second bridge arm construct a reverse current flow path, which further reduces the parasitic inductance in the loop.

[0045] In a more specific embodiment, the first terminal 7 is a DC+ power terminal, the second terminal 8 is a DC- power terminal, the first pole layer 4 is a positive pole layer, and the second pole layer 5 is a negative pole layer.

[0046] It should be noted that when the module is working, the current flows from the first terminal 7 into the first pole layer 4 and enters the power chip 3 of the first bridge arm, then flows through the AC layer 6 and the power chip 3 of the second bridge arm in sequence, and finally flows from the second pole layer 5 into the second terminal 8.

[0047] In a more specific embodiment, the first bridge arm and the second bridge arm are both copper clips 15 .

[0048] It is understandable that, in a specific implementation, by using the copper clip 15 as the bridge arm, the use of a large number of bonding wires can be avoided, thereby significantly reducing the parasitic inductance of the power loop.

[0049] In a more specific embodiment, it includes two first pole layers 4, two second pole layers 5, two AC layers 6 and two decoupling capacitors 13 that are axially symmetrically distributed. The first ends of the two first pole layers 4 are commonly connected to a first terminal 7, the first ends of the two second pole layers 5 are respectively connected to two second terminals 8, the second ends of the two AC layers 6 are commonly connected to the AC terminal 9, and the two decoupling capacitors 13 are respectively located between the first ends of the two first pole layers 4 and the first ends of the two second pole layers 5.

[0050] It is understandable that, in specific implementation, the first pole layer 4, the second pole layer 5, and the AC layer 6 of the copper layer on the substrate 1 of this embodiment are all etched into an axisymmetric structure and symmetrically distributed on the substrate 1. The internal layout of the power circuit of this embodiment is strictly symmetrical, which reduces the difference in parasitic parameters between the parallel branches. At the design level of the decoupling capacitor 13, the low-pass filter formed by the decoupling capacitor 13 and the parasitic inductance will affect the current sharing. The two decoupling capacitors 13 selected in this embodiment have excellent parameter consistency and good symmetry in the layout design. In the traditional power module design, when a capacitor is configured for each positive and negative terminal, the capacitors are usually concentrated in one place only by the terminal position design. This structure can only achieve static current balance between the parallel MOSFET and the diode, while the transient current difference of the parallel chips is still significant. This embodiment divides the second terminal 8 into two and optimizes the circuit layout so that the decoupling capacitor 13 is symmetrically distributed on both sides. Without destroying the reverse current flow path, the transient current difference of the chip on the left and right symmetrical flow path is greatly reduced, effectively avoiding the adverse effect of the low-pass filter on the current sharing.

[0051] In a more specific embodiment, a driving circuit is further included on the substrate 1, the driving circuit includes a power chip 3 and a driving terminal, the driving terminal includes a Kelvin source driving terminal 11 and a gate driving terminal 10, the first bridge arm and the second bridge arm are respectively connected to the power chip 3, and the Kelvin source driving terminal 11 and the gate driving terminal 10 are both connected to the power chip 3.

[0052] It is understandable that, in specific implementations, the common source connection method will cause the main circuit to cause significant interference to the drive signal. The Kelvin drive terminal separates the drive circuit from the power circuit by separately leading out the source sensing terminal of the switching device. In traditional power semiconductor drivers, the source or emitter is used for both power transmission and the drive signal circuit, while the Kelvin drive method provides an independent pin for the source, which is only used for feedback and control of the drive signal, so that the power current no longer passes through the drive signal circuit. This separation method can effectively reduce the negative impact of parasitic inductance. Parasitic inductance will cause voltage spikes and oscillations when the source current fluctuates greatly, while the Kelvin drive isolates the power circuit and the drive circuit, reducing these spikes. Therefore, in this embodiment, the source level of the power chip 3 of the first bridge arm is connected to the AC layer 6 through a copper clip 15, and the source level of the power chip 3 of the second bridge arm is connected to the second pole layer 5 through a copper clip 15. The power chips 3 of the first bridge arm and the second bridge arm are driven uniformly through the Kelvin source drive terminal 11 and the gate drive terminal 10, respectively. The drive circuit and the power circuit are isolated, the interference of the main circuit on the drive signal is eliminated, the switching time deviation is reduced, and the current sharing performance of the module is further improved.

[0053] In a more specific embodiment, the power chip 3 is a SiC MOSFET power chip.

[0054] In a more specific embodiment, two driving terminals are included, namely a first driving terminal and a second driving terminal. The power chip 3 of the first bridge arm is connected to the first driving terminal, and the power chip 3 of the second bridge arm is connected to the second driving terminal.

[0055] It is understandable that, in specific implementations, the first and second bridge arms have different operating states, and their current paths and voltage changes also differ. Using a shared drive terminal may result in mutual interference between the signals. For example, when the second bridge arm is turned on, a large current change may occur, causing fluctuations in the power supply voltage. If this fluctuation affects the drive signal of the upper bridge arm, it may cause malfunction of the power chip 3 in the first bridge arm. Providing independent drive terminals can isolate the drive signals of the first and second bridge arms, reducing the possibility of mutual interference and improving the stability and reliability of the circuit.

[0056] In a more specific embodiment, the drive circuit includes multiple first bridge arms and multiple second bridge arms, and further includes a drive copper layer 12 and an aluminum bonding wire 14. Each first bridge arm and each second bridge arm is connected to a power chip 3. The power chips 3 of the multiple first bridge arms are connected to the drive copper layer 12 extending from the first drive terminal through the aluminum bonding wire 14. The power chips 3 of the multiple second bridge arms are connected to the drive copper layer 12 extending from the second drive terminal through the aluminum bonding wire 14.

[0057] It is understandable that, in specific implementations, the power device capacity of a single bridge arm is limited. When driving high-power loads or providing high currents, multiple bridge arms connected in parallel can share the current, enabling the circuit to output higher power and meet the needs of high-power devices such as high-power motor drives and industrial inverters. For example, in the drive system of an electric vehicle, strong power is required to drive the motor, and a circuit composed of multiple bridge arms can provide sufficient current and power to enable the motor to output high torque and speed. On the other hand, the power chips 3 of multiple bridge arms are connected to the driving copper layer 12 led out from the driving terminal through the aluminum bonding wire 14. The driving copper layer 12 can serve as an intermediate connection layer to concentrate the connections of multiple power chips 3 together. Compared with direct connection with the driving terminal, the number of connection points between the bonding wire and the driving terminal is reduced, the complexity and difficulty of the connection are reduced, and the production efficiency and process reliability are improved. At the same time, by introducing the driving copper layer 12, the connection method of the aluminum bonding wire 14 and the copper layer can optimize the current path, reduce the influence of parasitic inductance and parasitic capacitance, improve the quality and stability of the driving signal, and enable the power chip 3 to respond to the driving signal more quickly and accurately, reducing switching loss and electromagnetic interference.

[0058] In a more specific embodiment, the first terminal 7 , the second terminal 8 and the AC terminal 9 are all arranged perpendicular to the substrate 1 .

[0059] It is understood that, in practice, a vertical arrangement can shorten and clearly define the wiring between terminals, reduce the risk of wire or pin crossover, and mitigate the effects of parasitic capacitance and inductance. This is particularly useful for high-frequency AC signals (such as AC terminal 9), effectively suppressing signal distortion and electromagnetic interference (EMI). For example, in a power module, positioning AC terminal 9 perpendicular to substrate 1 shortens the connection path to the filter capacitor, improving power supply stability.

[0060] In a more specific embodiment, the substrate 1 includes a DBC substrate 2, which has a two-layer structure, comprising an alumina ceramic substrate 1 and a copper layer. From top to bottom, the upper copper layer, upper ceramic layer, middle copper layer, lower ceramic layer, and lower copper layer are arranged. The upper copper layer within the half-bridge structure is divided into three parts: a first pole layer 4, a second pole layer 5, and an AC layer 6. Four parallel SiC MOSFET power chips for the first bridge arm are arranged on the first pole layer 4, and four parallel SiC MOSFET power chips for the second bridge arm are arranged on the AC layer 6, forming four symmetrical parallel branches, significantly reducing the parasitic inductance of the power circuit.

[0061] In a more specific embodiment, the first terminal 7 and the second terminal 8 are used to connect to a DC bus, and the AC terminal 9 is used to connect to a load.

[0062] In a more specific embodiment, the driver terminal is located at the center of the entire module. It is understood that, in a specific implementation, placing the driver terminal at the center ensures that the driver loop length of each chip is the same. This can avoid parasitic parameter differences caused by different loop lengths, synchronize switching between parallel chips, and balance current, which is conducive to long-term stable operation of the chips.

[0063] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features thereof can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A half-bridge module packaging structure, characterized in that: include: a substrate and a power circuit provided on the substrate, The power circuit includes: a first terminal, a second terminal, an AC terminal, a first pole layer, a second pole layer, an AC layer and a decoupling capacitor; The first end of the first pole layer is connected to the first terminal, the first end of the second pole layer is connected to the second terminal, the second end of the first pole layer is connected to the first end of the AC layer, and the second end of the AC layer is connected to both the AC terminal and the second end of the second pole layer; The first end of the first pole layer and the first end of the second pole layer are both located at one end of the substrate, and the second end of the AC layer and the second end of the second pole layer are both located at the other end of the substrate; the first pole layer and the AC layer form a first current path, and the second pole layer forms a second current path, and the currents in the first current path and the second current path flow in opposite directions; The first end of the decoupling capacitor is connected to the first end of the first polar layer, and the second end of the decoupling capacitor is connected to the first end of the second polar layer.

2. A half-bridge module packaging structure according to claim 1, characterized in that: The first terminal is located on one side of the decoupling capacitor, and the second terminal is located on the other side of the decoupling capacitor.

3. The half-bridge module packaging structure according to claim 1, characterized in that: The first pole layer, the second pole layer and the AC layer are strip-shaped. The AC layer is located outside the first pole layer, and the second pole layer is located outside the AC layer. The first current path and the second current path have the same length.

4. The half-bridge module packaging structure according to claim 3, characterized in that: The power circuit also includes: a first bridge arm and a second bridge arm, the second end of the first pole layer is connected to the first end of the AC layer through the first bridge arm, the second end of the AC layer is connected to the second end of the second pole layer through the second bridge arm, the current flows in the first bridge arm and the second bridge arm in opposite directions, and the connection direction of the first bridge arm and the second bridge arm is perpendicular to the current direction thereof.

5. The half-bridge module packaging structure according to claim 4, characterized in that: The first bridge arm and the second bridge arm are both copper clips.

6. A half-bridge module packaging structure according to any one of claims 1 to 5, characterized in that: It includes two first pole layers, two second pole layers, two AC layers and two decoupling capacitors that are axially symmetrically distributed. The first ends of the two first pole layers are commonly connected to a first terminal, the first ends of the two second pole layers are respectively connected to two second terminals, the second ends of the two AC layers are commonly connected to the AC terminal, and the two decoupling capacitors are respectively located between the first ends of the two first pole layers and the first ends of the two second pole layers.

7. The half-bridge module packaging structure according to claim 6, characterized in that: It also includes a driving circuit arranged on the substrate, the driving circuit includes a power chip and a driving terminal, the driving terminal includes a Kelvin source driving terminal and a gate driving terminal, the first bridge arm and the second bridge arm are respectively connected to the power chip, and the source driving terminal and the gate driving terminal are both connected to the power chip.

8. The half-bridge module packaging structure according to claim 7, characterized in that: The driving circuit includes two driving terminals, namely a first driving terminal and a second driving terminal. The power chip of the first bridge arm is connected to the first driving terminal, and the power chip of the second bridge arm is connected to the second driving terminal.

9. The half-bridge module packaging structure according to claim 7, characterized in that: It includes multiple first bridge arms and multiple second bridge arms, and the driving circuit also includes a driving copper layer and an aluminum bonding wire. Each of the first bridge arm and the second bridge arm is connected to one of the power chips. The power chips of the multiple first bridge arms are connected to the driving copper layer led out from the first driving terminal through the aluminum bonding wire, and the power chips of the multiple second bridge arms are connected to the driving copper layer led out from the second driving terminal through the aluminum bonding wire.

10. The half-bridge module packaging structure according to claim 1, characterized in that: The first terminal, the second terminal and the AC terminal are all arranged perpendicular to the substrate.

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