Laser chip, preparation method thereof and laser equipment
By setting grooves in the cutting area of the bar and penetrating the epitaxial layer, the problem of cavity marks during laser chip preparation is solved, and the performance and reliability of the laser chip are improved.
Patent Information
- Application Number
- CN202510668165.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-23
- Publication Date
- 2025-08-15
AI Technical Summary
During the preparation of laser chips, the difference in the lattice adaptation and thermal expansion coefficients of the epitaxial layer leads to uneven stress distribution at the interface during cleavage, resulting in cavity patterns, affecting the optical, electrical and reliability of the laser chip.
The trench is provided in the cutting area of the bar, and the trench penetrates part or all of the epitaxial layer, releases stress through the cleavage process, reduces the risk of cavity marks, and uses an etching process to form trenches to improve accuracy and avoid damage to the chip area.
It improves the optical, electrical and structural reliability of the laser chip, reduces the risk of cavity patterns, and improves the performance stability and reliability of the laser chip.
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Figure CN120497757A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of laser devices, and in particular to a laser chip, a preparation method thereof, and a laser device. Background Art
[0002] A laser bar typically consists of a substrate and an epitaxial layer formed of semiconductor material on the substrate. During the laser chip fabrication process, the bar is typically cleaved, for example, by mechanically splitting the bar along its natural cleavage planes to form smooth cavity surfaces, thereby cutting the bar into multiple independent laser chips. However, because the epitaxial layer is typically composed of brittle semiconductor materials (such as gallium arsenide and indium phosphide), differences in lattice matching or thermal expansion coefficients between the epitaxial layers during the bar cleavage process can lead to uneven stress distribution at the cleavage interface, resulting in cavity lines. If cavity lines extend into the epitaxial layer, they can easily degrade the optical and electrical performance and reliability of the laser chip. Summary of the Invention
[0003] Based on this, it is necessary to provide a laser chip, a preparation method thereof and a laser device to address the problem that the cavity lines generated in the epitaxial layer during cleavage easily affect the optical performance, electrical performance and reliability of the laser chip.
[0004] A method for preparing a laser chip, comprising: Providing a bar, the bar comprising a substrate and an epitaxial layer stacked in a first direction, the bar having chip regions and cutting regions alternately arranged in sequence along a second direction, the first direction and the second direction being perpendicular to each other; providing a groove in the cutting area, wherein the groove penetrates at least a portion of the epitaxial layer in the first direction; The bar is cleaved at the groove to separate the plurality of chip regions into a plurality of laser chips.
[0005] In the aforementioned laser chip fabrication method, grooves are first formed in the cut areas of the bar before cleaving the bar to form multiple laser chips. The bar is then cleaved in the grooves. Because the grooves penetrate at least a portion of the epitaxial layer, they relieve stress in the epitaxial layer during the cleavage process, reducing the risk of cavity lines forming in the epitaxial layer due to stress concentration, or the risk of cavity lines formed in the substrate extending into the epitaxial layer. This improves the optical, electrical, and reliability of the resulting laser chip. In one embodiment, the strip has two side surfaces facing each other in a third direction. During the step of forming a groove in the cutting area, the groove extends through the two side surfaces along the third direction, which is perpendicular to the first and second directions. Thus, the groove covers the entire chip area in the third direction, maximally relieving stress in the epitaxial layer and reducing the risk of cavity lines in the epitaxial layer.
[0006] In one embodiment, in the step of forming a groove in the cutting area, both sides of the groove in the second direction are spaced apart from the chip area, thereby preventing damage to the chip area during the groove formation and cleavage processes.
[0007] In one embodiment, the bar further includes a first electrode layer disposed on a side of the epitaxial layer facing away from the substrate. The first electrode layer is located in the chip region, and opposite sidewalls of the trench in the second direction are spaced apart from the first electrode layer in the second direction. This prevents damage to the first electrode layer during trench formation.
[0008] In one embodiment, during the step of cleaving the strip at the groove, the strip is cut along the bottom wall of the groove in the middle portion in the second direction. This allows the cleavage process to adapt to the groove configuration, effectively relieving stress in the epitaxial layer. Furthermore, the cleavage location is located away from the chip area, making it less likely for the cleavage process to affect the chip area.
[0009] In one embodiment, the epitaxial layer includes a first contact layer, a first cladding layer, a first waveguide layer, an active layer, a second waveguide layer, and a second cladding layer, stacked in sequence along the first direction from the epitaxial layer toward the substrate. During the step of providing a groove in the cutting region, the groove extends from the first contact layer through at least the active layer along the first direction. In this manner, the groove effectively relieves stress in the epitaxial layer, preventing the formation of cavity lines in at least the portion of the epitaxial layer corresponding to the active layer, thereby effectively reducing the impact of cavity lines on the performance and structural reliability of the laser chip.
[0010] In one embodiment, in the step of providing the grooves in the cutting area, the grooves are formed using an etching process. Using an etching process to form the grooves can improve the groove setting accuracy and reduce the impact of the groove setting on the chip area.
[0011] A laser chip is manufactured using the manufacturing method described in any of the above embodiments. The laser chip manufactured using the above manufacturing method is less likely to have cavity lines in the epitaxial layer, thereby improving the performance and structural reliability of the laser chip.
[0012] In one embodiment, two cavity surfaces of the laser chip facing each other in the second direction are each provided with a step groove formed by sidewalls and a bottom wall. The step groove is formed in an area outside the first electrode layer of the laser chip and is unlikely to affect the performance and structural reliability of the laser chip.
[0013] A laser device includes the laser chip described in any of the above embodiments. The laser chip is used in the laser device, and has good optical and electrical properties and structural reliability, thereby improving the beam quality and structural reliability of the laser device. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 Schematic diagram of the process of preparing a laser chip in some embodiments.
[0015] Figure 2 Schematic diagram of the structure of the bar in some embodiments.
[0016] Figure 3 Schematic diagram of the structure of the laser chip in some embodiments.
[0017] Figure 4 Schematic diagram of the structure of the bar at another angle in some embodiments.
[0018] Figure 5 Schematic diagram of the structure in which the bar is provided with grooves in some embodiments.
[0019] Figure 6 FIG. 1 is a schematic structural diagram of a bar with grooves at another angle in some embodiments. FIG.
[0020] Reference numerals: 10. Bar; 11. Substrate; 12. Epitaxial layer; 121. First contact layer; 122. First cladding layer; 123. First waveguide layer; 124. Active layer; 125. Second waveguide layer; 126. Second cladding layer; 127. Buffer layer; 13. Chip area; 14. Cutting area; 15. Groove; 16. First electrode layer; 17. Second electrode layer; 18. Insulating layer; 20. Laser chip; 21. Step groove; 31. First direction; 32. Second direction; 33. Third direction. DETAILED DESCRIPTION
[0021] To make the above-mentioned objects, features, and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.
[0022] In the description of this application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.
[0023] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include at least one of such features. In the description of this application, if the term "plurality" appears, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.
[0024] In this application, unless otherwise specified or limited, the terms "mounted," "connected," "connected," "fixed," etc., should be interpreted broadly. For example, these terms may refer to fixed connections, removable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediary; and internal communication between two components or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.
[0025] In this application, unless otherwise expressly specified or limited, if a first feature is described as being "above" or "below" a second feature, or similar descriptions, this may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is described as being "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is described as being "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.
[0026] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only embodiment.
[0027] See Figure 1 、 Figure 2 and Figure 3 , Figure 1 Schematic diagram showing the process of the method for preparing the laser chip 20 in some embodiments of the present application, Figure 2 Schematic diagram of the structure of the bar 10 in some embodiments of the present application is shown. Figure 3 Schematic diagram of the structure of the laser chip 20 in some embodiments. This application provides a method for preparing the laser chip 20, for example, for cleaving a bar 10 into multiple independent laser chips 20. The laser chips 20 involved in this application include, but are not limited to, any applicable type, such as edge-emitting lasers.
[0028] Combine Figure 2 and Figure 4 As shown, in some embodiments, the method for preparing the laser chip 20 includes the following steps: S110 , providing a strip 10 , the strip 10 including a substrate 11 and an epitaxial layer 12 stacked in a first direction 31 , the strip 10 having chip regions 13 and cutting regions 14 alternating in sequence along a second direction 32 , the first direction 31 and the second direction 32 being perpendicular to each other.
[0029] When the bar 10 is roughly shaped like a cube, the first direction 31 can be the thickness direction of the bar 10, and the second direction 32 can be the length direction of the bar 10. Depending on the type of laser chip 20 to be fabricated, the substrate 11 can be made of either a conductive or insulating material. After the bar 10 is cleaved to form multiple independent laser chips 20, the substrate 11 forms the substrate 11 of the laser chip 20. The substrate 11 provides structural support and heat dissipation for the laser chip 20. The epitaxial layer 12 can be formed by depositing thin semiconductor layers layer by layer on the substrate 11 using epitaxial growth techniques (such as metal-organic chemical vapor deposition or molecular beam epitaxy). Materials for the epitaxial layer 12 include, but are not limited to, indium gallium arsenide (InGaAs), gallium nitride (GaN), aluminum gallium arsenide (AlGaAs), gallium arsenide (GaAs), and the like. After the bar 10 is cleaved to form multiple independent laser chips 20, the epitaxial layer 12 of the bar 10 corresponds to the epitaxial layer 12 of multiple laser chips 20. The epitaxial layer 12 can play a role in forming an active region, limiting carriers and photons, and constructing a PN junction and electrical structure in the laser chip 20.
[0030] In step S110 , the cutting region 14 refers to a region to be cleaved, and the plurality of chip regions 13 are separated into a plurality of independent laser chips 20 after cleavage. Figure 2 Two chip regions 13 are indicated by two dotted boxes. Figure 4 In the figure, one chip area 13 is indicated by a dotted line frame, and one cutting area 14 is indicated by two spaced dotted lines.
[0031] S120 , forming a trench 15 in the cutting region 14 , wherein the trench 15 penetrates at least a portion of the epitaxial layer 12 in the first direction 31 .
[0032] The strip 10 may include two surfaces facing each other in a first direction 31, one of which is located on the side of the epitaxial layer 12 facing away from the substrate 11, and the other is located on the side of the substrate 11 facing away from the epitaxial layer 12. In step S120, a trench 15 may extend from the surface of the strip 10 located on the side of the epitaxial layer 12 facing away from the substrate 11 in the first direction 31 and penetrate at least a portion of the epitaxial layer 12. The trench 15 does not extend to the substrate 11 to avoid affecting the structural reliability of the fabricated laser chip 20.
[0033] refer to Figure 5 and Figure 6 As shown, S130 , the bar 10 is cleaved at the groove 15 to separate the plurality of chip regions 13 into a plurality of laser chips 20 .
[0034] In step S130, the bar 10 may be cut and cleaved at the bottom wall of the groove 15. Figure 6The dotted lines in the figure indicate the cutting paths during cleavage in some of the embodiments.
[0035] In the above-described method for fabricating the laser chip 20, grooves 15 are first formed in the cut region 14 of the bar 10 before cleaving the bar 10 to form multiple laser chips 20. The bar 10 is then cleaved at the grooves 15. Because the grooves 15 penetrate at least a portion of the epitaxial layer 12, they can relieve stress in the epitaxial layer 12 during the cleavage process, reducing the risk of cavity lines in the epitaxial layer 12 due to stress concentration, or the risk of cavity lines formed in the substrate 11 extending into the epitaxial layer 12. As a result, the epitaxial layer 12 of the laser chip 20 fabricated using the above-described method is less susceptible to cavity lines, thereby improving the optical, electrical, and reliability of the resulting laser chip 20.
[0036] refer to Figure 5 As shown, in some embodiments, the bar 10 has two side surfaces (eg, Figure 5 The third direction 33 is perpendicular to the first direction 31 and the second direction 32, and the third direction 33 can be the width direction of the bar 10. It can be understood that when the laser chip 20 is an edge-emitting laser, the two side surfaces form the high-reflection surface and the low-reflection surface of the laser chip 20 after cleavage. In step S120, the groove 15 runs through the two side surfaces along the third direction 33, that is, the groove 15 can be observed on both sides of the bar 10. In this way, the groove 15 covers the entire chip area 13 in the third direction 33, which can release the stress of the epitaxial layer 12 to the greatest extent, reduce the risk of cavity lines in the epitaxial layer 12, and also help to simplify the groove 15 formation process and reduce the difficulty of forming the groove 15.
[0037] refer to Figure 5 and Figure 6 As shown, in some embodiments, in step S120, both sides of the formed trench 15 in the second direction 32 are spaced apart from the chip region 13. For example, the trench 15 can be formed in the middle of the dicing region 14 in the second direction 32. In this way, the trench 15 is spaced apart from the chip region 13, which can prevent the chip region 13 from being damaged during the formation process of the trench 15 and the cleavage process at the trench 15.
[0038] refer to Figure 3 、 Figure 5 and Figure 6As shown, in some embodiments, the bar strip 10 further includes a first electrode layer 16 disposed on the side of the epitaxial layer 12 facing away from the substrate 11. The first electrode layer 16 is located in the chip region 13. For example, the first electrode layer 16 may include hollow grooves spaced sequentially along the second direction 32. The portions of the epitaxial layer 12 corresponding to the hollow grooves are uncovered by the first electrode layer 16, forming the cutting region 14 of the bar strip 10. The opposing side walls of the groove 15 in the second direction 32 are spaced apart from the first electrode layer 16 on both sides of the groove 15 in the second direction 32. This arrangement prevents damage to the first electrode layer 16 during the formation of the groove 15, thereby improving the electrical performance of the laser chip 20.
[0039] In some embodiments, the bar 10 may further include a second electrode layer 17 disposed on the side of the substrate 11 facing away from the epitaxial layer 12. After the bar 10 is cleaved to form a plurality of laser chips 20, the first electrode layer 16 may form the P-side electrode layer of the laser chip 20, and the second electrode layer 17 may form the N-side electrode layer of the laser chip 20.
[0040] In some embodiments, the bar 10 further includes an insulating layer 18 positioned between the first electrode layer 16 and the epitaxial layer 12. The insulating layer 18 has a hollowed-out portion within the chip region 13 in the second direction 32, and the first electrode layer 16 fills the hollowed-out portion of the insulating layer 18. After the bar 10 is cleaved to form multiple laser chips 20, the hollowed-out portion of the insulating layer 18 corresponds to the current injection region for the laser chips 20. The portion of the first electrode layer 16 within the hollowed-out portion of the insulating layer 18 contacts the epitaxial layer 12 and is used to inject current into the epitaxial layer 12, enabling the laser chips 20 to emit laser light.
[0041] refer to Figure 6 As shown, in some embodiments, in step S130, the bar 10 is cut along the middle position of the bottom wall of the groove 15 in the second direction 32, for example, Figure 6 The cutting path shown by the dotted line is located at the middle position of the bottom wall of the groove 15 in the second direction 32. With this arrangement, the cleavage process can adapt to the arrangement of the groove 15, so that the groove 15 can effectively release the epitaxial layer 12. At the same time, the cutting position is away from the chip area 13 and the first electrode layer 16, and the chip area 13 is not easily affected during the cleavage process.
[0042] exist Figure 6 In the embodiment shown, the groove 15 penetrates the entire epitaxial layer 12 along the first direction 31, that is, the bottom wall of the groove 15 corresponds to the surface of the substrate 11 facing the epitaxial layer 12, which can effectively release the stress of the entire epitaxial layer 12 and effectively reduce the risk of cavity lines in the epitaxial layer 12.
[0043] Of course, in some embodiments, the trench 15 may also only penetrate a portion of the epitaxial layer 12. Figure 3 and Figure 6 As shown, in some embodiments, along a first direction 31 from the epitaxial layer 12 toward the substrate 11, the epitaxial layer 12 includes a first contact layer 121, a first cladding layer 122, a first waveguide layer 123, an active layer 124, a second waveguide layer 125, a second cladding layer 126, and a buffer layer 127, which are stacked in sequence. The first contact layer 121 is used to form an ohmic contact with the first electrode layer 16 to reduce resistance and facilitate current injection. The first cladding layer 122 and the second cladding layer 126 are used to form a potential barrier to prevent electrons and holes from diffusing out of the active layer 124. The active layer 124 is used to generate stimulated emission. The first waveguide layer 123 and the second waveguide layer 125 are used to form an optical waveguide structure and optimize mode distribution. The buffer layer 127 is used to reduce the lattice mismatch between the epitaxial layer 12 and the substrate 11, thereby reducing defects in the laser chip 20.
[0044] In some embodiments, in step S120, the trench 15 extends from the first contact layer 121 along the first direction 31 through at least the active layer 124. The trench 15 may completely penetrate the active layer 124, so that the bottom wall of the trench 15 corresponds to the side of the second waveguide layer 125 facing the active layer 124. The trench 15 may also penetrate any one or more of the second waveguide layer 125, the second cladding layer 126, and the buffer layer 127. In this way, the trench 15 has a sufficient penetration length in the first direction 31 to effectively relieve stress in the epitaxial layer 12, prevent the formation of cavity lines in at least the portion of the epitaxial layer 12 corresponding to the active layer 124, and effectively reduce the impact of cavity lines on the performance and structural reliability of the laser chip 20.
[0045] In some embodiments, in step S120, an etching process may be used to form the grooves 15. Using an etching process to form the grooves 15 can improve the accuracy of the groove 15, prevent the grooves 15 from damaging the first electrode layer 16 and the portion of the epitaxial layer 12 located in the chip region 13, and reduce the impact of the grooves 15 on the chip region 13, thereby improving the performance stability and structural reliability of the laser chip 20. Of course, in step S120, the process for forming the grooves 15 includes, but is not limited to, photolithography, dry etching, wet etching, laser etching, ion beam etching, or any other suitable process, as long as the formed grooves 15 can relieve the stress of the epitaxial layer 12 in step S130.
[0046] refer to Figure 3 As shown, the present application further provides a laser chip 20, including but not limited to an edge-emitting laser, and manufactured using the manufacturing method described in any of the above embodiments. Laser chip 20 manufactured using the above manufacturing method is less likely to produce cavity lines in epitaxial layer 12, thereby improving the performance stability and structural reliability of laser chip 20.
[0047] It is understood that because the bar 10 is cut at the bottom wall of the groove 15 in step S130, the two cavity surfaces of the prepared laser chip 20 facing each other in the second direction 32 are both formed with a step groove 21 composed of sidewalls and a bottom wall. In the two laser chips 20 formed by two adjacent chip regions 13, two adjacent step grooves 21 correspond to one groove 15 of the bar 10, and two step grooves 21 are formed by a single groove 15. The step groove 21 is formed in an area outside the chip region 13 and is unlikely to affect the performance stability and structural reliability of the laser chip 20.
[0048] In some embodiments, in the bar 10, when both opposing sidewalls of the groove 15 in the second direction 32 are spaced apart from the first electrode layer 16, a gap exists between the sidewalls of the step groove 21 and the first electrode layer 16 in the fabricated laser chip 20, and the edge of the insulating layer 18 in the second direction 32 can be flush with the sidewalls of the groove 15. In other words, in the fabricated laser chip 20, the first electrode layer 16 is retracted relative to the insulating layer 18, and a step structure is formed between the first electrode layer 16 and the insulating layer 18. In this manner, the groove 15 is spaced apart from the first electrode layer 16, making it less likely to damage the first electrode layer 16 during the etching process of the groove 15. This improves the precision and structural integrity of the first electrode layer 16, thereby facilitating enhanced performance stability and structural reliability of the laser chip 20.
[0049] The present application also provides a laser device (not shown) comprising a laser chip 20 as described in any of the above embodiments. In the laser device, multiple laser chips 20 may be provided. These multiple laser chips 20 are arranged in an array and together constitute a laser emission module of the laser device. These multiple laser chips 20 can collectively emit laser light, thereby increasing the light-emitting area and light-emitting power of the laser emission module.
[0050] In some embodiments, the laser device may further include a laser receiving module. The laser transmitting module is used to transmit laser light toward a target object. The laser receiving module can receive laser light reflected from the target object through a sensor, thereby realizing functions such as distance measurement or depth detection of the target object. The specific type and structure of the laser device are not limited and can be any applicable laser lighting, projection, or detection device, and are not described in detail in this application.
[0051] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0052] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.
Claims
1. A method for preparing a laser chip, characterized in that: include: Providing a bar, the bar comprising a substrate and an epitaxial layer stacked in a first direction, the bar having chip regions and cutting regions alternately arranged in sequence along a second direction, the first direction and the second direction being perpendicular to each other; providing a groove in the cutting area, wherein the groove penetrates at least a portion of the epitaxial layer in the first direction; The bar is cleaved at the groove to separate the plurality of chip regions into a plurality of laser chips.
2. The method for preparing a laser chip according to claim 1, wherein: The bar has two side surfaces arranged opposite to each other in a third direction. In the step of providing a groove in the cutting area, the groove passes through the two side surfaces along the third direction, and the third direction is perpendicular to the first direction and the second direction.
3. The method for preparing a laser chip according to claim 1, wherein: In the step of providing a groove in the cutting area, both sides of the groove in the second direction are spaced apart from the chip area.
4. The method for preparing a laser chip according to claim 3, wherein: The bar further includes a first electrode layer disposed on a side of the epitaxial layer facing away from the substrate. The first electrode layer is located in the chip region. Both opposite side walls of the trench in the second direction are spaced apart from the first electrode layer in the second direction.
5. The method for preparing a laser chip according to claim 1, wherein: In the step of cleaving the bar at the groove, cutting is performed along the middle portion of the bottom wall of the groove in the second direction.
6. The method for preparing a laser chip according to claim 1, wherein: In a direction from the epitaxial layer to the substrate along the first direction, the epitaxial layer includes a first contact layer, a first cladding layer, a first waveguide layer, an active layer, a second waveguide layer, and a second cladding layer stacked in sequence. In the step of providing a groove in the cutting area, the groove extends from the first contact layer to at least the active layer along the first direction.
7. The method for preparing a laser chip according to claim 1, wherein: In the step of providing the grooves in the cutting area, the grooves are formed by an etching process.
8. A laser chip, characterized in that: Prepared by the preparation method according to any one of claims 1 to 7.
9. The laser chip according to claim 1, wherein: Two cavity surfaces of the laser chip facing each other in the second direction are both provided with a step groove consisting of a side wall and a bottom wall.
10. A laser device, characterized in that: The laser chip comprises the laser chip according to claim 8 or 9.