Power failure detection delay circuit and auxiliary power supply module

Abstract

The invention discloses a power failure detection delay circuit and an auxiliary power supply module, and belongs to the field of electric power supplies. The power failure detection delay circuit comprises a circuit input end, a voltage end, a circuit output end, a voltage detection unit and a delay output unit. The voltage detection unit is used for providing control voltage for the delay output unit under the condition that the voltage of the circuit input end is normal; the delay output unit is used for providing a working voltage to the circuit output end according to the voltage of the voltage end when the duration that the voltage of the circuit input end is smaller than a first target voltage reaches a target duration; under the condition that the voltage of the circuit input end is normal, the working voltage is stopped being supplied to the circuit output end according to the control voltage; the working voltage is used for controlling the auxiliary power module to supply power to the power distribution terminal. The power failure detection accuracy can be improved, the service life of the auxiliary power supply module is prolonged, and the power supply stability is improved.

Description

Technical Field

[0001] The present application relates to the field of electric power supplies, and in particular to a power-off detection delay circuit and an auxiliary power supply module. Background Art

[0002] When the main power supply voltage fails, the auxiliary power supply module must have sufficient power to supply the distribution terminal so that the distribution terminal can report service interruption information and collect positive active data at the time of power outage to meet the functional requirements of timely segmented and time-sharing settlement for users.

[0003] In related art, the auxiliary power module immediately supplies power to the distribution terminal upon detecting an abnormal drop in the main power supply voltage. However, this abnormal drop in the main power supply voltage may be caused by a brief voltage fluctuation, not a power outage. Frequent supply of power to the distribution terminal by the auxiliary power module shortens the service life of the auxiliary power module and affects power supply stability. Summary of the Invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a power failure detection delay circuit and an auxiliary power supply module, which can improve the accuracy of power failure detection, increase the service life of the auxiliary power supply module, and improve power supply stability.

[0005] In a first aspect, the present application provides a power failure detection delay circuit, which is applied to an auxiliary power supply module. The power failure detection delay circuit includes a circuit input terminal, a voltage terminal, a circuit output terminal, a voltage detection unit, and a delay output unit;

[0006] The voltage detection unit is connected to the circuit input terminal and the delay output unit respectively, and is used to provide a control voltage to the delay output unit when the voltage of the circuit input terminal is normal; and stop providing the control voltage to the delay output unit when the voltage of the circuit input terminal is less than a first target voltage;

[0007] The delayed output unit is respectively connected to the voltage end and the circuit output end, and is used to provide a working voltage to the circuit output end according to the voltage of the voltage end when the duration for which the voltage at the circuit input end is less than the first target voltage reaches a target duration; when the voltage at the circuit input end is normal, stop providing the working voltage to the circuit output end according to the control voltage; the working voltage is used to control the auxiliary power supply module to supply power to the power distribution terminal.

[0008] According to the power-off detection delay circuit of the present application, a delay output unit is set, and when the duration of time during which the voltage at the circuit input end is less than the first target voltage reaches the target duration, the delay output unit determines that the voltage at the circuit input end has powered off, and outputs the working voltage to the circuit output end according to the voltage at the voltage end, so that the auxiliary power supply module supplies power to the distribution terminal, thereby avoiding detecting short-term voltage fluctuations as power off, improving the accuracy of power-off detection, and avoiding the auxiliary power supply module supplying power to the distribution terminal when the voltage fluctuates for a short time, thereby increasing the service life of the auxiliary power supply module and improving the stability of the power supply system.

[0009] According to one embodiment of the present application, the delay output unit includes a first transistor;

[0010] The delayed output unit is further configured to, when the duration for which the voltage at the circuit input terminal is less than the first target voltage reaches the target duration, turn on the first transistor so that the voltage terminal is connected to the circuit output terminal, and provide the operating voltage to the circuit output terminal according to the voltage at the voltage terminal; and, when the voltage at the circuit input terminal is normal, turn off the first transistor according to the control voltage so that the voltage terminal is disconnected from the circuit output terminal, and stop providing the operating voltage to the circuit output terminal.

[0011] According to one embodiment of the present application, the delay output unit further includes a charging resistor and a charging capacitor;

[0012] The delayed output unit is further configured to, when the voltage at the circuit input terminal is less than a first target voltage, enable the voltage at the voltage terminal to charge the charging capacitor through the charging resistor, thereby increasing the voltage at the control terminal of the first transistor; and, when the charging time of the charging capacitor reaches the target time, enable the voltage at the control terminal of the first transistor to increase to its threshold voltage, thereby turning on the first transistor.

[0013] According to one embodiment of the present application, the delay output unit further includes a voltage regulator tube, an isolation diode, a first filter capacitor and a second filter capacitor;

[0014] The control terminal of the first transistor is connected to the voltage detection unit, the first terminal of the first transistor is connected to the voltage terminal, the second terminal of the first transistor is connected to the anode of the isolation diode, and the cathode of the isolation diode is connected to the circuit output terminal;

[0015] One end of the charging resistor is connected to the voltage terminal, the other end of the charging resistor is connected to the control terminal of the first transistor and one end of the charging capacitor respectively, and the other end of the charging capacitor is grounded; the voltage regulator diode is connected in parallel with the charging capacitor;

[0016] One end of the first filter capacitor is connected to the circuit output end, and the other end of the first filter capacitor is grounded; the second filter capacitor is connected in parallel with the first filter capacitor.

[0017] According to one embodiment of the present application, the voltage detection unit is further configured to release the charging voltage of the charging capacitor when the voltage at the input end of the circuit returns to normal.

[0018] According to one embodiment of the present application, the voltage detection unit is further used to determine that the voltage at the circuit input end has returned to normal when the voltage at the circuit input end is greater than a second target voltage; the second target voltage is greater than the first target voltage.

[0019] According to one embodiment of the present application, the voltage detection unit includes a switching element;

[0020] The voltage detection unit is also used to turn on the switching element to provide the control voltage to the delay output unit when the voltage at the circuit input end is normal; and to turn off the switching element to stop providing the control voltage to the delay output unit when the voltage at the circuit input end is less than the first target voltage.

[0021] According to one embodiment of the present application, the switching element includes an optocoupler, and the voltage detection unit further includes a diode, a third filter capacitor, a first resistor, a second resistor, a third resistor, and a fourth resistor;

[0022] The positive input terminal of the optocoupler is connected to the circuit input terminal via the first resistor and the second resistor connected in series, the negative input terminal of the optocoupler is grounded via the third resistor and the fourth resistor connected in series, the positive output terminal of the optocoupler is connected to the delay output unit, and the negative output terminal of the optocoupler is grounded;

[0023] The cathode of the diode is connected to the positive input terminal of the optocoupler, and the anode of the diode is connected to the negative input terminal of the optocoupler; the third filter capacitor is connected in parallel with the diode.

[0024] According to one embodiment of the present application, the switch element includes a second transistor, and the voltage detection unit further includes a fifth resistor, a sixth resistor, and a seventh resistor;

[0025] The control end of the second transistor is connected to the fifth resistor and the sixth resistor respectively, the other end of the fifth resistor is connected to the circuit input end, and the other end of the sixth resistor is grounded; the first end of the second transistor is connected to the delay output unit, and the second end of the second transistor is grounded via the seventh resistor.

[0026] In a second aspect, the present application provides an auxiliary power supply module, including a charging circuit, an energy storage unit, a boost circuit, and a power-off detection delay circuit;

[0027] The charging circuit is connected to the energy storage unit and is used to charge the energy storage unit through the power supply voltage when the main power supply voltage is normal;

[0028] The energy storage unit is connected to the boost circuit and is used to provide energy storage voltage to the boost circuit;

[0029] The power failure detection delay circuit is the power failure detection delay circuit as described in the first aspect above, wherein the circuit input end of the power failure detection delay circuit is connected to the charging circuit, and the voltage end and the circuit output end of the power failure detection delay circuit are respectively connected to the boost circuit;

[0030] The boost circuit is used to provide voltage to the voltage end of the power-off detection delay circuit, and to perform power supply operation at the operating voltage of the circuit output end of the power-off detection delay circuit to convert the energy storage voltage into a power supply voltage; the power supply voltage is used to power the power distribution terminal.

[0031] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0032] By setting a delayed output unit, when the duration of time during which the voltage at the circuit input end is less than the first target voltage reaches the target duration, the delayed output unit determines that the voltage at the circuit input end is powered off, and outputs the operating voltage to the circuit output end according to the voltage at the voltage end, so that the auxiliary power supply module supplies power to the distribution terminal, thereby avoiding detecting short-term voltage fluctuations as power off, improving the accuracy of power off detection, and avoiding the auxiliary power supply module supplying power to the distribution terminal when the voltage fluctuates for a short time, thereby increasing the service life of the auxiliary power supply module and improving the stability of the power supply system.

[0033] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0035] Figure 1 This is one of the schematic diagrams of the power failure detection delay circuit in the auxiliary power module provided in the embodiment of the present application;

[0036] Figure 2 This is the second schematic diagram of the power-off detection delay circuit in the auxiliary power module provided in an embodiment of the present application;

[0037] Figure 3 is a structural diagram of the auxiliary power supply module provided in an embodiment of the present application;

[0038] Figure 4 This is a circuit diagram of a voltage input unit in an auxiliary power supply module provided in an embodiment of the present application;

[0039] Figure 5 1 is a circuit diagram of a voltage conversion unit in an auxiliary power supply module provided in an embodiment of the present application;

[0040] Figure 6 This is a circuit diagram of a charging management unit in an auxiliary power module provided in an embodiment of the present application;

[0041] Figure 7 This is a circuit diagram of a first boost unit in an auxiliary power module provided in an embodiment of the present application;

[0042] Figure 8 This is a schematic diagram of the first part of the circuit of the second boost unit in the auxiliary power module provided in an embodiment of the present application;

[0043] Figure 9 This is a schematic diagram of the second circuit portion of the second boost unit in the auxiliary power module provided in an embodiment of the present application;

[0044] Figure 10 This is one of the schematic diagrams of the AC backflow prevention circuit in the auxiliary power module provided in the embodiment of the present application;

[0045] Figure 11 This is the second schematic diagram of the AC backflow prevention circuit in the auxiliary power module provided in the embodiment of the present application. DETAILED DESCRIPTION

[0046] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0047] The power-off detection delay circuit and the auxiliary power supply module provided in the embodiments of the present application are described below with reference to the accompanying drawings.

[0048] Figure 1 and Figure 2 This is a schematic diagram of the structure of a power failure detection delay circuit provided in an embodiment of the present application. The power failure detection delay circuit can be applied to an auxiliary power supply module.

[0049] like Figure 1 and Figure 2As shown, the power-off detection delay circuit provided in the embodiment of the present application includes a circuit input terminal VI, a voltage terminal V2, a circuit output terminal VCC1, a voltage detection unit 1 and a delay output unit 2.

[0050] The voltage detection unit 1 is connected to the circuit input terminal VI and the delay output unit 2 respectively, and is used to provide a control voltage to the delay output unit 2 when the voltage of the circuit input terminal VI is normal; when the voltage of the circuit input terminal VI is less than the first target voltage, stop providing the control voltage to the delay output unit 2.

[0051] The input terminal of the voltage detection unit 1 is connected to the circuit input terminal VI, and the output terminal of the voltage detection unit 1 is connected to the input terminal of the delay output unit 2. The circuit input terminal VI provides a voltage to the voltage detection unit 1, which detects the voltage at the circuit input terminal VI and determines whether the voltage at the circuit input terminal VI is less than a first target voltage. If the voltage at the circuit input terminal VI is greater than or equal to the first target voltage, the voltage at the circuit input terminal VI is determined to be normal, the voltage detection unit 1 is in the on state, and outputs a control voltage to the delay output unit 2. If the voltage at the circuit input terminal VI is less than the first target voltage, the voltage at the circuit input terminal VI is determined to have decreased abnormally. However, this abnormal decrease may be caused by a short-term voltage fluctuation and is not necessarily a voltage drop. If it is determined that the voltage at the circuit input terminal VI has decreased abnormally, the voltage detection unit 1 is in the off state and stops providing the control voltage to the delay output unit 2. In other words, the voltage detection unit 1 does not output a voltage to the delay output unit 2.

[0052] The delayed output unit 2 is connected to the voltage terminal V2 and the circuit output terminal VCC1 respectively, and is used to provide an operating voltage to the circuit output terminal VCC1 according to the voltage of the voltage terminal V2 when the duration of time during which the voltage at the circuit input terminal VI is less than the first target voltage reaches the target duration; when the voltage at the circuit input terminal VI is normal, the operating voltage is stopped from being provided to the circuit output terminal VCC1 according to the control voltage; the operating voltage is used to control the auxiliary power supply module to supply power to the power distribution terminal.

[0053] Voltage terminal V2 provides voltage to delay output unit 2. When voltage detection unit 1 stops providing the control voltage for a target duration (i.e., when the voltage at circuit input terminal V1 remains below the first target voltage for a target duration), circuit input terminal V1 is determined to be powered down. Delay output unit 2 is then turned on and supplies an operating voltage to circuit output terminal VCC1 based on the voltage at voltage terminal V2. The operating voltage output by circuit output terminal VCC1 is used to power the auxiliary power module, enabling it to supply power to the power distribution terminal.

[0054] When the duration that the voltage detection unit 1 stops providing the control voltage does not reach the target duration, that is, when the duration that the voltage at the circuit input terminal VI is less than the first target voltage does not reach the target duration, the delay output unit 2 is in the off state and stops providing the operating voltage to the circuit output terminal VCC1, that is, the circuit output terminal VCC1 does not output a voltage. When the voltage detection unit 1 provides the control voltage, that is, when the voltage at the circuit input terminal VI is normal, the delay output unit 2 is in the off state based on the control of the control voltage and stops providing the operating voltage to the circuit output terminal VCC1, that is, the circuit output terminal VCC1 does not output a voltage. When the circuit output terminal VCC1 does not output a voltage, the auxiliary power supply module cannot provide power, and the auxiliary power supply module does not supply power to the power distribution terminal.

[0055] It should be noted that the voltage at the circuit input terminal VI can be the voltage of the main power supply, or it can be the voltage after the voltage of the main power supply is processed (such as voltage conversion), that is, the voltage detection unit 1 can detect the voltage of the main power supply, or it can detect the voltage after the main power supply is processed. When the voltage of the main power supply is normal, the voltage at the circuit input terminal VI is normal, the auxiliary power supply module does not supply power, and the main power supply supplies power to the distribution terminal; when the voltage of the main power supply fails, the voltage at the circuit input terminal VI fails, the auxiliary power supply module supplies power, and the auxiliary power supply module supplies power to the distribution terminal. The distribution terminal can include at least one of a dedicated transformer terminal and an electric meter device.

[0056] The power-off detection delay circuit in this embodiment determines that the voltage at the circuit input end has lost power when the duration of time during which the voltage at the circuit input end is less than the first target voltage reaches the target duration, thereby avoiding detecting short-term voltage fluctuations as power-off, improving the accuracy of power-off detection, and avoiding the auxiliary power supply module from supplying power to the power distribution terminal when the voltage fluctuates for a short time, thereby reducing the power supply frequency of the auxiliary power supply module, increasing the service life of the auxiliary power supply module, and improving the power supply stability.

[0057] In some embodiments, the delayed output unit 2 includes a first transistor Q2. The control terminal of the first transistor Q2 is connected to the voltage detection unit 1, the first terminal of the first transistor Q2 is connected to the voltage terminal V2, and the second terminal of the first transistor Q2 is connected to the circuit output terminal VCC1. The first transistor Q2 can be a transistor, the control terminal of the first transistor Q2 can be the base of the transistor, the first terminal of the first transistor Q2 can be the collector of the transistor, and the second terminal of the first transistor Q2 can be the emitter of the transistor.

[0058] The delayed output unit 2 is further configured to, when the duration for which the voltage at the circuit input terminal VI is less than the first target voltage reaches a target duration, turn on the first transistor Q2, connect the voltage terminal V2 with the circuit output terminal VCC1, and provide an operating voltage to the circuit output terminal VCC1 according to the voltage at the voltage terminal V2; and, when the voltage at the circuit input terminal VI is normal, turn off the first transistor Q2 according to the control voltage, disconnect the voltage terminal V2 from the circuit output terminal VCC1, and stop providing an operating voltage to the circuit output terminal VCC1.

[0059] When the duration of time during which the voltage at the circuit input terminal VI is less than the first target voltage reaches the target duration, it is determined that the voltage at the circuit input terminal VI is powered off, the voltage detection unit 1 does not output voltage to the delayed output unit 2, and the voltage at the control terminal of the first transistor Q2 is increased to its threshold voltage through the voltage at the voltage terminal V2. The first transistor Q2 is turned on, and the voltage terminal V2 is connected to the circuit output terminal VCC1. The circuit output terminal VCC1 outputs an operating voltage for the auxiliary power supply module to supply power, so that the auxiliary power supply module supplies power to the power distribution terminal.

[0060] When the duration for which the voltage at the circuit input terminal VI is less than the first target voltage does not reach the target duration, the voltage detection unit 1 does not output a voltage to the delayed output unit 2, the voltage at the control terminal of the first transistor Q2 is less than its threshold voltage, the first transistor Q2 is in the off state, the voltage terminal V2 is disconnected from the circuit output terminal VCC1, and the circuit output terminal VCC1 does not output a voltage.

[0061] When the voltage at the circuit input terminal VI is normal, the voltage detection unit 1 outputs a control voltage to the delay output unit 2. The control voltage pulls down the voltage at the control terminal of the first transistor Q2. The first transistor Q2 is in the off state, the voltage terminal V2 is disconnected from the circuit output terminal VCC1, and the circuit output terminal VCC1 does not output a voltage.

[0062] In some embodiments, the delayed output unit 2 further includes a charging resistor R6 and a charging capacitor C3. One end of the charging capacitor C3 is connected to the control terminal of the first transistor Q2, and the other end of the charging capacitor C3 is grounded. One end of the charging resistor R6 is connected to the voltage terminal V2, and the other end of the charging resistor R6 is connected to the control terminal of the first transistor Q2. The charging resistor R6 and the charging capacitor C3 form an RC charging circuit. The charging capacitor C3 can be an electrolytic capacitor.

[0063] The delayed output unit 2 is further configured to, when the voltage at the circuit input terminal VI is less than a first target voltage, enable the voltage at the voltage terminal V2 to charge the charging capacitor C3 through the charging resistor R6, thereby increasing the voltage at the control terminal of the first transistor Q2; and when the charging time of the charging capacitor C3 reaches the target time, enable the voltage at the control terminal of the first transistor Q2 to increase to its threshold voltage, thereby turning on the first transistor Q2.

[0064] When the voltage at the circuit input terminal V1 is less than the first target voltage, the voltage detection unit 1 does not output a voltage to the delay output unit 2, the control terminal voltage of the first transistor Q2 is 0, and the first transistor Q2 is in the off state. The voltage at the voltage terminal V2 charges the charging capacitor C3 through the charging resistor R6, slowly increasing the control terminal voltage of the first transistor Q2. When the charging time of the charging capacitor C3 reaches the target time, the control terminal voltage of the first transistor Q2 rises to its threshold voltage, and the first transistor Q2 switches from the off state to the on state. The voltage terminal V2 is connected to the circuit output terminal VCC1, and the circuit output terminal VCC1 outputs the operating voltage.

[0065] The target duration T can be adjusted based on the capacitance of the charging capacitor C3 and the resistance of the charging resistor R6, i.e., T = R6 * C3. The capacitance of the charging capacitor C3 can be in the hundreds of microfarads, and the resistance of the charging resistor R6 can be in the tens of kilo-ohms to hundreds of kilo-ohms.

[0066] In some embodiments, as Figure 1 and Figure 2 As shown, the delayed output unit 2 also includes a voltage regulator diode ZD2, an isolation diode D3, a first filter capacitor EC1, and a second filter capacitor C4. The control terminal of the first transistor Q2 is connected to the voltage detection unit 1, the first terminal of the first transistor Q2 is connected to the voltage terminal V2, the second terminal of the first transistor Q2 is connected to the anode of the isolation diode D3, and the cathode of the isolation diode D3 is connected to the circuit output terminal VCC1; one end of the charging resistor R6 is connected to the voltage terminal V2, and the other end of the charging resistor R6 is respectively connected to the control terminal of the first transistor Q2 and one end of the charging capacitor C3, and the other end of the charging capacitor C3 is grounded; the voltage regulator diode ZD2 is connected in parallel with the charging capacitor C3; one end of the first filter capacitor EC1 is connected to the circuit output terminal VCC1, and the other end of the first filter capacitor EC1 is grounded; and the second filter capacitor C4 is connected in parallel with the first filter capacitor EC1.

[0067] The first filter capacitor EC1 may be an electrolytic capacitor. The voltage regulator ZD2 is used to prevent the voltage at the control terminal of the first transistor Q2 from being too high.

[0068] In some embodiments, the voltage detection unit 1 is further configured to determine that the voltage at the circuit input terminal VI returns to normal when the voltage at the circuit input terminal VI is greater than a second target voltage; the second target voltage is greater than the first target voltage.

[0069] In the event of a power outage at circuit input terminal V1, the voltage at circuit input terminal V1 is 0V. When the voltage at circuit input terminal V1 is greater than the second target voltage, it is determined that the voltage at circuit input terminal V1 has returned to normal. Voltage detection unit 1 immediately switches from an off state to an on state, providing a control voltage to delay output unit 2. Delay output unit 2, based on the control voltage, switches from an on state to an off state, ceasing to provide an operating voltage to circuit input terminal VCC1. This means that circuit input terminal VCC1 does not output an operating voltage, the auxiliary power supply module is unable to provide power, and the auxiliary power supply module stops supplying power to the power distribution terminal. Instead, the main power supply supplies power to the power distribution terminal.

[0070] It should be noted that the second target voltage is greater than the first target voltage, so that when the voltage at the circuit input terminal VI is stable, that is, when the voltage of the main power supply is stable, the auxiliary power supply module switches to the main power supply to supply power to the distribution terminal, thereby ensuring the power supply continuity of the distribution terminal and avoiding power interruption causing shutdown of the distribution terminal or data loss.

[0071] In some embodiments, the voltage detection unit 1 includes a switching element. Figure 1 As shown, the switching element may include an optocoupler U1; Figure 2 As shown, the switching element may also include a second transistor Q4.

[0072] The voltage detection unit 1 is also used to turn on the switching element to provide a control voltage to the delay output unit 2 when the voltage at the circuit input terminal VI is normal; and to turn off the switching element to stop providing the control voltage to the delay output unit 1 when the voltage at the circuit input terminal VI is less than the first target voltage.

[0073] When the voltage at the circuit input terminal VI is normal, the voltage at the circuit input terminal VI is capable of turning on the switch element, the voltage detection unit 1 is in the on state, and provides the control voltage to the delay output unit 2. When the voltage at the circuit input terminal VI is lower than the first target voltage, the voltage at the circuit input terminal VI is insufficient to turn on the switch element, the voltage detection unit 1 is in the off state, and stops providing the control voltage to the delay output unit 2. That is, the voltage detection unit 1 does not output a voltage to the delay output unit 2.

[0074] In some embodiments, as Figure 1 As shown, the switch element includes an optocoupler U1, and the voltage detection unit 1 further includes a diode D4, a third filter capacitor C2, a first resistor R8, a second resistor R7, a third resistor R12 and a fourth resistor R14.

[0075] The positive input terminal of the optocoupler U1 is connected to the circuit input terminal VI via a first resistor R8 and a second resistor R7 connected in series, the negative input terminal of the optocoupler U1 is grounded via a third resistor R12 and a fourth resistor R14 connected in series, the positive output terminal of the optocoupler U1 is connected to the delayed output unit 2, and the negative output terminal of the optocoupler U1 is grounded; the cathode of the diode D4 is connected to the positive input terminal of the optocoupler U1, and the anode of the diode D4 is connected to the negative input terminal of the optocoupler U1; the third filter capacitor C2 is connected in parallel with the diode D4.

[0076] The positive output terminal of the optocoupler U1 is connected to the control terminal of the first transistor Q2 in the delay output unit 2. The first resistor R8, the second resistor R7, the third resistor R12, and the fourth resistor R14 are all current-limiting resistors. The third filter capacitor C2 provides signal filtering, and the diode D4 provides overvoltage protection.

[0077] When the voltage at the circuit input terminal VI is normal, current flows through the primary-side light-emitting diode of the optocoupler U1, and the secondary-side phototransistor of the optocoupler U1 is turned on, allowing current to flow according to the current transfer ratio to provide a control voltage to the delay output unit 2. When the voltage at the circuit input terminal VI is lower than the first target voltage, no current flows through the primary-side light-emitting diode of the optocoupler U1, and the secondary-side phototransistor of the optocoupler U1 is turned off, stopping the supply of the control voltage to the delay output unit 2. In other words, the voltage detection unit 1 does not output a voltage to the delay output unit 2.

[0078] In some embodiments, as Figure 2 As shown, the switch element includes a second transistor Q4, and the voltage detection unit 1 also includes a fifth resistor R25, a sixth resistor R27, and a seventh resistor R29. The control terminal of the second transistor Q4 is connected to the fifth resistor R25 and the sixth resistor R27, respectively. The other end of the fifth resistor R25 is connected to the circuit input terminal V1, and the other end of the sixth resistor R27 is grounded. The first end of the second transistor Q4 is connected to the delay output unit 2, and the second end of the second transistor Q4 is grounded via the seventh resistor R29.

[0079] The second transistor Q4 may be a triode. The control terminal of the second transistor Q4 may be the base of the triode, the first terminal of the second transistor Q4 may be the collector of the triode, and the second terminal of the second transistor Q4 may be the emitter of the triode. The fifth resistor R25 and the sixth resistor R27 are both voltage divider resistors.

[0080] When the voltage at the circuit input terminal V1 is normal, the voltage at the control terminal of the second transistor Q4 reaches its threshold voltage, the second transistor Q4 is in the on state, and provides the control voltage to the delay output unit 2. When the voltage at the circuit input terminal V1 is lower than the first target voltage, the voltage at the control terminal of the second transistor Q4 does not reach its threshold voltage, the second transistor Q4 is in the off state, and stops providing the control voltage to the delay output unit 2. That is, the voltage detection unit 1 does not output a voltage to the delay output unit 2.

[0081] In some embodiments, the voltage detection unit 1 is further configured to release the charging voltage of the charging capacitor C3 when the voltage at the circuit input terminal VI returns to normal.

[0082] When the voltage at circuit input terminal V1 is lower than the first target voltage, the voltage at voltage terminal V2 charges charging capacitor C3 via charging resistor R6. When the voltage at circuit input terminal V1 returns to normal, the charged voltage at charging capacitor C3 needs to be released to reduce the voltage at the control terminal of first transistor Q2, turning off first transistor Q2, and causing circuit output terminal VCC1 to no longer output the operating voltage, and the auxiliary power supply module to no longer supply power to the power distribution terminal.

[0083] like Figure 1 As shown, when the switch element in the voltage detection unit 1 includes an optocoupler U1, the voltage at the circuit input terminal VI returns to normal, the optocoupler U1 is in the on state, and the charging capacitor C3 is stimulated to discharge slowly. Figure 2 As shown, when the switching element in the voltage detection unit 1 includes the second transistor Q4, the voltage at the circuit input terminal VI returns to normal, the second transistor Q4 is in the on state, and the charging voltage of the charging capacitor C3 is released through the seventh resistor R29.

[0084] According to the power-off detection delay circuit provided in the embodiment of the present application, a delay output unit 2 is set. When the duration of time during which the voltage at the circuit input terminal VI is less than the first target voltage reaches the target duration, the delay output unit 2 determines that the voltage at the circuit input terminal VI has lost power, and outputs an operating voltage to the circuit output terminal VCC1 according to the voltage at the voltage terminal V2, so that the auxiliary power supply module supplies power to the distribution terminal, thereby avoiding detecting short-term voltage fluctuations as power-off, improving the accuracy of power-off detection, and avoiding the auxiliary power supply module supplying power to the distribution terminal when the voltage fluctuates for a short time, thereby increasing the service life of the auxiliary power supply module and improving the stability of the power supply system.

[0085] Accordingly, an embodiment of the present application also provides an auxiliary power supply module, which is used to supply power to the distribution terminal when the main power supply voltage is lost. The distribution terminal may include at least one of a dedicated transformer terminal and an electric meter device (such as a three-phase meter).

[0086] like Figure 3As shown, the auxiliary power supply module provided in the embodiment of the present application includes a charging circuit 10, an energy storage unit 20, a power failure detection delay circuit 30 and a boost circuit 40. Among them, the power failure detection delay circuit 30 is the power failure detection delay circuit in the above embodiment and will not be described in detail here.

[0087] The charging circuit 10 is connected to the energy storage unit 20 and is used to charge the energy storage unit 20 through the main power voltage when the main power voltage is normal.

[0088] The input of the charging circuit 10 is connected to the main power supply voltage, and the output of the charging circuit 10 is connected to the energy storage unit 20. When the main power supply voltage is normal (e.g., within a preset voltage range), the charging circuit 10 converts the main power supply voltage into a voltage for charging the energy storage unit 20, while the main power supply voltage is also used to supply power to the distribution terminal. If the main power supply voltage is lost, the charging circuit 10 stops charging the energy storage unit 20, and the main power supply voltage is not used to supply power to the distribution terminal.

[0089] The power failure detection delay circuit 30 is connected to the charging circuit 10 and the boost circuit 40 respectively, and is used to output an operating voltage to the boost circuit 40 when the main power supply voltage is less than the target power supply voltage for a target period of time.

[0090] The circuit input terminal VI of the power failure detection delay circuit 30 is connected to the charging circuit 10 , and the voltage terminal V2 and the circuit output terminal VCC1 of the power failure detection delay circuit 30 are connected to the boost circuit 40 , respectively.

[0091] The power-off detection delay circuit 30 can detect the main power supply voltage via the circuit input terminal V1. If the voltage at the circuit input terminal V1 is normal, the main power supply voltage is determined to be normal. If the duration for which the voltage at the circuit input terminal V1 is less than the first target voltage does not reach the target duration, the main power supply voltage is determined to have been less than the target voltage for less than the target duration. If the duration for which the voltage at the circuit input terminal V1 is less than the first target voltage reaches the target duration, the main power supply voltage is determined to have been less than the target voltage for the target duration.

[0092] When the power-off detection delay circuit 30 detects that the main power supply voltage is normal, it does not output the operating voltage to the boost circuit 40; when it detects that the duration of the main power supply voltage being less than the target power supply voltage does not reach the target duration, it does not output the operating voltage to the boost circuit 40; when it detects that the duration of the main power supply voltage being less than the target power supply voltage reaches the target duration, it determines that the main power supply voltage is powered off, and outputs the operating voltage to the boost circuit 40 through the circuit output terminal VCC1.

[0093] The energy storage unit 20 is connected to the boost circuit 40 and is configured to output a stored energy voltage to the boost circuit 40. When the main power supply voltage is normal, the energy storage unit 20 stores electrical energy. When it detects that the main power supply voltage has been less than the target power supply voltage for a target duration, it outputs the stored energy voltage to the boost circuit 40.

[0094] The boost circuit 40 is used to provide voltage to the voltage terminal V2 of the power failure detection delay circuit 30, and to perform power supply operation at the operating voltage of the circuit output terminal VCC1 of the power failure detection delay circuit 30 to convert the energy storage voltage into a power supply voltage; the power supply voltage is used to power the power distribution terminal.

[0095] When the main power supply voltage is normal, the boost circuit 40 does not input the operating voltage and does not supply power. When the main power supply voltage is less than the target power supply voltage for less than the target duration, the boost circuit 40 does not input the operating voltage and does not supply power. When the main power supply voltage is less than the target power supply voltage for the target duration, the boost circuit 40 inputs the operating voltage and supplies power according to the operating voltage, converting the energy storage voltage provided by the energy storage unit 3 into the supply voltage. The supply voltage can be 110V DC.

[0096] In some embodiments, the auxiliary power module further includes a power output terminal 50, which is connected to the boost circuit 40 and configured to output a supply voltage. The power output terminal 50 outputs the supply voltage to the power distribution terminal, thereby enabling the auxiliary power module to supply power to the power distribution terminal in the event of a main power voltage failure.

[0097] This embodiment sets a charging and discharging strategy for the auxiliary power supply module. When the main power supply voltage is less than the target power supply voltage for a target period of time, it is determined that the main power supply voltage has lost power, and the auxiliary power supply module supplies power to the distribution terminal, thereby avoiding detecting short-term fluctuations in the main power supply voltage as a power outage, thereby avoiding the auxiliary power supply module supplying power to the distribution terminal when the main power supply voltage fluctuates for a short time, thereby increasing the service life of the auxiliary power supply module and improving the power supply stability.

[0098] In some embodiments, the energy storage unit 20 includes a battery, which includes any one of a lithium battery, a nickel-metal hydride battery, and a lead-acid battery. The power of the battery may be more than ten watts.

[0099] Lithium batteries have high energy density and low cost, nickel-metal hydride batteries can meet the requirements of miniaturization and safety, and lead-acid batteries are safe and low cost. The corresponding battery is selected as the energy storage unit 20 according to the actual application requirements.

[0100] Related technologies use supercapacitors as energy storage units, but their power supply time is short and cannot meet the power supply needs of distribution terminals after a main power supply voltage loss. This embodiment uses batteries as energy storage units. After a main power supply voltage loss, the batteries power the distribution terminals, supporting the power supply requirement of more than 30 minutes for freezing data at two sampling points in the distribution terminal and uploading it.

[0101] In some embodiments, as Figure 3 As shown, the charging circuit 10 includes a voltage input unit 11, a voltage conversion unit 12, and a charging management unit 13. The voltage input unit 11 is used to convert the main power supply voltage into a DC voltage. The voltage conversion unit 12 is connected to the voltage input unit 11 and is used to convert the DC voltage into a first voltage. The charging management unit 13 is connected to the voltage conversion unit 12 and is used to charge the energy storage unit 20 with a constant current using the first voltage when the main power supply voltage is normal.

[0102] When the main power supply voltage is normal, the voltage input unit 11 receives the main power supply voltage, which can be a single-phase AC voltage. The voltage input unit 11 performs AC-DC conversion on the main power supply voltage, converting it into a DC voltage and outputting the DC voltage to the voltage conversion unit 12. The voltage conversion unit 11 receives the DC voltage, converts it into a first voltage, and outputs the first voltage to the charging management unit 13. The charging management unit 13 receives the first voltage and converts it into a voltage for charging the energy storage unit 20, thereby charging the energy storage unit 20 using a constant current charging method.

[0103] In some embodiments, as Figure 4 As shown, the voltage input unit 11 includes a rectifier bridge BD1, a fuse F1, a varistor RV1, a filter inductor L1, a fourth filter capacitor CX1, a first electrolytic capacitor EC2, a second electrolytic capacitor EC3, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 and an eighth resistor R13.

[0104] One end of the fuse F1 is connected to the live wire ACL of the main power supply voltage, and the other end of the fuse F1 is respectively connected to one end of the varistor RV1 and one end of the filter inductor L1, and the other end of the filter inductor L1 is respectively connected to one end of the fourth filter capacitor CX1 and the first AC end AC1 of the rectifier bridge BD1; the other end of the varistor RV1 is respectively connected to the neutral line CAN of the main power supply voltage, the other end of the fourth filter capacitor CX1 and the second AC end AC2 of the rectifier bridge BD1; the positive output end V+ of the rectifier bridge BD1 is respectively connected to the output end VBus and the positive electrode of the first electrolytic capacitor EC2, the negative electrode of the first electrolytic capacitor EC2 is connected to the positive electrode of the second electrolytic capacitor EC3, and the negative electrode of the second electrolytic capacitor EC3 and the negative output end V- of the rectifier bridge BD1 are both grounded; the ninth resistor R9 and the tenth resistor R10 are connected in series to the positive and negative electrodes of the first electrolytic capacitor EC2, respectively, and the eleventh resistor R11 and the eighth resistor R13 are connected in series to the positive and negative electrodes of the second electrolytic capacitor EC3, respectively.

[0105] The filter inductor L1 and the fourth filter capacitor CX1 form an EMI filter circuit to filter the main power supply voltage. The rectifier bridge BD1 rectifies the main power supply voltage from AC to pulsating DC. The pulsating DC is filtered into a stable DC voltage by the first electrolytic capacitor EC2 and the second electrolytic capacitor EC3. The ninth resistor R9, the tenth resistor R10, the eleventh resistor R11, and the eighth resistor R13 are all voltage-equalizing resistors. The output terminal VBus of the voltage input unit 11 outputs a DC voltage to the voltage conversion unit 12.

[0106] In some embodiments, as Figure 5 As shown, the voltage conversion unit 12 includes a first transformer T2, a first flyback absorption circuit 121, a charging control circuit 122, a first feedback circuit 123, a first rectification and filtering circuit 124, a fourth transistor Q5 and a nineteenth resistor R52.

[0107] One end of the primary coil of the first transformer T2 is respectively connected to the output terminal VBus of the voltage input unit 11 and the first flyback absorption circuit 121, and the other end of the primary coil of the first transformer T2 is respectively connected to the first flyback absorption circuit 121 and the second end of the fourth transistor Q5. The first end of the fourth transistor Q5 is grounded via a nineteenth resistor R52. The charging control circuit 122 is respectively connected to the first feedback circuit 123 and the control end and the first end of the fourth transistor Q5. The first feedback circuit 123 is connected to the first rectifier and filter circuit 124. One end of the secondary coil of the first transformer T2 is connected to the output terminal V1 via the first rectifier and filter circuit 124, and the other end of the secondary coil of the first transformer T2 is grounded.

[0108] The nineteenth resistor R52 is a primary current sampling resistor. The fourth transistor Q5 may be a MOS transistor, the control terminal of the fourth transistor Q5 may be a gate of the MOS transistor, the first terminal of the fourth transistor Q5 may be a source of the MOS transistor, and the second terminal of the fourth transistor Q5 may be a drain of the MOS transistor.

[0109] The charging control circuit 122 controls the on and off switching of the fourth transistor Q5. The DC voltage output from the output terminal VBus of the voltage input unit 11 generates a primary high-frequency pulse signal through the fourth transistor Q5. When the fourth transistor Q5 is on, the primary coil of the first transformer T2 is excited by the DC voltage. At this time, the secondary of the first transformer T2 is in a reverse-biased cutoff state, and the voltage conversion unit 12 outputs no voltage. When the fourth transistor Q5 is off, the energy stored in the primary coil of the first transformer T2 is transferred to the secondary, where it is rectified and filtered by the first rectifier and filter circuit 124 to form a first voltage. The output terminal V1 of the voltage conversion unit 12 outputs the first voltage to the charging management unit 13.

[0110] In some embodiments, the charging management unit 13 is further configured to stop charging the energy storage unit 20 when the voltage of the energy storage unit 20 reaches a first voltage threshold; and to reduce the charging current of the energy storage unit 20 when the energy storage unit 20 is short-circuited.

[0111] The charging management unit 13 uses a constant charging current to charge the energy storage unit 20. When the voltage of the energy storage unit 20 reaches a preset constant current charging transition voltage, the charging current of the energy storage unit 20 is reduced, so that the energy storage unit 20 enters a maintenance charging state from a constant current charging state; when the voltage of the energy storage unit 20 reaches a charging cut-off voltage, charging of the energy storage unit 20 is stopped.

[0112] If an overvoltage fault occurs in the energy storage unit 20, that is, if the voltage of the energy storage unit 20 reaches a first voltage threshold, the charging management unit 13 stops charging the energy storage unit 20, providing undervoltage protection for the energy storage unit 20. If a short circuit fault occurs in the energy storage unit 20, the charging current of the energy storage unit 20 is reduced to provide short-circuit protection for the energy storage unit 20.

[0113] In some embodiments, as Figure 6 As shown, the charging management unit 13 includes a fifth transistor Q7, a sixth transistor Q6, and a charging inductor L4. The charging management unit 13 is further configured to periodically control the fifth transistor Q7 and the sixth transistor Q6 to be simultaneously turned on and off when the energy storage unit 20 is short-circuited. When the fifth transistor Q7 and the sixth transistor Q6 are simultaneously turned on, the charging inductor L4 is charged with the first voltage. When the fifth transistor Q7 and the sixth transistor Q6 are simultaneously turned off, the energy storage unit 20 is charged via the charging inductor L4.

[0114] In this embodiment, when the energy storage unit 20 is short-circuited, the charging current of the energy storage unit 20 can be effectively reduced by periodically controlling the fifth transistor Q7 and the sixth transistor Q6 to be turned on and off at the same time, thereby providing short-circuit protection for the energy storage unit 20.

[0115] The circuit topology of the charging management unit 13 may adopt a BOOST boost circuit.

[0116] In some embodiments, the charging management unit 13 further includes a constant current chip U7, a sampling resistor R43, an output capacitor EC7, and a first feedback circuit. The input terminal VIN and the enable terminal CE of the constant current chip U7 are respectively connected to the output terminal V1 of the voltage conversion unit 12. One end of the sampling resistor R43 is connected to the output terminal V1 of the voltage conversion unit 12. The other end of the sampling resistor R43 is respectively connected to the sampling terminal CSN of the constant current chip U7 and the second end of the sixth transistor Q6. The control end of the sixth transistor Q6 is connected to the first output terminal HDRV of the constant current chip U7. The first end of the sixth transistor Q6 is connected to one end of the charging inductor L4. The other end of the charging inductor L4 is respectively connected to the second end of the fifth transistor Q7 and the voltage terminal VBAT of the energy storage unit 20. The control end of the fifth transistor Q7 is connected to the second output terminal LDRV of the constant current chip U7. The first end of the fifth transistor Q7 is grounded. One end of the first feedback circuit is connected to the energy storage unit 20. The other end of the first feedback circuit is connected to the feedback terminal FB of the constant current chip U7. One end of the output capacitor EC7 is connected to the voltage terminal VBAT of the energy storage unit 20. The other end of the output capacitor EC7 is grounded.

[0117] The output capacitor EC7 may be an electrolytic capacitor. The fifth transistor Q7 may be an NMOS transistor, the control terminal of the fifth transistor Q7 may be the gate of the NMOS transistor, the first terminal of the fifth transistor Q7 may be the source of the NMOS transistor, and the second terminal of the fifth transistor Q7 may be the drain of the NMOS transistor. The sixth transistor Q6 may be a PMOS transistor, the control terminal of the sixth transistor Q6 may be the gate of the PMOS transistor, the first terminal of the sixth transistor Q6 may be the source of the PMOS transistor, and the second terminal of the sixth transistor Q6 may be the drain of the PMOS transistor.

[0118] The charging management unit 13 also includes a 20th resistor R49, an eighth diode D8, and a second diode D15. The 20th resistor R49 is connected between the control terminal of the fifth transistor Q7 and the first output terminal LDRV of the constant current chip U7. The anode of the eighth diode D8 is grounded, and the cathode of the eighth diode D8 is connected to one end of the charging inductor L4 and the first end of the sixth transistor Q6, respectively. The anode of the second diode D15 is connected to the other end of the charging inductor L4 and the second end of the fifth transistor Q7, respectively, and the cathode of the second diode D15 is connected to the voltage terminal VBAT of the energy storage unit 20.

[0119] In some embodiments, the first feedback circuit includes a twenty-first resistor R48 and a twenty-second resistor R55. The feedback terminal FB of the constant current chip U7 is respectively connected to one end of the twenty-first resistor R48 and one end of the twenty-second resistor R55. The other end of the twenty-first resistor R48 is connected to the voltage terminal VBAT of the energy storage unit 20, and the other end of the twenty-second resistor R55 is grounded. The twenty-first resistor R48 and the twenty-second resistor R55 are both voltage divider resistors.

[0120] During the constant current charging process of the energy storage unit 20 by the charging management unit 13, the first voltage output by the output terminal V1 of the voltage conversion unit 12 is connected to the charging management unit 13, and the constant current chip U7 enters the constant current charging state. In the constant current charging state, the fifth transistor Q7 and the sixth transistor Q6 are both turned on, the current of the charging inductor L4 increases, and the energy in the output capacitor EC7 is transferred to the energy storage unit 20. The sampling resistor R43 detects the external current. When the inductor current rises to the current upper limit set by the sampling resistor R43, the fifth transistor Q7 is turned off, the inductor current decreases, and the energy in the charging inductor L4 is transferred to the output capacitor EC7 and the energy storage unit 20. When the inductor current drops to the current lower limit set by the sampling resistor R43, the fifth transistor Q7 is turned on again, and this cycle is repeated to achieve constant current charging.

[0121] The voltage of the energy storage unit 20 is divided and fed back to the feedback terminal FB of the constant current chip U7 through the twenty-first resistor R48 and the twenty-second resistor R55. When the voltage at the feedback terminal FB reaches the constant current charging breakover voltage, the charging current is reduced by adjusting the on and off durations of the fifth transistor Q7, causing the energy storage unit 20 to transition from the constant current charging state to the maintenance charging state. This process continues until the voltage of the energy storage unit reaches the charging cutoff voltage.

[0122] In some embodiments, the power failure detection delay circuit 30 is connected to the voltage input unit 11 and is further configured to determine that the duration of time the main power supply voltage is less than the first target voltage reaches the target duration when the duration of time the DC voltage is less than the first target voltage reaches the target duration. Figure 1 shown.

[0123] The circuit input terminal VI of the power-off detection delay circuit 30 is connected to the output terminal VBus of the voltage input unit 11. The circuit input terminal VI of the power-off detection delay circuit 30 is the DC voltage of the output terminal VBus of the voltage input unit 11. The power-off condition of the main power supply voltage is determined by detecting the DC voltage of the output terminal VBus of the voltage input unit 11. If the power-off detection delay circuit 30 detects that the DC voltage is normal (e.g., the DC voltage is within a first voltage range), the main power supply voltage is determined to be normal. If the power-off detection delay circuit 30 detects that the duration of the DC voltage being less than the first target voltage does not reach the target duration, the main power supply voltage is determined to have been less than the target voltage for a duration that does not reach the target duration. If the power-off detection delay circuit 30 detects that the duration of the DC voltage being less than the first target voltage reaches the target duration, the main power supply voltage is determined to have been less than the target voltage for a duration that reaches the target duration, indicating that the main power supply voltage has been powered off. The first target voltage is different from the target power supply voltage.

[0124] In some embodiments, the power failure detection delay circuit 30 is connected to the voltage conversion unit 12 and is further configured to determine that the duration of time the main power supply voltage is less than the first target voltage reaches the target duration when the duration of time the first voltage is less than the third target voltage reaches the target duration. Figure 2 shown.

[0125] The circuit input terminal VI of the power-off detection delay circuit 30 is connected to the output terminal V1 of the voltage conversion unit 12. The circuit input terminal VI of the power-off detection delay circuit 30 is the first voltage of the output terminal V1 of the voltage conversion unit 12. The power-off condition of the main power supply voltage is determined by detecting the first voltage of the output terminal V1 of the voltage conversion unit 12. If the power-off detection delay circuit 30 detects that the first voltage is normal (e.g., the first voltage is within the second voltage range), the main power supply voltage is determined to be normal. If the power-off detection delay circuit 30 detects that the duration of time the first voltage is less than the first target voltage does not reach the target duration, the main power supply voltage is determined to have been less than the target voltage for less than the target duration. If the power-off detection delay circuit 30 detects that the duration of time the first voltage is less than the first target voltage reaches the target duration, the main power supply voltage is determined to have been less than the target voltage for the target duration, indicating a power-off condition. The first target voltage is different from the target voltage.

[0126] The power failure detection delay circuit 30 in this embodiment can detect the power failure of the main power supply voltage in multiple ways, thereby improving the diversity of detection.

[0127] In some embodiments, as Figure 3As shown, the boost circuit 40 includes a first boost unit 41 and a second boost unit 42. The first boost unit 41 is connected to the energy storage unit 20 and is configured to convert the energy storage voltage into a second voltage. The power failure detection delay circuit 30 is connected to the first boost unit 41 and the second boost unit 42, respectively, and is further configured to output an operating voltage to the second boost unit 42 via a second voltage when the main power supply voltage is less than the first target voltage for a target duration. The second boost unit 42 is connected to the energy storage unit 20 and the power output terminal 50, respectively, and is configured to operate at the operating voltage, thereby converting the energy storage voltage into a supply voltage and providing it to the power output terminal 50.

[0128] The first boost unit 41 is connected to the voltage terminal VBAT of the energy storage unit 20 to receive the energy storage voltage of the energy storage unit 20 and boost the energy storage voltage to a second voltage. The output terminal VCC0 of the first boost unit 41 outputs the second voltage. The voltage terminal V2 of the power failure detection delay circuit 30 is connected to the output terminal VCC0 of the first boost unit 41. The voltage of the voltage terminal V2 of the power failure detection delay circuit 30 is the second voltage of the output terminal VCC0 of the first boost unit 41. The circuit output terminal VCC1 of the power failure detection delay circuit 30 is connected to the second boost unit 42.

[0129] When the power-off detection delay circuit 30 detects that the main power supply voltage is normal, the voltage terminal V2 of the power-off detection delay circuit 30 is controlled to be disconnected from the circuit output terminal VCC1, and the output of the operating voltage to the second boost unit 42 is stopped; when the power-off detection delay circuit 30 detects that the duration of time during which the main power supply voltage is less than the first target voltage does not reach the first target duration, the voltage terminal V2 of the power-off detection delay circuit 30 is controlled to be disconnected from the circuit output terminal VCC1, and the output of the operating voltage to the second boost unit 42 is stopped; when the power-off detection delay circuit 30 detects that the duration of time during which the main power supply voltage is less than the first target voltage reaches the first target duration, the voltage terminal V2 of the power-off detection delay circuit 30 is controlled to be connected to the circuit output terminal VCC1, and the operating voltage is output to the second boost unit 42 through the second voltage.

[0130] The second boost unit 42 is connected to the voltage terminal VBAT of the energy storage unit 20 to receive the energy storage voltage of the energy storage unit 20. When the second boost unit 42 is in power supply operation, it converts the energy storage voltage provided by the energy storage unit 3 into a power supply voltage. The output terminal VC of the second boost unit 42 is connected to the power output terminal 50, so that the power output terminal 50 outputs the supply voltage to the power distribution terminal. In the event of a main power supply voltage failure, the auxiliary power supply module can be used to supply power to the power distribution terminal.

[0131] In some embodiments, the first boost unit 41 is further configured to stop converting the energy storage voltage into the second voltage when the energy storage voltage is less than a second voltage threshold.

[0132] In the event of a main power supply voltage loss, the auxiliary power module supplies power to the power distribution terminal, and the energy storage unit 20 is in a discharging state. When the energy storage voltage of the energy storage unit 20 falls below the second voltage threshold, the first boost unit 41 stops operating, does not output the second voltage to the power failure detection delay circuit 30, and does not output the operating voltage to the second boost unit 42. The second boost unit 42 stops supplying power, and the auxiliary power module stops supplying power to the power distribution terminal, thereby providing undervoltage protection for the energy storage unit 20.

[0133] In some embodiments, as Figures 7 to 9 As shown, the first boost unit 41 includes a startup resistor R21, and is connected to the second boost unit 42 via the startup resistor R21. The second boost unit 42 is also configured to lower the operating voltage to stop power supply in the event of a short circuit at the power output terminal 50. The first boost unit 41 is also configured to charge the second boost unit 42 via the startup resistor R21, thereby increasing the operating voltage and resuming power supply operation.

[0134] In the event of a short circuit at the power output terminal 50, the second boost unit 42 lowers the operating voltage to below the minimum startup voltage for short-circuit protection. At this point, the second boost unit 42 stops supplying power, meaning it does not output a supply voltage to the power output terminal 50. After the short circuit at the power output terminal 50 is resolved, the first boost unit 41 charges the power supply terminal of the second boost unit 42 (which is connected to the operating voltage) via the startup resistor R21, causing the operating voltage to rise again. The second boost unit 42 then resumes supplying power to the power output terminal 50, thus achieving short-circuit self-recovery.

[0135] In some embodiments, as Figures 7 to 9 As shown, the first boost unit 41 also includes a boost inductor L2, a boost diode D6, a boost chip U2, an enable circuit and a second feedback circuit; the second boost unit 42 includes a transformer (i.e., a second transformer T3), a flyback absorption circuit (i.e., a second flyback absorption circuit 421), a boost control circuit 423, a third transistor Q8 and a third feedback circuit 424.

[0136] The voltage terminal VBAT of the energy storage unit 20 is connected to the second secondary winding T3B2 of the second transformer T3 via a series-connected boost inductor L2, a boost diode D6, and a starting resistor R21. The input terminal IN and the control terminal SW of the boost chip U2 are respectively connected to the two ends of the boost inductor L2. The enable terminal EN of the boost chip U2 is connected to the voltage terminal VBAT of the energy storage unit 20 via an enable circuit. The feedback terminal FB of the boost chip U2 is connected to the cathode of the boost diode D6 via a second feedback circuit.

[0137] One end of the primary coil T3A of the second transformer T3 is connected to the voltage terminal VBAT of the energy storage unit 20 and the second flyback absorption circuit 421, respectively. The other end of the primary coil T3A of the second transformer T3 is connected to the second flyback absorption circuit 421 and the second end of the third transistor Q8, respectively. The boost control circuit 423 is connected to the circuit output terminal VCC1 of the power-off detection delay circuit 30, the third feedback circuit 424, and the control terminal and the first end of the third transistor Q8, respectively. The first secondary coil T3B1 of the second transformer T3 and the third feedback circuit 424 are connected to the power output terminal 50, respectively.

[0138] In some embodiments, the second boost unit 42 further includes a second rectifier and filter circuit 425, a twelfth resistor R44, a seventh filter capacitor C7, and a fourth diode D7. One end of the first secondary winding T3B1 of the second transformer T3 and the third feedback circuit 424 are connected to the output terminal VC of the second boost unit 42 via the second rectifier and filter circuit 425. The output terminal VC of the second boost unit 42 is connected to the power supply output terminal 50. The other end of the first secondary winding T3B1 of the second transformer T3 is grounded. A first end of the third transistor Q8 is grounded via one end of the twelfth resistor R44.

[0139] One end of the second secondary winding T3B2 of the second transformer T3 is connected to the anode of the fourth diode D7, the cathode of the fourth diode D7 is connected to the output terminal VCC0 of the first boost unit 41, and the other end of the second secondary winding T3B2 of the second transformer T3 is grounded; one end of the seventh filter capacitor C7 is connected to the output terminal VCC0 of the first boost unit 41, and the other end of the seventh filter capacitor C7 is grounded.

[0140] The twelfth resistor R44 is a primary current sampling resistor. The third transistor Q8 may be a MOS transistor, the control terminal of the third transistor Q8 may be a gate of the MOS transistor, the first terminal of the third transistor Q8 may be a source of the MOS transistor, and the second terminal of the third transistor Q8 may be a drain of the MOS transistor.

[0141] The main circuit topology of the second boost unit 42 adopts a flyback circuit topology. The energy storage voltage of the energy storage unit 20 is connected to the second boost unit 42, generating a primary high-frequency pulse signal through the third transistor Q8. The boost control circuit 423 controls the conduction and shutdown of the third transistor Q8. When the third transistor Q8 is turned on, the primary winding T3A of the second transformer T3 is excited by the energy storage voltage. At this time, the secondary of the second transformer T3 is in a reverse-biased cutoff state and does not output a supply voltage. After the third transistor Q8 is turned off, the energy stored in the primary winding T3A of the second transformer T3 is transferred to the secondary through the second rectifier and filter circuit 425 to output the supply voltage to the output terminal VC of the second boost unit 42.

[0142] In some embodiments, the first boost unit 41 further includes a fifth diode D5 and a first capacitor C5. The fifth diode D5 is connected between the startup resistor R21 and the output terminal VCC0 of the first boost unit 41. One end of the first capacitor C5 is connected to the voltage terminal VBAT of the energy storage unit 20, and the other end of the first capacitor C5 is grounded.

[0143] The enabling circuit includes a thirteenth resistor R16, a fourteenth resistor R18, a fifteenth resistor R20, and a second capacitor C8. The enable terminal EN of the boost chip U2 is connected to one end of the thirteenth resistor R16 and one end of the fourteenth resistor R18, respectively. The other end of the thirteenth resistor R16 is grounded, and the other end of the fourteenth resistor R18 is connected to the voltage terminal VBAT of the energy storage unit 20. The fifteenth resistor R20 and the second capacitor C8 are respectively connected in parallel with the fourteenth resistor R18.

[0144] The second feedback circuit includes a sixteenth resistor R15, a seventeenth resistor R17, an eighteenth resistor R19, and a third capacitor C6. A feedback terminal FB of the boost chip U2 is connected to one end of the sixteenth resistor R15, one end of the seventeenth resistor R17, and one end of the eighteenth resistor R19, respectively. The other end of the sixteenth resistor R15 is connected to the cathode of the boost diode D6, the other end of the seventeenth resistor R17 is grounded, and the other end of the eighteenth resistor R19 is grounded. One end of the third capacitor C6 is connected to the cathode of the boost diode D6, and the other end of the third capacitor C6 is grounded.

[0145] Among them, the first capacitor C5 is the input filter capacitor, the third capacitor C6 is the output filter capacitor, and the fifth diode D5 is the isolation diode. The energy storage voltage of the energy storage unit 20 is boosted to the supply voltage via the boost inductor L2 and the boost diode D6. When the energy storage voltage of the energy storage unit 20 is greater than or equal to the second voltage threshold, the boost chip U2 is enabled, and the output terminal VCC0 of the first boost unit 41 outputs the supply voltage. When the energy storage voltage of the energy storage unit 20 is less than the second voltage threshold, the first boost unit 41 does not operate, and the output terminal VCC0 of the first boost unit 41 does not output the supply voltage, thereby achieving the purpose of undervoltage protection for the energy storage unit 20.

[0146] Furthermore, after the boost circuit 40 starts up normally, the output terminal VCC0 of the first boost unit 41 is connected to the secondary winding of the second transformer T3, which then provides power to the chip. In the event of a short circuit at the power output terminal 50, the boost control circuit 423 lowers the supply voltage to below the minimum startup voltage, and the second boost unit 42 stops supplying power, thus achieving short-circuit protection. After the short circuit at the power output terminal 50 is resolved, the first boost unit 4 charges the chip power supply terminal via the startup resistor R21, raising the supply voltage. The second boost unit 42 then resumes powering the chip, thus achieving short-circuit self-recovery.

[0147] In some embodiments, the auxiliary power module further includes an AC backfeed prevention circuit 60. The AC backfeed prevention circuit 60 is connected between the boost circuit 40 and the power output terminal 50. The AC backfeed prevention circuit 60 is configured to be in an on state when the boost circuit 40 outputs a supply voltage, providing the supply voltage to the power output terminal 50; and to be in an off state when the power output terminal 50 inputs an AC voltage, disconnecting the boost circuit 40 from the power output terminal 50.

[0148] The auxiliary power supply module in this embodiment also has the function of preventing AC backflow, which can effectively suppress the instantaneous surge current when the current output terminal 50 is reversely connected and injected with AC voltage, thereby ensuring that the components in the auxiliary power supply module are not damaged.

[0149] In some embodiments, as Figure 10 and Figure 11 As shown, the AC backfeed prevention circuit 60 includes a voltage input terminal, a voltage output terminal, a first backfeed prevention unit 61 and a second backfeed prevention unit 62. The voltage input terminal includes a positive input terminal VC+ and a negative input terminal VC-, and the voltage output terminal includes a positive output terminal VOUT+ and a negative output terminal VOUT-.

[0150] The voltage input terminal of the AC backfeed prevention circuit 60 is connected to the second boost unit 42. When the output terminal VC of the second boost unit 42 outputs the supply voltage, the voltage input terminal of the AC backfeed prevention circuit 60 is the supply voltage. The voltage output terminal of the AC backfeed prevention circuit 60 is connected to the power output terminal 50.

[0151] The first anti-backfeed unit 61 is connected to the positive input terminal VC+ and the positive output terminal VOUT+ respectively, and is configured to be in an on state when a voltage is input to the voltage input terminal; and to be in an off state when a positive AC voltage is input to the positive output terminal VOUT+ and a negative AC voltage is input to the negative output terminal VOUT-, thereby disconnecting the positive input terminal VC+ from the positive output terminal VOUT+.

[0152] The second anti-backfeed unit 62 is connected to the negative input terminal VC- and the negative output terminal VOUT- respectively. The second anti-backfeed unit 62 is also connected to the positive input terminal VC+ or the positive output terminal VOUT+. It is configured to be in an on state when a voltage is input to the voltage input terminal; and to be in an off state when a negative AC voltage is input to the positive output terminal VOUT+ and a positive AC voltage is input to the negative output terminal VOUT-, thereby disconnecting the negative input terminal VC- and the negative output terminal VOUT-.

[0153] In which, when the voltage input terminal inputs a voltage (i.e., the power supply voltage), the positive input terminal VC+ inputs a positive DC voltage, the negative input terminal VC- is grounded, and the first anti-backfeed unit 61 and the second anti-backfeed unit 62 are both in the on state, so that the positive input terminal VC+, the negative input terminal VC-, the positive output terminal VOUT+ and the negative output terminal VOUT- are connected, and the AC backfeed prevention circuit 60 is in the on state, providing the power supply voltage of the voltage input terminal to the voltage output terminal, so that the power output terminal 50 outputs the power supply voltage to power the distribution terminal.

[0154] When AC power is input to the voltage output terminal, if a positive AC voltage is input to the positive output terminal VOUT+ and a negative AC voltage is input to the negative output terminal VOUT-, the first anti-backflow unit 61 is in an off state, disconnecting the positive input terminal VC+ and the positive output terminal VOUT+, preventing the AC power from the voltage output terminal from being transmitted to the voltage input terminal, i.e., preventing AC power from flowing back. If a negative AC voltage is input to the positive output terminal VOUT+ and a positive AC voltage is input to the negative output terminal VOUT-, the second anti-backflow unit 62 is in an off state, disconnecting the negative input terminal VC- and the negative output terminal VOUT-, preventing the AC power from the voltage output terminal from being transmitted to the voltage input terminal, i.e., preventing AC power from flowing back, thereby avoiding damage to the auxiliary power module. The AC power can be 220V or 380V AC.

[0155] In some embodiments, as Figure 10 and Figure 11 As shown, the first anti-backflow unit 61 includes an anti-backflow diode D1 , an anode of the anti-backflow diode D1 is connected to the positive input terminal VC+, and a cathode of the anti-backflow diode D1 is connected to the positive output terminal VC-.

[0156] When the voltage input terminal inputs a supply voltage, the positive input terminal VC+ inputs a positive DC voltage, the negative input terminal VC- is grounded, the anti-backfeed diode D1 is turned on, and the first anti-backfeed unit 61 is in the on state. When the voltage output terminal inputs AC power, if the positive output terminal VOUT+ inputs a positive AC voltage and the negative output terminal VOUT- inputs a negative AC voltage, the anti-backfeed diode D1 is turned off, the first anti-backfeed unit 61 is in the off state, and the positive input terminal VC+ and the positive output terminal VOUT+ are disconnected to prevent AC power from flowing back. If the positive output terminal VOUT+ inputs a negative AC voltage and the negative output terminal VOUT- inputs a positive AC voltage, the anti-backfeed diode D1 can be turned on, the first anti-backfeed unit 61 is in the on state, but the second anti-backfeed unit 62 is in the off state, preventing AC power from flowing back.

[0157] In some embodiments, as Figure 10As shown, the second anti-backfeed unit 62 includes a seventh transistor Q1 and a thermistor PTC1. The control terminal of the seventh transistor Q1 is connected to the positive input terminal VC+, the first terminal of the seventh transistor Q1 is connected to the negative input terminal VC-, the second terminal of the seventh transistor Q1 is connected to one end of the thermistor PTC1, and the other end of the thermistor PTC1 is connected to the negative output terminal VOUT-. The seventh transistor Q1 can be a MOS transistor with an internal diode, the control terminal of the seventh transistor Q1 can be the gate of the MOS transistor, the first terminal of the seventh transistor Q1 can be the source of the MOS transistor, and the second terminal of the seventh transistor Q1 can be the drain of the MOS transistor.

[0158] The second anti-backfeed unit 62 is further configured to, when a supply voltage is input to the voltage input terminal, turn on the seventh transistor Q1, so that the second anti-backfeed unit 62 is in an on state; and, when a negative AC voltage is input to the positive output terminal VOUT+ and a positive AC voltage is input to the negative output terminal VOUT-, increase the resistance of the thermistor PTC1 and turn off the seventh transistor Q1, so that the negative input terminal VC- and the negative output terminal VOUT- are disconnected.

[0159] When a supply voltage is input to the voltage input terminal, a positive DC voltage is input to the positive input terminal VC+, and the negative input terminal VC- is grounded, turning on the seventh transistor Q1 and placing the second anti-backfeed unit 62 in an on state. When an AC power is input to the voltage output terminal, if a positive AC voltage is input to the positive output terminal VOUT+ and a negative AC voltage is input to the negative output terminal VOUT-, the anti-backfeed diode D1 is turned off, preventing current from flowing into the second anti-backfeed unit 62, thereby preventing AC power from flowing back. If a negative AC voltage is input to the positive output terminal VOUT+ and a positive AC voltage is input to the negative output terminal VOUT-, a large current instantly flows through the seventh transistor Q1, causing the thermistor PTC1 to heat up severely after the large current flows through it, causing the resistance of the thermistor PTC1 to rise sharply. At the same time, because the voltage at the control terminal of the seventh transistor Q1 does not reach its threshold voltage, the seventh transistor Q1 is turned off, and the second anti-backfeed unit 62 is in an off state, disconnecting the negative input terminal VC- from the negative output terminal VOUT-, thereby preventing AC power from flowing back.

[0160] In some embodiments, the second anti-backfeed unit 62 further includes a twenty-third resistor R4 , a twenty-fourth resistor R3 , a twenty-fifth resistor R5 , a sixth filter capacitor C1 , and a second voltage-stabilizing diode ZD1 .

[0161] The control end of the seventh transistor Q1 is connected to one end of the twenty-third resistor R4, the other end of the twenty-third resistor R4 is respectively connected to one end of the twenty-fourth resistor R3 and one end of the twenty-fifth resistor R5, the other end of the twenty-fourth resistor R3 is connected to the positive input terminal VC+, the other end of the twenty-fifth resistor R5 is respectively connected to the negative input terminal VC- and the first end of the seventh transistor Q1, and the second end of the seventh transistor Q1 is connected to the negative output terminal VOUT- via the thermistor PTC1; the sixth filter capacitor C1 and the second voltage regulator diode ZD1 are respectively connected in parallel with the twenty-fifth resistor R5.

[0162] The twenty-third resistor R4 is a current-limiting resistor for the control terminal of the seventh transistor Q1 , the twenty-fourth resistor R3 and the twenty-fifth resistor R5 are both voltage-dividing resistors, and the second voltage-stabilizing diode ZD1 is used to ensure that the control terminal of the seventh transistor Q1 does not suffer from overvoltage failure.

[0163] In some embodiments, as Figure 11 As shown, the second anti-backfeed unit 62 includes a relay K1. The two ends of the contact of the relay K1 are respectively connected to the negative input terminal VC- and the negative output terminal VOUT-, and the two ends of the coil of the relay K1 are respectively connected to the positive output terminal VOUT+ and the negative output terminal VOUT-.

[0164] The second anti-backfeed unit 62 is further configured to control the contacts of the relay K1 to close when a supply voltage is input to the voltage input terminal, thereby placing the second anti-backfeed unit 62 in a conducting state; and to control the contacts of the relay K1 to open when a negative AC voltage is input to the positive output terminal VOUT+ and a positive AC voltage is input to the negative output terminal VOUT-, thereby disconnecting the negative input terminal VC- from the negative output terminal VOUT-.

[0165] When a supply voltage is input to the voltage input terminal, a positive DC voltage is input to the positive input terminal VC+, the negative input terminal VC- is grounded, the positive output terminal VOUT+ outputs a positive voltage, and the negative output terminal VOUT- outputs a negative voltage. The voltage difference between the positive output terminal VOUT+ and the negative output terminal VOUT- is applied to the coil of relay K1, the contacts of relay K1 are closed, and the second anti-backfeed unit 62 is in a conductive state. When an alternating current is input to the voltage output terminal, if a positive AC voltage is input to the positive output terminal VOUT+ and a negative AC voltage is input to the negative output terminal VOUT-, the anti-backfeed diode D1 is turned off, and current cannot flow into the second anti-backfeed unit 62, preventing AC power from flowing back. If a negative AC voltage is input to the positive output terminal VOUT+ and a positive AC voltage is input to the negative output terminal VOUT-, no voltage is applied to the coil of relay K1, the contacts of relay K1 are opened, and the second anti-backfeed unit 62 is in a turned-off state, disconnecting the negative input terminal VC- from the negative output terminal VOUT-, preventing AC power from flowing back.

[0166] In some embodiments, the second anti-backflow unit 62 further includes a twenty-sixth resistor R34 , a freewheeling diode D12 , and a sixth diode D14 .

[0167] The two ends of the contact of the relay K1 are respectively connected to the negative input terminal VC- and the negative output terminal VOUT-, and the two ends of the coil of the relay K1 are respectively connected to the positive electrode and negative electrode of the freewheeling diode D12; the positive electrode of the sixth diode D14 is connected to the positive electrode of the freewheeling diode D12, and the negative electrode of the sixth diode D14 is connected to the negative output terminal VOUT-; one end of the twenty-sixth resistor R34 is connected to the negative electrode of the freewheeling diode D12, and the other end of the twenty-sixth resistor R34 is connected to the positive output terminal VOUT+.

[0168] In some embodiments, the AC backfeed prevention circuit further includes an alarm unit 3. The first backfeed prevention unit 61 is further configured to be turned on when a negative AC voltage is input to the positive output terminal VOUT+ and a positive AC voltage is input to the negative output terminal VOUT-. The alarm unit 2 is connected to the positive input terminal VC+, the negative output terminal VOUT-, and the first backfeed prevention unit 61, respectively, and is configured to generate an alarm when a negative AC voltage is input to the positive output terminal VOUT+ and a positive AC voltage is input to the negative output terminal VOUT-.

[0169] When voltage is input to the voltage input terminal, a positive DC voltage is input to the positive input terminal VC+, and the negative input terminal VC- is grounded, the alarm unit 3 does not generate an alarm. When AC power is input to the voltage output terminal, if a positive AC voltage is input to the positive output terminal VOUT+ and a negative AC voltage is input to the negative output terminal VOUT-, the first anti-backfeed unit 61 is in the off state, current cannot flow into the alarm unit 3, and the alarm unit 3 does not generate an alarm. If a negative AC voltage is input to the positive output terminal VOUT+ and a positive AC voltage is input to the negative output terminal VOUT-, the alarm unit 3 generates an alarm.

[0170] In some embodiments, the alarm unit 3 includes a light emitting unit, which is further configured to control the light emitting unit to emit light when a negative AC voltage is input to the positive output terminal VOUT+ and a positive AC voltage is input to the negative output terminal VOUT−, so as to generate an alarm.

[0171] When voltage is input to the voltage input terminal, a positive DC voltage is input to the positive input terminal VC+, and the negative input terminal VC- is grounded, the first anti-backfeed unit 61 is in the on state, the light-emitting unit in the alarm unit 3 is short-circuited, the light-emitting unit does not emit light, and the alarm unit 3 does not issue an alarm. When AC power is input to the voltage output terminal, if a positive AC voltage is input to the positive output terminal VOUT+ and a negative AC voltage is input to the negative output terminal VOUT-, the first anti-backfeed unit 61 is in the off state, current cannot flow into the alarm unit 3, the light-emitting unit does not emit light, and the alarm unit 3 does not issue an alarm. If a negative AC voltage is input to the positive output terminal VOUT+ and a positive AC voltage is input to the negative output terminal VOUT-, the first anti-backfeed unit 61 is in the on state, the light-emitting unit in the alarm unit 3 is turned on, the light-emitting unit emits light, and the alarm unit 3 issues an alarm.

[0172] In some embodiments, the light emitting unit includes a light emitting diode LED1 , and the alarm unit 3 further includes a seventh diode D2 , a twenty-seventh resistor R2 , and a twenty-eighth resistor R1 .

[0173] The anode of the light-emitting diode LED1 is connected to the negative output terminal VOUT-, and the cathode of the light-emitting diode LED1 is connected to the positive input terminal VC+ and the first anti-backfeed unit 61 respectively via the twenty-seventh resistor R2 and the twenty-eighth resistor R1 connected in series; the anode of the seventh diode D2 is connected to the cathode of the light-emitting diode LED1, and the cathode of the seventh diode D2 is connected to the anode of the light-emitting diode LED1.

[0174] In the case where the first anti-backflow unit 61 includes an anti-backflow diode D1, the cathode of the light-emitting diode LED1 is connected to the positive input terminal VC+ and the anode of the anti-backflow diode D1 via a twenty-seventh resistor R2 and a twenty-eighth resistor R1 connected in series. The twenty-seventh resistor R2 and the twenty-eighth resistor R1 are both current-limiting resistors that limit the current flowing through the light-emitting diode LED1. The seventh diode D2 is configured to short-circuit the light-emitting diode LED1 when a voltage is input to the voltage input terminal.

[0175] According to the auxiliary power supply module provided in the embodiment of the present application, the charging circuit 10 charges the energy storage unit 20 through the main power supply voltage when the main power supply voltage is normal. The power-off detection delay circuit 30 determines that the main power supply voltage has lost power when the duration during which the main power supply voltage is less than the first target voltage reaches the target duration. The boost circuit 40 converts the energy storage voltage of the energy storage unit 20 into a power supply voltage to supply power to the power distribution terminal, thereby avoiding detecting short-term fluctuations in the main power supply voltage as a power outage, thereby avoiding the auxiliary power supply module from supplying power to the power distribution terminal when the main power supply voltage fluctuates briefly, thereby improving the service life of the auxiliary power supply module and improving the power supply stability.

[0176] Furthermore, if an overvoltage fault occurs in the energy storage unit 20, the energy storage unit 20 is protected against undervoltage. If a short circuit fault occurs in the energy storage unit 20, the energy storage unit 20 is protected against short circuits. When the voltage of the energy storage unit 20 is low, power to the distribution terminal is stopped to prevent overdischarge of the energy storage unit 20. If a short circuit fault occurs at the power output terminal 50, the auxiliary power supply module is protected against short circuits, and the module is able to self-recover after the short circuit at the power output terminal 50 is eliminated. When an AC voltage is connected to the power output terminal 50, AC backflow is prevented and an alarm is issued.

[0177] In addition, the auxiliary power module is housed in a power box that can be installed at the meter end of the distribution terminal. By simply reinstalling the meter end cover, existing terminal equipment can be retrofitted. Installation is simple and requires no changes to the terminal's wiring or modifications. The power box measures 147mm x 27mm, meeting the need for miniaturization. It is also waterproof and detachable for easy operation and maintenance.

[0178] Accordingly, an embodiment of the present application also provides a power distribution system.

[0179] The power distribution system provided in the embodiment of the present application includes an auxiliary power supply module and a power distribution terminal. Among them, the auxiliary power supply module is the auxiliary power supply module in the above embodiment. The power distribution terminal is connected to the power output end of the auxiliary power supply module, and is used to be powered by the main power supply voltage when the main power supply voltage is normal; when the duration of the main power supply voltage being less than the first target voltage reaches the target duration, the power is supplied by the power supply voltage output by the auxiliary power supply module. Among them, the power distribution terminal may include at least one of a dedicated transformer terminal and an electric meter device (such as a three-phase meter).

[0180] The power distribution terminal includes a main power supply terminal and an auxiliary power supply terminal. The main power supply terminal is connected to the main power supply voltage, and the auxiliary power supply terminal is connected to the power output terminal of the auxiliary power supply module. When the main power supply voltage is normal, the main power supply voltage supplies power to the distribution terminal through the main power supply terminal. When the main power supply voltage is less than the first target voltage for a target duration, the auxiliary power supply module determines that the main power supply voltage has been lost. The auxiliary power supply module outputs the power supply voltage to the distribution terminal through the auxiliary power supply terminal to supply power to the distribution terminal, allowing the distribution terminal to continue operating and complete power outage event reporting and time-sharing power data transmission.

[0181] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "first," "second," and the like generally distinguish objects of a class and do not limit the number of objects. For example, the first object may be one or more.

[0182] In the description of this application, “plurality” means two or more.

[0183] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0184] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A power failure detection delay circuit, characterized in that: Applied to the auxiliary power supply module, the power-off detection delay circuit includes a circuit input terminal, a voltage terminal, a circuit output terminal, a voltage detection unit and a delay output unit; The voltage detection unit is connected to the circuit input terminal and the delay output unit respectively, and is used to provide a control voltage to the delay output unit when the voltage of the circuit input terminal is normal; and stop providing the control voltage to the delay output unit when the voltage of the circuit input terminal is less than a first target voltage; The delayed output unit is respectively connected to the voltage end and the circuit output end, and is used to provide a working voltage to the circuit output end according to the voltage of the voltage end when the duration for which the voltage at the circuit input end is less than the first target voltage reaches a target duration; when the voltage at the circuit input end is normal, stop providing the working voltage to the circuit output end according to the control voltage; the working voltage is used to control the auxiliary power supply module to supply power to the power distribution terminal.

2. The power failure detection delay circuit according to claim 1, wherein: The delay output unit includes a first transistor; The delayed output unit is further configured to, when the duration for which the voltage at the circuit input terminal is less than the first target voltage reaches the target duration, turn on the first transistor so that the voltage terminal is connected to the circuit output terminal, and provide the operating voltage to the circuit output terminal according to the voltage at the voltage terminal; and, when the voltage at the circuit input terminal is normal, turn off the first transistor according to the control voltage so that the voltage terminal is disconnected from the circuit output terminal, and stop providing the operating voltage to the circuit output terminal.

3. The power failure detection delay circuit according to claim 2, wherein: The delay output unit further includes a charging resistor and a charging capacitor; The delay output unit is further configured to, when the voltage at the circuit input terminal is lower than a first target voltage, enable the voltage at the voltage terminal to charge the charging capacitor via the charging resistor, so as to increase the voltage at the control terminal of the first transistor; When the charging time of the charging capacitor reaches the target time, the voltage of the control terminal of the first transistor is increased to its threshold voltage to turn on the first transistor.

4. The power failure detection delay circuit according to claim 3, wherein: The delay output unit further includes a voltage regulator tube, an isolation diode, a first filter capacitor and a second filter capacitor; The control terminal of the first transistor is connected to the voltage detection unit, the first terminal of the first transistor is connected to the voltage terminal, the second terminal of the first transistor is connected to the anode of the isolation diode, and the cathode of the isolation diode is connected to the circuit output terminal; One end of the charging resistor is connected to the voltage terminal, the other end of the charging resistor is connected to the control terminal of the first transistor and one end of the charging capacitor respectively, and the other end of the charging capacitor is grounded; the voltage regulator diode is connected in parallel with the charging capacitor; One end of the first filter capacitor is connected to the circuit output end, and the other end of the first filter capacitor is grounded; the second filter capacitor is connected in parallel with the first filter capacitor.

5. The power failure detection delay circuit according to claim 3, wherein: The voltage detection unit is further configured to release the charging voltage of the charging capacitor when the voltage at the circuit input terminal returns to normal.

6. The power failure detection delay circuit according to claim 1, wherein: The voltage detection unit is further configured to determine that the voltage at the circuit input end has returned to normal when the voltage at the circuit input end is greater than a second target voltage; the second target voltage is greater than the first target voltage.

7. The power failure detection delay circuit according to any one of claims 1 to 6, characterized in that: The voltage detection unit includes a switching element; The voltage detection unit is also used to turn on the switching element to provide the control voltage to the delay output unit when the voltage at the circuit input end is normal; and to turn off the switching element to stop providing the control voltage to the delay output unit when the voltage at the circuit input end is less than the first target voltage.

8. The power failure detection delay circuit according to claim 7, wherein: The switch element includes an optocoupler, and the voltage detection unit further includes a diode, a third filter capacitor, a first resistor, a second resistor, a third resistor, and a fourth resistor; The positive input terminal of the optocoupler is connected to the circuit input terminal via the first resistor and the second resistor connected in series, the negative input terminal of the optocoupler is grounded via the third resistor and the fourth resistor connected in series, the positive output terminal of the optocoupler is connected to the delay output unit, and the negative output terminal of the optocoupler is grounded; The cathode of the diode is connected to the positive input terminal of the optocoupler, and the anode of the diode is connected to the negative input terminal of the optocoupler; the third filter capacitor is connected in parallel with the diode.

9. The power failure detection delay circuit according to claim 7, wherein: The switch element includes a second transistor, and the voltage detection unit further includes a fifth resistor, a sixth resistor, and a seventh resistor; The control end of the second transistor is connected to the fifth resistor and the sixth resistor respectively, the other end of the fifth resistor is connected to the circuit input end, and the other end of the sixth resistor is grounded; the first end of the second transistor is connected to the delay output unit, and the second end of the second transistor is grounded via the seventh resistor.

10. An auxiliary power supply module, characterized in that: It includes a charging circuit, an energy storage unit, a boost circuit and a power-off detection delay circuit; The charging circuit is connected to the energy storage unit and is used to charge the energy storage unit through the power supply voltage when the main power supply voltage is normal; The energy storage unit is connected to the boost circuit and is used to provide energy storage voltage to the boost circuit; The power failure detection delay circuit is the power failure detection delay circuit according to any one of claims 1 to 9, wherein a circuit input end of the power failure detection delay circuit is connected to the charging circuit, and a voltage end and a circuit output end of the power failure detection delay circuit are respectively connected to the boost circuit; The boost circuit is used to provide voltage to the voltage end of the power-off detection delay circuit, and to perform power supply operation at the operating voltage of the circuit output end of the power-off detection delay circuit to convert the energy storage voltage into a power supply voltage; the power supply voltage is used to power the power distribution terminal.

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