A novel under-sampling least square digital predistortion method and system

Abstract

This invention discloses a novel undersampled least-squares digital predistortion method and system, belonging to the field of mobile communication. This method adds a bandpass filter to the receiving analog side, segments the received feedback signal, constructs a least-squares coefficient update equation, groups the feedback signals according to different terms, constructs basis functions using 3rd and 5th term basis functions, passes them through a digital low-pass filter, and finally uses least-squares estimation to determine the coefficients of the 3rd and 5th basis functions corresponding to the power level. The forward data is then fed back, and the forward data looks up the corresponding coefficients based on the power level and calculates the predistortion output. This solves the problem of excessive energy consumption in existing technologies that require displaying lookup tables for digital predistortion.

Description

Technical Field

[0001] This invention belongs to the field of mobile communication technology, specifically relating to a novel undersampled least squares digital predistortion method and system. Background Technology

[0002] With the development of communication technology, signal bandwidth has become increasingly wider, from 5MHz and 10MHz in the past to 100MHz and 200MHz today. This wider bandwidth leads to increased signal distortion after passing through the power amplifier. Therefore, various algorithms and devices are often used to eliminate this distortion. Common distortion methods include feedforward, feedback, analog predistortion, and digital predistortion. Among these, digital predistortion is widely used due to its lower cost and better performance. The digital predistortion method adds a predistortion module before the power amplifier. By superimposing the inverse function of the power amplifier, the nonlinearity after passing through the power amplifier is precisely canceled out, thereby improving the linearity range of the power amplifier and reducing adjacent band interference (ACLR) and in-band EVM.

[0003] In digital predistortion, since it is necessary to acquire the distorted signal after power amplification, and the spectrum of the distorted signal will be broadened to 3 to 5 times the bandwidth, a high sampling rate ADC is often required to acquire the real and imaginary data. It is generally believed that when the sampling rate is 4 to 5 times the signal bandwidth, the full sampling of the distorted signal can be obtained.

[0004] For example, when the signal bandwidth is 100MHz, the sampling rate of both the real and imaginary parts of the ADC needs to be 500 MSPS to achieve full sampling. This leads to higher costs for analog components, which contradicts the low-cost principle of DPD (Digital Device Processing). To solve this problem, it is necessary to consider a method to reduce the ADC sampling rate, which we call undersampling ADC in this paper, thereby reducing the overall cost of the analog section and the related analog requirements.

[0005] Furthermore, in the forward pass of DPD, LUT tables are often used for forward predistortion processing. The amplitude values ​​of the input signal often need to be quantized and mapped to the corresponding LUT tables. This results in a very large number of LUT tables, requiring a lot of storage resources. Moreover, due to the quantization of LUT tables, there is often quantization loss. Summary of the Invention

[0006] To address the problems of excessive resource consumption and high ADC sampling rate in the predistortion process of existing technologies, this invention proposes a novel undersampled least squares digital predistortion method and system, which can reduce the size of the LUT and the sampling rate of the ADC.

[0007] To achieve the above objectives, the technical solution adopted by this invention is: to provide a novel undersampled least squares digital predistortion method, comprising the following steps:

[0008] S1: Divide the input signal into segments;

[0009] S2: Construct the predistortion basis functions;

[0010] S3: Calculate the output of the 3rd and 5th order basis filters;

[0011] S4: Perform LS coefficient pre-distortion training;

[0012] S5: Construct the predistorter;

[0013] Preferably, in step S1, the input signal is categorized according to its power, and the signal address is converted into a 3rd-order term address, a 5th-order term address, etc., and then uniformly set to the input signal as... First, the input signal is quantized into M bits.

[0014]

[0015] Among them, high Bits are the addresses of cubic entries, the middle one. Bits represent the address of the 5th term, the lowest M- - Q Represents the signal address; each input signal is determined by its high-order value. and the middle Bits are used to divide different power levels, and the coefficients between different power levels are different.

[0016] In a more efficient manner, the predistortion basis function is constructed in step S2 as follows: Let the basis function be... Let the value of the signal address be represented as Then the basis functions are expressed as:

[0017]

[0018] In step S3, the calculation process for the 3rd and 5th order basis filter outputs is as follows:

[0019] Let the output of the 3rd order basis filter be The output after 5th-order basis filtering The low-pass filter coefficients are Let the length of the low-pass filter be L, where n represents the filtered output at time n, then we have:

[0020]

[0021]

[0022] The new substrate after the low-pass filter is and .

[0023] In the optimal S4 process, the pre-distortion training of LS coefficients specifically manifests as follows:

[0024] Construct the LS equations,

[0025]

[0026] in

[0027]

[0028]

[0029] Then, using the LS estimation method, the coefficient combination C is obtained as follows:

[0030]

[0031] in This represents finding the inverse matrix of B.

[0032] In step S5, the predistorter is constructed as follows: First, the input signal is selected according to different power levels, using the same method as in the coefficient calculation, and the input signal is uniformly set to... The input signal is quantized into M bits.

[0033]

[0034] Among them, high Bits are the addresses of cubic entries, the middle one. Bits represent the address of the 5th term, the lowest M- - Represents the signal address, let the value of the signal address be expressed as ,

[0035] Then, using the 3rd and 5th term addresses, a lookup table is performed to retrieve the coefficient for the corresponding power level. Let the retrieved coefficient be... and The final output of the predistorter is:

[0036]

[0037] Among them | |Represents the Find the absolute value.

[0038] This invention also provides a novel undersampled least squares digital predistortion system, comprising a predistorter, a DAC circuit, a PA circuit, a coupler circuit, an antenna, a BPF circuit, a frequency conversion circuit, a full-band model estimation module, a predistorter coefficient training module, an ADC circuit, and a calculation module.

[0039] Preferably, the BPF circuit includes a first BPF circuit and a second BPF circuit; the first BPF circuit is placed on the analog side of the receiver.

[0040] Preferably, the frequency converter circuit includes an up-converter circuit and a down-converter circuit.

[0041] Preferably, the predistorter is connected to the DAC circuit, the DAC circuit is connected to the upconversion circuit, the upconversion circuit is connected to the PA circuit, the coupler circuit is connected to the PA circuit, and the antenna is connected to the coupler. The other end of the coupler is connected to the first BPF circuit, the first BPF circuit is connected to the downconversion circuit, the downconversion circuit is connected to the ADC circuit, one end of the ADC circuit is connected to the predistorter coefficient training module, the other end of the ADC circuit is connected to the predistorter coefficient training module, and the second BPF circuit is also connected to the predistorter coefficient training module.

[0042] Preferably, the first BPF circuit is placed on the analog side of the receiver.

[0043] Ideally, the DAC circuit segments the received feedback signal and constructs the LS coefficient update equation. Then, it groups the input signal according to different input signal power, constructs the basis function using the 3rd and 5th term basis, and estimates the coefficients of the 3rd and 5th basis for the corresponding power level using the LS algorithm through a digital low-pass filter. Finally, it feeds the forward data to the predistorter coefficient training module.

[0044] Ideally, the predistorter coefficient training module finds the corresponding coefficients based on the power level and calculates the predistortion output to complete the digital predistortion process.

[0045] The English translations used in this invention are as follows:

[0046] DPD Digital Pre-Distortion PA Power Amplifier ADC Analog Digital Converter MSPS Mega sample per second EVM Error Vector Magnitude ACLR Adjacent Channel Leakage Ratio LUT Look Up Table

[0047] Compared with the prior art, the technical solution of the present invention has the following advantages / benefits:

[0048] 1. This invention performs segmented calculations on the input signal, reducing the consumption of LUT.

[0049] 2. The present invention modifies the signal processing flow by first passing the input signal through the ADC circuit and then through the BPF circuit, thereby reducing the sampling rate of the ADC. Attached Figure Description

[0050] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort.

[0051] Figure 1 This is a schematic diagram of the structure of a novel undersampling least squares digital predistortion method and system according to the present invention.

[0052] Figure 2 This is a schematic diagram of the gear positions divided by the input signal of the present invention. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention are described clearly and completely below. Obviously, the described embodiments are only a part of the embodiments of this invention, not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this invention. Therefore, the detailed description of the embodiments of this invention provided below is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the invention.

[0054] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

[0055] Example 1: A novel undersampled least squares digital predistortion method is provided, comprising the following steps:

[0056] S1: Divide the input signal into segments;

[0057] S2: Construct the predistortion basis functions;

[0058] S3: Calculate the output of the 3rd and 5th order basis filters;

[0059] S4: Perform LS coefficient pre-distortion training;

[0060] S5: Construct the predistorter;

[0061] In step S1, such as Figure 2 As shown, the input signal is categorized according to its power, and the signal address is converted into a 3rd-order term address, a 5th-order term address, etc., and then uniformly denoted as the input signal. First, the input signal is quantized into M bits.

[0062]

[0063] Among them, high Bits are the addresses of cubic entries, the middle one. Bits represent the address of the 5th term, the lowest M- - Q Represents the signal address; each input signal is determined by its high-order value. and the middle Bits are used to divide different power levels, and the coefficients between different power levels are different.

[0064] In step S2, the process of constructing the predistortion basis function is as follows: Let the basis function be... Let the value of the signal address be represented as Then the basis functions are expressed as:

[0065]

[0066] In step S3, the calculation process for the 3rd and 5th order basis filter outputs is as follows:

[0067] Let the output of the 3rd order basis filter be The output after 5th-order basis filtering The low-pass filter coefficients are Let the length of the low-pass filter be L, where n represents the filtered output at time n, then we have:

[0068]

[0069]

[0070] The new substrate after the low-pass filter is and .

[0071] During S4, the predistortion training of LS coefficients specifically manifests as follows:

[0072] Construct the LS equations,

[0073]

[0074] in

[0075]

[0076]

[0077] Then, using the LS estimation method, the coefficient combination C is obtained as follows:

[0078]

[0079] in This represents finding the inverse matrix of B.

[0080] In step S5, the predistorter is constructed as follows: Figure 2 As shown, firstly, the input signal selects the power level according to different power levels. The selection method is consistent with the coefficient calculation, and the input signal is uniformly set to... The input signal is quantized into M bits.

[0081]

[0082] Among them, high Bits are the addresses of cubic entries, the middle one. Bits represent the address of the 5th term, the lowest M- - Represents the signal address, let the value of the signal address be expressed as ,

[0083] Then, using the 3rd and 5th term addresses, a lookup table is performed to retrieve the coefficient for the corresponding power level. Let the retrieved coefficient be... and The final output of the predistorter is:

[0084]

[0085] Among them | |Represents the Find the absolute value.

[0086] Example 2: Figure 1 As shown, a novel undersampled least squares digital predistortion system includes a predistorter, a DAC circuit, a PA circuit, a coupler circuit, an antenna, a BPF circuit, a frequency conversion circuit, a full-band model estimation module, a predistorter coefficient training module, an ADC circuit, and a calculation module.

[0087] The BPF circuit includes a first BPF circuit and a second BPF circuit; the first BPF circuit is placed on the analog side of the receiver.

[0088] A frequency converter circuit includes an up-conversion circuit and a down-conversion circuit.

[0089] The predistorter is connected to the DAC circuit, which is connected to the upconverter circuit. The upconverter circuit is connected to the PA circuit, and the coupler circuit is connected to the PA circuit. The antenna is connected to the coupler, and the other end of the coupler is connected to the first BPF circuit. The first BPF circuit is connected to the downconverter circuit, which is connected to the ADC circuit. One end of the ADC circuit is connected to the predistorter coefficient training module, and the other end of the ADC circuit is also connected to the predistorter coefficient training module. The second BPF circuit is also connected to the predistorter coefficient training module.

[0090] A bandpass filter is added to the receiving analog side. The obtained feedback signal is then segmented, and an LS coefficient update equation is constructed. The feedback signals are then grouped according to different terms. The basis functions are constructed using the 3rd and 5th term basis functions and passed through a digital low-pass filter. Finally, the coefficients of the 3rd and 5th term basis functions corresponding to the power level are estimated using LS and the forward data is fed back. The forward data finds the corresponding coefficients according to the power level and calculates the predistortion output.

[0091] BPF stands for band-pass filter, ADC stands for analog-to-digital converter, and PA stands for power amplifier.

[0092] The above are merely preferred embodiments of the present invention. It should be noted that the above preferred embodiments should not be considered as limitations on the present invention, and the scope of protection of the present invention should be determined by the scope defined in the claims. For those skilled in the art, several improvements and modifications can be made without departing from the spirit and scope of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A novel undersampled least squares digital predistortion method, characterized in that, Includes the following steps: S1: Divide the input signal into segments; S2: Construct the predistortion basis functions; S3: Calculate the output of the 3rd and 5th order basis filters; S4: Perform least squares coefficient pre-distortion training; S5: Construct the predistorter to complete digital predistortion; In step S1, the input signal is categorized according to its power, and the signal address is converted into a 3rd-order term address and a 5th-order term address, with the input signal uniformly designated as... First, the input signal is quantized into M bits: ； In step S5, the predistorter is constructed as follows: First, the input signal is selected according to different power levels. The selection method is consistent with the coefficient calculation, and the input signal is uniformly set to... The input signal is quantized into M bits. , Let the value of the signal address be represented as Then, using the 3rd and 5th term addresses, a lookup table is performed to retrieve the coefficient for the corresponding power level. Let the retrieved coefficient be... and The final output of the predistorter is: , Among them | |Represents the Find the absolute value.

2. The novel undersampled least squares digital predistortion method according to claim 1, characterized in that, In step S2, the process of constructing the predistortion basis function is as follows: Let the basis function be... Let the value of the signal address be represented as Then the basis functions are expressed as: , Among them | | represents taking the absolute value, C1 represents the first estimated coefficient, and C2 represents the second estimated coefficient. A digital signal representing quantization.

3. A novel undersampled least squares digital predistortion method according to claim 2, characterized in that, In step S3, the calculation process for the 3rd and 5th order basis filter outputs is as follows: Let the output of the 3rd order basis filter be The output after 5th-order basis filtering The low-pass filter coefficients are Let the length of the low-pass filter be L, where n represents the filtered output at time n, then we have: , The new substrate after the low-pass filter is and .

4. A novel undersampled least squares digital predistortion method according to claim 3, characterized in that, In the S4 process, the least squares coefficient predistortion training is specifically manifested as follows: Constructing LS equations , in , Then, using the least squares estimation method, the coefficient combination C is obtained as follows: , in This represents finding the inverse of matrix B.

5. A novel undersampled least squares digital predistortion system, characterized in that, It includes a predistorter, a DAC circuit, a PA circuit, a coupler circuit, an antenna, a BPF circuit, a frequency conversion circuit, a full-band model estimation module, a predistorter coefficient training module, an ADC circuit, and a calculation module. The BPF circuit includes a first BPF circuit and a second BPF circuit. The frequency conversion circuit includes an up-conversion circuit and a down-conversion circuit. The predistorter is connected to the DAC circuit, the DAC circuit is connected to the upconversion circuit, the upconversion circuit is connected to the PA circuit, the coupler circuit is connected to the PA circuit, and the antenna is connected to the coupler. The other end of the coupler is connected to the first BPF circuit, the first BPF circuit is connected to the downconversion circuit, the downconversion circuit is connected to the ADC circuit, one end of the ADC circuit is connected to the predistorter coefficient training module, and the other end of the ADC circuit is connected to the second BPF circuit. The second BPF circuit is also connected to the predistorter coefficient training module. The first BPF circuit is placed on the analog side of the receiver; The DAC circuit segments the obtained feedback signal and constructs the LS coefficient update equation. Then, it groups the input signal according to different input signal power, constructs the basis function using the 3rd and 5th term basis, and estimates the coefficients of the 3rd and 5th basis for the corresponding power level using the LS algorithm through a digital low-pass filter. Finally, it feeds forward data to the predistorter coefficient training module. The signal segmentation process is as follows: The signal address is converted into a 3rd-order term address and a 5th-order term address, and the input signal is uniformly set to... First, the input signal is quantized into M bits: , The construction process of the predistorter is as follows: First, the input signal is selected according to different power levels. The selection method is the same as in the coefficient calculation. Let the input signal be uniformly set to... Quantize the input signal into M bits. , Let the value of the signal address be represented as Then, using the 3rd and 5th term addresses, a lookup table is performed to retrieve the coefficient for the corresponding power level. Let the retrieved coefficient be... and The final output of the predistorter is: , Among them | |Represents the Find the absolute value.

6. A novel undersampled least squares digital predistortion system according to claim 5, characterized in that, The predistorter coefficient training module finds the corresponding coefficients according to the power level and calculates the predistortion output to complete the digital predistortion process.

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