A high-precision comparator for SAR ADC

Abstract

The present invention discloses a high-precision comparator for a SAR ADC, belonging to the technical field of comparators. The high-precision comparator has a cascade structure, wherein the first to Nth stages are static amplifier stages, wherein the circuit structure of each stage is identical, and the internal device size and drive current are adjusted according to the load conditions; the final stage is a latch, which converts the amplified analog signal into a digital output through positive feedback. The present invention, through the low-voltage design of the amplifier load end, can allow the input common-mode level of the comparator to be the power supply voltage VDD. In this way, when the SAR ADC samples the bottom plate, the capacitor top plate of its DAC does not require an additional common-mode level generation circuit, but only needs to be connected to the power supply voltage VDD, which can achieve the purpose of saving area and power consumption. At the same time, the comparator can support low-power supply voltage applications.

Description

Technical Field

[0001] The present invention belongs to the technical field of comparators, and in particular relates to a high-precision comparator for SAR ADC. Background Art

[0002] For general-purpose SAR ADCs (successive approximation analog-to-digital converters), which require high precision but relatively low speed, backplane sampling with synchronous timing is often used. In the backplane sampling scheme, the lower plate of the SAR ADC's DAC (digital-to-analog converter) capacitor is connected to the input signal during the sampling phase, while the upper plate is connected to the common-mode voltage. This requires a common-mode voltage generation circuit, which results in additional area and power consumption. Furthermore, the load of a traditional amplifier circuit is a diode-connected MOS transistor, which consumes the voltage margin of Vgs (gate-source voltage), limiting the amplifier's bias voltage margin when VDD is low. Another commonly used load is a resistive load, but this also makes it difficult to balance gain and bias common-mode voltage. Summary of the Invention

[0003] The object of the present invention is to provide a high-precision comparator for SAR ADC, which can reduce a common-mode level generating circuit in the SAR ADC and support a lower power supply voltage bias, thereby solving the problems raised in the above background technology.

[0004] To achieve the above objectives, the present invention provides the following technical solution: a high-precision comparator for a SAR ADC, wherein the high-precision comparator has a cascade structure, wherein the first through Nth stages are static amplifier stages, wherein each stage has the same circuit structure, and the internal device size and drive current are adjusted according to the load conditions; the last stage is a latch, which converts the amplified analog signal into a digital output through positive feedback;

[0005] Among them, the input signal of the comparator is the differential input VINP_CMP / VIN_CMP, which is respectively connected to the positive / negative input terminal VIP / VIN of the first-stage amplifier; the positive / negative output terminal line of the first-stage amplifier is named VOP1 / VON1, which is respectively connected to the positive / negative input terminal VIP / VIN of the subsequent circuit; the output lines of the amplifiers from the second to the Nth stage are named VOP2 / VON2 to VOPN / VONN; the last stage is a latch, and the output line of its output port DOP / DON is named DP_CMP / DN_CMP, which is the output signal of the entire comparator.

[0006] Preferably, the first to N-stage static amplifiers further connect a reset signal RST to the RST terminal of the amplifier, and the RST terminals of all N-stage static amplifiers are connected together;

[0007] The first to N-stage static amplifiers are also connected to the comparator automatic zeroing control signal CKAZ to the CKAZ terminal of the amplifier, and the CKAZ terminals of all N-stage static amplifiers are connected together;

[0008] The first to N-stage static amplifiers are further connected to output a common-mode level reset signal CKCM to the CKCM terminal of the amplifier, and the CKCM terminals of all N-stage static amplifiers are connected together;

[0009] The first to N-stage static amplifiers also connect input bias current to their IK_IN terminals, wherein the IK_IN of each stage static amplifier is independent, and the current input signals from the first to N-stage static amplifiers are IK_IN1, IK_IN2 to IK_INN respectively;

[0010] The control signal of the latch is CKLAT.

[0011] Preferably, when the control signal CKLAT=1, the latch starts working and converts the result of the N-stage amplifier into a digital signal through the positive feedback inside the latch. Each time the successive approximation of the SAR ADC is completed after the DAC is established and the comparator amplification is completed, CKLAT=1 starts the latch conversion.

[0012] Preferably, in the first to N-stage static amplifier, the reset signal RST terminal is connected to the reverse reset signal RST_B through the inverter I1; the output common-mode reset signal CKCM terminal is connected to the reverse common-mode reset signal CKCM_B through the inverter I2; and the comparator automatic zeroing control signal CKAZ terminal is connected to the bootstrap switch circuit I3 to AZ_BST;

[0013] Among them, the bootstrap switch circuit is a bootstrap switch. When CKAZ=1, AZ_BST is bootstrapped to twice the power supply voltage 2*VDD; when CKAZ=0, AZ_BST is also 0.

[0014] Preferably, in the high-precision comparator, the input signal VIP / VIN is respectively connected to the gate terminals of the N-type MOS transistor differential input pair M2 and M3; the source terminals of the N-type MOS transistors M2 and M3 are connected to the drain terminal of the tail current source M1A; the drain terminals of the N-type MOS transistors M2 and M3 are respectively connected to the line VN1 / VP1; the source terminal and drain terminal of the reset device P-type MOS transistor M4 are respectively connected to VN1 / VP1, and its gate terminal is connected to the line RST_B; the positive terminals of the resistors R1 and R2 are respectively connected to VN1 and VP1, and the negative terminals of the resistors R1 and R2 are connected together, and the line is named VCM1; the drain terminals of the P-type MOS transistors M5 and M6 are respectively connected to VN1 and VP1, and the source terminals of the P-type MOS transistors M5 and M6 are connected to the power supply voltage VDD. The gate terminals of MOS transistors M5 and M6 are connected together, and the line is named VCM2. The IK_IN terminal is connected to the drain and gate terminals of N-type MOS transistor M1D, and is also connected to the gate terminals of M1A, M1B, and M1C. The source terminals of N-type MOS transistors M1A, M1B, M1C, and M1D are all grounded. The drain terminal of N-type MOS transistor M1C is connected to the drain and gate terminals of P-type MOS transistor M9, and the gate terminal of P-type MOS transistor M7. The source terminals of P-type MOS transistors M9 and M7 are connected to the power supply VDD. The drain terminal of P-type MOS transistor M7 is connected to the VCM1 line. The gate terminal of P-type MOS transistor M8 is connected to the VCM1 line, and the drain terminal is connected to the VCM2 line. The positive terminal of resistor R3 is connected to the VCM2 line grid, and the negative terminal is connected to the drain terminal of M1B, which is one level above the gate of M8.

[0015] The upper plate of capacitor C1 is connected to VN1, and the lower plate is connected to VON; the upper plate of capacitor C2 is connected to VP1, and the lower plate is connected to VOP; the source and drain of N-type MOS transistor M10 are respectively connected across the upper and lower plates of capacitor C1, and the gate is connected to CKCM_B; the source and drain of N-type MOS transistor M11 are respectively connected across the upper and lower plates of capacitor C2, and the gate is connected to CKCM_B; the source and drain of N-type MOS transistor M12 are respectively connected to VOP and VON, and the gate is connected to AZ_BST.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] A high-precision comparator of the present invention, through a low-voltage design at the amplifier load end, allows the comparator's input common-mode level to be the power supply voltage VDD. Thus, when a SAR ADC samples on the bottom plate, the capacitor top plate of its DAC does not require an additional common-mode level generation circuit and only needs to be connected to the power supply voltage VDD. This can save area and power consumption, and the comparator can also support low-power-supply voltage applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1This is the traditional SAR ADC circuit block diagram.

[0019] Figure 2 This is a cascade structure diagram of the high-precision comparator of the present invention.

[0020] Figure 3 This is a block diagram of the high-precision comparator circuit of the present invention.

[0021] Figure 4 This is a specific timing diagram of the clock control signal of the high-precision comparator of the present invention. DETAILED DESCRIPTION

[0022] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0023] Figure 1 This is a traditional SAR ADC block diagram, which mainly consists of a capacitor DAC (Digital to Analog converter) array, a comparator, a REF circuit (reference level drive circuit), clock logic, and data logic.

[0024] like Figure 2As shown, the comparator has a cascaded structure. Stages 1 through 4 are static amplifier stages. The circuit structure of each stage is identical, but the internal device size and drive current are adjusted based on the load. The final stage is a latch, which converts the amplified analog signal into a digital output through positive feedback. The comparator inputs are differential inputs VINP_CMP / VIN_CMP, connected to the positive / negative inputs VIP / VIN of the first-stage amplifier, respectively. The positive / negative outputs of the first-stage amplifier are wired VOP1 / VON1, connected to the positive / negative inputs VIP / VIN of the subsequent stage, respectively. The outputs of stages 2 through 4 are wired VOP2 / VON2 to VOPN / VONN. The outputs of the final stage, DOP / DON, are wired DP_CMP / DN_CMP, representing the output signal of the entire comparator. Stages 1 through 4 are static amplifiers, and the reset signal RST is connected to the RST terminal of each amplifier. The RST terminals of all N stages are connected together. Stages 1 through 4 are static amplifiers, each connected to the CKAZ terminal of the amplifier. All CKAZ terminals of the N-stage amplifiers are connected together. Stages 1 through 4 are static amplifiers, each connected to the CKCM terminal of the amplifier. All CKCM terminals of the N-stage amplifiers are connected together. Stages 1 through 4 are static amplifiers, each connected to the input bias current terminal IK_IN. Each stage's IK_IN terminal is independent, and the current input signals are IK_IN1, IK_IN2, and IK_INN, respectively. CKLAT is the control signal for the final latch.

[0025] Figure 3 This is a circuit block diagram of the high-precision comparator of the present invention. The first through Nth stages are static amplifiers with the following structure: The reset signal RST is connected to the inverted reset signal RST_B via inverter I1. The output common-mode reset signal CKCM is connected to the inverted common-mode reset signal CKCM_B via inverter I2. The comparator auto-zero control signal CKAZ is connected to the bootstrap switch circuit I3 to AZ_BST. The bootstrap switch circuit is a conventional one. When CKAZ = 1, the voltage is boosted to twice the supply voltage (2*VDD); when CKAZ = 0, AZ_BST is also set to 0.

[0026] Input signals VIP / VIN are connected to the gates of the differential input pair of N-type MOS transistors M2 / M3, respectively. The sources of M2 / M3 are connected to the drain of tail current source M1A. The drains of M2 / M3 are connected to lines VN1 / VP1, respectively. The source and drain of reset device P-type MOS transistor M4 are connected across VN1 / VP1, respectively, and its gate is connected to the RST_B line. The positive terminals of resistors R1 and R2 are connected to VN1 and VP1, respectively, and the negative terminals of the two resistors are connected together, a line named VCM1. The drains of P-type MOS transistors M5 and M6 are connected to VN1 and VP1, respectively, and their sources are connected to the power supply voltage VDD. The gates of the two P-type MOS transistors are connected together, a line named VCM2. IK_IN is connected to the drain and gate of N-type MOS transistor M1D, as well as to the gates of M1A / M1B / M1C. The sources of N-type MOS transistors M1A / M1B / M1C / M1D are all connected to ground. The drain of N-type MOS transistor M1C is connected to the drain and gate of P-type MOS transistor M9, as well as the gate of P-type MOS transistor M7. The sources of M9 and M7 are connected to the power supply VDD. The drain of M7 is connected to the VCM1 line. The gate of P-type MOS transistor M8 is connected to the VCM1 line, and its drain is connected to the VCM2 line. The positive terminal of resistor R3 is connected to the grid of VCM2 line, and the negative terminal is connected to the drain of M1B, the level above the gate of M8. The upper plate of capacitor C1 is connected to VN1, and the lower plate is connected to VON. The upper plate of capacitor C2 is connected to VP1, and the lower plate is connected to VOP. The source / drain of N-type MOS transistor M10 is connected across the upper and lower plates of capacitor C1, respectively, and its gate is connected to CKCM_B. The source / drain of N-type MOS transistor M11 is connected across the upper and lower plates of capacitor C2, respectively, and its gate is connected to CKCM_B. The source and drain terminals of the N-type MOS transistor M12 are connected to VOP and VON respectively, and the gate terminal is connected to AZ_BST.

[0027] like Figure 4 As shown, the specific timing of the above clock control signals is:

[0028] The comparator's input control clocks, CKCK and CKAZ, are both active when the ADC sampling clock is high. The rising edge of CKCM is aligned with the rising edge of the ADC sampling clock, but its high-level duration is shorter than the sampling clock, typically set to approximately one-third the sampling clock's high level duration. The falling edge of CKAZ is aligned with the falling edge of the sampling clock, and the rising edge of CKAZ is aligned with the falling edge of CKCM. RST takes effect during the ADC conversion cycle, before the DAC in the SAR ADC has settled, resetting the amplifier. Each SAR ADC's successive approximation phase requires pulling the RST signal to 1 during the DAC's settling phase.

[0029] CKLAT is the control signal of the last-stage latch. When CKLAT=1, the latch starts working and converts the result of the N-stage amplifier into a digital signal through the positive feedback inside the latch. Each time the successive approximation of the SAR ADC is completed after the DAC is established and the comparator amplification is completed, CKLAT=1 starts the latch conversion.

[0030] A high-precision comparator of the present invention utilizes a low-voltage design at the amplifier load end, allowing the comparator's input common-mode level to be equal to the power supply voltage VDD. This allows the SAR ADC, when sampling on the bottom plate, to use a DAC capacitor top plate without requiring additional common-mode level generation circuitry; it only needs to be connected to the power supply voltage VDD. This reduces area and power consumption. Furthermore, the comparator supports low-power-voltage applications.

[0031] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0032] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A high-precision comparator for SAR ADC, characterized in that: The high-precision comparator has a cascade structure, with the first to Nth stages being static amplifier stages. The circuit structure of each stage is identical, with the internal device size and drive current adjusted according to the load conditions. The last stage is a latch, which converts the amplified analog signal into a digital output through positive feedback. The comparator's input signal is the differential input VINP_CMP / VIN_CMP, connected to the positive / negative input terminals VIP / VIN of the first-stage amplifier, respectively. The positive / negative output terminals of the first-stage amplifier are named VOP1 / VON1, connected to the positive / negative input terminals VIP / VIN of the subsequent circuit, respectively. The output lines of the amplifiers from the second to the Nth stage are named VOP2 / VON2 to VOPN / VONN. The final stage is a latch, and the output lines of its output ports DOP / DON are named DP_CMP / DN_CMP, which are the output signals of the entire comparator. In the high-precision comparator, the input signals VIP / VIN are respectively connected to the gate terminals of the N-type MOS transistor differential input pair M2 and M3; the source terminals of the N-type MOS transistors M2 and M3 are connected to the drain terminal of the tail current source M1A; the drain terminals of the N-type MOS transistors M2 and M3 are respectively connected to the line VN1 / VP1; the source terminal and drain terminal of the reset device P-type MOS transistor M4 are respectively connected to VN1 / VP1, and its gate terminal is connected to the line RST_B; the positive terminals of the resistors R1 and R2 are respectively connected to VN1 and VP1, and the negative terminals of the resistors R1 and R2 are connected together, and the line is named VCM1; the drain terminals of the P-type MOS transistors M5 and M6 are respectively connected to VN1 and VP1, and the source terminals of the P-type MOS transistors M5 and M6 are connected to the power supply voltage VDD. The gate terminals of S transistors M5 and M6 are connected together, and the line is named VCM2. The IK_IN terminal is connected to the drain and gate terminals of N-type MOS transistor M1D, and also to the gate terminals of M1A, M1B, and M1C. The source terminals of N-type MOS transistors M1A, M1B, M1C, and M1D are all grounded. The drain terminal of N-type MOS transistor M1C is connected to the drain and gate terminals of P-type MOS transistor M9, and the gate terminal of P-type MOS transistor M7. The source terminals of P-type MOS transistors M9 and M7 are connected to the power supply VDD. The drain terminal of P-type MOS transistor M7 is connected to the VCM1 line. The gate terminal of P-type MOS transistor M8 is connected to the VCM1 line, and the drain terminal is connected to the VCM2 line. The positive terminal of resistor R3 is connected to the VCM2 line grid, and the negative terminal is connected to the drain terminal of M1B, which is one level above the gate of M8. The upper plate of capacitor C1 is connected to VN1, and the lower plate is connected to VON; the upper plate of capacitor C2 is connected to VP1, and the lower plate is connected to VOP; the source and drain of N-type MOS transistor M10 are respectively connected across the upper and lower plates of capacitor C1, and the gate is connected to CKCM_B; the source and drain of N-type MOS transistor M11 are respectively connected across the upper and lower plates of capacitor C2, and the gate is connected to CKCM_B; the source and drain of N-type MOS transistor M12 are respectively connected to VOP and VON, and the gate is connected to AZ_BST.

2. The high-precision comparator for SAR ADC according to claim 1, wherein: The first to N-stage static amplifiers are also connected with a reset signal RST to the RST terminal of the amplifier, and the RST terminals of all N-stage static amplifiers are connected together; The first to N-stage static amplifiers are also connected to the comparator automatic zeroing control signal CKAZ to the CKAZ terminal of the amplifier, and the CKAZ terminals of all N-stage static amplifiers are connected together; The first to N-stage static amplifiers are further connected to output a common-mode level reset signal CKCM to the CKCM terminal of the amplifier, and the CKCM terminals of all N-stage static amplifiers are connected together; The first to N-stage static amplifiers also connect input bias current to their IK_IN terminals, wherein the IK_IN of each stage static amplifier is independent, and the current input signals from the first to N-stage static amplifiers are IK_IN1, IK_IN2 to IK_INN respectively; The control signal of the latch is CKLAT. When the control signal CKLAT=1, the latch starts working and converts the result of the N-stage amplifier into a digital signal through the positive feedback inside the latch. Each time the successive approximation of the SAR ADC is completed after the DAC is established and the comparator amplification is completed, CKLAT=1 starts the latch conversion.

3. The high-precision comparator for SAR ADC according to claim 2, wherein: In the first-stage to N-stage static amplifier, the reset signal RST terminal is connected to the reverse reset signal RST_B through the inverter I1; the output common-mode level reset signal CKCM terminal is connected to the reverse common-mode level reset signal CKCM_B through the inverter I2; the comparator automatic zeroing control signal CKAZ terminal is connected to the bootstrap switch circuit I3 to AZ_BST; Among them, the bootstrap switch circuit is a bootstrap switch. When CKAZ=1, the output AZ_BST of the bootstrap switch circuit is bootstrapped to twice the power supply voltage 2*VDD; when CKAZ=0, AZ_BST is also 0.

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