Asynchronous reset state controllable trigger circuit structure

Abstract

The present invention relates to the field of chip technology, and more particularly to a flip-flop circuit structure with a controllable asynchronous reset state, comprising a first flip-flop, a second flip-flop, a reset setting module, and a set setting module, wherein a first reset data terminal and a first set data terminal are both used to receive a first reset signal, a second reset data terminal and a second set data terminal are both connected to a second output terminal, the reset output terminal is connected to the first reset terminal, and the set output terminal is connected to the first set terminal, and the second reset terminal is used to receive a second reset signal; the signal output by the reset output terminal and the signal output by the set output terminal are mutually exclusive, and when the first reset signal is valid, the first flip-flop is reset to 0 by the first reset terminal or set to 1 by the first set terminal. The present invention can control the asynchronous reset state of the flip-flop according to application requirements.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a trigger circuit structure with a controllable asynchronous reset state. Background Art

[0002] The reset operation of a flip-flop can be performed synchronously or asynchronously, depending on the design requirements. Synchronous reset relies on a clock signal, while asynchronous reset can take effect immediately at any time. The active level of the reset signal also affects the behavior of the reset operation. The reset signal of an asynchronous reset can reset the flip-flop at any time, independent of the clock signal. The existing technology has a fixed asynchronous reset value for the flip-flop. When the reset signal is valid, the flip-flop is fixed to 0 or fixed to 1, which is uncontrollable. However, in some application scenarios, such as power management design, the flip-flop needs to be reset to different values ​​at different application stages, rather than a fixed value. Therefore, how to provide a flip-flop circuit structure with controllable asynchronous reset state has become a technical problem that needs to be solved urgently. Summary of the Invention

[0003] The present invention aims to provide a trigger circuit structure with a controllable asynchronous reset state, which can control the asynchronous reset state of the trigger according to application requirements.

[0004] According to a first aspect of the present invention, there is provided a trigger circuit structure with controllable asynchronous reset state, comprising a first trigger, a second trigger, a reset setting module and a set setting module, wherein:

[0005] The first trigger includes a first reset terminal, a first set terminal, and a first data terminal;

[0006] The second trigger includes a second reset terminal and a second output terminal;

[0007] The reset setting module includes a first reset data terminal, a second reset data terminal and a reset output terminal;

[0008] The setting module includes a first setting data terminal, a second setting data terminal and a setting output terminal;

[0009] The first reset data terminal and the first set data terminal are both used to receive a first reset signal, the second reset data terminal and the second set data terminal are both connected to the second output terminal, the reset output terminal is connected to the first reset terminal, the set output terminal is connected to the first set terminal, and the second reset terminal is used to receive a second reset signal;

[0010] The signal output by the reset output terminal and the signal output by the set output terminal are mutually exclusive. When the first reset signal is valid, the first trigger is reset to 0 by the first reset terminal or set to 1 by the first set terminal. When the first reset signal is invalid, the first trigger updates the value stored in the first trigger to the value input by the first data terminal when the rising edge of the clock connected to the first trigger arrives.

[0011] The present invention has significant advantages and beneficial effects compared to the prior art. By utilizing the above technical solution, the present invention provides an asynchronous reset state controllable trigger circuit structure that achieves considerable technological advancement and practicality, and has wide industrial application value, with at least the following beneficial effects:

[0012] The present invention provides two triggers and a reset setting module and a set setting module. The output value of one of the triggers is combined with the reset setting module and the set setting module so that the signal output by the reset output terminal and the signal output by the set output terminal are mutually exclusive. When the first reset signal is valid, the first trigger is reset to 0 by the first reset terminal or set to 1 by the first set terminal, thereby realizing the ability to control the asynchronous reset state of the trigger according to application requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A schematic diagram of the structure of a trigger circuit with controllable asynchronous reset state provided by one embodiment of the present invention;

[0015] Figure 2 A schematic diagram of the structure of a trigger circuit with controllable asynchronous reset state provided in the first embodiment of the present invention;

[0016] Figure 3 A schematic diagram of the structure of a trigger circuit with controllable asynchronous reset state provided in the second embodiment of the present invention;

[0017] Figure 4 A schematic diagram of the structure of a trigger circuit with controllable asynchronous reset state provided in the third embodiment of the present invention;

[0018] Figure 5 This is a schematic diagram of the structure of an asynchronous reset state controllable trigger circuit provided in Example 4 of the present invention. DETAILED DESCRIPTION

[0019] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0020] The embodiment of the present invention provides a trigger circuit structure with controllable asynchronous reset state, such as Figure 1 As shown, it includes a first trigger, a second trigger, a reset setting module and a set setting module.

[0021] The first flip-flop includes a first reset terminal (R1), a first set terminal (S1), and a first data terminal (D1). It is understood that the first flip-flop also includes a first output port (Q1) and a clock port (not shown in the figure) for inputting a corresponding clock signal. The second flip-flop includes a second reset terminal (R2), a second output terminal (Q2), and a second data terminal (D2). It is understood that the second flip-flop also includes a clock port (not shown in the figure) for inputting a corresponding clock signal. The second data terminal is connected to a combinational logic circuit.

[0022] The reset setting module includes a first reset data terminal, a second reset data terminal and a reset output terminal. The set setting module includes a first set data terminal, a second set data terminal and a set output terminal.

[0023] The first reset data terminal and the first set data terminal are both used to receive a first reset signal. The second reset data terminal and the second set data terminal are both connected to a second output terminal. The reset output terminal is connected to the first reset terminal, and the set output terminal is connected to the first set terminal. The second reset terminal is used to receive a second reset signal. The first reset signal and the second reset signal are different reset signals. The second reset signal is used to set an initial value or reset value for a second flip-flop. When the second flip-flop is in normal operation, the value in the second flip-flop is determined by the clock signal and data port of the second flip-flop.

[0024] The signal output by the reset output terminal and the signal output by the set output terminal are mutually exclusive. When the first reset signal is valid, the first flip-flop is reset to 0 by the first reset terminal or set to 1 by the first set terminal. That is, when the first reset signal is valid, only one of the signal output by the reset output terminal and the signal output by the set output terminal will affect the value of the first flip-flop, thereby achieving controllable asynchronous reset state of the first flip-flop. When the first reset signal is invalid, the signal output by the reset output terminal and the signal output by the set output terminal do not affect the value of the first flip-flop. The first flip-flop updates the value stored in the first flip-flop to the value input by the first data terminal when the rising edge of the clock connected to the first flip-flop arrives.

[0025] As an embodiment, the circuit structure may further include an output control circuit, wherein the data end of the output control circuit is connected to the second output end, and the output end of the output control circuit is connected to the second reset data end and the second set data end. The output control circuit is used to adjust the value output by the second output end and transmit the adjusted value to the second reset data end and the second set data end, thereby increasing the flexibility of asynchronous reset state control.

[0026] The first reset terminal and the first set terminal can be configured as asynchronous low-level active ports or asynchronous high-level active ports. An asynchronous low-level active port is an asynchronous port that performs a reset or set operation upon receiving a low level. An asynchronous high-level active port is an asynchronous port that performs a reset or set operation upon receiving a high level. This is described below using several specific embodiments.

[0027] Example 1

[0028] like Figure 2 In the example shown, both the first reset terminal and the first set terminal are asynchronous low-level active ports.

[0029] The setting module includes a first selector, wherein the first input port (1) of the first selector is set as the first setting data terminal, the second input port (0) of the first selector is set as a fixed connection high level, the enable port of the first selector is set as the second setting data terminal, and the output terminal of the first selector is set as the setting output terminal. When the enable port input of the first selector is 1, the first input port of the first selector is connected, and when the enable port input of the first selector is 0, the second input port of the first selector is connected.

[0030] The reset setting module includes a second selector and an inverter (I). The first input port of the second selector is set to the first reset data terminal, the second input port of the second selector is set to be fixedly connected to a high level, the enable terminal of the second selector is connected to the output terminal of the inverter, the data terminal of the inverter is set to the second reset data terminal, and the output terminal of the second selector is set to the reset output terminal. When the enable port input of the second selector is 1, the first input port of the second selector is connected, and when the enable port input of the first selector is 0, the second input port of the first selector is connected.

[0031] When the first reset signal is low and the value output by the second output terminal is 0, the enable port input of the first selector is 0, the second input port of the first selector is selected, the set output terminal output is high, and the set operation is not performed. After the inverter inputs 0, the output is 1, the enable port input of the second selector is 1, the first input port of the second selector is turned on, the reset output terminal is low, and the first flip-flop is reset to 0. It can be understood that for the structure described in Example 1, when the first reset terminal and the first set terminal are both asynchronous low-level active ports, if the value in the first flip-flop needs to be set to 0, it is sufficient to control the second flip-flop to output 0.

[0032] When the first reset signal is low and the value output by the second output terminal is 1, the enable port input of the first selector is 1, the first input port of the first selector is connected, the set output terminal is low, and the first flip-flop is set to 1. After the inverter inputs 1, the output is 0, the enable port input of the second selector is 0, the second input port of the second selector is connected, the reset output terminal is high, and the reset operation is not performed. It can be understood that for the structure described in Example 1, when the first reset terminal and the first set terminal are both asynchronous low-level active ports, if the value in the first flip-flop needs to be set to 1, it is sufficient to control the second flip-flop to output 1.

[0033] Example 2

[0034] like Figure 3 In the example shown, both the first reset terminal and the first set terminal are asynchronous low-level active ports.

[0035] The set setting module includes a first selector and an inverter, wherein the first input port (1) of the first selector is set as the first reset data terminal, the second input port (0) of the first selector is set as a fixed high level, the enable port of the first selector is connected to the output terminal of the inverter, the data terminal of the inverter is set as the second set data terminal, and the output terminal of the first selector is set as the set output terminal. When the enable port input of the first selector is 1, the first input port of the first selector is connected, and when the enable port input of the first selector is 0, the second input port of the first selector is connected.

[0036] The reset setting module includes a second selector, wherein a first input port of the second selector is set to the first reset data terminal, a second input port of the second selector is set to be fixedly connected to a high level, an enable port of the second selector is set to the second reset data terminal, and an output port of the second selector is set to the reset output terminal. When the enable port input of the second selector is 1, the first input port of the second selector is connected, and when the enable port input of the first selector is 0, the second input port of the first selector is connected.

[0037] When the first reset signal is valid and the value output by the second output terminal is 0, the inverter inputs 0 and then outputs 1, the enable port input of the first selector is 1, the first input port of the first selector is selected, the set output terminal outputs a low level, and the first flip-flop is set to 1. The enable port input of the second selector is 0, the second input port of the second selector is selected, the reset output terminal is high, and the reset operation is not performed. It can be understood that for the structure described in Example 2, when the first reset terminal and the first set terminal are both asynchronous low-level active ports, if the value in the first flip-flop needs to be set to 1, the second flip-flop can be controlled to output 0.

[0038] When the first reset signal is valid and the value output by the second output terminal is 1, the inverter inputs 1 and then outputs 0, then the enable port input of the first selector is 0, the second input port of the first selector is connected, the set output terminal is high, and the set operation is not performed. The enable port input of the second selector is 1, the first input port of the second selector is connected, the reset output terminal is low, and the first flip-flop is reset to 0. It can be understood that for the structure described in Example 2, when the first reset terminal and the first set terminal are both asynchronous low-level active ports, if the value in the first flip-flop needs to be set to 0, it is sufficient to control the second flip-flop to output 1.

[0039] Example 3:

[0040] like Figure 4In the example shown, both the first reset terminal and the first set terminal are asynchronous high-level active ports.

[0041] The setting module includes a first selector, wherein the first input port (1) of the first selector is set as the first setting data terminal, the second input port (0) of the first selector is set as a fixed low level, the enable port of the first selector is set as the second setting data terminal, and the output terminal of the first selector is set as the setting output terminal. When the enable port input of the first selector is 1, the first input port of the first selector is connected, and when the enable port input of the first selector is 0, the second input port of the first selector is connected.

[0042] The reset setting module includes a second selector and an inverter. The first input port of the second selector is set to the first reset data terminal, the second input port of the second selector is set to be fixedly connected to a low level, the enable terminal of the second selector is connected to the output terminal of the inverter, the data terminal of the inverter is set to the second reset data terminal, and the output terminal of the second selector is set to the reset output terminal. When the enable port input of the second selector is 1, the first input port of the second selector is connected, and when the enable port input of the first selector is 0, the second input port of the first selector is connected.

[0043] When the first reset signal is high and the value output by the second output terminal is 0, the enable port input of the first selector is 0, the second input port of the first selector is selected, the set output terminal output is low, and the set operation is not performed. After the inverter inputs 0, the output is 1, the enable port input of the second selector is 1, the first input port of the second selector is turned on, the reset output terminal is high, and the first flip-flop is reset to 0. It can be understood that for the structure described in Example 3, when the first reset terminal and the first set terminal are both asynchronous high-level active ports, if the value in the first flip-flop needs to be set to 0, it is sufficient to control the second flip-flop to output 0.

[0044] When the first reset signal is high and the value output by the second output terminal is 1, the enable port input of the first selector is 1, the first input port of the first selector is connected, the set output terminal is high, and the first flip-flop is set to 1. After the inverter inputs 1, the output is 0, the enable port input of the second selector is 0, the second input port of the second selector is connected, the reset output terminal is low, and the reset operation is not performed. It can be understood that for the structure described in Example 3, when the first reset terminal and the first set terminal are both asynchronous high-level active ports, if the value in the first flip-flop needs to be set to 1, it is sufficient to control the second flip-flop to output 1.

[0045] Example 4:

[0046] like Figure 5 In the example shown, both the first reset terminal and the first set terminal are asynchronous high-level active ports.

[0047] The set setting module includes a first selector and an inverter, wherein the first input port (1) of the first selector is set as the first reset data terminal, the second input port (0) of the first selector is set as a fixed low level, the enable port of the first selector is connected to the output terminal of the inverter, the data terminal of the inverter is set as the second set data terminal, and the output terminal of the first selector is set as the set output terminal. When the enable port input of the first selector is 1, the first input port of the first selector is connected, and when the enable port input of the first selector is 0, the second input port of the first selector is connected.

[0048] The reset setting module includes a second selector, wherein a first input port of the second selector is set to the first reset data terminal, a second input port of the second selector is set to be fixedly connected to a low level, an enable port of the second selector is set to the second reset data terminal, and an output port of the second selector is set to the reset output terminal. When the enable port input of the second selector is 1, the first input port of the second selector is connected, and when the enable port input of the first selector is 0, the second input port of the first selector is connected.

[0049] When the first reset signal is high and the value output by the second output terminal is 0, the inverter inputs 0 and then outputs 1, the enable port input of the first selector is 1, the first input port of the first selector is selected, the set output terminal outputs a high level, and the first flip-flop is set to 1. The enable port input of the second selector is 0, the second input port of the second selector is selected, the reset output terminal is low, and the reset operation is not performed. It can be understood that for the structure described in Example 4, when the first reset terminal and the first set terminal are both asynchronous high-level active ports, if it is necessary to set the value in the first flip-flop to 1, it is sufficient to control the second flip-flop to output 0.

[0050] When the first reset signal is high and the value output by the second output terminal is 1, the inverter inputs 1 and then outputs 0, then the enable port input of the first selector is 0, the second input port of the first selector is connected, the set output terminal is low, and the set operation is not performed. The enable port input of the second selector is 1, the first input port of the second selector is connected, the reset output terminal is high, and the first flip-flop is reset to 0. It can be understood that for the structure described in Example 4, when the first reset terminal and the first set terminal are both asynchronous high-level active ports, if the value in the first flip-flop needs to be set to 0, it is sufficient to control the second flip-flop to output 1.

[0051] An embodiment of the present invention provides two triggers as well as a reset setting module and a set setting module. The output value of one of the triggers is combined with the reset setting module and the set setting module so that the signal output by the reset output terminal and the signal output by the set output terminal are mutually exclusive. When the first reset signal is valid, the first trigger is reset to 0 by the first reset terminal or set to 1 by the first set terminal, thereby realizing the ability to control the asynchronous reset state of the trigger according to application requirements.

[0052] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make slight changes or modifications to equivalent embodiments using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A trigger circuit structure with controllable asynchronous reset state, characterized in that: It includes a first trigger, a second trigger, a reset setting module and a set setting module, wherein: The first trigger includes a first reset terminal, a first set terminal, and a first data terminal; The second trigger includes a second reset terminal and a second output terminal; The reset setting module includes a first reset data terminal, a second reset data terminal and a reset output terminal; The setting module includes a first setting data terminal, a second setting data terminal and a setting output terminal; The first reset data terminal and the first set data terminal are both used to receive a first reset signal, the second reset data terminal and the second set data terminal are both connected to the second output terminal, the reset output terminal is connected to the first reset terminal, and the set output terminal is connected to the first set terminal, the second reset terminal is used to receive a second reset signal, the first reset signal and the second reset signal are different reset signals, the second reset signal is used to set an initial value or a reset value set by the second flip-flop, when the second flip-flop is in a normal working state, the value in the second flip-flop is determined by the clock signal and the data port of the second flip-flop; The signal output by the reset output terminal and the signal output by the set output terminal are mutually exclusive. When the first reset signal is valid, the first trigger is reset to 0 by the first reset terminal or set to 1 by the first set terminal. When the first reset signal is valid, only one of the signal output by the reset output terminal and the signal output by the set output terminal will affect the value of the first trigger. When the first reset signal is invalid, neither the signal output by the reset output terminal nor the signal output by the set output terminal affects the value of the first trigger. The first trigger updates the value stored in the first trigger to the value input by the first data terminal when the rising edge of the clock connected to the first trigger arrives.

2. The circuit structure according to claim 1, wherein: The first reset terminal and the first set terminal are both asynchronous low-level active ports.

3. The circuit structure according to claim 2, wherein: The set setting module includes a first selector, wherein the first input port of the first selector is set to the first set data terminal, the second input port of the first selector is set to be fixedly connected to a high level, the enable port of the first selector is set to the second set data terminal, and the output terminal of the first selector is set to the set output terminal; when the enable port input of the first selector is 1, the first input port of the first selector is connected, and when the enable port input of the first selector is 0, the second input port of the first selector is connected; The reset setting module includes a second selector and an inverter, the first input port of the second selector is set to the first reset data end, the second input port of the second selector is set to a fixed connection high level, the enable end of the second selector is connected to the output end of the inverter, the data end of the inverter is set to the second reset data end, and the output end of the second selector is set to the reset output end; when the enable port input of the second selector is 1, the first input port of the second selector is connected, and when the enable port input of the first selector is 0, the second input port of the first selector is connected.

4. The circuit structure according to claim 2, wherein: The set setting module includes a first selector and an inverter, the first input port of the first selector is set to the first reset data terminal, the second input port of the first selector is set to be fixedly connected to a high level, the enable port of the first selector is connected to the output terminal of the inverter, the data terminal of the inverter is set to the second set data terminal, and the output terminal of the first selector is set to the set output terminal. When the enable port input of the first selector is 1, the first input port of the first selector is connected, and when the enable port input of the first selector is 0, the second input port of the first selector is connected; The reset setting module includes a second selector, the first input port of the second selector is set to the first reset data end, the second input port of the second selector is set to a fixed connection high level, the enable end of the second selector is set to the second reset data end, and the output end of the second selector is set to the reset output end; when the enable port input of the second selector is 1, the first input port of the second selector is connected, and when the enable port input of the first selector is 0, the second input port of the first selector is connected.

5. The circuit structure according to claim 1, wherein: The first reset terminal and the first set terminal are both asynchronous high-level active ports.

6. The circuit structure according to claim 5, characterized in that: The set setting module includes a first selector, wherein the first input port of the first selector is set to the first set data terminal, the second input port of the first selector is set to be fixedly connected to a low level, the enable port of the first selector is set to the second set data terminal, and the output terminal of the first selector is set to the set output terminal. When the enable port input of the first selector is 1, the first input port of the first selector is connected, and when the enable port input of the first selector is 0, the second input port of the first selector is connected; The reset setting module includes a second selector and an inverter, the first input port of the second selector is set to the first reset data end, the second input port of the second selector is set to a fixed connection low level, the enable end of the second selector is connected to the output end of the inverter, the data end of the inverter is set to the second reset data end, and the output end of the second selector is set to the reset output end; when the enable port input of the second selector is 1, the first input port of the second selector is connected, and when the enable port input of the first selector is 0, the second input port of the first selector is connected.

7. The circuit structure according to claim 5, characterized in that: The set setting module includes a first selector and an inverter, wherein the first input port of the first selector is set to the first reset data terminal, the second input port of the first selector is set to be fixedly connected to a low level, the enable port of the first selector is connected to the output terminal of the inverter, the data terminal of the inverter is set to the second set data terminal, and the output terminal of the first selector is set to the set output terminal. When the enable port input of the first selector is 1, the first input port of the first selector is connected, and when the enable port input of the first selector is 0, the second input port of the first selector is connected; The reset setting module includes a second selector, the first input port of the second selector is set to the first reset data end, the second input port of the second selector is set to a fixed connection low level, the enable end of the second selector is set to the second reset data end, and the output end of the second selector is set to the reset output end; when the enable port input of the second selector is 1, the first input port of the second selector is connected, and when the enable port input of the first selector is 0, the second input port of the first selector is connected.

8. The circuit structure according to claim 1, wherein: The circuit structure also includes an output control circuit, the data end of the output control circuit is connected to the second output end, the output end of the output control circuit is connected to the second reset data end and the second set data end, the output control circuit is used to adjust the value output by the second output end and transmit the adjusted value to the second reset data end and the second set data end.

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