Data receiving method and device based on PHY chip

Abstract

The invention provides a data receiving method and device based on a PHY chip, and relates to the technical field of data transmission. When the method is executed, first synchronous data is sampled by using a sampling clock, so that pulse enabling is generated at a rising edge position of the first synchronous data, the pulse enabling is used for determining a counter value of a counter, and the counter value is a reset value or a count value; the first synchronous data is obtained by sampling the enable mark by using a sampling clock. When the first data frame is transmitted, first synchronous data and second synchronous data are sampled according to the reset value, and the second synchronous data are obtained by sampling a data signal through a sampling clock. And when the second data frame is transmitted, determining a sampling object according to the clock source, and sampling the sampling object based on the counter value. Therefore, when the data frame is transmitted, the sampling time of the data is accurately controlled, and the data receiving effect of the PHY chip is further improved.

Description

Technical Field

[0001] The present application relates to the technical field of data transmission, and in particular to a data receiving method and device based on a PHY chip. Background Art

[0002] The MII interface is a specification that provides a data transmission interface between the MAC (Media Access Control) layer and the PHY (Physical Layer). Signals sent from the MAC to the PHY chip include CLK25, TXENA, TXD[3:0], and MDC; signals sent from the PHY chip to the MAC include TX_CLK, RX_CLK, RXDV, and RXD[3:0]. CLK25 is the main clock input to the PHY chip, TXENA and TXD[3:0] are the enable and data signals sent from the MAC to the PHY chip, respectively. TX_CLK is the synchronization clock for transmit enable and data. In existing MII interface solutions, due to the large number of MAC interfaces, to reduce the number of MAC interfaces, the TX_CLK input is often removed, and data synchronization is performed using other solutions to prevent sampling errors.

[0003] In the prior art, sampling errors are generally prevented through the following methods: 1. The PHY clock CLK25 is provided by the MAC, ensuring synchronization between the PHY's internal sampling clock and the MAC's transmitted data. 2. A phase offset configuration is added to the MAC for MII_TXENA and MII_TXD[3:0]. The phase of MII_TXENA and MII_TXD[3:0] sent by the MAC is modified in 10ns increments. If the phase of the PHY sampling clock and the MAC's transmitted data does not meet the required phase, the offset is modified to ensure synchronous sampling by the PHY. However, data reception is still unsatisfactory.

[0004] In summary, how to improve the data receiving effect of the PHY chip is an urgent problem that those skilled in the art need to solve. Summary of the Invention

[0005] In view of this, the present application provides a data receiving method and device based on a PHY chip, aiming to improve the data receiving effect of the PHY chip.

[0006] In a first aspect, the present application provides a data receiving method based on a PHY chip, comprising: The first synchronization data is sampled using a sampling clock so that a pulse enable is generated at a rising edge position of the first synchronization data; the pulse enable is used to determine a counter value of a counter; the counter value is a reset value or a count value; the first synchronization data is obtained by sampling an enable flag using the sampling clock; When transmitting the first data frame, sampling the first synchronization data and the second synchronization data according to the reset value; the second synchronization data is obtained by sampling the data signal using the sampling clock; When transmitting the second data frame, a sampling object is determined according to a clock source, and the sampling object is sampled based on the counter value.

[0007] Optionally, before sampling the first synchronization data using the sampling clock, the method further includes: continuously sampling the enable flag twice using the sampling clock to obtain third synchronization data and the first synchronization data respectively; The data signal is sampled twice continuously using the sampling clock to obtain fourth synchronous data and the second synchronous data respectively.

[0008] Optionally, when transmitting the first data frame, if the pulse enable is at a high level, the counter is reset and the counter value is the reset value; if the pulse enable is at a low level, the counter increments by a cycle and the counter value is the count value.

[0009] Optionally, if the clock source is not provided by the MAC, determining a sampling object according to the clock source and sampling the sampling object based on the counter value when transmitting the second data frame includes: If the pulse enable is at the high level, the counter is reset, and the counter value is the reset value; The first synchronization data and the second synchronization data are sampled based on the reset value.

[0010] Optionally, if the clock source is provided by the MAC, determining a sampling object according to the clock source and sampling the sampling object based on the counter value when transmitting the second data frame includes: The third synchronization data and the fourth synchronization data are sampled based on a first count value; the count value includes the first count value; and the first count value is located in a previous cycle of the reset value.

[0011] Optionally, after determining a sampling object according to a clock source and sampling the sampling object based on the counter value when transmitting the second data frame, the method further includes: The enable flag and the data signal are sampled based on a second count value; the count value includes the second count value; and the second count value is located in a previous cycle of the first count value.

[0012] In a second aspect, the present application provides a data receiving device based on a PHY chip, comprising: a pulse enable generating module, configured to sample first synchronization data using a sampling clock so as to generate a pulse enable at a rising edge of the first synchronization data; the pulse enable is used to determine a counter value of a counter; the counter value is a reset value or a count value; the first synchronization data is obtained by sampling an enable flag using the sampling clock; A first transmission module is configured to sample the first synchronization data and the second synchronization data according to the reset value when transmitting the first data frame; the second synchronization data is obtained by sampling the data signal using the sampling clock; The second transmission module is configured to determine a sampling object according to a clock source and sample the sampling object based on the counter value when transmitting the second data frame.

[0013] Optionally, the device further comprises: a first synchronization module, configured to continuously sample the enable flag twice using the sampling clock to obtain third synchronization data and the first synchronization data respectively; The second synchronization module is configured to continuously sample the data signal twice using the sampling clock to obtain fourth synchronization data and the second synchronization data respectively.

[0014] Optionally, when transmitting the first data frame, if the pulse enable is at a high level, the counter is reset and the counter value is the reset value; if the pulse enable is at a low level, the counter increments by a cycle and the counter value is the count value.

[0015] Optionally, if the clock source is not provided by MAC, the second transmission module includes: A reset unit, configured to reset the counter if the pulse enable is at a high level, and the counter value is the reset value; The first sampling unit is configured to sample the first synchronization data and the second synchronization data based on the reset value.

[0016] Optionally, if the clock source is provided by a MAC, the second transmission module includes: a second sampling unit, configured to sample the third synchronization data and the fourth synchronization data based on a first count value, wherein the count value includes the first count value, and the first count value is located in a previous cycle of the reset value; Optionally, the device further comprises: The third sampling unit is configured to sample the enable flag and the data signal based on a second count value; the count value includes the second count value; and the second count value is located in a previous cycle of the first count value.

[0017] The present application provides a data receiving method based on a PHY chip. When executing the method, the first synchronous data is first sampled using a sampling clock, so that a pulse enable is generated at the rising edge position of the first synchronous data, wherein the pulse enable is used to determine the counter value of the counter, the counter value is a reset value or a count value, and the first synchronous data is obtained by sampling the enable mark using the sampling clock. When transmitting the first data frame, the first synchronous data and the second synchronous data are sampled according to the reset value, wherein the second synchronous data is obtained by sampling the data signal using the sampling clock. When transmitting the second data frame, the sampling object is determined according to the clock source, and the sampling object is sampled based on the counter value. In this way, based on the pulse enable generated at the rising edge position of the first synchronous data, the counter value of the counter is determined, and when transmitting the data frame, the sampling moment of the data is accurately controlled, that is, the data is sampled at the middle position, ensuring that the data is received at the correct time point, thereby improving the data reception effect of the PHY chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0019] Figure 1 A schematic diagram of a circuit for connecting the MAC layer and the PHY layer using an MII interface; Figure 2 A schematic diagram of another circuit connecting the MAC layer and the PHY layer for an MII interface; Figure 3 It is a sampling waveform diagram; Figure 4 A flowchart of a data receiving method based on a PHY chip provided in an embodiment of the present application; Figure 5 A waveform diagram of a sampling method for receiving data based on a PHY chip provided in an embodiment of the present application; Figure 6 A waveform diagram of a MII_TXENA phase shifted according to an embodiment of the present application; Figure 7 A schematic diagram of sampling waveforms of another data receiving method based on a PHY chip provided in an embodiment of the present application; Figure 8 A schematic diagram of sampling waveforms of another data receiving method based on a PHY chip provided in an embodiment of the present application; Figure 9A schematic diagram of the structure of a data receiving device based on a PHY chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The following will clearly and completely describe the technical solutions in the embodiments of this application in conjunction with the accompanying drawings. This application provides a data receiving method and device based on a PHY chip, which are used in the field of data transmission technology. The above is only an example and does not limit the application areas of the names of the methods and devices provided in this application.

[0021] like Figure 1 As shown, Figure 1 This is a circuit diagram of an MII interface connecting the MAC layer and the PHY layer. The MII interface is a specification that provides a data transmission interface between the MAC (Media Access Control) layer and the PHY (Physical Layer). The signals sent by the MAC to the PHY chip (which performs PHY layer functions) include CLK25, TXENA, TXD[3:0], and MDC; the signals sent by the PHY chip to the MAC include TX_CLK, RX_CLK, RXDV, and RXD[3:0]. CLK25 is the PHY chip's input master clock, TXENA and TXD[3:0] are the enable and data signals sent by the MAC to the PHY chip, respectively. TX_CLK is the synchronization clock for transmit enable and data.

[0022] In existing MII interface solutions, due to the large number of MAC interfaces, in order to reduce the number of MAC interfaces, the TX_CLK input is usually removed and other solutions are used for data synchronization to prevent sampling errors. The existing solutions are: 1. The PHY clock CLK25 is provided by the MAC, which ensures the synchronization of the sampling clock inside the PHY and the data sent by the MAC; 2. Add phase offset configuration for MII_TXENA and MII_TXD[3:0] in MAC, and modify the phase of MII_TXENA and MII_TXD[3:0] sent by MAC in units of 10ns. If the phase of PHY sampling clock and MAC send data does not meet the requirements, the offset can be modified to meet the synchronous sampling of PHY.

[0023] The specific circuit connection is as follows Figure 2 As shown, Figure 2 A circuit diagram showing another type of MII interface connecting the MAC layer and the PHY layer.

[0024] The specific process of the existing solution is: first complete the PCB according to the above solution, then test the TX_CLK output by the PHY, and set the MAC's TX shift, that is, the above phase offset, according to the actual tested clock phase to meet the PHY chip's synchronous sampling of the MAC's sent data. Sampling waveform Figure 3 As shown, Figure 3 It is a sampling waveform diagram.

[0025] The above technical solution requires that the PHY clock be provided by the MAC to ensure that the sampling clock is synchronous. Then, a phase offset is implemented in the MAC to ensure that the PHY can sample the correct data. However, it has the following disadvantages: 1. When the PHY uses another clock source to provide the 25M clock, that is, when the MAC and PHY sampling clock frequencies are the same but the phases are different and uncertain, the above solution cannot solve the problem; 2. The operation process is too complicated and the offset time needs to be modified according to the designed PCB situation; 3. If the PCB design is modified, the offset time needs to be modified again; 4. As temperature or environment changes, the TX shift setting may need to be modified; 5. Because a shift is added to MAC, that is, TXENA and TXD[3:0] are delayed, the transmission delay of the data frame is increased.

[0026] Therefore, in the prior art, there is a problem that the data receiving effect of the PHY chip is poor.

[0027] After research, the inventors proposed the technical solution of the present application. First, the first synchronous data is sampled using a sampling clock, so that a pulse enable is generated at the rising edge position of the first synchronous data, wherein the pulse enable is used to determine the counter value of the counter, and the counter value is a reset value or a count value. The first synchronous data is obtained by sampling the enable mark using the sampling clock. When transmitting the first data frame, the first synchronous data and the second synchronous data are sampled according to the reset value, wherein the second synchronous data is obtained by sampling the data signal using the sampling clock. When transmitting the second data frame, the sampling object is determined according to the clock source, and the sampling object is sampled based on the counter value. In this way, based on the pulse enable generated at the rising edge position of the first synchronous data, the counter value of the counter is determined, and when transmitting the data frame, the sampling moment of the data is accurately controlled, that is, the data is sampled at the middle position, ensuring that the data is received at the correct time point, thereby improving the data reception effect of the PHY chip.

[0028] like Figure 4 As shown, Figure 4 A flowchart of a data receiving method based on a PHY chip provided in an embodiment of the present application includes: S401: Sample the first synchronous data using a sampling clock, so that a pulse enable is generated at a rising edge position of the first synchronous data.

[0029] First, before executing the implementation in step S401, it is necessary to first sample the enable flag twice continuously using the sampling clock, wherein the first sampling generates the third synchronization data, and the second sampling generates the first synchronization data. The data signal is then sampled twice continuously using the sampling clock, wherein the first sampling generates the fourth synchronization data, and the second sampling generates the second synchronization data. The third synchronization data is an intermediate product of the process of generating the first synchronization data, and the fourth synchronization data is an intermediate product of the process of generating the second synchronization data.

[0030] Next, the first synchronous data is sampled using the sampling clock, so that a high-level pulse is generated at the rising edge position of the first synchronous data (corresponding to the same time), thereby obtaining a pulse enable.

[0031] S402: When transmitting the first data frame, sample the first synchronization data and the second synchronization data according to the reset value.

[0032] First, it should be noted that the first data frame and the second data frame are consecutive data frames, that is, the first data frame is the first data frame in the consecutive data frames, the second data frame is the second data frame in the consecutive data frames, and so on, the third data frame is the third data frame in the consecutive data frames.

[0033] When transmitting the first data frame, it is necessary to first determine whether the pulse enable is at a high level. If the pulse enable is at a high level, the counter is reset and the counter value is the reset value. If the pulse enable is at a low level, the counter increments by one cycle and the counter value is the count value. When the counter value reaches the reset value, the sampling clock is used to sample the first and second synchronous data to complete data reception.

[0034] S403: When transmitting the second data frame, determine a sampling object according to a clock source, and sample the sampling object based on a counter value.

[0035] Before executing step S403 , it is necessary to determine whether the clock source of the PHY is provided by the MAC.

[0036] If the clock source is not provided by the MAC, the first and second synchronization data are sampled when the counter value reaches the reset value to complete data reception. When transmitting the third and subsequent data frames, the first and second synchronization data are sampled using the sampling clock when the counter value reaches the reset value to complete data reception.

[0037] If the clock source is provided by the MAC, the sampling clock is used to sample the third and fourth synchronous data frames when the counter value reaches the first count value in the cycle preceding the reset value to complete data reception. When transmitting the third and subsequent data frames, the enable flag and data signal are marked when the counter value reaches the second count value in the cycle preceding the first count value to complete data reception. This approach of reducing latency by pre-sampling twice stabilizes the transmission of subsequent data frames. If pre-sampling is used only once, a sudden reduction of 20 ns between two data frames could affect subsequent data frames.

[0038] In an embodiment of the present application, the first synchronous data is first sampled using a sampling clock, so that a pulse enable is generated at the rising edge position of the first synchronous data, wherein the pulse enable is used to determine the counter value of the counter, the counter value is a reset value or a count value, and the first synchronous data is obtained by sampling the enable mark using the sampling clock. When transmitting the first data frame, the first synchronous data and the second synchronous data are sampled according to the reset value, wherein the second synchronous data is obtained by sampling the data signal using the sampling clock. When transmitting the second data frame, the sampling object is determined according to the clock source, and the sampling object is sampled based on the counter value. In this way, based on the pulse enable generated at the rising edge position of the first synchronous data, the counter value of the counter is determined, and when transmitting the data frame, the sampling moment of the data is accurately controlled, that is, the data is sampled at the middle position, ensuring that the data is received at the correct time point, thereby improving the data reception effect of the PHY chip.

[0039] The above describes the data receiving method based on the PHY chip provided in the embodiment of the present application. The following is an exemplary description of the method in combination with a specific application scenario.

[0040] First, synchronize the data enable flag MII_TXENA and the data signal MII_TXD[3:0]. The specific steps are as follows: Since the data enable flag MII_TXENA, the data signal MII_TXD[3:0] and the 100M clock inside the chip are non-cognate clocks, when sampling the data enable flag MII_TXENA and the data signal MII_TXD[3:0], in order to avoid metastable states, synchronization operations are required. Use the 100M clock, i.e., the sampling clock, and sample it twice in succession. Figure 7 As shown, Figure 7 This is a waveform diagram of another sampling method for data receiving based on a PHY chip provided in an embodiment of the present application. The data enable flag MII_TXENA and the data signal MII_TXD[3:0] are sampled once with a 100M clock to obtain the third synchronization data TXENA_SYN1 and the fourth synchronization data TXD_SYN1[3:0]. Figure 5 As shown, Figure 5 A waveform diagram of a sampling of a data receiving method based on a PHY chip provided in an embodiment of the present application, wherein the data enable mark MII_TXENA and the data signal MII_TXD[3:0] are sampled twice continuously with a 100M clock to obtain the first synchronization data TXENA_SYN2 and the second synchronization data TXD_SYN2[3:0].

[0041] Among them, MII_TXENA is the data enable flag. If it is high, it means that the data MII_TXD[3:0] is valid, that is, data frame transmission is in progress. If it is low, it means that the data frame transmission is completed, that is, a high-level stage of MII_TXENA represents a data frame transmission stage.

[0042] like Figure 5 As shown, the first synchronization data TXENA_SYN2 is sampled using the 100M clock inside the PHY chip. At the rising edge position of the first synchronization data TXENA_SYN2 (corresponding to the same time), that is, time T3, a high-level pulse is generated, thereby obtaining a pulse enable, that is, Figure 5 TXENA_POS in .

[0043] The embodiment of the present application also includes a 2-bit counter, which determines the value of the counter according to the frequency / period of the 100M sampling clock and the data signal MII_TXD[3:0] inside the PHY chip. Since the data signal MII_TXD[3:0] is generated by the 25M clock domain, the period of each data signal is 40ns, and the period of the 100M data sampling clock is 10ns, that is, the period of each data signal MII_TXD[3:0] is 1 / 4 of the period of the data sampling clock, so the value of the counter can be set to 0, 1, 2 and 3, a total of four counter values, and the reset value of the counter is set to 0. Figure 5 As shown in the figure, when the pulse enable is detected as a high level at time T3~T4, the counter is reset at time T4~T5, and the counter value is the reset value 0 at this time; when the pulse enable is detected as a low level after time T4, the counter performs a self-incrementing cycle, and the counter value is 1, 2, 3, 0, 1, 2 in a cycle.

[0044] If the PHY clock source is not provided by the MAC but a 25M clock from another clock source, there is uncertainty between the phase of the MAC data sent and the phase of the PHY sampling clock. If the PHY clock source is provided by the MAC, there is synchronization between the phase of the MAC data sent and the phase of the PHY sampling clock. Therefore, it is necessary to determine whether the PHY chip's clock source is provided by the MAC chip.

[0045] If the PHY clock source is not provided by the MAC, perform the following steps: When the pulse enable is high, the counter value is reset to 0; when the pulse enable is low, the counter counts by itself. Figure 5 As shown in the figure, when the value of the counter (CNT) is 0 at time T4~T5, the first synchronization data TXENA_SYN2 and the second synchronization data TXD_SYN2[3:0] are sampled using the 100M sampling clock at time T5; when the value of the counter is 1, 2 or 3, the sampling of the first synchronization data TXENA_SYN2 and the second synchronization data TXD_SYN2[3:0] is stopped, and the data remains unchanged.

[0046] In this case, the PHY clock source is not provided by the MAC. When transmitting each data frame, it is necessary to use the pulse enable TXENA_POS to reset the counter to ensure correct data sampling. Therefore, in this application environment, each data frame has a 20ns transmission delay. Although the 20ns transmission delay is lost, accurate sampling can still be achieved without affecting the overall data frame transmission.

[0047] It should be noted that the data signal MII_TXD[3:0] is generated in the 25M clock domain, and the cycle length of each data is 40ns. For a 100M clock with a 10ns period, the counter values can be set to four values, 0 to 3. The reset value is set to 0 because the subsequent sampling circuit samples at 0, which is the middle position of the second synchronous data TXD_SYN2[3:0]. This means that the signal is stable at this time, and the sampling result is the most accurate.

[0048] In some cases, if the phase of MII_TXENA shifts, the pulse enable will also shift accordingly, thereby automatically modifying the position of subsequent sampling to achieve automatic shift, as shown in the following example. Figure 6 As shown, Figure 6 A waveform diagram of a phase shift of MII_TXENA provided in an embodiment of the present application. When the phase of MII_TXENA shifts, the pulse enable will also shift accordingly, thereby automatically modifying the position of subsequent sampling, corresponding to Figure 5 and Figure 6 That is, when the phase of MII_TXENA shifts, the corresponding TXENA_SYN2 after synchronization also shifts, and the rising edge changes from T3 to T6. As a result, the rising edge of the generated high-level pulse enable also changes from T3 to T6, and the sampling position also changes from T5 to T8, realizing automatic shift.

[0049] If the PHY clock source is provided by the MAC, perform the following steps: First, it is necessary to determine whether the data frame to be received is the nth data frame after power-on, where n is a positive integer.

[0050] 1. When n is equal to 1, the specific receiving steps are as follows: like Figure 5 As shown in the figure, when the value of the counter (CNT) at time T4~T5 is 0, the first synchronization data TXENA_SYN2 and the second synchronization data TXD_SYN2[3:0] are sampled at time T5; when the value of the counter is 1, 2 or 3, the sampling of the first synchronization data TXENA_SYN2 and the second synchronization data TXD_SYN2[3:0] is stopped, and the data remains unchanged.

[0051] 2. When n is equal to 2, the specific receiving steps are as follows: like Figure 7 As shown, when the pulse enable TXENA_POS is low, that is, before time T3 and after time T4, the counter performs a self-incrementing cycle count. When the pulse enable TXENA_POS is high, that is, from time T3 to T4, no reset is performed, and the counter maintains synchronous counting. When the value of the counter at time T3 to T4 is 3, that is, the first count value of the cycle before the reset value, the third synchronous data TXENA_SYN1 and the fourth synchronous data TXD_SYN1[3:0] are sampled at time T4, that is, the sampling is advanced by one cycle, and the sampling object is also advanced by one cycle. At this time, the delay is reduced by 10ns, that is, the delay is 10ns; when the value of the counter is 0, 1, or 2, the sampling of the third synchronous data TXENA_SYN1 and the fourth synchronous data TXD_SYN1[3:0] is stopped, and the data remains unchanged.

[0052] 3. When n is greater than or equal to 3, the specific receiving steps are as follows: like Figure 8 As shown, Figure 8 A waveform diagram of another sampling method for data receiving based on a PHY chip provided in an embodiment of the present application. When the pulse enable TXENA_POS is at a low level, that is, before the T3 moment and after the T4 moment, the counter performs a self-incremental cycle count. When the pulse enable TXENA_POS is at a high level, that is, from T3 to T4, it is not reset and the counter maintains synchronous counting. When the value of the counter is 2, that is, the second count value of the cycle before the first count value, the data enable mark MII_TXENA and the data signal MII_TXD[3:0] are sampled at the T3 moment, that is, the sampling is advanced by one cycle, and the sampling object is also advanced by one cycle. At this time, the delay is reduced by 10ns again, that is, the delay is 0ns. When the value of the counter is 0, 1, or 3, the sampling of the data enable mark MII_TXENA and the data signal MII_TXD[3:0] is stopped, and the data remains unchanged.

[0053] In this case, the PHY clock source is provided by the MAC, and the phase of the MAC data sent is synchronized with the sampling clock phase of the PHY. The synchronization operation is performed only when the first data frame is transmitted, that is, the pulse enable TXENA_POS is used to reset the counter. This synchronization can be maintained in subsequent data frames. At this time, the subsequent sampling time can also be modified to reduce the transmission delay of subsequent data frames and improve data transmission efficiency. At the same time, the sampling time will be automatically adjusted with the offset of MII_TXENA, realizing automatic shift, thereby improving the accuracy of data reception.

[0054] In the field of industrial Ethernet, in order to reduce port usage, the TX_CLK port is removed, which causes the problem of synchronous sampling of data transmission from MAC to PHY. The present invention solves many problems existing in the existing technology and broadens the applicability. At the same time, it takes into account the situations where the PHY clock source is provided by the MAC as well as the situation where the PHY clock source is not provided by the MAC, ensuring that the PHY accurately samples the data sent by the MAC, simplifying the complete application process, and reducing the complexity of chip application.

[0055] The above are some specific implementations of the data receiving method based on the PHY chip provided in the embodiments of the present application. Based on this, the present application also provides a corresponding device. The device provided in the embodiments of the present application will be introduced from the perspective of functional modularization.

[0056] like Figure 9 As shown, Figure 9 This is a schematic structural diagram of a data receiving device based on a PHY chip provided in an embodiment of the present application. The data receiving device based on a PHY chip 900 includes: a pulse enable generating module 910 configured to sample first synchronization data using a sampling clock so as to generate a pulse enable at a rising edge of the first synchronization data; the pulse enable is used to determine a counter value of a counter; the counter value is a reset value or a count value; the first synchronization data is obtained by sampling an enable flag using the sampling clock; A first transmission module 920 is configured to sample the first synchronization data and the second synchronization data according to the reset value when transmitting the first data frame; the second synchronization data is obtained by sampling the data signal using the sampling clock; The second transmission module 930 is configured to determine a sampling object according to a clock source and sample the sampling object based on the counter value when transmitting the second data frame.

[0057] Optionally, the apparatus 900 further includes: a first synchronization module, configured to continuously sample the enable flag twice using the sampling clock to obtain third synchronization data and the first synchronization data respectively; The second synchronization module is configured to continuously sample the data signal twice using the sampling clock to obtain fourth synchronization data and the second synchronization data respectively.

[0058] Optionally, when transmitting the first data frame, if the pulse enable is at a high level, the counter is reset and the counter value is the reset value; if the pulse enable is at a low level, the counter increments by a cycle and the counter value is the count value.

[0059] Optionally, if the clock source is not provided by MAC, the second transmission module 930 includes: A reset unit, configured to reset the counter if the pulse enable is at a high level, and the counter value is the reset value; The first sampling unit is configured to sample the first synchronization data and the second synchronization data based on the reset value.

[0060] Optionally, if the clock source is provided by a MAC, the second transmission module 930 includes: The second sampling unit is configured to sample the third synchronization data and the fourth synchronization data based on a first count value; the count value includes the first count value; and the first count value is located in a previous cycle of the reset value.

[0061] Optionally, the apparatus 900 further includes: The third sampling unit is configured to sample the enable flag and the data signal based on a second count value; the count value includes the second count value; and the second count value is located in a previous cycle of the first count value.

[0062] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0063] It should also be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the equipment and device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments. The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components indicated as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without expending creative work.

[0064] The above is merely one specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A data receiving method based on a PHY chip, characterized in that: include: Sampling the first synchronous data using a sampling clock so that a pulse enable is generated at a rising edge position of the first synchronous data; The pulse enable is used to determine a counter value of a counter; The counter value is a reset value or a count value; the first synchronization data is obtained by sampling the enable flag using the sampling clock; When transmitting the first data frame, sampling the first synchronization data and the second synchronization data according to the reset value; the second synchronization data is obtained by sampling the data signal using the sampling clock; When transmitting the second data frame, a sampling object is determined according to a clock source, and the sampling object is sampled based on the counter value.

2. The method according to claim 1, characterized in that Before sampling the first synchronization data using the sampling clock, the method further includes: continuously sampling the enable flag twice using the sampling clock to obtain third synchronization data and the first synchronization data respectively; The data signal is sampled twice continuously using the sampling clock to obtain fourth synchronous data and the second synchronous data respectively.

3. The method according to claim 2, characterized in that When transmitting the first data frame, if the pulse enable is at a high level, the counter is reset and the counter value is the reset value; if the pulse enable is at a low level, the counter increments by one cycle and the counter value is the count value.

4. The method according to claim 3, characterized in that If the clock source is not provided by the MAC, determining a sampling object according to the clock source when transmitting the second data frame, and sampling the sampling object based on the counter value, includes: If the pulse enable is at the high level, the counter is reset, and the counter value is the reset value; The first synchronization data and the second synchronization data are sampled based on the reset value.

5. The method according to claim 3, characterized in that If the clock source is provided by a MAC, determining a sampling object according to the clock source when transmitting the second data frame, and sampling the sampling object based on the counter value, includes: The third synchronization data and the fourth synchronization data are sampled based on a first count value; the count value includes the first count value; and the first count value is located in a previous cycle of the reset value.

6. The method according to claim 5, characterized in that After determining a sampling object according to a clock source and sampling the sampling object based on the counter value when transmitting the second data frame, the method further includes: The enable flag and the data signal are sampled based on a second count value; the count value includes the second count value; and the second count value is located in a previous cycle of the first count value.

7. A data receiving device based on a PHY chip, characterized in that: include: A pulse enable generating module, configured to sample the first synchronization data using a sampling clock so as to generate a pulse enable at a rising edge position of the first synchronization data; The pulse enable is used to determine a counter value of a counter; The counter value is a reset value or a count value; the first synchronization data is obtained by sampling the enable flag using the sampling clock; A first transmission module is configured to sample the first synchronization data and the second synchronization data according to the reset value when transmitting the first data frame; the second synchronization data is obtained by sampling the data signal using the sampling clock; The second transmission module is configured to determine a sampling object according to a clock source and sample the sampling object based on the counter value when transmitting the second data frame.

8. The device according to claim 7, characterized in that The device further comprises: a first synchronization module, configured to continuously sample the enable flag twice using the sampling clock to obtain third synchronization data and the first synchronization data respectively; The second synchronization module is configured to continuously sample the data signal twice using the sampling clock to obtain fourth synchronization data and the second synchronization data respectively.

9. The device according to claim 8, characterized in that When transmitting the first data frame, if the pulse enable is at a high level, the counter is reset and the counter value is the reset value; if the pulse enable is at a low level, the counter increments by one cycle and the counter value is the count value.

10. The device according to claim 9, characterized in that If the clock source is not provided by the MAC, the second transmission module includes: A reset unit, configured to reset the counter if the pulse enable is at a high level, and the counter value is the reset value; The first sampling unit is configured to sample the first synchronization data and the second synchronization data based on the reset value.

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