High-definition video signal watermark embedding device and embedding method

Abstract

The invention discloses a high-definition video signal watermark embedding device and an embedding method. The device comprises a watermark embedding device and a watermark gateway, the method comprises the following steps that: a signal source inputs a video signal in an HDMI (High Definition Multimedia Interface) or DVI (Digital Video Interface) format into a watermark embedding device; the watermark embedding device carries out receiving, clock synchronization and analysis on an input video signal, the video signal embedded with the watermark is sent to the display through an output interface of the watermark embedding device, and the display equipment presents video content with the watermark; the watermark gateway is used as a central control and management module, establishes TCP / IP network connection with one or more sets of watermark embedding devices, and communicates through an Ethernet switch or a local area network; a manager accesses the watermark gateway through a GUI client, a Web UI or a character terminal, and configures, monitors, operates and maintains the watermark device. According to the method, the survivability of the watermark under the attacks of screen shooting distortion, compression transformation and the like is improved, and the leakage tracking ability is effectively enhanced; and the method has good safety and maintainability.

Description

Technical Field

[0001] The present invention relates to the technical field of information security protection, and in particular to a high-definition video signal watermark embedding device and embedding method. Background Art

[0002] With the rapid development of informatization and digital office work, protecting confidential data and digital assets has become a pressing issue. However, traditional access control and encryption protection methods primarily target network transmission or storage processes, and are ineffective in preventing the illegal capture of screen content via external recording devices (such as smartphones). Unauthorized screen capture has become a major risk for the leakage of sensitive information, posing a severe challenge to information security in government, military, finance, and enterprise sectors.

[0003] Traditional digital watermarking technology typically processes image content at the software level to achieve content protection and traceability. However, existing watermark embedding methods mostly rely on pre-installed software devices in video capture or transmission equipment. This approach presents two significant problems: First, the devices used in some practical application scenarios do not have the necessary software installation requirements, or the installation of third-party watermarking programs is prohibited for security and compatibility reasons; second, the computing resources and device performance of some embedded terminal devices are limited, making it difficult to support the operation of complex video watermarking algorithms, resulting in unstable or unachievable watermark embedding effects.

[0004] Therefore, there is an urgent need for a video watermark embedding solution with higher security, greater flexibility, versatility, and plug-and-play functionality to achieve real-time protection and leakage tracing of screen display content, which has important practical application prospects. Summary of the Invention

[0005] Purpose of the invention: The purpose of the present invention is to provide a high-definition video signal watermark embedding device and embedding method to achieve real-time protection and leakage tracing of screen display content.

[0006] Technical solution: The high-definition video signal watermark embedding device described in the present invention includes two parts: a watermark embedding device and a watermark gateway. The watermark embedding device embeds watermarks through a set of equipment independent of the original computer device. The watermark gateway manages one or more sets of watermark embedding devices, and dynamically issues watermark configurations, turns on or off visible watermarks and invisible watermarks, and monitors video images. The watermark gateway and the watermark embedding device are connected by an Ethernet link, and communication is established through TCP / IP. The watermark embedding device is physically connected between the signal source and the display terminal, which is a "bypass deployment" that does not interfere with the original device and does not make software changes to the computer device.

[0007] Furthermore, the watermark embedding device embeds the watermark in a non-invasive manner.

[0008] The method for embedding a high-definition video signal watermark according to the present invention comprises the following steps:

[0009] S1: The signal source inputs the video signal in HDMI or DVI format to the watermark embedding device;

[0010] S2: The watermark embedding device receives, synchronizes the clock, and parses the input video signal. Based on the current watermark configuration, it obtains the corresponding watermark control instructions and parameters from the watermark gateway. According to the control strategy, it embeds visible and invisible watermarks in the video frame.

[0011] S3: The video signal after embedding the watermark is sent to the display through the output interface of the watermark embedding device, and the display device presents the video content with the watermark;

[0012] S4: The watermark gateway serves as a central control and management module, establishing a TCP / IP network connection with one or more watermark embedding devices and communicating through an Ethernet switch or a local area network;

[0013] S5: Management personnel access the watermark gateway through the GUI client, Web UI or character terminal to perform configuration, monitoring and operation and maintenance of the watermark device, including real-time viewing of the video output status, video content audit, current policy, operation log, error alarm and other information of each watermark device, to achieve unified management and policy issuance.

[0014] Furthermore, video signals are collected, video images are processed, and video signals are output.

[0015] Furthermore, collecting the video signal includes:

[0016] S21: Convert the high-definition video signal in DVI format to the video signal in VGA format;

[0017] S22: Convert the VGA format video signal into an AXI4-Stream Video signal;

[0018] S23: Send the AXI4-Stream Video signal to a high-speed memory such as DDR through VDMA and write it into the frame buffer BUF0.

[0019] Furthermore, the video image processing includes:

[0020] S24: Read the frame cached in S2.1 from the BUF0 frame buffer in a high-speed memory such as DDR;

[0021] S25: scaling the video frame to the target resolution (for example, the input video is 720P and the output video is 1080P);

[0022] S26: Apply a visible watermark algorithm to the video frame based on the following formula:

[0023] I=W0(I0,M,α)=(1-α)·I0+α·M

[0024] Where I is the image after embedding the watermark; W0(·) represents the operation of embedding the watermark into the image, I0 is the original image, that is, the video frame before embedding the watermark; M is the watermark image, the size of which is the same as I0; α∈[0,1] is the parameter that controls the transparency of the watermark, the larger the value, the more obvious the watermark;

[0025] S27: Apply invisible watermark algorithm to the video frame;

[0026] S28: Writing the processed video back to a high-speed memory such as DDR and writing it to the frame buffer BUF1.

[0027] Furthermore, the output video signal includes:

[0028] S29: Reads the stored frame from the BUF1 buffer in a high-speed memory such as DDR and converts it into an AXI4-Stream Video signal through VDMA;

[0029] S210: Generate a video timing sequence with the same resolution and frame rate based on the acquired video timing information;

[0030] S211: Convert the AXI4-Stream Video signal to a VGA format video signal;

[0031] S212: Convert the VGA format video signal into a DVI format high-definition video signal for output.

[0032] Furthermore, the outputting of the video signal includes: the step S24 includes:

[0033] S241: Generate a watermark pattern using an algorithm: Generate a 64-bit BCH error correction code from a maximum 30-bit watermark message, concatenate the two to form a watermark message W, and then concatenate and rearrange the two into an 8×8 matrix as the watermark pattern;

[0034] S242: Convert the video frame I in RGB format to YPbPr format and separate the brightness channel I Y , chroma channel I U , Saturation Channel I V ; Use its brightness signal I Y Used for watermark embedding to obtain watermark image I Y ';

[0035] S243: Extract I using SIFT algorithm Y Feature points;

[0036] S244: Filter out n feature points to ensure that their embedding areas do not overlap and their strengths are as large as possible; the filtering rule is expressed as:

[0037]

[0038] Among them, p i represents the i-th feature point; S(·) represents the embedding area of the feature point, and In(·) represents the intensity of the feature point;

[0039] S245: Select the 10 feature points with the largest response values as the target point set P s ;

[0040] S246: With P s Each point in is taken as the center, and a 64×64 area is intercepted as the watermark embedding domain;

[0041] S247: Divide each region into multiple 8×8 blocks;

[0042] S248: Perform DCT transform on each 8×8 small block;

[0043] S249: Extract the intermediate frequency coefficients (4, 5) and (5, 4) for each 8×8 block and record them as C 4，5 and C 5，4 , modulated based on watermark information;

[0044]

[0045] Perform IDCT on each 8×8 block to obtain the modified image block; Y ′、I U , I V Resynthesize and convert to RGB format watermark frame I′.

[0046] Furthermore, the step S210 includes: initializing the state machine FSM0; obtaining an instruction for generating a clock from the AXI4-Lite interface; updating the state machine FSM0 according to the instruction and the current state, and using the MMCM DRP to call the MMCM to generate the clock.

[0047] Furthermore, the step S4 includes:

[0048] S41: A Layer 2 link is established between the watermark gateway and the watermark embedding device via Ethernet, supporting automatic discovery and configuration functions to ensure connection stability and manageability;

[0049] S42: The watermark gateway acts as a DHCP server and dynamically allocates IP addresses to the watermark embedding devices according to the pre-entered MAC address list; the control address and port information of the watermark gateway are broadcasted in the Option 43 field in the DHCP message;

[0050] S43: The watermark embedding device automatically initiates a connection request to the watermark gateway according to the DHCP allocation result, and establishes an encrypted and secure control channel through, for example, CAPWAP DTLS, IEEE 802.1X or a certificate-based authentication mechanism;

[0051] S44: After the watermark embedding device completes identity authentication, it initiates a registration request to the watermark gateway and uploads its device information, including device type, serial number, current firmware version, supported watermark capability parameters, etc. After successful registration, the watermark gateway can add the device to the device management list;

[0052] S45: The watermark gateway periodically polls the operating status of the watermark embedding device according to a preset timing strategy;

[0053] S46: Administrators can control the terminal through the watermark gateway and manually or periodically issue watermark policy configurations;

[0054] S47: After receiving the new strategy, the watermark embedding device verifies and automatically switches the watermark parameters, realizing hot update of the watermark style without interrupting the video signal; at the same time, all changes and execution results will be recorded in the local log and reported to the watermark gateway simultaneously.

[0055] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages:

[0056] (1) The present invention achieves non-invasive watermark embedding of high-definition video signals by deploying the watermark embedding device in a bypass manner outside the computer device, avoiding interference with existing business devices and having higher compatibility and deployment flexibility. The device adopts a software and hardware collaborative design, and processes the video signal output by the GPU in real time through FPGA, supports stable analysis and watermark embedding of high-definition video sources such as 1080P@60Hz, and meets the real-time requirements of the current high-resolution and high-refresh rate office environment. At the same time, the supporting watermark gateway supports centralized management of multiple sets of watermark embedding devices, and can dynamically issue personalized watermark strategies to achieve refined user-level accountability and protection;

[0057] (2) This invention takes into account both visibility and robustness in the design of the watermark algorithm. By combining local feature extraction based on I-SIFT with frequency domain watermarking technology, it improves the survivability of the watermark under attacks such as screen distortion and compression transformation, and effectively enhances the ability to track leaks.

[0058] (3) At the device management level, the present invention implements encrypted communication and automatic registration mechanisms through Ethernet links, and has good security and maintainability. It does not require modification of the host device or installation of additional software. It is suitable for scenarios such as government offices, military scientific research, and financial data centers that have strict requirements on information confidentiality, and has significant engineering practical value and promotion and application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 Flowchart for the implementation of the present invention;

[0060] Figure 2 It is a schematic diagram of the architecture of the present invention;

[0061] Figure 3 This is a schematic diagram of the watermark embedding principle of the present invention;

[0062] Figure 4 This is a schematic diagram of a DVI receiver module of the present invention;

[0063] Figure 5 A schematic diagram of a clock network for the clock recovery step of the present invention;

[0064] Figure 6 This is a schematic diagram of the DVI transmitter module of the present invention;

[0065] Figure 7 This is a schematic diagram of the dynamic clock module of the present invention;

[0066] Figure 8 The state transition diagram of the dynamic clock module of the present invention;

[0067] Figure 9 Schematic diagram of the TMDS decoding algorithm of the present invention;

[0068] Figure 10 Schematic diagram of the TMDS encoding algorithm of the present invention;

[0069] Figure 11 A test platform connection topology diagram of an embodiment;

[0070] Figure 12 This is a comparison diagram before and after watermark embedding of the embodiment. DETAILED DESCRIPTION

[0071] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0072] Aiming at the information leakage problem caused by current screen shooting, the present invention proposes a high-definition video signal watermark embedding device, which is divided into two parts, namely the watermark embedding device and the watermark gateway. Figure 2As shown. The watermark embedding device embeds watermarks by using a set of equipment independent of the original computer device, and uses a non-invasive method to embed watermarks. The watermark gateway can manage one or more watermark embedding devices, and realize functions such as dynamic watermark configuration, turning on or off visible watermarks and / or invisible watermarks, and video image monitoring. The watermark gateway and the watermark embedding device are connected by an Ethernet link, and communication is established through TCP / IP. Administrators can log in to the watermark gateway through a GUI program, WebUI or character terminal to manage multiple watermark embedding devices, such as Figure 1 shown.

[0073] The present invention also proposes a method for embedding a watermark in a high-definition video signal, which comprises the following steps:

[0074] S1: The signal source (such as a confidential computer, server, or other video output terminal) inputs the video signal in HDMI or DVI format to the watermark embedding device; the device is physically connected between the signal source and the display terminal, which is a "bypass deployment" that does not interfere with the original device and does not require software changes to the computer device;

[0075] S2: The watermark embedding device receives, synchronizes the clock and analyzes the input video signal, and obtains the corresponding watermark control instructions and parameters from the watermark gateway according to the current watermark configuration; according to the control strategy, it embeds visible watermarks (such as user ID, timestamp, device number, etc.) and / or invisible watermarks (such as traceability information achieved by frequency domain transformation, feature point embedding, etc.) in the video frame, such as Figure 3 As shown;

[0076] S21: Collect video signals

[0077] Convert the DVI format high-definition video signal to the VGA format video signal; Figure 4 As shown, the TMDS differential clock is restored to the serial clock and the corresponding pixel clock, as shown in Figure 5 As shown in the figure, the TMDS differential BGR pixel data channel is decoded into a VGA video signal, a horizontal synchronization signal, a field synchronization signal, and a video data enable signal; a legal EDID information is constructed and transmitted to the signal source through the DDC channel.

[0078] Data decoding consists of the following steps:

[0079] For each color channel, registers D and Q are established; D is 10-bit TMDS data and Q is the output 8-bit pixel data;

[0080] For each color channel, the specific encoding algorithm of the channel is as follows Figure 9 shown.

[0081] Convert the VGA video signal to an AXI4-Stream Video signal. Generate a watermark pattern using the following algorithm: A 64-bit BCH error correction code is generated from the maximum 30-bit watermark message. The two are concatenated to form the watermark message W, which is then re-arranged into an 8×8 matrix as the watermark pattern.

[0082] Convert the RGB video frame I to YPbPr format and separate the brightness channel I Y , chroma channel I U , Saturation Channel I V ; Use its brightness signal I Y Used for watermark embedding to obtain watermark image I Y ';

[0083] Use SIFT algorithm to extract I Y Feature points; select n feature points to ensure that their embedding areas do not overlap and their strength is as large as possible; the screening rule can be expressed as:

[0084]

[0085] Among them, p i represents the i-th feature point; S(·) represents the embedding area of the feature point, and In(·) represents the intensity of the feature point;

[0086] Select the 10 feature points with the largest response value as the target point set P s , with P s As the center of each point in the image, a 64×64 area is intercepted as the watermark embedding domain; each area is divided into multiple 8×8 blocks; DCT transform is performed on each 8×8 block; the intermediate frequency coefficients (4, 5) and (5, 4) of each 8×8 block are extracted and recorded as C 4，5 and C 5，4 , modulated based on watermark information;

[0087]

[0088] Perform IDCT on each 8×8 block to obtain the modified image block; Y ′、I U , I V Resynthesize and convert to RGB format watermark frame I′.

[0089] The AXI4-Stream Video signal is sent to a high-speed memory such as DDR through VDMA and written into the frame buffer BUF0.

[0090] S22: Video Image Processing

[0091] Read the S2.1 cached frames from the BUF0 frame buffer in a high-speed memory such as DDR; scale the video frames to the target resolution (for example, the input video is 720P and the output video is 1080P); and apply a visible watermark algorithm to the video frames based on the following formula:

[0092] I=W0(I0,M,α)=(1-α)·I0+α·M

[0093] Where I is the image after watermarking; W0(·) represents the operation of embedding the watermark into the image, and a simple linear weighted mixing method is used here; I0 is the original image, that is, the video frame before watermarking; M is the watermarked image (or watermark message), and its size is the same as I0; α∈[0,1] is a parameter that controls the transparency of the watermark, and the larger the value, the more obvious the watermark.

[0094] Apply an invisible watermark algorithm to the video frame; write the processed video back to a high-speed memory such as DDR and write it to the frame buffer BUF1.

[0095] S23: Output video signal

[0096] Read the frames stored in S2.2 from the BUF1 buffer in high-speed memory such as DDR and convert them into AXI4-Stream Video signals through VDMA;

[0097] According to the video timing information obtained in S21, a video timing with the same resolution and frame rate is generated; Figure 7 As shown, initialize the state machine FSM0; obtain the instruction to generate the clock from the AXI4-Lite interface; update the state machine FSM0 according to the instruction and the current state, as shown Figure 8 As shown, MMCM DRP is used to call MMCM to generate the clock.

[0098] Convert AXI4-Stream Video signals to VGA format video signals;

[0099] Convert VGA format video signals to DVI format high-definition video signals for output, such as Figure 6 As shown, the global clock signal of the module is generated by the pixel clock and the serial clock; the VGA video signal, the horizontal synchronization signal, the field synchronization signal and the video data enable signal are decoded into the TMDS differential BGR pixel data channel; and serialized data and clock are generated, wherein the clock signal is realized by serializing the constant 1111100000.

[0100] Data encoding involves the following steps:

[0101] For each color channel, the following registers are established: D, C0, C1, DE; D is 8-bit pixel data, C1 and C0 are the control data of the channel, and DE is the data enable signal;

[0102] For each color channel, a register cnt is created to track the imbalance state of the data flow. A positive value indicates that more "1"s than "0"s have been sent; a negative value indicates that more "0"s than "1"s have been sent. The expression cnt{t-1} represents the imbalance value corresponding to the previous set of input data; the expression cnt(t) represents the new imbalance value corresponding to the current input data.

[0103] For each color channel, create a 10-bit register q_out as the encoded output value;

[0104] For each color channel, the following operators are defined: N1{x} returns the number of "1"s in parameter x, and N0{x} returns the number of "0"s in parameter x; the specific encoding algorithm for this channel is as follows: Figure 10 shown.

[0105] S3: The video signal after embedding the watermark is sent to the display through the output interface (HDMI / DVI) of the watermark embedding device, and the display device presents the video content with the watermark;

[0106] S4: The watermark gateway serves as a central control and management module, establishing a TCP / IP network connection with one or more watermark embedding devices and communicating through an Ethernet switch or a local area network;

[0107] S41: A Layer 2 link is established between the watermark gateway and the watermark embedding device via Ethernet, supporting automatic discovery and configuration functions to ensure connection stability and manageability;

[0108] S42: The watermark gateway acts as a DHCP server and dynamically allocates IP addresses to the watermark embedding devices according to the pre-entered MAC address list. To facilitate the watermark device to locate the watermark gateway, the DHCP message broadcasts the control address and port information of the watermark gateway through the Option 43 field.

[0109] S43: The watermark embedding device automatically initiates a connection request to the watermark gateway based on the DHCP allocation result, and establishes an encrypted and secure control channel through, for example, CAPWAP DTLS, IEEE 802.1X, or a certificate-based authentication mechanism to ensure the confidentiality and integrity of watermark policy transmission and device control;

[0110] S44: After the watermark embedding device completes identity authentication, it initiates a registration request to the watermark gateway and uploads its device information, including device type, serial number, current firmware version, supported watermark capability parameters, etc. After successful registration, the watermark gateway can add the device to the device management list;

[0111] S45: The watermark gateway regularly polls the running status of the watermark embedding device according to the preset timing strategy, including: the currently running watermark strategy ID, watermark embedding mode (visible / invisible), output resolution, signal stability, abnormal log and other information, and displays it on the management terminal interface;

[0112] S46: Administrators can manually or periodically issue watermark policy configurations through the watermark gateway control terminal (e.g., Web UI, GUI client, or terminal command line), including but not limited to: watermark content (e.g., user name, device number, current time), display style (e.g., font, transparency, position), whether to enable visible watermark and / or invisible watermark, and binding user policy templates;

[0113] S47: After receiving the new strategy, the watermark embedding device verifies and automatically switches the watermark parameters, realizing hot update of the watermark style without interrupting the video signal; at the same time, all changes and execution results will be recorded in the local log and reported to the watermark gateway synchronously for audit tracking.

[0114] S5: Administrators can access the watermark gateway through the GUI client, Web UI or character terminal (such as SSH login) to perform configuration, monitoring and operation and maintenance of the watermark device, including real-time viewing of the video output status, video content audit, current policy, operation log, error alarm and other information of each watermark device, to achieve unified management and policy issuance of the entire screen camera protection device.

[0115] This invention utilizes an AMD ZYNQ-7000 series SoC to implement the design of the aforementioned high-definition video signal watermarking device, electronic device, and storage medium. This embodiment utilizes the xc7z020 processor, a Micron Technology MT41K256M16TW 512MB DDR3 chip as cache, and a Phison Semiconductor FL128SAIF00 16MB NAND flash memory to store the bitstream and PS program. A Fittia FT2232H chip converts USB to JTAG and UART, enabling programming and debugging of the processor and modifying the watermark information.

[0116] In order to verify the function of the present invention, the following Figure 11The test platform shown in the figure. The HDMI signal passes through the aforementioned watermarking device and HDMI capture card. The watermarking device adds a watermark, while the HDMI capture card outputs the image without modification, allowing the host computer to capture the video signal. The host computer connects to the PYNQ-Z2 via JTAG and UART for control.

[0117] like Figure 12 The figure shows four screenshots (first row) and their corresponding watermarked screenshots (second row). The average PSNR of the example images before and after watermarking is 42.8003, meeting the requirement of being imperceptible. It is worth noting that the watermarked images were captured by a capture card, and only an invisible watermark was applied.

Claims

1. A high-definition video signal watermark embedding device, characterized in that: It consists of two parts: a watermark embedding device and a watermark gateway. The watermark embedding device embeds watermarks through a set of equipment independent of the original computer device. The watermark gateway manages one or more watermark embedding devices, and dynamically issues watermark configurations, turns on or off visible and invisible watermarks, and monitors video images. The watermark gateway and the watermark embedding device are connected by an Ethernet link and establish communication through TCP / IP. The watermark embedding device is physically connected between the signal source and the display terminal, which is a "bypass deployment" that does not interfere with the original device and does not require software changes to the computer device.

2. The high-definition video signal watermark embedding device according to claim 1, characterized in that: The watermark embedding device embeds the watermark in a non-invasive manner.

3. A method for embedding watermarks in high-definition video signals, characterized in that: The steps include: S1: The signal source inputs the video signal in HDMI or DVI format to the watermark embedding device; S2: The watermark embedding device receives, synchronizes the clock, and parses the input video signal. Based on the current watermark configuration, it obtains the corresponding watermark control instructions and parameters from the watermark gateway. According to the control strategy, it embeds visible and invisible watermarks in the video frame. S3: The video signal after embedding the watermark is sent to the display through the output interface of the watermark embedding device, and the display device presents the video content with the watermark; S4: The watermark gateway serves as a central control and management module, establishing a TCP / IP network connection with one or more watermark embedding devices and communicating through an Ethernet switch or a local area network; S5: Management personnel access the watermark gateway through the GUI client, Web UI or character terminal to perform configuration, monitoring and operation and maintenance of the watermark device, including real-time viewing of the video output status, video content audit, current policy, operation log, error alarm and other information of each watermark device, to achieve unified management and policy issuance.

4. The method for embedding watermark in a high-definition video signal according to claim 3, characterized in that: The step S2 includes: collecting video signals, processing video images, and outputting video signals.

5. The method for embedding watermark in a high-definition video signal according to claim 4, wherein: The collecting of video signals comprises: S21: Convert the high-definition video signal in DVI format to the video signal in VGA format; S22: Convert the VGA format video signal into an AXI4-Stream Video signal; S23: Send the AXI4-Stream Video signal to a high-speed memory such as DDR through VDMA and write it into the frame buffer BUF0.

6. The method for embedding watermark in a high-definition video signal according to claim 4, characterized in that: The video image processing includes: S24: Read the frame cached in S2.1 from the BUF0 frame buffer in a high-speed memory such as DDR; S25: scaling the video frame to the target resolution (for example, the input video is 720P and the output video is 1080P); S26: Apply a visible watermark algorithm to the video frame based on the following formula: I=W0(I0,M,α)=(1-α)·I0+α·M Where I is the image after embedding the watermark; W0(·) represents the operation of embedding the watermark into the image, I0 is the original image, that is, the video frame before embedding the watermark; M is the watermark image, the size of which is the same as I0; α∈[0,1] is the parameter that controls the transparency of the watermark, the larger the value, the more obvious the watermark; S27: applying an invisible watermark algorithm to the video frame; S28: Writing the processed video back to a high-speed memory such as DDR and writing it to the frame buffer BUF1.

7. The method for embedding watermark in a high-definition video signal according to claim 4, characterized in that: The output video signal includes: S29: Reads the stored frame from the BUF1 buffer in a high-speed memory such as DDR and converts it into an AXI4-StreamVideo signal through VDMA; S210: Generate a video timing sequence with the same resolution and frame rate based on the acquired video timing information; S211: Convert the AXI4-Stream Video signal to a VGA format video signal; S212: Convert the VGA format video signal into a DVI format high-definition video signal for output.

8. The method for embedding watermarks in high-definition video signals according to claim 5, wherein: The output video signal includes: the step S24 includes: S241: Generate a watermark pattern using an algorithm: Generate a 64-bit BCH error correction code from a maximum 30-bit watermark message, concatenate the two to form a watermark message W, and then concatenate and rearrange the two into an 8×8 matrix as the watermark pattern; S242: Convert the video frame I in RGB format to YPbPr format and separate the brightness channel I Y , chroma channel I U , Saturation Channel I V ; Use its brightness signal I Y Used for watermark embedding to obtain watermark image I Y '; S243: Extract I using SIFT algorithm Y Feature points; S244: Filter out n feature points to ensure that their embedding areas do not overlap and their strengths are as large as possible; the filtering rule is expressed as: Among them, p i represents the i-th feature point; S(·) represents the embedding area of the feature point, and In(·) represents the intensity of the feature point; S245: Select the 10 feature points with the largest response values as the target point set P s ; S246: With P s Each point in is taken as the center, and a 64×64 area is intercepted as the watermark embedding domain; S247: Divide each region into multiple 8×8 blocks; S248: Perform DCT transform on each 8×8 small block; S249: Extract the intermediate frequency coefficients (4, 5) and (5, 4) for each 8×8 block and record them as C 4，5 and C 5，4 , modulated based on watermark information; Perform IDCT on each 8×8 block to obtain the modified image block; Y ′、I U , I V Resynthesize and convert to RGB format watermark frame I′.

9. The method for embedding watermark in a high-definition video signal according to claim 7, wherein: The step S210 includes: initializing the state machine FSM0; obtaining an instruction for generating a clock from the AXI4-Lite interface; updating the state machine FSM0 according to the instruction and the current state, and using the MMCM DRP to call the MMCM to generate the clock.

10. The method for embedding watermark in a high-definition video signal according to claim 3, wherein: The step S4 comprises: S41: A Layer 2 link is established between the watermark gateway and the watermark embedding device via Ethernet, supporting automatic discovery and configuration functions to ensure connection stability and manageability; S42: The watermark gateway acts as a DHCP server and dynamically allocates IP addresses to the watermark embedding devices according to the pre-entered MAC address list; the DHCP message broadcasts the control address and port information of the watermark gateway through the Option 43 field; S43: The watermark embedding device automatically initiates a connection request to the watermark gateway according to the DHCP allocation result, and establishes an encrypted and secure control channel through, for example, CAPWAP DTLS, IEEE 802.1X or a certificate-based authentication mechanism; S44: After the watermark embedding device completes identity authentication, it initiates a registration request to the watermark gateway and uploads its device information, including device type, serial number, current firmware version, supported watermark capability parameters, etc. After successful registration, the watermark gateway can add the device to the device management list; S45: The watermark gateway periodically polls the operating status of the watermark embedding device according to a preset timing strategy; S46: Administrators can control the terminal through the watermark gateway and manually or periodically issue watermark policy configurations; S47: After receiving the new strategy, the watermark embedding device verifies and automatically switches the watermark parameters, realizing hot update of the watermark style without interrupting the video signal; at the same time, all changes and execution results will be recorded in the local log and reported to the watermark gateway simultaneously.

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